Process method for realizing SiC transverse voltage-withstanding structure

Abstract

The invention relates to the field of semiconductor devices, in particular to a process method for realizing a SiC transverse voltage withstanding structure without depending on a P-type substrate wafer or adopting a P-type epitaxial process, and the process method can be used for devices such as a SiC LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) and the like.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a process method for realizing a SiC lateral voltage-resistant structure which neither relies on a P-type substrate wafer nor adopts a P-type epitaxial process, and can be used for devices such as SiC LDMOS (Lateral Double-Diffused MOSFET). Background Art

[0002] SiC lateral devices have both the material advantages of SiC and the integration advantages of lateral devices. They have the characteristics of high breakdown voltage, low specific on-resistance, easy integration with IC, and good heat dissipation. They have broad application space in monolithic integrated power circuits and radio frequency circuits.

[0003] However, to make SiC lateral devices, the first task is to construct a grounded P-type region located below the drift region to prevent the flow of electrons in the drift region to the substrate electrode. Currently, one of the available methods to construct the P-type region is to make the drift region on a heavily doped P-type substrate wafer. However, due to the problems of aluminum source depletion, difficulty in controlling a single crystal type and doping concentration during wafer growth and subsequent device manufacturing, the P-type substrate wafer has lower quality and higher resistivity, which increases the parasitic effect.

[0004] In order to remove the dependence on P-type substrate wafers, some researchers have proposed growing a grounded P-type epitaxial region on a high-voltage N-type substrate wafer as the base of the voltage-resistant region. Although this method uses an N-type substrate wafer and has higher process feasibility, the subsequent P-type epitaxial region is similar to the P-type substrate wafer and also has serious quality problems. At the same time, the P-type region produced by the epitaxial process cannot be patterned and it is difficult to achieve lateral variable doping, which limits the improvement of device performance and the realization of more functions.

[0005] At present, there is no process method to realize SiC lateral voltage-resistant structure that does not rely on P-type substrate wafers or use P-type epitaxial process. This problem has become a technical bottleneck that seriously restricts the development of SiC lateral devices. Summary of the invention

[0006] The purpose of the present invention is to provide a process method for realizing a SiC lateral voltage-resistant structure that does not rely on a P-type substrate wafer or a P-type epitaxial process, and adopts a high-quality, low-resistivity, high-voltage-connected N-type substrate wafer, forms a P-type buried layer by P-type ion implantation and then N-type drift region epitaxy, and then forms a P-type well region connected to the P-type buried layer by P-type ion implantation and grounding it, thereby realizing a SiC lateral voltage-resistant structure with a feasible process. Furthermore, the P-type buried layer in the lateral voltage-resistant structure is graphically designed, and the drift region is optimized, so that a variety of lateral devices with excellent performance and rich functions can be obtained.

[0007] The process method for realizing SiC lateral pressure-resistant structure proposed by the present invention is as follows: Figure 1 As shown, the specific steps are:

[0008] Step 1: If Figure 1 - (a) shows a heavily doped N-type substrate wafer (01) being prepared;

[0009] Step 2: If Figure 1 - (b), epitaxy is performed on an N-type substrate wafer (01) to form a lightly doped N-type epitaxial layer (02);

[0010] Step 3: If Figure 1 - (c), local ion implantation and annealing are performed on the N-type epitaxy (02) to form a P-type buried layer (03);

[0011] Step 4: If Figure 1 - (d) shows that a thin N-type drift region (05) is formed by epitaxy;

[0012] Step 5: If Figure 1 -(e), ion implantation is performed on the N-type drift region (05) and annealing is performed to form a P-type well region (04);

[0013] Step 6: If Figure 1 -(f) shows that the active region and electrodes of the device are fabricated using conventional process methods.

[0014] The SiC lateral voltage-withstand structure that can be realized based on the process method proposed in the present invention is shown in FIG2(a), comprising an N-type substrate wafer (01), an N-type epitaxial layer (02), a P-type buried layer (03), a P-type well region (04), an N-type drift region (05), a source P+ (06), a source N+ (07), a drain N+ (08), a source (09), a gate oxide (10), a gate (11), a drain (12) and a substrate electrode (13). The N-type epitaxy (02) is arranged above the N-type substrate wafer (01); the P-type buried layer (03) is arranged at the top of the inside of the N-type epitaxy (02), and its left side is connected to the left boundary of the device, and its right side is at a distance from the right boundary of the device; the P-type well region (04) and the N-type drift region (05) are arranged side by side above the N-type epitaxy (02), wherein the P-type well region (04) is on the left and the N-type drift region (05) is on the right; the source electrode P+ (06) is arranged at the top of the inside of the P-type well region (04), and its left side is connected to the left boundary of the device; the source electrode N+ (07) is arranged at the top of the inside of the P-type well region (04), and its left side is connected to the source electrode P+ (06); the drain electrode N+ (08) is arranged The gate electrode (11) is arranged above the gate oxide (10); the drain electrode (12) is arranged above the drain electrode N+ (08); and the substrate electrode (13) is arranged below the N-type substrate wafer (01).

[0015] The device manufactured by the process method of the present invention has N-type substrate wafer and epitaxial layer, which has good quality. At the same time, the P-type buried layer (03) obtained by ion implantation is also better than Figure 1 (b) In the existing structure, the P-type substrate wafer (14) and Figure 1 (c) The P-type epitaxial layer (16) in the existing structure has better quality. Moreover, the P-type buried layer (03) is realized by ion implantation process, which is better than Figure 1 (c) The P-type epitaxy (16) can achieve variable doping through mask design, thereby achieving higher device performance and more device functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of the process method for manufacturing a SiC lateral pressure-resistant structure proposed by the present invention;

[0017] FIG. 2( a ) is a SiC LDMOS fabricated using the process method proposed in the present invention;

[0018] FIG2( b ) shows a SiC LDMOS fabricated using a conventional process method;

[0019] FIG2(c) shows a SiC LDMOS fabricated using another conventional process method;

[0020] Figure 3 Another SiC LDMOS with a P-type top layer is manufactured by applying the process method proposed by the present invention;

[0021] Figure 4 Another SiCLDMOS with a laterally variable doped P-type buried layer manufactured by the process method proposed by the present invention;

[0022] Figure 5 Another SiC LDMOS with a P-type buried layer I is manufactured by using the process method proposed by the present invention;

[0023] Figure 6 An integrated high- and low-side SiC NMOS is manufactured using the process method proposed by the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0025] Example 1

[0026] This embodiment provides a process for manufacturing a SiC lateral pressure-resistant structure, and the specific steps are as follows:

[0027] Step 1: If Figure 1 - (a) shows a heavily doped N-type substrate wafer (01) being prepared;

[0028] Step 2: If Figure 1 - (b), epitaxy is performed on an N-type substrate wafer (01) to form a lightly doped N-type epitaxial layer (02);

[0029] Step 3: If Figure 1 - (c), ion implantation is performed on the N-type epitaxy (02) and annealing is performed to form a P-type buried layer (03);

[0030] Step 4: If Figure 1 - (d) shows that a thin N-type drift region (05) is formed by epitaxy;

[0031] Step 5: If Figure 1 -(e), ion implantation is performed on the N-type drift region (05) and annealing is performed to form a P-type well region (04);

[0032] Step 6: If Figure 1 -(f) shows that the active region and electrodes of the device are fabricated using conventional process methods.

[0033] Example 2

[0034] This embodiment provides a SiC LDMOS structure manufactured based on the method of Embodiment 1, as shown in FIG. 2( a ):

[0035] The invention comprises an N-type substrate wafer (01), an N-type epitaxial layer (02), a P-type buried layer (03), a P-type well region (04), an N-type drift region (05), a source P+ (06), a source N+ (07), a drain N+ (08), a source (09), a gate oxide (10), a gate (11), a drain (12) and a substrate electrode (13). The N-type epitaxy (02) is arranged above the N-type substrate wafer (01); the P-type buried layer (03) is arranged at the top of the inside of the N-type epitaxy (02), and its left side is connected to the left boundary of the device, and its right side is at a distance from the right boundary of the device; the P-type well region (04) and the N-type drift region (05) are arranged side by side above the N-type epitaxy (02), wherein the P-type well region (04) is on the left and the N-type drift region (05) is on the right; the source electrode P+ (06) is arranged at the top of the inside of the P-type well region (04), and its left side is connected to the left boundary of the device; the source electrode N+ (07) is arranged at the top of the inside of the P-type well region (04), and its left side is connected to the source electrode P+ (06); the drain electrode N+ (08) is arranged The gate electrode (11) is arranged above the gate oxide (10); the drain electrode (12) is arranged above the drain electrode N+ (08); and the substrate electrode (13) is arranged below the N-type substrate wafer (01). When the device is working, the drain (12) and the substrate electrode (13) are connected to the high voltage end, and the P-type buried layer (03) and the P-type well region (04) are connected to the source (09) and then grounded.

[0036] In this embodiment, the N-type substrate wafer (01), the N-type epitaxy (02) and the P-type buried layer (03) achieved by ion implantation all have relatively high quality.

[0037] Comparative Example 1

[0038] FIG2( b ) shows a SiC LDMOS fabricated using a conventional process;

[0039] The device comprises a P-type well region (04), an N-type drift region (05), a source electrode P+ (06), a source electrode N+ (07), a drain electrode N+ (08), a source electrode (09), a gate oxide (10), a gate electrode (11), a drain electrode (12), a substrate electrode (13), a P-type substrate wafer (14) and a P-type buffer layer (15). The P-type buffer layer (15) is arranged above the P-type substrate wafer (14); the P-type well region (04) and the N-type drift region (05) are arranged side by side above the P-type buffer layer (15), wherein the P-type well region (04) is on the left and the N-type drift region (05) is on the right; the substrate electrode (13) is arranged below the P-type substrate wafer (14); and the remaining structures are similar to those in FIG. 2(a). When the device is working, the P-type substrate wafer (14) is grounded through the substrate electrode (13), thereby preventing the electrons in the drift region from flowing to the substrate electrode.

[0040] In this comparative example, the P-type substrate wafer (14) has problems such as aluminum source depletion, difficulty in controlling a single crystal form and doping concentration during wafer growth and subsequent device manufacturing, showing lower quality and higher resistivity, and increasing parasitic effects.

[0041] Comparative Example 2

[0042] FIG2( c ) shows another SiC LDMOS fabricated using a conventional process method;

[0043] The invention comprises an N-type substrate wafer (01), an N-type epitaxial (02), a P-type well region (04), an N-type drift region (05), a source P+ (06), a source N+ (07), a drain N+ (08), a source (09), a gate oxide (10), a gate (11), a drain (12), a substrate electrode (13) and a P-type epitaxial (16). The P-type epitaxial (16) is arranged above the N-type epitaxial (02); the P-type well region (04) and the N-type drift region (05) are arranged side by side above the P-type epitaxial (16), wherein the P-type well region (04) is on the left and the N-type drift region (05) is on the right; the rest of the structure is similar to FIG2(a).

[0044] In this comparative example, the P-type epitaxial (16) is similar to the P-type substrate wafer (14), and also has quality problems. At the same time, the P-type epitaxial (16) produced by the epitaxial process cannot be patterned and it is difficult to achieve lateral variable doping, which limits the improvement of device performance and the realization of more functions.

[0045] Example 3

[0046] This embodiment provides another SiC LDMOS with a P-type top layer manufactured based on the method of Embodiment 1, such as Figure 3 As shown:

[0047] The invention comprises an N-type substrate wafer (01), an N-type epitaxial layer (02), a P-type buried layer (03), a P-type well region (04), an N-type drift region (05), a source P+ (06), a source N+ (07), a drain N+ (08), a source (09), a gate oxide (10), a gate (11), a drain (12), a substrate electrode (13) and a P-type top region (17). The P-type top region (17) is arranged at the top of the inside of the N-type drift region (05); the rest of the structure is similar to FIG2(a).

[0048] In this embodiment, the P-type top region (17) is realized by ion implantation process and has high quality. When the device is working, the P-type top region (17) further depletes the N-type drift region (05), forming a double RESURF effect, thereby optimizing the device performance.

[0049] Example 4

[0050] This embodiment provides another SiCLDMOS with a lateral variable doping P-type buried layer manufactured based on the method of Embodiment 1, such as Figure 4 As shown:

[0051] The invention comprises an N-type substrate wafer (01), an N-type epitaxial (02), a P-type well region (04), an N-type drift region (05), a source P+ (06), a source N+ (07), a drain N+ (08), a source (09), a gate oxide (10), a gate (11), a drain (12), a substrate electrode (13), a P-type top region (17) and a lateral variable doping P-type buried layer (18). The lateral variable doping P-type buried layer (18) is arranged at the top of the inside of the N-type epitaxial (02), and its left side is connected to the left boundary of the device; the rest of the structure is the same as Figure 3 resemblance.

[0052] In this embodiment, the laterally doped P-type buried layer (18) is ion implanted using a mask with a cross-finger design, achieving a concentration gradually decreasing from left to right, more effectively modulating the surface electric field distribution, and optimizing device performance.

[0053] Example 5

[0054] This embodiment provides another SiC LDMOS with a P-type buried layer I manufactured based on the method of Embodiment 1, such as Figure 5 As shown:

[0055] The invention comprises an N-type substrate wafer (01), an N-type epitaxial layer (02), a P-type buried layer (03), a P-type well region (04), a source P+ (06), a source N+ (07), a drain N+ (08), a source (09), a gate oxide (10), a gate (11), a drain (12), a substrate electrode (13), a P-type buried layer I (19), an N-type drift region I (20) and an N-type drift region II (21). The P-type well region (04) is arranged above the N-type epitaxy (02), and its left side is connected to the left boundary of the device; the N-type drift region I (20) is arranged above the N-type epitaxy (02), and its left side is connected to the P-type well region (04), and its right side is connected to the right boundary of the device; the P-type buried layer I (19) is arranged at the top of the inside of the N-type drift region I (20); the N-type drift region II (21) is arranged above the N-type drift region I (20), and its left side is connected to the P-type well region (04), and its right side is connected to the right boundary of the device, and its upper boundary is connected to the upper boundary of the P-type well region (04); the remaining structure is similar to FIG. 2(a).

[0056] In this embodiment, the P-type buried layer I (19) is realized by ion implantation process and has high quality. When the device is working, the P-type buried layer I (19) further depletes the N-type drift region I (20) and the N-type drift region II (21), forming a Triple RESURF effect, thereby optimizing the device performance.

[0057] Example 6

[0058] This embodiment provides another integrated high-side and low-side SiC NMOS manufactured based on the method of Embodiment 1, such as Figure 6 As shown:

[0059] The invention comprises an N-type substrate wafer (01), an N-type epitaxial layer (02), a P-type buried layer II (22), a P-type buried layer III (23), an N-type drift region III (24), a P-type well region I (25), an N-type well region (26), an N-type drift region IV (27), a P-type well region II (28), a P-type top region I (29), a P-type top region II (30), a low-side drain region N+ (31), a low-side source region N+ (32), a low-side source region P+ (33), a high-side drain region N+ (34), a high-side source region N+ (35), a high-side source region P+ (36), a low-side drain (37), a low-side gate oxide (38), a low-side gate (39), a low-side source (40), a high-side drain (41), a high-side gate oxide (42), a high-side gate (43) and a high-side source (44). The N-type epitaxy (02) is arranged above the N-type substrate wafer (01); the P-type buried layer II (22) is arranged at the top of the N-type epitaxy (02); the P-type buried layer III (23) is arranged at the top of the N-type epitaxy (02), and its left side is separated from the P-type buried layer II (22) by an N-type well region (26), and its right side is connected to the right boundary of the device; the N-type drift region III (24), the P-type well region I (25), the N-type well region (26) and the P-type well region II (28) are arranged side by side from left to right. The N-type epitaxial region (02) is disposed above the N-type epitaxial region (02), and the left side of the N-type drift region III (24) is connected to the left boundary of the device, and the right side of the P-type well region I (25) is connected to the right boundary of the P-type buried layer II (22), and the left side of the P-type well region II (28) is connected to the left boundary of the P-type buried layer III (23), and the right side of the P-type well region II (28) is connected to the right boundary of the device; the N-type drift region IV (27) is disposed inside the P-type well region II (28); the P-type top region I (29) is disposed at the top of the inside of the N-type drift region III (24); the P-type top region II ( The low side drain region N+ (31) is arranged at the top of the N type drift region III (24), and its left side is connected to the left edge of the device; the low side source region N+ (32) is arranged at the top of the P type well region I (25), and its right side is connected to the low side source region P+ (33); the low side source region P+ (33) is arranged at the top of the P type well region I (25), and its right side is connected to the right edge of the P type well region I (25); the high side drain region N+ (34) is arranged at the top of the N type drift region III (24), and its left side is connected to the left edge of the device; the low side source region N+ (32 ... ) is arranged at the top of the N-type drift region IV (27), and its left side is connected to the left boundary of the N-type drift region IV (27), and its right side is connected to the P-type top region II (30); the high-side source region N+ (35) is arranged at the top of the P-type well region II (28), and its right side is connected to the high-side source region P+ (36); the high-side source region P+ (36) is arranged at the top of the P-type well region II (28), and its right side is connected to the right boundary of the device; the low-side drain (37) is arranged above the low-side drain region N+ (31);The low-side gate oxide (38) is arranged above the N-type drift region III (24), the P-type well region I (25) and the low-side source region N+ (32), and it completely covers the P-type well region I (25), and it partially covers the N-type drift region III (24) and the low-side source region N+ (32); the low-side gate (39) is arranged above the low-side gate oxide (38); the low-side source (40) is arranged above the low-side source region N+ (32) and the low-side source region P+ (33), and it partially covers the low-side source region N+ (32) and the low-side source region P+ (33); the high-side drain (41) is arranged above the high-side drain region N+ (34); The high-side gate oxide (42) is arranged above the N-type drift region IV (27), the P-type well region II (28) and the high-side source region N+ (35), and it completely covers the P-type well region II (28), and it partially covers the N-type drift region IV (27) and the high-side source region N+ (35); the high-side gate (43) is arranged above the high-side gate oxide (42); the high-side source (44) is arranged above the high-side source region N+ (35) and the high-side source region P+ (36), and it partially covers the high-side source region N+ (35) and the high-side source region P+ (36); the substrate electrode (13) is arranged below the N-type substrate wafer (01). ;

[0060] In this embodiment, the P-type buried layer II (22) and the P-type buried layer III (23) and the P-type top region I (29) and the P-type top region II (30) are realized by ion implantation process and have high quality. When the device is working, the low-side gate (39) is connected to the input end, the high-side gate (43) is connected to the input end through the high-voltage level shift circuit, and the low-side source (40) and the high-side drain (41) are short-circuited as the output end. This integrated high-low side SiC NMOS is conducive to the manufacture of high-performance SiC power integrated circuits.

[0061] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A process for realizing a SiC lateral voltage-resistant structure without relying on a P-type substrate wafer or using a P-type epitaxial process, comprising the following steps: Step 1: Prepare a heavily doped N-type substrate wafer (01); Step 2: performing N-type epitaxy on the N-type substrate wafer (01) to form a lightly doped N-type epitaxy (02), wherein the N-type epitaxy (02) is located above the N-type substrate wafer (01); Step 3: Locally implanting P-type ions on the N-type epitaxial layer (02), and forming a P-type buried layer (03) after annealing. The P-type buried layer (03) is located at the top of the N-type epitaxial layer (02), and its left side is connected to the left boundary of the device, and its lower side and right side are both wrapped by the N-type epitaxial layer (02); Step 4: performing N-type epitaxy on the N-type epitaxy (02) and the P-type buried layer (03) to form an N-type drift region (05), wherein the N-type drift region (05) is located above the N-type epitaxy (02) and the P-type buried layer (03); Step 5: Locally implanting P-type ions on the N-type drift region (05), and forming a P-type well region (04) after annealing. The P-type well region (04) is located at the top of the N-type drift region (05), and its left side is connected to the left boundary of the device, its lower side is connected to the P-type buried layer (03), and its right side does not exceed the right boundary of the P-type buried layer (03); Finally, conventional process methods are used to complete the production of the remaining active areas and electrodes in the device.

2. The process for realizing a SiC lateral pressure-resistant structure without relying on a P-type substrate wafer or using a P-type epitaxial process according to claim 1, characterized in that Add the sixth step: Step 6: Locally implanting P-type ions on the N-type drift region (05), and forming a P-type top region (17) after annealing. The P-type top region (17) is located at the top of the N-type drift region (05) and to the right of the P-type well region (04). The left side, the bottom side, and the right side of the P-type top region (17) are all wrapped by the N-type drift region (05). Finally, conventional process methods are used to complete the production of the remaining active areas and electrodes in the device.

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