Complementary field effect transistor, manufacturing method thereof and static random access memory
By designing an overlapping memory electrode structure in the complementary field effect transistor, the problem of insufficient area of static random access memory memory is solved, and the length of memory cells is achieved, which is reduced by 156nm, and further through the back interconnect structure Optimized to 136nm.
Patent Information
- Application Number
- CN202411296314.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-20
AI Technical Summary
The memory cell area of existing static random access memory still has room for improvement, especially below the 3-nanometer node. Traditional three-gate or double-gate fin field effect transistors are limited and cannot be further reduced.
By designing the projected portions of the second storage electrode and the first storage electrode overlap in the complementary field effect transistor, the wiring space is reduced, thereby reducing the memory cell area of the static random access memory. The specific method includes forming an alternately stacked semiconductor layer structure on one side of the substrate, etching to form a fin structure, and forming overlapping storage electrodes on the gate of the fin structure.
The memory cell length of the static random access memory is reduced from 240 nm to 156 nm, further reducing the area of the memory cell, and further optimizing the back double-layer local interconnect structure to achieve a memory cell length of 136 nm.
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Figure CN119170571A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a complementary field effect transistor and a manufacturing method thereof, and a static random access memory. Background Art
[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. The traditional three-gate or double-gate Fin Field-Effect Transistor (FinFET) is limited to nodes below 3 nanometers (nm). Nanosheet-Gate all round Fin Field-Effect Transistor (Nanosheet-GAAFET) has been developed that is not limited by the 3nm node. Furthermore, the Complementary Field-Effect Transistor (CFET) has received widespread attention and research because it has broken through the 1nm node limitation.
[0003] Currently, complementary field effect transistors can be used to form static random access memory (SRAM) memory cells, thereby significantly reducing the area of the static random access memory. Figure 1 FIG. 1 is a schematic diagram of a circuit of a storage unit of a static random access memory, referring to FIG. Figure 2 and Figure 3 The following are the structural layouts corresponding to the memory cells of two types of static random access memory. That is to say, by adjusting the design of the memory cell from planar transistors to complementary field effect transistors, the length of the memory cell is shortened from 240nm to 156nm, which has greatly reduced the area of the memory cell of the static random access memory.
[0004] However, there is currently a demand for a smaller storage unit area of a static random access memory. Summary of the invention
[0005] In view of this, the purpose of the present application is to provide a complementary field effect transistor and a manufacturing method thereof, and a static random access memory, which can reduce the wiring space by partially overlapping the projections of the second storage electrode and the first storage electrode, thereby reducing the area of the storage unit of the static random access memory.
[0006] The present application provides a method for manufacturing a complementary field effect transistor, the method comprising:
[0007] Providing a substrate, forming a plurality of stacked structures consisting of alternately stacked first semiconductor layers and second semiconductor layers on one side of the substrate, wherein the stacked structures include a buffer layer located in a middle region along a direction perpendicular to a plane where the substrate is located;
[0008] Etching the stacked structure and a partially thick substrate to form a fin structure, wherein the fin structure includes a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure are separated by the buffer layer, and the fin structure includes a first fin structure and a second fin structure;
[0009] Etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, wherein the top source region and the top drain region are located between the top channel region and the bottom drain region are located between the bottom source region and the bottom drain region; forming inner sidewalls on the sidewalls of the top structure and the sidewalls of the bottom structure;
[0010] forming a bottom source and a bottom drain in the bottom source region and the bottom drain region; forming a top source and a top drain on the bottom source and the bottom drain;
[0011] The first semiconductor layer in the top channel region and the bottom channel region is removed, a plurality of gaps to be filled are formed between the second semiconductor layers, a gate is filled in the plurality of gaps to be filled, the gate surrounds the second semiconductor layer, and a stack of the plurality of second semiconductor layers forms a top channel structure and a bottom channel structure respectively;
[0012] A first storage electrode is formed on the gate of the first fin structure, and a second storage electrode is formed on the gate of the second fin structure, wherein the second storage electrode and the first storage electrode overlap in their projections on a plane perpendicular to the substrate.
[0013] Optionally, the second storage electrode includes a top overlapping electrode, a first connecting electrode and a second storage surrounding electrode;
[0014] The forming of a second storage electrode on the gate of the second fin structure comprises:
[0015] forming a second storage surrounding electrode on the gate of the second fin structure;
[0016] A first connection electrode and a top overlapping electrode are formed, wherein the first connection electrode is electrically connected to the second storage surrounding electrode and the top overlapping electrode, and the top overlapping electrode and the first storage electrode overlap in their projection portions on a plane perpendicular to the substrate.
[0017] Optionally, before forming a first storage electrode on the gate of the first fin structure and forming a second storage electrode on the gate of the second fin structure, the method further includes:
[0018] forming a third dielectric layer on the gate of the first fin structure and the gate of the second fin structure;
[0019] Etching the third dielectric layer on both sides of the top structure to form a second groove, wherein the second groove exposes the gate of the first fin structure and the gate of the second fin structure;
[0020] The forming of a first storage electrode on the gate of the first fin structure and a second storage surrounding electrode on the gate of the second fin structure comprises:
[0021] forming a first storage electrode on the gate of the first fin structure exposed by the second groove, and forming a second storage surrounding electrode on the gate of the second fin structure exposed by the second groove;
[0022] Before forming the first connection electrode and the top overlapping electrode, the method further includes:
[0023] forming a fourth dielectric layer, wherein the fourth dielectric layer covers the first storage electrode and the second storage electrode;
[0024] The forming of the first connecting electrode and the top overlapping electrode, wherein the first connecting electrode is electrically connected to the second storage surrounding electrode and the top overlapping electrode, comprises:
[0025] Etching the fourth dielectric layer to form a connecting through hole;
[0026] forming a first connection electrode in the connection through hole;
[0027] A top overlapping electrode is formed on the surface of the fourth dielectric layer, and the top overlapping electrode is electrically connected to the first connecting electrode.
[0028] Optionally, forming an inner side wall on a side wall of the top structure and a side wall of the bottom structure comprises:
[0029] Etching and removing a portion of the first semiconductor layer on the sidewalls of the top structure and the sidewalls of the bottom structure, and etching and removing the buffer layer, to form a concave structure and a buffer isolation structure, respectively;
[0030] An inner sidewall is formed in the concave structure, and an isolation layer is formed in the buffer isolation structure.
[0031] Optionally, the method further comprises:
[0032] The substrate is etched to form a back power connection layer, a back ground connection layer, a back bit line connection layer and a back word line connection layer.
[0033] The present application provides a complementary field effect transistor, the complementary field effect transistor comprising:
[0034] substrate;
[0035] A first top source, a first top drain, a first top channel structure, a first bottom source, a first bottom drain, a first bottom channel structure, a second top source, a second top drain, a second top channel structure, a second bottom source, a second bottom drain and a second bottom channel structure are disposed on one side of the substrate, wherein the first top channel structure, the second top channel structure, the first bottom channel structure and the second bottom channel structure include a stack formed by a plurality of nanosheets;
[0036] a first gate and a second gate, the first gate surrounding the nanosheets of the first top structure and the first bottom structure, the second gate surrounding the nanosheets of the second top structure and the second bottom structure;
[0037] A first storage electrode is formed on the first gate, and a second storage electrode is formed on the second gate. The second storage electrode and the first storage electrode overlap in their projections on a plane perpendicular to the substrate.
[0038] Optionally, the second storage electrode includes a top overlapping electrode, a first connecting electrode and a second storage surrounding electrode;
[0039] The second storage surrounding electrode surrounds the second gate;
[0040] The first connection electrode electrically connects the top overlapping electrode and the second storage surrounding electrode;
[0041] The top overlapping electrode and the first storage electrode partially overlap in their projections on a plane perpendicular to the substrate.
[0042] Optionally, an isolation layer is provided between the top channel structure and the bottom channel structure.
[0043] Optionally, a target sidewall is provided on a sidewall of the isolation layer.
[0044] The present application provides a static random access memory, comprising a plurality of storage units, wherein the storage units include any one of the complementary field effect transistors described above.
[0045] The present application provides a method for manufacturing a complementary field effect transistor, the method comprising: providing a substrate, forming a plurality of stacked structures alternately stacked by a first semiconductor layer and a second semiconductor layer on one side of the substrate, and the stacked structure includes a buffer layer located in the middle region along a direction perpendicular to the plane where the substrate is located. Etching the stacked structure and a substrate with a partial thickness to form a fin structure, the fin structure includes a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure are separated by a buffer layer, and the fin structure includes a first fin structure and a second fin structure. Etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, the top source region and the top drain region are between the top channel region, the bottom source region and the bottom drain region are between the bottom channel region, and an inner sidewall is formed on the sidewall of the top structure and the sidewall of the bottom structure. A bottom source and a bottom drain are formed in the bottom source region and the bottom drain region, and a top source and a top drain are formed on the bottom source and the bottom drain. The first semiconductor layer in the top channel region and the bottom channel region is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers. The gate is filled in the plurality of gaps to be filled, and the gate surrounds the second semiconductor layer. The stack formed by the plurality of second semiconductor layers forms a top channel structure and a bottom channel structure, respectively. A first storage electrode is formed on the gate of the first fin structure, and a second storage electrode is formed on the gate of the second fin structure. The second storage electrode and the first storage electrode overlap in their projections on a plane perpendicular to the substrate. It can be seen that the present application reduces the wiring space by setting the second storage electrode and the first storage electrode to a structure in which the projections overlap, thereby reducing the area of the storage unit of the static random access memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0047] Figure 1 A circuit diagram of a storage unit of a static random access memory is shown;
[0048] Figure 2 A structural layout corresponding to a storage unit of a static random access memory is shown;
[0049] Figure 3 Another structural layout corresponding to a storage unit of a static random access memory is shown;
[0050] Figure 4A schematic flow chart of a method for manufacturing a complementary field effect transistor provided in an embodiment of the present application is shown;
[0051] Figure 5 The structure layout corresponding to a storage unit of a static random access memory provided by an embodiment of the present application is shown;
[0052] Figure 6 Shows Figure 5 A top-level schematic diagram of the provided structural layout;
[0053] Figure 7 Shows Figure 5 The underlying schematic diagram of the provided structural layout;
[0054] Figure 8 A schematic diagram of a three-dimensional structure of a complementary field effect transistor provided in an embodiment of the present application is shown;
[0055] Figure 9-Figure 3 9 shows a schematic structural diagram of a complementary field effect transistor manufactured according to the method for manufacturing a complementary field effect transistor provided in an embodiment of the present application;
[0056] Fig.40 The structure layout corresponding to a storage unit of a static random access memory provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0057] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0058] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.
[0059] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.
[0060] refer to Figure 1, which is a circuit diagram of a storage unit of a static random access memory. The storage unit of SRAM is called a byte (bit), which can only store a signal 0 or 1. Such a bit is composed of 6 transistors, which are divided into 2 P-type metal oxide semiconductor field effect transistors (P Metal-Oxide-Semiconductor Field-Effect Transistor, PMOS) and 4 N-type metal oxide semiconductor field effect transistors (N Metal-Oxide-Semiconductor Field-Effect Transistor, NMOS), among which PMOS is Figure 1 PU1 and PU2 in the NMOS are Figure 1 PD1, PD2, AC1 and AC2, Q and QB represent storage bits, Figure 1 VDD represents the power supply terminal, VSS represents the ground terminal, WL represents the word line, and BL represents the bit line.
[0061] refer to Figure 2 and Figure 3 As shown, the structural layout corresponding to the storage units of two types of static random access memories. Figure 2 The middle one is a planar transistor with only one-tier structure. Figure 3 The two-tier structure is a complementary field effect transistor, with NMOS (Top-tier: NMOS) on the top layer and PMOS (Bottom-tier: PMOS) on the bottom layer. In other words, by adjusting the design of the memory cell from a planar transistor to a complementary field effect transistor, the length of the memory cell has been shortened from 240nm to 156nm, which has greatly reduced the area of the memory cell of the static random access memory.
[0062] However, there is currently a demand for a smaller storage unit area of a static random access memory.
[0063] Based on this, the present application provides a method for manufacturing a complementary field effect transistor, the method comprising: providing a substrate, forming a plurality of stacked structures alternately stacked by a first semiconductor layer and a second semiconductor layer on one side of the substrate, and the stacked structure includes a buffer layer located in the middle region along a direction perpendicular to the plane where the substrate is located. Etching the stacked structure and a substrate with a partial thickness to form a fin structure, the fin structure includes a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure are separated by a buffer layer, and the fin structure includes a first fin structure and a second fin structure. Etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, the top source region and the top drain region are between the top channel region, the bottom source region and the bottom drain region are between the bottom channel region, and an inner sidewall is formed on the sidewall of the top structure and the sidewall of the bottom structure. A bottom source and a bottom drain are formed in the bottom source region and the bottom drain region, and a top source and a top drain are formed on the bottom source and the bottom drain. The first semiconductor layer in the top channel region and the bottom channel region is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers. The gate is filled in the plurality of gaps to be filled, and the gate surrounds the second semiconductor layer. The stack formed by the plurality of second semiconductor layers forms a top channel structure and a bottom channel structure, respectively. A first storage electrode is formed on the gate of the first fin structure, and a second storage electrode is formed on the gate of the second fin structure. The second storage electrode and the first storage electrode overlap in their projections on a plane perpendicular to the substrate. It can be seen that the present application reduces the wiring space by setting the second storage electrode and the first storage electrode to a structure in which the projections overlap, thereby reducing the area of the storage unit of the static random access memory.
[0064] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
[0065] See also Figure 4 , which is a schematic flow chart of a method for manufacturing a complementary field effect transistor provided in an embodiment of the present application.
[0066] The present application embodiment is according to Figure 5 The structure layout corresponding to the storage unit of the static random access memory shown is used to manufacture complementary field effect transistors, Figure 5 The structure of the storage cell in the example consists of two layers, the top layer is NMOS, and the reference Figure 6 As shown, the bottom layer is PMOS, reference Figure 7 shown. Figure 5 The memory cell in the system also has a backside electrical lead-out structure designed to reduce wiring space. The structural layout of the backside electrical lead-out structure is shown in Figure 1. Figure 8 shown.
[0067] Fig. 9 Shown is a three-dimensional structural schematic diagram of a complementary field effect transistor provided in an embodiment of the present application. By performing cross-sections on the three-dimensional structural schematic diagram in the XX', YY', Y1-Y1', Y2-Y2' and Y3-Y3' directions, cross-sectional structural schematic diagrams of complementary field effect transistors of A, B, C, D and E are obtained respectively. Fig.32B and Fig.39C is the cross section in the Y2-Y2' direction corresponding to D, Fig.38B and Fig.39B is the cross section in the Y1-Y1' direction corresponding to C, Fig.31B , Fig.32C , Fig.33A , Fig.34A , Fig.35A , Fig.36A and Fig.39D It is the cross section in the Y3-Y3' direction corresponding to E.
[0068] The method for manufacturing a complementary field effect transistor provided in the embodiment of the present application comprises the following steps:
[0069] S101, providing a substrate, forming a stacked structure consisting of a first semiconductor layer and a second semiconductor layer alternately stacked on one side of the substrate, wherein the stacked structure includes a buffer layer located in a middle region along a direction perpendicular to a plane where the substrate is located, and referring to Fig. 10A and Fig. 10B shown.
[0070] In an embodiment of the present application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, and the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.
[0071] As an example, impurities may be injected into the bulk silicon substrate, and a highly doped well region may be formed after annealing to achieve the desired well depth. For different device types, the doping type of the substrate 110 is different, wherein for a P-type semiconductor device, the highly doped well region is an N-well, and the injected impurities are n-type impurity ions, such as phosphorus (P) ions, wherein for an N-type semiconductor device, the highly doped well region is a p-well, and the injected impurities are p-type impurity ions, such as boron (B) ions.
[0072] In the embodiment of the present application, a stacked structure in which the first semiconductor layer 121 and the second semiconductor layer 122 are alternately stacked may be formed on one side of the substrate 110. Fig. 10A and Fig. 10B shown.
[0073] Specifically, for different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be the same, for example, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon or germanium. For different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be different, for example, for a P-type semiconductor device, the material of the first semiconductor layer 121 may be silicon, and the material of the second semiconductor layer 122 may be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon.
[0074] Considering that the stacked structure can be used to form two transistors with different doping types stacked up and down, when the material is silicon, silicon of different doping types can also be used. For example, the material of the second semiconductor layer 122 located at the top is P-type doped silicon, and the material of the second semiconductor layer 122 located at the bottom can be N-type doped silicon.
[0075] Along the direction perpendicular to the plane where the substrate 110 is located, the stacked structure includes a buffer layer 123 located in the middle region, and the buffer layer 123 is used to separate two transistors of different doping types stacked up and down to be formed later. The material of the buffer layer 123 can be the same as that of the first semiconductor layer 121, and the first semiconductor layer 121 is formed on both sides of the surface of the buffer layer 123.
[0076] As a possible implementation, along the direction perpendicular to the plane where the substrate 110 is located, if the material of the first semiconductor layer 121 is silicon germanium, the proportion of Ge in the first semiconductor layer 121 in the stacked structure gradually increases and then decreases, wherein the proportion of Ge in the buffer layer 123 is the highest. As an example, the proportion of Ge increases from 30% to 60% and then decreases to 30%.
[0077] In practical applications, silicon oxide may be formed on the substrate 110 . The stacked structure may be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.
[0078] S102, etching the stacked structure and a partial thickness of the substrate to form a fin structure, the fin structure includes a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure are separated by a buffer layer, and an embedded power line is formed between the two substrate structures, referring to Fig.11A and FIG. 11B to FIG. 13A and Fig. 13B shown.
[0079] In the embodiment of the present application, the stacked structure and the partially thick substrate 100 may be etched to form two fin structures, namely a first fin structure 910 and a second fin structure 920, both of which include a top structure 510, a bottom structure 520 and a substrate structure 530, wherein the top structure 510 and the bottom structure 520 are separated by a buffer layer 123. The process flow of forming the fin structure is specifically described below.
[0080] S1021, sidewall transfer process, reference Fig.11A and Fig. 11B shown.
[0081] In an embodiment of the present application, a self-aligned sidewall transfer process is used to form a first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is: a sacrificial layer 202 is covered on the stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Photolithography is used to perform patterning and etching of part of the sacrificial layer 202, and silicon nitride material is deposited. Anisotropic etching is then used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure is retained. The first sidewall 201 acts as a hard mask in the subsequent photolithography for forming the fin.
[0082] S1022, forming a fin structure, reference Fig. 12A and Fig. 12B shown.
[0083] In the embodiment of the present application, the stacked structure and a partial thickness of the substrate can be etched by an etching process to form a plurality of periodically distributed fins, as shown in FIG. Fig. 12A and Fig. 12B As shown. The first sidewall 201 is used as a mask for etching to form a fin with a stacked structure. The top of the fin is a top structure 510 and a bottom structure 520 formed by the stacked structure. The top structure 510 and the bottom structure 520 are separated by a buffer layer 123. The top structure 510 and the bottom structure 520 are channel regions. The bottom of the fin is a substrate 110, forming a fin as shown in FIG. Fig. 12B The fin shown in FIG. The fin includes not only a stacked structure but also a single crystal silicon structure that penetrates into the substrate 110. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin structure will be used to form a nanosheet of a complementary field effect transistor. Although Fig. 12B While two fins are shown, it should be understood that any suitable number and configuration of fins may be used in practical applications.
[0084] In practical applications, after the fin structure is formed, the first sidewall 201 may be removed.
[0085] S1023, forming shallow trench isolation 203 (STI), reference Fig.13A and Fig. 13B shown.
[0086] In an embodiment of the present application, a shallow trench isolation 203 may be formed between different fins. Specifically, a dielectric material may be deposited and a selective back etching process may be performed to expose the three-dimensional fins, specifically exposing the top structure 510 and the bottom structure 520, thereby forming a shallow trench isolation 203 adjacent to the fin structure. The surface of the shallow trench isolation 203 on one side away from the substrate 110 may be flush with the surface of the side of the stacked structure in the fin structure close to the substrate 110, or may be higher or lower than the surface. The shallow trench isolation 203 may be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fin structures.
[0087] S103, etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, the top source region and the top drain region are between the top channel region, the bottom source region and the bottom drain region are between the bottom channel region, and inner sidewalls are formed on the sidewalls of the top structure and the sidewalls of the bottom structure, referring to Fig.14A and FIG. 14B to FIG. 17A and Fig. 17B shown.
[0088] In the embodiments of the present application, considering that two transistors of different doping types need to be stacked up and down subsequently, the source and drain of the two transistors need to be formed separately. First, the source and drain regions of the two transistors need to be formed, and then the inner sidewalls need to be formed. The specific process is described in detail below.
[0089] S1031, forming a dummy gate 204 and a second spacer 205, referring to Fig.14A and Fig. 14B shown.
[0090] In an embodiment of the present application, a dummy gate stack is formed on the exposed fin structure and in a direction perpendicular to the fin line, i.e., in the XX direction. The dummy gate stack is a multi-layer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204 and a hard mask layer (not shown). The dummy gate stack can be formed by processes such as thermal oxidation, chemical vapor deposition, and sputtering. The dummy gate stack spans the stacked structure on the upper part of the fin structure, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polysilicon or amorphous silicon. The material of the hard mask layer can be oxide, carbide, organic matter, etc.
[0091] In the embodiment of the present application, second spacers 205 can be respectively provided on both sides of the dummy gate stack along the fin line direction, i.e., the YY direction, and the second spacers 205 on both sides have the same thickness. The material of the second spacers 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.
[0092] S1032, etching the top structure 510, the buffer layer 123 and the bottom structure 520 to form a top source region 1101, a top drain region 1102, a bottom source region 1201 and a bottom drain region 1202, refer to Fig.15A shown.
[0093] In the embodiment of the present application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process, specifically, the top structure 510, the buffer layer 123 and the bottom structure 520 are etched to form a top source region 1101, a top drain region 1102, a bottom source region 1201 and a bottom drain region 1202, a top channel region 1103 is between the top source region 1101 and the top drain region 1102, and a bottom channel region 1203 is between the bottom source region 1201 and the bottom drain region 1202. Among them, the top source region 1101, the top drain region 1102, the bottom source region 1201 and the bottom drain region 1202 no longer have a stacked structure after being etched, refer to Fig.15A shown.
[0094] S1033, forming a concave structure, reference Fig.16A and Fig. 16B shown.
[0095] In the embodiment of the present application, the first semiconductor layer 121 located in the top structure 510 and the bottom structure 520 is selectively etched along the YY direction, that is, the first semiconductor layer 121 of the sidewall of the top structure 510 and the sidewall of the bottom structure 520 is etched away, and the second semiconductor layer 122 is not damaged. The first semiconductor layer 121 forms a concave structure along the YY direction compared to the missing part of the second semiconductor layer 122. That is, pull-back etching is performed to etch away part of the first semiconductor layer 121 from the bottom source region 1201 and the bottom drain region 1202 to the bottom channel region 1203, and etch away part from the top source region 1101 and the top drain region 1102 to the top channel region 1103. Fig.16A and Fig. 16B shown.
[0096] While the first semiconductor layer 121 in the top structure 510 and the bottom structure 520 is selectively etched, the buffer layer 123 is also etched away to form a buffer isolation structure. Fig.16A and Fig. 16B shown.
[0097] S1034, forming inner wall 206, reference Fig.17A and Fig. 17B shown.
[0098] In the embodiment of the present application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the bottom structure 520 located in the bottom channel region 1203 and the top structure 510 in the top channel region 1103, i.e., the periphery of the fin, and the dielectric material is etched to form an inner sidewall 206, and the inner sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane where the substrate 110 is located. In other words, the concave structure caused by etching S1033 is filled by the inner sidewall 206, and the material of the inner sidewall 206 can be silicon nitride or silicon oxide.
[0099] In addition to filling the concave structure, the dielectric material also fills the buffer isolation structure, thereby forming an isolation layer 200 .
[0100] S104, forming a bottom source and a bottom drain in the bottom source region and the bottom drain region, and forming a top source and a top drain on the bottom source and the bottom drain, referring to FIG. 18A to FIG. 23A shown.
[0101] In the embodiment of the present application, after etching the stacked structure to form the bottom source region 1201 and the bottom drain region 1202, a bottom source 131 and a bottom drain 132 may be formed in the bottom source region 1201 and the bottom drain region 1202, respectively. Fig.18A As shown. The side surface of the bottom source 131 and the bottom drain 132 away from the substrate 110 can be flush with the side surface of the isolation layer 200 close to the substrate 110. And a top source 133 and a top drain 134 are formed on the bottom source 131 and the bottom drain 132, referring to Fig.23A shown.
[0102] Specifically, for different types of semiconductor devices, the source material and the drain material may be different. For P-type semiconductor devices, the source and drain materials are boron-doped silicon germanium, i.e., SiGe:B; for N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.
[0103] Before forming the top source 133 and the top drain 134 , other processes are provided, which will be described in detail below.
[0104] S1041, forming a target sidewall 300, referring to Fig.19A shown.
[0105] In the embodiment of the present application, after forming the bottom source 131 and the bottom drain 132, a target sidewall 300 may be formed, and the target sidewall 300 covers the sidewall of the inner sidewall 206, that is, the target sidewall 300 is respectively arranged on both sides of the inner sidewall 206 along the fin line direction, that is, the YY direction, and the target sidewalls 300 on both sides have the same thickness. The material of the target sidewall 300 may be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.
[0106] S1042, forming a first dielectric layer 420, the first dielectric layer 420 covers the top structure 510 and the target sidewall 300, referring to Fig. 20A and Fig. 20B shown.
[0107] In the embodiment of the present application, after forming the target sidewall 300, a dielectric material may be deposited and a planarization process may be performed to form a first dielectric layer 420, the first dielectric layer 420 covering the top structure 510 and the target sidewall 300, as shown in FIG. Fig. 20A and Fig. 20B shown.
[0108] S1043, etching the first dielectric layer 420 to the side surface of the buffer layer 123 away from the substrate 110, refer to Fig.21A shown.
[0109] In an embodiment of the present application, after forming the first dielectric layer 420 , the first dielectric layer 420 can be etched back to a surface of the buffer layer 123 away from the substrate 110 , and the etched first dielectric layer 420 covers the bottom source 131 and the bottom drain 132 .
[0110] S1044, etching the target sidewall 300 to the side surface of the isolation layer 200 away from the substrate 110, refer to Fig.22A shown.
[0111] In the embodiment of the present application, after etching the first dielectric layer 420 , the target sidewall 300 may be further etched to the surface of the isolation layer 200 away from the substrate 110 , that is, the target sidewall 300 is only provided on the sidewall of the isolation layer 200 .
[0112] In the embodiment of the present application, a top source 133 and a top drain 134 may be formed on the first dielectric layer 420 so as to form a source and a drain of the transistor located at the upper part of the two transistors stacked up and down, referring to Fig.23A The top source 133 and the top drain 134 may be located on the first dielectric layer 420 .
[0113] Specifically, for different types of semiconductor devices, the source material and the drain material may be different. For P-type semiconductor devices, the source and drain materials are boron-doped silicon germanium, i.e., SiGe:B; for N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.
[0114] S105, removing the first semiconductor layer in the top channel region and the bottom channel region, forming a plurality of gaps to be filled between the second semiconductor layers, filling the plurality of gaps to be filled with gates, the gates surrounding the second semiconductor layers, and stacking the plurality of second semiconductor layers to form a top channel structure and a bottom channel structure, respectively, with reference to Fig.24A and FIG. 24B to FIG. 29A and Fig.29B shown.
[0115] In the embodiment of the present application, the first semiconductor layer 121 in the top channel region 1103 and the bottom channel region 1203 may be removed, that is, a nanosheet channel release process may be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, as shown in FIG. Fig.25A and Fig.25B Then, the gate 160 is filled in the plurality of gaps 402 to be filled, referring to Fig.29A and Fig.29B shown.
[0116] Specifically, the first semiconductor layer 121 in the stacked structure located in the top channel region 1103 and the bottom channel region 1203 can be selectively etched to release the nanosheet channel. In other words, the stacked structure exposed by the fin is processed to remove the first semiconductor layer 121 of each layer, which is a sacrificial layer, and release the nanosheet formed by the second semiconductor layer 122.
[0117] In the embodiments of the present application, there are several possible implementation methods for performing nanosheet channel release for different types of devices:
[0118] In a first possible implementation, for P-type and N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon germanium, and the silicon germanium is selectively removed, and the second semiconductor layer 122, i.e., silicon, is retained to form a silicon stack nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon germanium at a faster rate than silicon can be used.
[0119] In a second possible implementation, for a P-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon, and the silicon is selectively removed, and the second semiconductor layer 122, i.e., silicon germanium, is retained to form a silicon germanium stacked nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon germanium can be used.
[0120] In a third possible implementation, for an N-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon germanium, and the silicon germanium is selectively removed, and the second semiconductor layer 122, i.e., silicon, is retained to form a silicon stack nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon germanium at a faster rate than silicon can be used.
[0121] In the embodiment of the present application, before removing the first semiconductor layer 121 in the top channel region 1103 and the bottom channel region 1203 , the dummy gate 204 may be removed first. The specific process flow is as follows.
[0122] S1051, remove the false gate 204, refer to Fig.24A and Fig. 24B shown.
[0123] In the embodiment of the present application, a spacer layer 207 may be deposited on the surface of the dummy gate 204, the top source 133 and the top drain 134 to prevent the interconnection short circuit between the dummy gate 204 and the top source 133 or the top drain 1342 in the subsequent steps, and the spacer layer 207 may be subjected to a chemical mechanical polishing process to make it flat. Fig.24A and Fig. 24B As shown, the dummy gate 204 formed of the polysilicon or amorphous silicon is etched or corroded by a selective etching or corrosion process, that is, the dummy gate 204 is removed.
[0124] In the embodiment of the present application, after forming a plurality of gaps 402 to be filled, an interface layer may be formed on the surface of the second semiconductor layer 122 and the interface between the interface layer and the second semiconductor layer 122 may be passivated. Specifically, the material of the interface layer may be silicon oxide.
[0125] In the embodiment of the present application, after the interface layer is formed, a high-k dielectric layer may be formed on the surface of the interface layer, and the high-k dielectric layer surrounds the surface of the interface layer. Specifically, the material of the high-k dielectric layer may be HfO2, HfSiO x , HfON, HfSiON, HfAlOx, HfLaO x 、Al2O3、ZrO2、ZrSiO x , Ta2O5 or La2O3 or a combination of them.
[0126] Taking into account the formation of different types of transistors above and below, it is necessary to use isolation layers to isolate different types of transistors and different types of work function layers to realize different types of transistors. The specific process flow is introduced below.
[0127] S1052, forming a second type work function layer 710 in all the gaps 402 to be filled, referring to Fig.26A and Fig.26B shown.
[0128] In the embodiment of the present application, a second type work function layer 710 may be formed in all the gaps 402 to be filled, and the second type work function layer 710 surrounds the surface of the high-k dielectric layer. Specifically, the second type work function layer 710 is a P-type work function layer (P-WFL).
[0129] S1053, filling the gap 402 to be filled in the bottom structure 520 with a protective layer 730, refer to Fig.27A and Fig.27B shown.
[0130] In the embodiment of the present application, an isolation material may be deposited, and then the isolation material may be etched back to the position of the isolation gap 403 to form the protection layer 730. Specifically, the isolation material may be etched back to the position of 1 / 2 of the isolation gap 403. Fig.27A and Fig.27B As shown, the protection layer 730 fills the gap 402 to be filled in the bottom structure 520 .
[0131] S1054, removing the second type work function layer 710 in the gap 402 to be filled in the top structure 510, and forming a first type work function layer 720 in the gap 402 to be filled in the top structure 510, referring to Fig.28A and Fig.28B shown.
[0132] In the embodiment of the present application, the second type work function layer 710 in the gap 402 to be filled in the top structure 510 is removed by using the protective layer 730 as a mask, and the first type work function layer 720 is formed in the gap 402 to be filled in the top structure 510, so that the first type work function layer 720 is formed in the top structure 510, and the second type work function layer 710 is formed in the bottom structure 520. Specifically, the first type work function layer 720 is an N-type work function layer (N-WFL). The second type work function layer 710 in the gap 402 to be filled in the top structure 510 can be removed by an etching process.
[0133] S1055, remove the protective layer 730, refer to Fig.29A and Fig.29B shown.
[0134] In the embodiment of the present application, after the first type work function layer 720 and the second type work function layer 710 are formed, the protection layer 730 may be removed.
[0135] In practical applications, the protective layer 730 may be removed first, and then the first type work function layer 720 may be formed in all the gaps 402 to be filled. That is, the second type work function layer 710 may be formed first in the gaps 402 to be filled in the bottom structure 520, and then the first type work function layer 720 may be formed.
[0136] In the embodiment of the present application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple second semiconductor layers 122, and the gate 160 can be filled in the multiple gaps 402 to be filled. The gate 160 surrounds the second semiconductor layer 122 to form a ring gate structure. Specifically, the gate 160 surrounds the first type work function layer 720 and the second type work function layer 710. The stack composed of the multiple second semiconductor layers 122 forms a top channel structure and a bottom channel structure, that is, a nanosheet channel of a complementary field effect transistor is formed, refer to Fig. 30A and Fig. 30B shown.
[0137] In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the space after the spacer layer 207 and the dummy gate 204 are removed. The gate 160 covering the spacer layer 207 can be chemically mechanically polished for planarization.
[0138] S106, forming a first storage electrode on the gate of the first fin structure, forming a second storage electrode on the gate of the second fin structure, wherein the second storage electrode and the first storage electrode overlap in their projections on a plane perpendicular to the substrate, referring to Fig.31A and FIG. 31B to FIG. 36A shown.
[0139] In the embodiment of the present application, after the gate 160 is formed, a first storage electrode 360 may be formed on the gate 160 of the first fin structure 910, and a second storage electrode 370 may be formed on the gate 160 of the second fin structure 920, and the second storage electrode 370 and the first storage electrode 360 overlap in their projections on a plane perpendicular to the substrate 110. The specific formation process is described in detail below.
[0140] S1061 , forming a third dielectric layer 440 on the gate 160 of the first fin structure 910 and the gate 160 of the second fin structure 920 .
[0141] In an embodiment of the present application, after forming the gate 160, a dielectric material can be deposited and a planarization process can be performed to form a third dielectric layer 440, wherein the third dielectric layer 440 covers the gate 160 of the first fin structure 910 and the gate 160 of the second fin structure 920, wherein the third dielectric layer 440 also covers the top source 133 and the top drain 134.
[0142] S1062, etching the third dielectric layer 440 on both sides of the top structure 510 to form a second groove 620, the second groove 620 exposes the gate 160 of the first fin structure 910 and the gate 160 of the second fin structure 920, refer to Fig.31A and Fig.31B shown.
[0143] In the embodiment of the present application, after forming the third dielectric layer 440, the third dielectric layer 440 on both sides of the top structure 510 can be etched to the gate 160 of the first fin structure 910 and the gate 160 of the second fin structure 920 to form a second groove 620. Fig.31A As shown, the second groove 620 exposes the gate 160 of the first fin structure 910 and the gate 160 of the second fin structure 920. The second groove 620 also exposes the top source 133 and the top drain 134, referring to Fig.31B shown.
[0144] The second groove 620 also exposes the bottom drain 132. Fig. 30A The second groove 620 also exposes the bottom source 131 and the bottom drain 132, referring to Fig.31B shown.
[0145] Taking into account that there is a portion of overlapping projections between the second storage electrode 370 and the first storage electrode 360, in order to avoid a short circuit between the second storage electrode 370 and the first storage electrode 360, the second storage electrode 370 includes a top overlapping electrode 371, a first connecting electrode 372 and a second storage surrounding electrode 373, wherein the first connecting electrode 372 electrically connects the top overlapping electrode 371 and the second storage surrounding electrode 373, wherein the top overlapping electrode 371 and the first storage electrode 360 overlap in their projections on a plane perpendicular to the substrate 110.
[0146] S1063, forming a second storage surrounding electrode 373 on the gate 160 of the second fin structure 920, referring to Fig.32A , Fig.32B and Fig.32C shown.
[0147] In the embodiment of the present application, after the gate 160 of the first fin structure 910 and the gate 160 of the second fin structure 920 are exposed by the second groove 620, the first storage electrode 360 and the second storage surrounding electrode 373 can be formed on the gate 160 of the first fin structure 910, referring to Fig.32B shown.
[0148] When the first storage electrode 360 is formed, the first storage electrode 360 is also formed on the bottom drain electrode 132 and the top drain electrode 134. Fig.32A and Fig.32C When the first storage electrode 360 is formed, a second storage surrounding electrode 373 is formed on the bottom source electrode 131 and the top source electrode 133. Fig.32C When the first storage electrode 360 is formed, a top ground connection layer 332, a top word line connection layer 342 and a top bit line connection layer 352 are formed on the top source electrode 133, respectively. Fig.32A and Fig.32B shown.
[0149] S1064 , forming a first connection electrode 372 and a top overlapping electrode 371 .
[0150] In the embodiment of the present application, after forming the second storage surrounding electrode 373 , the first connection electrode 372 and the top overlapping electrode 371 may be formed, and the top overlapping electrode 371 and the second storage surrounding electrode 373 may be electrically connected by the first connection electrode 372 .
[0151] Specifically, a dielectric material may be deposited first to form a fourth dielectric layer 450, and the fourth dielectric layer 450 covers the first storage electrode 360 and the second storage electrode 370. Fig.33A The fourth dielectric layer 450 is etched to form a connecting through hole 630, referring to Fig.34A The first connection electrode 372 is formed in the connection through hole 630, referring to Fig.35A A top overlapping electrode 371 is formed on the surface of the fourth dielectric layer 450, wherein the top overlapping electrode 371 is electrically connected to the first connecting electrode 372. Fig.36A After forming the top overlapping electrode 371 , the dielectric material may be further deposited, that is, the thickness of the fourth dielectric layer 450 may be increased.
[0152] refer to Fig.36A As shown, the top overlapping electrode 371 is electrically connected to the thinner first connecting electrode 372 and the second storage surrounding electrode 373, thereby realizing electrical connection to the gate 160 of the second fin structure 920. In this way, there is enough space for the top overlapping electrode 371 to be set, thereby realizing the layering of the top overlapping electrode 371 and the first storage electrode 360, and then realizing the layered storage of the second storage electrode 370 and the first storage electrode 360. The second storage electrode 370 and the first storage electrode 360 are not on the same plane, that is, the layered interconnection structure of the second storage electrode 370 and the first storage electrode 360 is formed through the front local interconnection.
[0153] In the embodiment of the present application, after forming the second storage electrode 370 and the first storage electrode 360, a back power connection layer 310, a back ground connection layer 331, a back bit line connection layer 351 and a back word line connection layer 341 may be formed on the back of the substrate 110 to achieve electrical connection. The specific formation process is described in detail below.
[0154] S1071, bonding the temporary substrate 111 and the thinned substrate 110, reference Fig.37A and Fig.37B shown.
[0155] In the embodiment of the present application, the front side of the complementary field effect transistor is bonded to the temporary substrate 111 to protect the complementary field effect transistor and facilitate the subsequent thinning of the substrate 110. The substrate 110 is thinned, specifically, it can be thinned to the vicinity of the STI 203. After the substrate 110 is thinned, a dielectric material can also be deposited to form a sixth dielectric layer 460.
[0156] S1072, forming a contact hole 810.
[0157] In the embodiment of the present application, after the substrate 110 is thinned, the substrate 110 is conveniently etched to form the contact hole 810, referring to Fig.38A and Fig.38B The contact hole 810 includes a back contact hole (BSCON) 811 and a back interlayer contact via (BSVPR) 812. Fig.38B shown.
[0158] S1073 , filling the contact hole 810 .
[0159] In the embodiment of the present application, a metal material may be deposited into the contact hole 810 to fill the contact hole 810. The back power connection layer 310 is formed respectively, referring to Fig.39A and Fig.39B As shown, a back ground connection layer 331, a back bit line connection layer 351 and a back word line connection layer 341 are formed, referring to Fig.39B , Fig.39C and Fig.39D shown.
[0160] In practical applications, the first storage electrode may be a Q storage electrode. The second storage electrode may be a QB storage electrode. The second storage electrode and the first storage electrode may be arranged in a structure where the projection overlaps, or the first storage electrode may be arranged to overlap above the second storage electrode, thereby realizing layered storage of the second storage electrode and the first storage electrode, and also reducing the wiring space.
[0161] It can be seen that the present application reduces the wiring space and the area of the storage unit of the static random access memory by setting the second storage electrode and the first storage electrode to have a projection overlap structure, thereby shortening the length of the storage unit of the static random access memory from 156nm to 136nm. Fig.40 In addition, by providing a double-layer local interconnect structure at the back, the area of the storage unit of the static random access memory can also be reduced. Fig.40 The specific numerical value of the area reduction of the storage unit shown is an example and does not limit the actual area reduction degree of the present application.
[0162] Based on the method for manufacturing a complementary field effect transistor provided in the above embodiment, the embodiment of the present application further provides a complementary field effect transistor, and its working principle is described in detail below in conjunction with the accompanying drawings.
[0163] See also Fig.39A , Fig.39B , Fig.39C and Fig.39D As shown, this figure is a schematic diagram of the cross-sectional structure of the complementary field effect transistor provided in an embodiment of the present application.
[0164] The complementary field effect transistor provided in this embodiment includes:
[0165] Substrate 110;
[0166] A first top source 135, a first top drain 136, a first top channel structure, a first bottom source 131, a first bottom drain 132, a first bottom channel structure, a second top source 137, a second top drain 138, a second top channel structure, a second bottom source 133, a second bottom drain 134 and a second bottom channel structure are disposed on one side of the substrate 110, wherein the first top channel structure, the second top channel structure, the first bottom channel structure and the second bottom channel structure include a stack formed by a plurality of nanosheets;
[0167] a first gate and a second gate, the first gate surrounding the nanosheets of the first top structure and the first bottom structure, the second gate surrounding the nanosheets of the second top structure and the second bottom structure;
[0168] A first storage electrode 360 is formed on the first gate electrode, and a second storage electrode 370 is formed on the second gate electrode. The second storage electrode 370 and the first storage electrode 260 overlap in their projections on a plane perpendicular to the substrate.
[0169] As a possible implementation, the second storage electrode 370 includes a top overlapping electrode 371, a first connecting electrode 372 and a second storage surrounding electrode 373;
[0170] The second storage surrounding electrode 373 surrounds the second gate;
[0171] The first connection electrode 372 electrically connects the top overlapping electrode 371 and the second storage surrounding electrode 373;
[0172] The top overlapping electrode 371 and the first storage electrode 360 partially overlap in their projections on a plane perpendicular to the substrate 110 .
[0173] As a possible implementation manner, an isolation layer 200 is disposed between the top channel structure and the bottom channel structure.
[0174] As a possible implementation manner, a target sidewall 300 is disposed on the sidewall of the isolation layer 200 .
[0175] Based on a complementary field effect transistor provided in the above embodiment, an embodiment of the present application further provides a static random access memory, the static random access memory includes a plurality of storage units, and the storage unit includes the complementary field effect transistor described in any one of the above embodiments.
[0176] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the structural embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The structural embodiment described above is only illustrative, and ordinary technicians in this field can understand and implement it without creative work.
[0177] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.
Claims
1. A method for manufacturing a complementary field effect transistor, characterized in that: The method comprises: Providing a substrate, forming a plurality of stacked structures consisting of alternately stacked first semiconductor layers and second semiconductor layers on one side of the substrate, wherein the stacked structures include a buffer layer located in a middle region along a direction perpendicular to a plane where the substrate is located; Etching the stacked structure and a partially thick substrate to form a fin structure, wherein the fin structure includes a top structure, a bottom structure and a substrate structure, the top structure and the bottom structure are separated by the buffer layer, and the fin structure includes a first fin structure and a second fin structure; Etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, wherein the top source region and the top drain region are located between the top channel region and the bottom drain region are located between the bottom source region and the bottom drain region; forming inner sidewalls on the sidewalls of the top structure and the sidewalls of the bottom structure; forming a bottom source and a bottom drain in the bottom source region and the bottom drain region; forming a top source and a top drain on the bottom source and the bottom drain; The first semiconductor layer in the top channel region and the bottom channel region is removed, a plurality of gaps to be filled are formed between the second semiconductor layers, a gate is filled in the plurality of gaps to be filled, the gate surrounds the second semiconductor layer, and a stack of the plurality of second semiconductor layers forms a top channel structure and a bottom channel structure respectively; A first storage electrode is formed on the gate of the first fin structure, and a second storage electrode is formed on the gate of the second fin structure, wherein the second storage electrode and the first storage electrode overlap in their projections on a plane perpendicular to the substrate.
2. The manufacturing method according to claim 1, characterized in that: The second storage electrode includes a top overlapping electrode, a first connecting electrode, and a second storage surrounding electrode; The forming of a second storage electrode on the gate of the second fin structure comprises: forming a second storage surrounding electrode on the gate of the second fin structure; A first connection electrode and a top overlapping electrode are formed, wherein the first connection electrode is electrically connected to the second storage surrounding electrode and the top overlapping electrode, and the top overlapping electrode and the first storage electrode overlap in their projection portions on a plane perpendicular to the substrate.
3. The manufacturing method according to claim 2, characterized in that: Before forming a first storage electrode on the gate of the first fin structure and forming a second storage electrode on the gate of the second fin structure, the method further includes: forming a third dielectric layer on the gate of the first fin structure and the gate of the second fin structure; Etching the third dielectric layer on both sides of the top structure to form a second groove, wherein the second groove exposes the gate of the first fin structure and the gate of the second fin structure; The forming of a first storage electrode on the gate of the first fin structure and a second storage surrounding electrode on the gate of the second fin structure comprises: forming a first storage electrode on the gate of the first fin structure exposed by the second groove, and forming a second storage surrounding electrode on the gate of the second fin structure exposed by the second groove; Before forming the first connection electrode and the top overlapping electrode, the method further includes: forming a fourth dielectric layer, wherein the fourth dielectric layer covers the first storage electrode and the second storage electrode; The forming of the first connecting electrode and the top overlapping electrode, wherein the first connecting electrode is electrically connected to the second storage surrounding electrode and the top overlapping electrode, comprises: Etching the fourth dielectric layer to form a connecting through hole; forming a first connection electrode in the connection through hole; A top overlapping electrode is formed on the surface of the fourth dielectric layer, and the top overlapping electrode is electrically connected to the first connecting electrode.
4. The manufacturing method according to claim 1, characterized in that: The forming of the inner side wall on the side wall of the top structure and the side wall of the bottom structure comprises: Etching and removing a portion of the first semiconductor layer on the sidewalls of the top structure and the sidewalls of the bottom structure, and etching and removing the buffer layer, to form a concave structure and a buffer isolation structure, respectively; An inner sidewall is formed in the concave structure, and an isolation layer is formed in the buffer isolation structure.
5. The manufacturing method according to claim 1, characterized in that: The method further comprises: The substrate is etched to form a back power connection layer, a back ground connection layer, a back bit line connection layer and a back word line connection layer.
6. A complementary field effect transistor, characterized in that: The complementary field effect transistor comprises: substrate; A first top source, a first top drain, a first top channel structure, a first bottom source, a first bottom drain, a first bottom channel structure, a second top source, a second top drain, a second top channel structure, a second bottom source, a second bottom drain and a second bottom channel structure are disposed on one side of the substrate, wherein the first top channel structure, the second top channel structure, the first bottom channel structure and the second bottom channel structure include a stack formed by a plurality of nanosheets; a first gate and a second gate, the first gate surrounding the nanosheets of the first top structure and the first bottom structure, the second gate surrounding the nanosheets of the second top structure and the second bottom structure; A first storage electrode is formed on the first gate, and a second storage electrode is formed on the second gate. The second storage electrode and the first storage electrode overlap in their projections on a plane perpendicular to the substrate.
7. The complementary field effect transistor according to claim 6, characterized in that: The second storage electrode includes a top overlapping electrode, a first connecting electrode, and a second storage surrounding electrode; The second storage surrounding electrode surrounds the second gate; The first connection electrode electrically connects the top overlapping electrode and the second storage surrounding electrode; The top overlapping electrode and the first storage electrode partially overlap in their projections on a plane perpendicular to the substrate.
8. The complementary field effect transistor according to claim 6, characterized in that: An isolation layer is disposed between the top channel structure and the bottom channel structure.
9. The complementary field effect transistor according to claim 8, characterized in that: The sidewall of the isolation layer is provided with a target sidewall.
10. A static random access memory, characterized in that: It comprises a plurality of memory cells, each of which comprises a complementary field effect transistor as claimed in any one of claims 6 to 9.