LDMOS transistor and manufacturing method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor and a manufacturing method thereof, the LDMOS transistor comprises an intrinsic region and a terminal region which are distributed along a first direction, and the intrinsic region comprises a well region of a first doping type; the body region of the second doping type is located in the well region; the drift region is located in the well region and comprises at least one first injection layer of a first doping type and at least one second injection layer of a second doping type; the source region of the first doping type is located in the body region, and the drain region of the first doping type is located in the well region; the terminal region comprises a third injection region of a second doping type in contact with the second injection layer, the direction of the source region pointing to the drain region is a second direction, the direction of the lower surface of the well region pointing to the upper surface of the well region is a third direction, and the first direction, the second direction and the third direction are perpendicular to one another. The second implant layer is disposed to be separated from the body region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically, to an LDMOS transistor and a method for manufacturing the LDMOS transistor. Background Art

[0002] High voltage and high current place increasingly higher demands on laterally diffused metal oxide semiconductors (LDMOS): on the one hand, the chip area of ​​high-current application products depends on the successive reduction of the on-resistance Rsp, which places higher demands on the ultimate optimization of the breakdown voltage BV and the on-resistance Rsp; on the other hand, higher demands are also placed on the reliability of the device's high-current short-circuit capability. Summary of the invention

[0003] In view of this, an object of the present invention is to provide an LDMOS transistor and a method for manufacturing the same, so as to solve the problems existing in the prior art.

[0004] According to a first aspect of the present invention, there is provided an LDMOS transistor, comprising: an intrinsic region and a terminal region distributed along a first direction, the intrinsic region comprising: a well region of a first doping type; a body region of a second doping type extending from an upper surface of the well region to an interior of the well region; a drift region located in the well region, the drift region comprising at least one layer of a first injection region of a first doping type and at least one layer of a second injection region of a second doping type; a source region of a first doping type located in the body region, and a drain region of a first doping type located in the well region, the terminal region comprising a third injection region of a second doping type in contact with the second injection region, wherein a direction from the source region to the drain region is set to a second direction, a direction from the lower surface of the well region to the upper surface of the well region is set to a third direction, the first direction, the second direction, and the third direction are perpendicular to each other, and the second injection layer is set to be separated from the body region.

[0005] Preferably, each layer of the first implantation region includes a plurality of mutually separated first doping regions distributed along the second direction.

[0006] Preferably, each layer of the second implanted region includes a plurality of second doped regions separated from each other and distributed along the second direction.

[0007] Preferably, the second injection region is arranged below the first injection region.

[0008] Preferably, one layer of the first implantation region is in contact with an upper surface of the well region.

[0009] Preferably, the drain region is located in the first injection region.

[0010] Preferably, when the first injection region or the second injection region includes at least two layers, the first injection region and the second injection region are alternately distributed in the third direction.

[0011] Preferably, the third injection region includes a third doping region in contact with the second injection region and a second well region in contact with the third doping region, and the second well region is in contact with the body region of the intrinsic region.

[0012] Preferably, the third doping region is distributed at two ends of the second injection region along the first direction, and the second well region is distributed at two ends of the body region along the first direction.

[0013] Preferably, the intrinsic region also includes: an insulating structure, located at least on the upper surface of the well region between the source region and the drain region, and a gate conductor, extending from the source region at least to above a portion of the drift region and located on the insulating structure, wherein the insulating structure includes a gate dielectric layer near the source region and a second insulating layer near the drain region.

[0014] Preferably, the drift region is located at least below the second insulating layer.

[0015] Preferably, the second insulating layer is configured as a thin dielectric layer, a voltage-resistant dielectric layer thicker than the gate dielectric layer, or a shallow isolation trench, or a combination of the two.

[0016] According to a second aspect of the present invention, a method for manufacturing an LDMOS transistor is provided, comprising: forming an intrinsic region and a terminal region distributed along a first direction; the step of forming the intrinsic region comprises: forming a well region of a first doping type; forming a body region of a second doping type extending from the upper surface of the well region to the interior of the well region; forming a drift region located in the well region, the drift region comprising at least one layer of a first injection region of the first doping type and at least one layer of a second injection region of the second doping type; forming a source region of the first doping type located in the body region, and forming a drain region of the first doping type located in the well region; and the step of forming the terminal region comprises forming a third injection region of the second doping type in contact with the second injection region, wherein the direction of the source region pointing to the drain region is set to a second direction, the direction of the lower surface of the well region pointing to the upper surface of the well region is set to a third direction, the first direction, the second direction, and the third direction are perpendicular to each other, and the second injection region is set to be separated from the body region.

[0017] Preferably, the step of forming a drift region located in the well region includes: forming a first mask; based on the first mask, forming at least one layer of a first injection region of a first doping type, and forming a second mask; based on the second mask, forming at least one layer of a second injection region of a second doping type.

[0018] Preferably, after forming the first injection region and before forming the second injection region, the method further includes forming a second insulating layer located above the drift region and on the surface of the well region.

[0019] Preferably, forming the third injection region includes: forming a third doped region in contact with the second injection region, and forming a second well region in contact with the third doped region, wherein the second well region is in contact with the body region of the intrinsic region.

[0020] Preferably, when the second implantation region is provided as a continuous layer structure, the first implantation region and the third doping region are formed simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A cross-sectional view showing a prior art LDMOS transistor;

[0023] Figure 2 A plan view showing an LDMOS transistor according to a first embodiment of the present invention;

[0024] Figure 3 A cross-sectional view showing an intrinsic region of an LDMOS transistor according to a first embodiment of the present invention;

[0025] Figure 4 A cross-sectional view showing a terminal region of an LDMOS transistor according to a first embodiment of the present invention;

[0026] Figure 5 A plan view showing an LDMOS transistor according to a second embodiment of the present invention;

[0027] Figure 6 A cross-sectional view showing an intrinsic region of an LDMOS transistor according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0029] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0030] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0031] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0032] like Figure 1 , which is a cross-sectional view of an LDMOS transistor in the prior art. The LDMOS transistor comprises a substrate 101, a well region 102 located on the substrate 101, a drift region 105 of a first doping type located in the well region 102, a body region 104 of a second doping type located in the well region, a drain region 108 located in the drift region 105, and a source region 107 and a body contact region 106 located in the body region 104. The LDMOS transistor further comprises an implantation region 103 of a second doping type located below the drift region 105, the implantation region 103 extending to below the source region 104 and contacting the source region 104. The injection region 103 and the drift region 105 can deplete each other to reduce the electric field on the surface of the transistor and greatly reduce the on-resistance of the transistor. However, when the large current minority carriers in the drain region flow to the body contact region 106 through the surface channels of the drift region 105 and the body region 104, it will cause the parasitic npn (source region / body region / well region, source region / injection region / drift region) transistor to turn on, making the large current short-circuit capability of the LDMOS transistor very poor.

[0033] Figure 2 1 is a plan view showing an LDMOS transistor according to a first embodiment of the present invention, Figure 3 A cross-sectional view of an intrinsic region of an LDMOS transistor according to a first embodiment of the present invention is shown. Specifically, Figure 3 For along Figure 2 The cross-sectional structure of the axis EF in the figure, Figure 4 A cross-sectional view showing a terminal region of an LDMOS transistor according to a first embodiment of the present invention, specifically, Figure 4 For along Figure 2 The cross-sectional structure of the axis AB in FIG. Figure 2 , Figure 3 as well as Figure 4 ,like Figure 2 As shown, the LDMOS transistor includes an intrinsic region 300 and a terminal region 400 distributed along a first direction F1. Figure 3 As shown, the intrinsic region includes: a well region 202 of a first doping type; a body region 204 of a second doping type extending from the upper surface of the well region to the inside of the well region; a drift region located in the well region 202, the drift region including at least one first doping type first injection region 205 and at least one second doping type second injection region 203; a first doping type source region 207 located in the body region 204, and a first doping type drain region 208 located in the well region 202. The first injection region 205 is set to increase the doping concentration of the well region and further reduce the specific on-resistance of the transistor; in addition, the second injection region 203 is set to mutually deplete with the first injection region 205 to reduce the surface electric field between the gate and drain of the transistor and improve the breakdown voltage of the transistor. Therefore, the shape, position, number, etc. of the first injection region 205 and the second injection region 203 are not limited, as long as they can be mutually depleted to optimize the breakdown voltage and specific on-resistance. Wherein, the first doping type is set to one of N type and P type, and the second doping type is set to the other of N type and P type.

[0034] like Figure 4 As shown, the terminal region includes a third injection region of the second doping type in contact with the second injection region 203. Specifically, the third injection region includes a third doping region 220 in contact with the second injection region 203 and a second well region 221 in contact with the third doping region 220, and the second well region 221 is in contact with the body region 204 in the intrinsic region 300.

[0035] Specifically, Figure 2 and Figure 4 As shown, the third doped region 220 is distributed at both ends of the second injection region 203 along the first direction. Preferably, the third doped region 220 and the second injection region 203 are synchronously formed in the same layer, and the second well region 221 is distributed at both ends of the body region 204 along the first direction.

[0036] Among them, the direction of the source region 207 pointing to the drain region 208 is set to a second direction F2, and the direction of the lower surface of the well region 202 pointing to the upper surface of the well region 202 is set to a third direction F3, the first direction F1, the second direction F2, and the third direction F3 are perpendicular to each other. In this embodiment, the first injection region 205 of the first doping type and the second doping type body region 204 are set to be separated, and at the same time, the second injection region 203 of the second doping type and the second doping type body region 204 are set to be separated, so as to reduce the minority carriers on the drain side flowing to the source region 207 and the body contact region 206 through the second injection region 203 and the body region 204 of the intrinsic region, and increase the minority carriers on the drain side flowing to the source region 207 and the body contact region 206 through the terminal region 400.

[0037] Specifically, Figure 2 As shown, the LDMOS transistor also includes a body contact region 206 located in the body region 204 and adjacent to the source region 207; an insulating structure located at least on the upper surface of the well region between the source region 207 and the drain region 208, wherein the insulating structure includes a gate dielectric layer 211 close to the source region and a second insulating layer 209 close to the drain region; a gate conductor 210 is at least located on the gate dielectric layer 211, and further extends to a portion of the second insulating layer 209. The gate conductor is set to polysilicon material. The second insulating layer 209 is set to be one or a combination of a thin dielectric layer, a thick dielectric layer (silicon local oxide layer or nitride layer), or a shallow isolation trench. Preferably, the thin dielectric layer can be the same thickness as the gate dielectric layer.

[0038] In this embodiment, the first injection region 205 is at least located below the second insulating layer 209, and the first injection region 205 is arranged to contact the upper surface of the well region 202, that is, to contact the second insulating layer 209, and the drain region 208 is located in the first injection region 205. The first injection region 205 is arranged to be located on the surface of the well region to increase the doping concentration of the well region surface, so that the carriers flowing from the drain region to the source region are more inclined to flow along the first injection region 205 on the surface, thereby reducing the flow resistance and path of the carriers. In other embodiments, the first injection region 205 may also not contact the upper surface of the well region 202, that is, the upper surface of the first injection region 205 is spaced a certain distance from the upper surface of the well region.

[0039] In this embodiment, the second injection region 203 is arranged below the first injection region 205, so that the first injection region 205 and the second injection region 203 are better mutually depleted. Wherein, the spacing between the first injection region 205 and the second injection region 203 is greater than or equal to 0. In other embodiments, the first injection region 205 and the second injection region 203 may also be arranged left and right, or the second injection region 203 surrounds the first injection region 205, etc., and the positional relationship between the first injection region 205 and the second injection region 203 is not limited in any way.

[0040] In this embodiment, the number of layers of the first injection region 205 and the second injection region 203 is set to one. In other embodiments, the number of layers of the first injection region 205 and the second injection region 203 can also be set to multiple, the first injection region 205 and the second injection region 203 are alternately arranged along the third direction, or multiple first injection regions 205 are adjacently arranged, multiple second injection regions 203 are adjacently arranged, and multiple second injection regions 203 are arranged below multiple first injection regions 205. The spacing between adjacent first injection regions 205 and second injection regions 203 is greater than or equal to 0.

[0041] In addition, the LDMOS transistor also includes a substrate 201 of a second doping type, the well region 202 is located in the substrate 201, and the well region is of a first doping type. In other embodiments, it may also include an epitaxial layer of a second doping type located on the substrate 201, wherein the body region and the drift region are both located in the epitaxial layer, and the body region is in contact with the first injection region, as long as the doping type of the well region surface (except the channel region) from the source region to the drain region is the same as the doping type of the source and drain regions. In other embodiments, it may also include an epitaxial layer and a buried layer of a second doping type located between the substrate 201 and the well region, which is not limited here.

[0042] In this embodiment, the terminal area also includes a shallow trench isolation structure 222, which is in contact with the second insulating layer 209 of the intrinsic region, and a conductor layer 223 located on part of the second well region 221 and part of the shallow trench isolation structure 222, and the conductor layer 223 is in contact with the gate conductor of the intrinsic region.

[0043] The present invention optimizes the breakdown voltage and specific on-resistance of the LDMOS transistor by setting the first injection region 205 and the second injection region 203. In addition, the second injection region 203 is separated from the body region, and the third injection region of the terminal region is set so that the minority carriers on the drain side (taking the first doping type as N type as an example, the minority carriers are hole carriers) flow through the second injection region 203 to the second doping region 220 and the second well region 221 of the terminal region, and finally flow to the source region and the body contact region 206. Such a setting can greatly reduce the base current of the parasitic NPN in the intrinsic region 300, inhibit the opening of the parasitic NPN, and greatly improve the reliability of large current short circuit.

[0044] Figure 5 1 is a plan view showing an LDMOS transistor according to a second embodiment of the present invention, Figure 6 The cross-sectional view of the intrinsic region of the LDMOS transistor according to the second embodiment of the present invention is shown. The difference between the LDMOS transistor of this embodiment and the LDMOS transistor of the first embodiment is that the drift region structure is different, and the other structures are the same and will not be described here.

[0045] The drift region includes at least one layer of first injection region 305 of a first doping type and at least one layer of second injection region 303 of a second doping type, each layer of the first injection region includes a plurality of separately arranged first doping regions 3051, and each layer of the second injection region includes a plurality of separately arranged second doping regions 3031. Specifically, in this embodiment, the first injection region 305 and the second injection region 303 are both arranged as one layer, the plurality of separately arranged first doping regions 3051 are arranged along the second direction, the plurality of separately arranged second doping regions 3031 are arranged along the second direction, and the second doping regions 3031 are located below the first doping regions 3051. Preferably, one second doping region 3031 is arranged below each first doping region 3051. The spacing between adjacent first doping regions and second doping regions in the third direction is greater than or equal to 0.

[0046] In this embodiment, the spacing between adjacent first doping regions 3051 is the same, and the spacing between adjacent second doping regions 3031 is the same. In other embodiments, the spacing between adjacent first doping regions 3051 and the width of each first doping region 3051 can be set arbitrarily according to requirements, and the spacing between adjacent second doping regions 3031 and the width of each second doping region 3031 can be set arbitrarily according to requirements to maximize the optimization of breakdown voltage and specific on-resistance, and reduce the parasitic npn base current to inhibit the opening of npn. Figure 3 The structure is Figure 6 The structure is a special case where the distance between the first doping region 3051 and the second doping region 3031 is zero. Figure 6 The structure has greater freedom to balance the required large current short-circuit capability of the device and the required specific on-resistance, especially when the spacing between the first doped regions 3051 is greater than the spacing between the second doped regions 3031, the second injection region can more completely deplete the first injection region.

[0047] The present invention also provides a method for manufacturing an LDMOS transistor, the method being applicable to Figure 2 and Figure 5 LDMOS transistor, but not limited thereto. Specifically, the method includes: forming an intrinsic region 300 and a terminal region 400 distributed along a first direction. The steps of forming the intrinsic region include: forming a well region 202 of a first doping type; forming a body region 204 of a second doping type extending from the upper surface of the well region to the inside of the well region; forming a drift region located in the well region, the drift region including at least one layer of a first injection region 205 / 305 of a first doping type and at least one layer of a second injection region 203 / 303 of a second doping type; forming a source region 207 of a first doping type located in the body region 204, and forming a drain region 208 of a first doping type located in the well region 202. The step of forming the terminal region includes forming a third injection region of a second doping type in contact with the second injection region 203 / 303, wherein the direction of the source region 207 pointing to the drain region 208 is set to a second direction, and the direction of the lower surface of the well region pointing to the upper surface of the well region is set to a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other. The second injection region 203 / 303 is configured to be separated from the body region 204 to reduce the flow of minority carriers on the drain region side through the second injection region and the body region of the intrinsic region to the body contact region, and increase the flow of minority carriers on the drain region side through the terminal region to the body contact region.

[0048] The step of forming the drift region in the well region includes: forming a mask including an injection window; forming at least one layer of a first injection region of a first doping type based on the first mask, and forming at least one layer of a second injection region of a second doping type based on the second mask. The first injection region and the second injection region of different depths can be formed by adjusting the injection energy and the injection dose. The injection windows of the first mask and the second mask can be the same or different.

[0049] When the first injection region 205 / 305 and the second injection region 203 / 303 are formed by using the two masks with different injection windows, after forming the first injection region 205 / 305 and before forming the second injection region 203 / 303, a second insulating layer 209 located above the drift region and on the upper surface of the well region is further formed. In the present embodiment, the second insulating layer 209 is configured as a local silicon oxide layer, wherein the local silicon oxide layer is a local thermally grown silicon oxide layer, and in other embodiments, the second insulating layer 209 may also be configured as a deposited silicon oxide layer and / or a deposited silicon nitride layer.

[0050] The step of forming the third injection region includes: forming a third doping region 220 in contact with the second injection region 203 / 303, and forming a second well region 221 in contact with the third doping region 220, wherein the second well region 221 is in contact with the body region 204 of the intrinsic region. When the second injection region 203 is set as a continuous structure, preferably, the second injection region 203 and the third doping region 220 are formed simultaneously.

[0051] The method further includes forming a gate dielectric layer 211 extending from the source region to the second insulating layer 209 ; and forming a gate conductor 210 on the gate dielectric layer 211 , wherein the gate conductor 210 extends from the source region 207 to at least a portion of the second insulating layer 209 .

[0052] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An LDMOS transistor, It is characterized in that include: The intrinsic region and the terminal region are distributed along the first direction, The intrinsic region includes: a well region of a first doping type; a body region of a second doping type extending from an upper surface of the well region to an interior of the well region; a drift region located in the well region, the drift region including at least one layer of a first injection region of the first doping type and at least one layer of a second injection region of the second doping type; a source region of the first doping type located in the body region, and a drain region of the first doping type located in the well region, The terminal region includes a third implant region of the second doping type in contact with the second implant region, Among them, the direction from the source region to the drain region is set as the second direction, the direction from the lower surface of the well region to the upper surface of the well region is set as the third direction, the first direction, the second direction, and the third direction are perpendicular to each other, and the second injection layer is set to be separated from the body region.

2. The LDMOS transistor according to claim 1, It is characterized in that Each layer of the first implantation region includes a plurality of mutually separated first doping regions distributed along the second direction.

3. The LDMOS transistor according to claim 1, It is characterized in that Each layer of the second implanted region includes a plurality of second doped regions separated from each other and distributed along a second direction.

4. The LDMOS transistor according to claim 1, It is characterized in that The second injection region is disposed below the first injection region.

5. The LDMOS transistor according to claim 1, It is characterized in that One layer of the first implantation region contacts the upper surface of the well region.

6. The LDMOS transistor according to claim 5, It is characterized in that The drain region is located in the first injection region.

7. The LDMOS transistor according to claim 1, It is characterized in that When the first injection region or the second injection region includes at least two layers, the first injection region and the second injection region are alternately distributed in the third direction.

8. The LDMOS transistor according to claim 1, It is characterized in that The third implantation region includes a third doping region contacting the second implantation region and a second well region contacting the third doping region, wherein the second well region contacts the body region of the intrinsic region.

9. The LDMOS transistor according to claim 8, It is characterized in that The third doping region is distributed at two ends of the second implantation region along the first direction, and the second well region is distributed at two ends of the body region along the first direction.

10. The LDMOS transistor according to claim 1, It is characterized in that The intrinsic region also includes: an insulating structure, at least located on the upper surface of the well region between the source region and the drain region, and a gate conductor extending from the source region to at least a portion of the drift region and located on the insulating structure, Wherein, the insulating structure includes a gate dielectric layer close to the source region and a second insulating layer close to the drain region.

11. The LDMOS transistor according to claim 10, It is characterized in that The drift region is at least located below the second insulating layer.

12. The LDMOS transistor according to claim 10, It is characterized in that The second insulating layer is configured as a thin dielectric layer, a voltage-resistant dielectric layer thicker than the gate dielectric layer, or a shallow isolation trench, or a combination of the two.

13. A method for manufacturing an LDMOS transistor, It is characterized in that include: forming an intrinsic region and a terminal region distributed along a first direction, The steps of forming the intrinsic region include: forming a well region of a first doping type; forming a body region of a second doping type extending from an upper surface of the well region to an interior of the well region; forming a drift region located in the well region, the drift region including at least one layer of a first injection region of the first doping type and at least one layer of a second injection region of the second doping type; forming a source region of the first doping type located in the body region, and forming a drain region of the first doping type located in the well region, The step of forming the terminal region includes forming a third implant region of the second doping type in contact with the second implant region, Among them, the direction of the source region pointing to the drain region is set as the second direction, the direction of the lower surface of the well region pointing to the upper surface of the well region is set as the third direction, the first direction, the second direction, and the third direction are perpendicular to each other, and the second injection region is set to be separated from the body region.

14. The method according to claim 13, It is characterized in that The step of forming a drift region in the well region comprises: forming a first mask; Based on the first mask, at least one first implantation region of the first doping type is formed, and forming a second mask; Based on the second mask, at least one layer of a second implantation region of a second doping type is formed.

15. The method according to claim 14, It is characterized in that After forming the first injection region and before forming the second injection region, the method further includes forming a second insulating layer located above the drift region and on the surface of the well region.

16. The method according to claim 13, It is characterized in that Forming the third injection region includes: forming a third doped region in contact with the second injection region, and forming a second well region in contact with the third doped region, wherein the second well region is in contact with the body region of the intrinsic region.

17. The method according to claim 16, It is characterized in that When the second implantation region is provided as a continuous layer structure, the first implantation region and the third doping region are formed simultaneously.

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