Multi-path adaptive routing method and optical network-on-chip system

Abstract

The invention provides a multipath adaptive routing method and an optical network-on-chip system, and the method comprises the steps: carrying out the topology of a shared data buffer on each router, obtaining an optical network-on-chip, enabling adjacent routers in the optical network-on-chip to share the shared data buffer, enabling each router to be connected with an IP node, enabling a first IP node to generate link building request information, and enabling the first IP node to carry out the link building request information; the link establishment request information is sent to a second IP node corresponding to the link establishment request information through a first router connected with the first IP node, the second IP node generates confirmation information based on the link establishment request information, and the confirmation information is sent to the first IP node through a second router connected with the second IP node to establish a target optical path, the to-be-transmitted data information is transmitted from the first IP node to the second IP node along the target optical path, the router is simple in structure, and the resource transmission capacity of an on-chip optical network system is improved by combining the network topology node connection condition and the cache condition provided by the FIFO register in the router.

Description

Technical Field

[0001] The present disclosure relates to the technical field of on-chip network devices and resource control, and in particular to a multi-path adaptive routing method and an optical on-chip network system. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the disclosure that are recited in the claims. No description herein is admitted to be prior art by inclusion in this section.

[0003] Optical network on chip is a chip-level optical interconnect technology that aims to achieve high-performance and low-power inter-core communication for multi-core processors. It uses optical interconnection and has the advantages of high bandwidth density and low communication latency. However, in the related art, the optical network on chip system and the routers therein have excessive hardware redundancy and overly complex structure, and the routing algorithm will occupy the resources of the routing processing unit, resulting in limited application of optical transmission in the system on chip. Summary of the invention

[0004] In view of this, the purpose of the present disclosure is to propose a multi-path adaptive routing method and an optical network on a chip system, which at least to a certain extent solves one of the technical problems in the related art.

[0005] Based on the above purpose, the first aspect of the exemplary embodiment of the present disclosure provides a multi-path adaptive routing method, the method comprising:

[0006] Based on the shared data buffer set on each of the routers, a topology is performed to obtain an optical network on a chip, wherein adjacent routers in the optical network on a chip share the shared data buffer, and each router in the optical network on a chip is connected to an IP node;

[0007] The first IP node generates a link establishment request message, and sends the link establishment request message to a second IP node corresponding to the link establishment request message via a first router connected to the first IP node;

[0008] The second IP node generates confirmation information based on the link establishment request information, and sends the confirmation information to the first IP node via a second router connected to the second IP node to establish a target optical path;

[0009] The data information to be transmitted is transmitted from the first IP node to the second IP node along the target optical path.

[0010] Based on the same inventive concept, a second aspect of the exemplary embodiments of the present disclosure provides an optical network-on-chip system, including: a number of routers and IP cores;

[0011] Each of the routers is provided with a local data buffer and two shared data buffers, and adjacent routers share the shared data buffers;

[0012] The local data buffer is connected to the IP core.

[0013] From the above, it can be seen that the embodiment of the present disclosure provides a multi-path adaptive routing method and an optical chip network system, the method includes: based on a common data buffer set on each of the routers in a number of routers, a topology is performed to obtain an optical chip network, the adjacent routers in the optical chip network share the common data buffer, each router in the optical chip network is connected to an IP node, the first IP node generates a link establishment request information, and sends the link establishment request information to the second IP node corresponding to the link establishment request information via the first router connected to the first IP node, the second IP node generates confirmation information based on the link establishment request information, and sends the confirmation information to the first IP node via the second router connected to the second IP node to establish a target optical path, and transmit the data information to be transmitted from the first IP node to the second IP node along the target optical path. The adjacent routers in the optical chip network provided by the present disclosure share a data buffer, which reduces the redundancy of the hardware and the complexity of the structure, and dynamically adjusts the routing path of the information packet based on the structure, reduces the end-to-end delay caused by network congestion, reduces the transmission energy consumption and transmission loss, and improves the resource transmission capacity of the on-chip optical network system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic diagram of a structure of a network-on-a-chip system provided as an exemplary embodiment of the prior art;

[0016] Figure 2 A schematic diagram of a structure of a network-on-a-chip system provided for an exemplary embodiment of the present disclosure;

[0017] Figure 3 A schematic diagram of a flow chart of a multi-path adaptive routing method provided for an exemplary embodiment of the present disclosure;

[0018] Figure 4 A schematic diagram of a router structure provided for an exemplary embodiment of the present disclosure;

[0019] Figure 5 A schematic diagram of a network-on-a-chip routing network provided for an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] It is understandable that before using the technical solutions disclosed in the embodiments of this application, the type, scope of use, usage scenarios, etc. of the personal information involved in this application should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.

[0021] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly prompt the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can autonomously choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present application according to the prompt message.

[0022] As an optional but non-limiting implementation, in response to receiving an active request from the user, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0023] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation method of the present application. Other methods that meet the relevant laws and regulations may also be applied to the implementation method of the present application.

[0024] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and relevant provisions.

[0025] In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the principles and spirit of the present disclosure will be described with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present disclosure, and are not intended to limit the scope of the present disclosure in any way. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] It should be understood herein that any number of elements in the drawings is for illustration rather than limitation, and any naming is only for distinction rather than having any limiting meaning.

[0027] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connecting" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. The article "one" or "a" before an element does not exclude the existence of multiple such elements.

[0028] The principle and spirit of the present disclosure are explained in detail below with reference to several representative embodiments of the present disclosure.

[0029] As described in the background technology, in the related art, the optical network-on-chip router has excessive hardware redundancy and overly complex structure. The routing algorithm will occupy the resources of the routing processing unit, resulting in the limitation of the application of optical transmission in the on-chip system. Specifically:

[0030] refer to Figure 1 , which demonstrates an optical on-chip network in related technologies:

[0031] Among them, it includes five routers, each router is connected to an IP core; wherein, the first router includes: a first data buffer 1101, a second data buffer 1103, a third data buffer 1104, a fourth data buffer 1104, a fifth data buffer 1105 and a data processing unit 1106; the fifth data buffer 1105 is connected between the data processing unit 1106 and the IP core 1110, the first data buffer 1101 in the first router is connected to the sixth data buffer 1201 in the second router, the second data buffer 1102 in the first router is connected to the seventh data buffer 1301 in the third router, the third data buffer 1103 in the first router is connected to the eighth data buffer 1401 in the fourth router, and the fourth data buffer 1104 in the first router is connected to the ninth data buffer 1501 in the fifth router.

[0032] Based on Figure 1 The optical network on chip shown is illustrated by taking the example of data to be transmitted being sent from the first IP core to the second IP core:

[0033] The data to be transmitted generated by the first IP core needs to be read and processed by the first router to which the first IP core is connected, and a routing algorithm is performed based on each data buffer in the first router and each data buffer in the second router to which the second IP core is connected to select a path, and the data to be transmitted is sent from the first IP core to the second IP core.

[0034] From the above description, it can be seen that the optical network-on-chip system and the router structure therein in the related art are too complex and the hardware is overly redundant. The routing algorithm will occupy the resources of the routing processing unit, thereby limiting the application of optical transmission in the on-chip system.

[0035] In order to solve the above problems, the present disclosure provides a multi-path adaptive routing method and an optical chip network system solution, which specifically includes:

[0036] refer to Figure 2 , comprising five identical routers and IP cores; wherein the first router is provided with a first common data buffer 2101, a second common data buffer 2102, a local data buffer 2103 and a data processing unit 2104; the local data buffer 2103 is connected between the data processing unit 2104 and the IP core 2110, the first common data buffer 2101 is connected to the fifth router, the second common data buffer 2102 is connected to the fourth router, the positive direction of the x-axis of the first router is connected to the third common data buffer 2201 in the second router, and the negative direction of the y-axis of the first router is connected to the fourth common data buffer 2301 in the third router. The present invention designs a network-on-a-chip router that is convenient for reconstructing the network based on the common routing structure on a light chip, and the router of the present invention comprises: FIFO-L (local data buffer), a first common FIFO (first common data buffer), a second common FIFO (second common data buffer) and a data processing unit, and the two common FIFOs are arranged in an array, so as to reduce the hardware resource overhead and alleviate the transmission loss introduced by too much hardware.

[0037] contrast Figure 2 and Figure 1 As can be seen from the above description, the adjacent routers in the optical on-chip network provided by the present disclosure share data buffers, which reduces the redundancy of hardware and the complexity of the structure, and dynamically adjusts the routing path of information packets based on the structure, reduces the end-to-end delay caused by network congestion, reduces transmission energy consumption and transmission loss, and improves the resource transmission capacity of the on-chip optical network system. Based on the same inventive concept, corresponding to the structural schematic diagram provided in any of the above embodiments, the present disclosure also provides a multi-path adaptive routing method:

[0038] Based on the common data buffer set on each of the routers in a number of routers, a topology is performed to obtain a network on a light chip, wherein the adjacent routers in the network on a light chip share the common data buffer, and each router in the network on a light chip is connected to an IP node, and the first IP node generates a link establishment request message, and sends the link establishment request message to the second IP node corresponding to the link establishment request message via the first router connected to the first IP node, and the second IP node generates confirmation information based on the link establishment request message, and sends the confirmation information to the first IP node via the second router connected to the second IP node, so as to establish a target optical path, and transmit the data information to be transmitted from the first IP node to the second IP node along the target optical path. This method is improved based on the commonly used deterministic routing algorithm, and a multi-path adaptive routing algorithm that can be implemented with a gate array structure is designed to avoid the congestion caused by the deterministic routing algorithm and the defect of being unable to avoid congestion, and reduce the difficulty of algorithm design and routing control. In addition, the network on a light chip router and routing algorithm of the present invention are only used for network resource allocation, and will not affect other parts of the network, and have strong adaptability.

[0039] refer to Figure 3 , a multi-path adaptive routing method, the method comprising the following steps:

[0040] Step S310, performing topology based on a common data buffer set on each of the plurality of routers to obtain a network on a light chip, wherein adjacent routers in the network on a light chip share the common data buffer, and each router in the network on a light chip is connected to an IP node.

[0041] The following describes how to perform topology:

[0042] In specific implementation, the topology includes at least one of the following:

[0043] A mesh topology (Mesh topology) is implemented based on a common data buffer provided on each of the routers among several routers, or a torus topology (Torus topology) is implemented based on a common data buffer provided on each of the routers among several routers.

[0044] In the above exemplary embodiment, the topology method is introduced. The following describes the connection between each router in the optical network on a chip and an IP node:

[0045] In a specific implementation, each of the routers in the optical network on a chip is connected to an IP node, including:

[0046] In an optical network on a chip, each of the routers is connected to an IP node, which means that each optical router is responsible for processing and forwarding data from or to the IP node. This configuration ensures that data can be efficiently transmitted between different nodes and meets the communication bandwidth requirements.

[0047] As a specific example, refer to Figure 4 , taking a 4×4 network as an example, in an on-chip optical network based on Mesh topology, each router node and the IP node connected to it need to be numbered. Let the horizontal direction be the X direction, from 0 to 3, and the vertical direction be the Y direction, from 0 to 3, to establish a two-dimensional coordinate system, then each node has its corresponding coordinate to represent the number, and the connected IP node has the same coordinate as the router node, for example: IP(0,0), router(2,2), and the following will take the example of sending a data packet from the first IPIP(0,0) to the second IPIP(2,2).

[0048] Step S320: The first IP node generates a link establishment request message, and sends the link establishment request message to a second IP node corresponding to the link establishment request message via a first router connected to the first IP node.

[0049] In specific implementation, the link establishment request information includes:

[0050] The link establishment request information usually refers to the initial synchronization (SYN) message sent by the client to the server during the TCP connection establishment process. This message carries some necessary information, such as the initial sequence number, exchange window size, and MSS.

[0051] Next, we will introduce how to generate path comparison results:

[0052] The first IP node transmits the link establishment request information to the first local data buffer of the first router, and in response to the first router polling the first local data buffer, the first router reads the link establishment request information to obtain first node position information, performs gate array judgment on the first node position information to obtain available port information, performs register count comparison on the available port information, and generates a path comparison result.

[0053] In a specific implementation, the first IP node transmits the link establishment request information to the first local data buffer of the first router, and in response to the router polling the first local data buffer, comprises:

[0054] Following the above specific embodiments, refer to Figure 2The first router of the first IP node (IP(0,0)) is provided with a first shared data buffer 2101, a second shared data buffer 2102, a local data buffer 2103 and a data processing unit 2104. The local data buffer 2103 is connected between the data processing unit 2104 and the IP core 2110, performs an initialization operation on the IP core 2110, generates a link establishment request information, and polls the link establishment request information to the local data buffer 2103.

[0055] In a specific implementation, the link establishment request information is read based on the first router to obtain the first node location information, including:

[0056] Following the above specific embodiments, refer to Figure 2 The data processing unit 2104 interprets the link establishment request information in the local data buffer 2103 and obtains the location information of the first node (IP (0,0)). Figure 5 The location information of the first node (IP(0,0)) includes four parts: dx, dy, flag_x and flag_y. dx and dy indicate the transmission direction of information on the x-axis and y-axis. If the value is low, it is transmitted along the negative half axis of the x-axis or y-axis, and if the value is high, it is transmitted along the positive half axis of the x-axis or y-axis. Flag_x and flag_y indicate whether the coordinate difference between the destination routing node and the current routing node is 0. If the value is high, it indicates that the coordinate difference is 0, and if the value is low, it indicates that the coordinate difference is not 0.

[0057] In a specific implementation, gate array judgment is performed on the first node position information to obtain available port information, including:

[0058] Following the above specific embodiments, refer to Figure 5 , the gate array judges the location information of the first node (IP(0,0)). After the gate array judgement, the available port information (Port[3:0]) is generated and output as a four-bit value. The four bits represent the availability of the west, north, east, and south ports from left to right. A high level indicates availability and a low level indicates unavailability.

[0059] In a specific implementation, register count comparison is performed on the available port information to generate a path comparison result, including:

[0060] Following the above specific embodiments, refer to Figure 5 , because the algorithm satisfies the shortest path, only two ports are available at most. The total number of valid entries in the FIFO register (Count[3:0]) outputs the four-bit FIFO register count comparison result, which represents the comparison results of the northwest, southwest, northeast, and southeast FIFO counts. A result of 1 indicates that the former count result is larger, and a result of 0 indicates that the latter count result is larger or the two are equal.

[0061] In the above exemplary embodiments, a method for generating a path comparison result is introduced. Now, a method for generating an optimal transmission path is introduced:

[0062] In this exemplary embodiment, generating an optimal transmission path based on the path comparison result includes:

[0063] The path comparison result includes: a single transmission port or two transmission ports, based on which the optimal transmission path is generated, or an aggregation function is performed on the two transmission ports to generate the optimal transmission path.

[0064] In a specific implementation, performing aggregation function judgment on the two transmission ports to generate the optimal transmission path includes:

[0065] Following the above specific embodiments, refer to Figure 5 , the multi-path adaptive routing selection module uses the aggregation function (Count function) to determine the end of the shared data buffer that stores less data for output. Finally, Output[2:0] is obtained, where Output 000 indicates local output, 001 indicates output in the negative direction of the x-axis, 010 indicates output in the positive direction of the y-axis, 011 indicates output in the positive direction of the x-axis, and 100 indicates output in the negative direction of the y-axis. The remaining three are reserved fields. Finally, the data is transmitted to the corresponding shared data buffer unit along the judgment port of the Output output, and the steps of this embodiment are repeated until the optimal path for the first IP node (IP(0,0)) to transmit information to the second IP node (IP(2,2)) is generated.

[0066] In the above exemplary embodiment, a method of generating an optimal transmission path is introduced. Next, a method of transmitting the link establishment request information to the second IP node along the optimal transmission path is introduced:

[0067] In a specific implementation, the method of transmitting the link establishment request information to the second IP node along the optimal transmission path includes:

[0068] Following the above specific embodiment, the link establishment request information generated by the first IP node (IP (0,0)) is transmitted to the second IP node (IP (2,2)) along the optimal path.

[0069] Step S330: The second IP node generates confirmation information based on the link establishment request information, and sends the confirmation information to the first IP node via a second router connected to the second IP node to establish a target optical path.

[0070] The following describes how to establish the target light path:

[0071] In this exemplary embodiment, the second IP node generates confirmation information based on the link establishment request information, and sends the confirmation information to the first IP node via a second router connected to the second IP node to establish a target optical path, including:

[0072] The router in the optimal transmission path is controlled based on a microring resonator to obtain a light path to be confirmed, and the confirmation information is sent to the first IP node through the light path to be confirmed via a second router connected to the second IP node to establish a target light path.

[0073] In a specific implementation, the router in the optimal transmission path is controlled based on a microring resonator to obtain an optical path to be confirmed, including:

[0074] Following the above specific embodiments, refer to Figure 4 Each network-on-a-chip router is equipped with a microring resonator to control the optical waveguide and switch the optical path. For local input, For local output, For the north direction input, Output for the north direction, For input from the west, Output in the west direction, For the south direction input, Output in the south direction, For input from the east direction, The output is in the east direction. When the second IP node (IP(2,2)) receives the link request information transmitted by the first IP node (IP(0,0)), it will generate confirmation information (ACK information). At this time, the source node of the confirmation information (ACK information) is the second IP node (IP(2,2)), and the destination node is the first IP node (IP(0,0)). Figure 5, the gate array is used to judge the location information of the second node (IP(2,2)). After the gate array judgment, the available port information (Port[3:0]) is generated and output as a four-bit value. The four bits represent the availability of the west, north, east and south ports from left to right. A high level indicates availability and a low level indicates unavailability. The total number of valid entries in the FIFO register (Count[3:0]) outputs the four-bit FIFO register count comparison result, which represents the comparison results of the northwest, southwest, northeast and southeast FIFO counts. If the result is 1, it means that the former count result is larger, and if the result is 0, it means that the latter count result is larger or the two are equal. The multi-path adaptive routing selection module determines the end of the shared data buffer with less data storage through the aggregation function (Count function) for output. Finally, Output[2:0] is obtained. Output 000 indicates local output, 001 indicates output in the negative direction of the x-axis, 010 indicates output in the positive direction of the y-axis, 011 indicates output in the positive direction of the x-axis, 100 indicates output in the negative direction of the y-axis, and the remaining three are reserved fields. Finally, the data is transmitted to the corresponding shared data buffer unit along the judgment port of the Output output, and the steps of this embodiment are repeated until the optimal path for the second IP node (IP (2, 2)) to transmit the information to the first IP node (IP (0, 0)) is generated. The router in the optimal path will turn on or off the corresponding microring resonator and prohibit the router from transmitting confirmation information (ACK information) again, thereby obtaining the optical path to be confirmed.

[0075] In a specific implementation, the confirmation information is sent to the first IP node through the optical path to be confirmed via the second router connected to the second IP node to establish the target optical path, including:

[0076] Following the above specific embodiments, refer to Figure 4 The second IP node (IP (2,2)) transmits confirmation information (ACK information) to the first IP node (IP (0,0)) along the optimal path of the information transmitted to the first IP node (IP (0,0)) to establish the target optical path.

[0077] Step S340: Transmit the data information to be transmitted from the first IP node to the second IP node along the target optical path.

[0078] The following describes a method of transmitting the data information to be transmitted from the first IP node to the second IP node along the target optical path:

[0079] In this exemplary embodiment, the data information to be transmitted is transmitted from the first IP node to the second IP node along the target optical path, including:

[0080] The data information to be transmitted is converted electrically to optically to obtain the data information to be transmitted as an optical signal, and the data information to be transmitted as an optical signal is transmitted from the first IP node to the second IP node along the target optical path.

[0081] In a specific implementation, the data information to be transmitted is subjected to electro-optical conversion to obtain the data information to be transmitted as an optical signal, including:

[0082] Following the above specific embodiments, refer to Figure 4 , the data information to be transmitted of the first IP node (IP(0,0)) is converted electrically to optically to obtain the data information to be transmitted as an optical signal.

[0083] In a specific implementation, transmitting the data information to be transmitted by the optical signal from the first IP node to the second IP node along the target optical path includes:

[0084] Following the above specific embodiments, refer to Figure 4 , the data information to be transmitted of the optical signal of the first IP node (IP(0,0)) is transmitted along the target optical path to the second IP node (IP(2,2)).

[0085] In the above exemplary embodiment, a method of transmitting the data information to be transmitted from the first IP node to the second IP node along the target optical path is introduced. The following describes a method of obtaining the transmission data information after the optical signal data information to be transmitted is transmitted from the first IP node to the second IP node along the target optical path:

[0086] In this exemplary embodiment, obtaining the transmission data information includes:

[0087] The second IP node receives the optical signal transmission data information transmitted from the first IP node along the target optical path, and performs photoelectric conversion on the optical signal transmission data information to obtain transmission data information.

[0088] In a specific implementation, the second IP node receives the optical signal transmission data information transmitted from the first IP node along the target optical path, including:

[0089] Following the above specific embodiments, refer to Figure 4 The second IP node (IP(2,2)) receives the optical signal transmission data information transmitted from the first IP node (IP(0,0)) along the target optical path.

[0090] In a specific implementation, the optical signal transmission data information is subjected to photoelectric conversion to obtain the transmission data information, including:

[0091] Following the above specific embodiments, refer to Figure 4The optical signal transmission data information received by the second IP node (IP(2,2)) is subjected to photoelectric conversion to obtain the transmission data information from the first IP node (IP(0,0)).

[0092] It should be noted that the method of the embodiment of the present disclosure can be performed by a single device, such as a computer or a server. The method of the present embodiment can also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0093] It should be noted that the above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0094] Those skilled in the art will appreciate that the embodiments of the present disclosure may be implemented as a system, method, or computer program product. Therefore, the present disclosure may be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." In addition, in some embodiments, the present disclosure may also be implemented in the form of a computer program product in one or more computer-readable media, which contains computer-readable program code.

[0095] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive examples) of computer-readable storage media may include, for example: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device.

[0096] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0097] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0098] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0099] It should be understood that each box in the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, and these computer program instructions are executed by a computer or other programmable data processing device to produce a device that implements the functions / operations specified in the boxes in the flowchart and / or block diagram.

[0100] These computer program instructions may also be stored in a computer-readable medium that enables a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable medium produce a product that includes an instruction device that implements the functions / operations specified in the blocks in the flowchart and / or block diagram.

[0101] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby enabling the instructions executed on the computer or other programmable device to provide a process for implementing the functions / operations specified in the blocks in the flowchart and / or block diagram.

[0102] In addition, although the operations of the disclosed method are described in a particular order in the accompanying drawings, this does not require or imply that the operations must be performed in this particular order, or that all the operations shown must be performed to achieve the desired results. On the contrary, the steps depicted in the flow chart can be performed in a different order. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be decomposed into multiple steps.

[0103] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0104] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0105] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0106] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0107] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0108] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

[0109] Although the spirit and principle of the present disclosure have been described with reference to several specific embodiments, it should be understood that the present disclosure is not limited to the disclosed specific embodiments, and the division of various aspects does not mean that the features in these aspects cannot be combined to benefit, and such division is only for the convenience of expression. The present disclosure is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the attached claims. The scope of the attached claims conforms to the broadest interpretation, thereby including all such modifications and equivalent structures and functions.

Claims

1. A multi-path adaptive routing method, characterized in that: include: Based on the shared data buffer set on each of the routers, a topology is performed to obtain an optical network on a chip, wherein adjacent routers in the optical network on a chip share the shared data buffer, and each router in the optical network on a chip is connected to an IP node; The first IP node generates a link establishment request message, and sends the link establishment request message to a second IP node corresponding to the link establishment request message via a first router connected to the first IP node; The second IP node generates confirmation information based on the link establishment request information, and sends the confirmation information to the first IP node via a second router connected to the second IP node to establish a target optical path; The data information to be transmitted is transmitted from the first IP node to the second IP node along the target optical path.

2. The method according to claim 1, characterized in that The topology includes: mesh topology or torus topology; The topology is performed based on a common data buffer set on each of the routers to obtain an optical network on a chip, including: A mesh topology is performed based on the common data buffer set on each of the routers in the plurality of the routers to obtain the optical network on a chip; or, The network on a chip is obtained by performing a torus topology based on the common data buffer provided on each of the routers.

3. The method according to claim 1, characterized in that The first IP node generates link establishment request information, and sends the link establishment request information to a second IP node corresponding to the link establishment request information via a first router connected to the first IP node, including: The first IP node transmits the link establishment request information to a first local data buffer of the first router, and in response to the router polling the first local data buffer, obtains first node location information based on reading the link establishment request information by the first router; Performing gate array judgment on the first node position information to obtain available port information; Performing register count comparison on the available port information to generate a path comparison result, and generating an optimal transmission path based on the path comparison result; The link establishment request information is transmitted to the second IP node along the optimal transmission path.

4. The method according to claim 3, characterized in that The path comparison result includes: a single transmission port or two transmission ports; The generating the optimal transmission path based on the path comparison result includes: Based on the single transmission port, generating the optimal transmission path; or, An aggregation function is performed on the two transmission ports to generate the optimal transmission path.

5. The method according to claim 3, characterized in that: The second IP node generates confirmation information based on the link establishment request information, and sends the confirmation information to the first IP node via a second router connected to the second IP node to establish a target optical path, including: The second IP node generates the confirmation information based on the link establishment request information, and sends the confirmation information to the first IP node along the optimal transmission path via a second router connected to the second IP node to establish a target optical path.

6. The method according to claim 5, characterized in that The sending the confirmation information to the first IP node along the optimal transmission path via the second router connected to the second IP node comprises: Controlling the router in the optimal transmission path based on the microring resonator to obtain an optical path to be confirmed; The confirmation information is sent to the first IP node through the optical path to be confirmed via a second router connected to the second IP node, so as to establish a target optical path.

7. The method according to claim 1, characterized in that The step of transmitting the data information to be transmitted from the first IP node to the second IP node along the target optical path includes: Performing electro-optical conversion on the data information to be transmitted to obtain the data information to be transmitted as an optical signal; The data information to be transmitted by the optical signal is transmitted from the first IP node to the second IP node along the target optical path.

8. The method according to claim 7, characterized in that After transmitting the optical signal data information to be transmitted from the first IP node to the second IP node along the target optical path, the method further includes: The second IP node receives the optical signal transmission data information transmitted from the first IP node along the target optical path; The optical signal transmission data information is subjected to photoelectric conversion to obtain transmission data information.

9. An optical network-on-chip system, characterized in that: include: Several routers and IP cores; Each of the routers is provided with a local data buffer and two shared data buffers, and adjacent routers share the shared data buffers; The local data buffer is connected to the IP core.

10. The system according to claim 9, characterized in that The plurality of routers are connected in an array arrangement based on the common data buffer.

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