An accelerated storage method and an accelerated storage system

Abstract

The present invention relates to the technical field of storage systems, and discloses an accelerated storage method and an accelerated storage system, wherein the accelerated storage system comprises a CPU module, and a DDR module, a storage module and a file table cache module respectively connected to the CPU module in communication; the storage module comprises a first FAT area and a data storage area; the method comprises: when a read / write operation instruction is detected, the CPU module determines the file table area to be updated corresponding to the read / write operation instruction from the DDR module, and establishes the file table area to be updated in the file table cache module, so as to update the file table area to be updated in the file table cache module. The present invention is conducive to reducing the occupancy frequency of the storage module and improving storage efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of storage systems, and in particular to an accelerated storage method and an accelerated storage system. Background Art

[0002] In current embedded data storage technology, it is often necessary to read and write a large amount of data. The reading and writing process is accompanied by two processes: updating the file table of FAT (File Allocation Table) and storing data. Both processes need to share the transmission channel of the storage module to execute. Specifically, when the system stores data, the main processes are: reading file table information, updating file table information, writing data content to the specified area, and updating file information again.

[0003] Therefore, when a task of writing data to the storage module is generated, the actual writing operation of the data needs to initiate multiple read and write operations on the file table; in this process, frequent and small data block operations on the FAT file table will occupy the transmission channel of the storage module. Once the transmission channel of the storage module is occupied by the file table update process, the process of storing data cannot be carried out, so the read and write update of the file system information table area cannot be carried out at the same time as the data reading and writing, which will affect the storage efficiency.

[0004] Therefore, in the existing storage technology, since the transmission channel of the storage module is frequently occupied, the FAT file table update cannot be performed simultaneously with the data reading and writing, so the storage efficiency is low. Summary of the invention

[0005] The main purpose of the present invention is to provide an accelerated storage system and a storage method thereof, aiming to solve the problem in the existing storage technology that the FAT file table update cannot be performed simultaneously with data reading and writing due to the frequent occupancy of the transmission channel of the storage module, resulting in low storage efficiency.

[0006] To achieve the above object, the present invention provides an accelerated storage method, wherein the accelerated storage system includes a CPU module, and a DDR module, a storage module, and a file table cache module respectively connected to the CPU module for communication; the storage module includes a first FAT area and a data storage area; the method includes the following steps:

[0007] When a read / write operation instruction is detected, the CPU module determines the file table area to be updated corresponding to the read / write operation instruction from the DDR module, and establishes the file table area to be updated in the file table cache module, so as to update the file table area to be updated in the file table cache module;

[0008] According to the read-write operation instruction, the CPU module allocates a read-write address for the read-write operation instruction;

[0009] Performing read and write operations on the data storage area of ​​the storage module according to the allocated read and write addresses;

[0010] Determine whether the file table transfer conditions are met;

[0011] When the file table transfer condition is met, the CPU module updates the file table area updated in the file table cache module to the DDR module, and transfers the updated file table area from the DDR module to the first FAT area of ​​the storage module.

[0012] Optionally, the method further includes:

[0013] Detect file table access instructions;

[0014] When the file table access instruction is detected, the CPU module reads the file table information corresponding to the file table access instruction from the file table cache module;

[0015] Determine whether the reading is successful;

[0016] If so, the file table information corresponding to the file table access instruction read from the file table cache module is returned to the user;

[0017] If not, the CPU module reads the file table information corresponding to the file table access instruction from the first FAT area of ​​the storage module, and returns the file table information corresponding to the file table access instruction read from the first FAT area of ​​the storage module to the user.

[0018] Optionally, the method further includes:

[0019] A file table buffer and a mapping table management area are established in the file table cache module to update the file table area to be updated corresponding to the read and write operation instructions in the file table buffer, and the mapping table management area manages the mapping relationship between the file table area updated in the file table buffer and the first FAT area in the storage module.

[0020] Optionally, the step of determining whether the file table transfer condition is met includes:

[0021] Detecting whether the acceleration storage system is idle;

[0022] and / or

[0023] Detect whether the data writing amount in the file table cache module reaches a preset threshold.

[0024] Optionally, when a read / write operation instruction is detected, the CPU module determines the file table area to be updated corresponding to the read / write operation instruction from the DDR module, and establishes the file table area to be updated in the file table cache module, before the step of updating the file table area to be updated in the file table cache module, further comprising:

[0025] Establishing a first FAT area and a data storage area in the storage module, wherein the first FAT area includes a boot area, a file table area and a file table backup area, and the data storage area is used to store write data;

[0026] A second FAT area and a first mapping table are established in the DDR module, wherein the first mapping table is used to record a mapping relationship between addresses in the first FAT area and the second FAT area.

[0027] Optionally, when a read / write operation instruction is detected, the CPU module determines the file table area to be updated corresponding to the read / write operation instruction from the DDR module, and establishes the file table area to be updated in the file table cache module, so as to update the file table area to be updated in the file table cache module, comprising:

[0028] When a read / write operation instruction is detected, the CPU module obtains the file table area to be updated in the first FAT area of ​​the read / write operation instruction;

[0029] The CPU module determines the file table area to be updated in the second FAT area from the second FAT area of ​​the DDR module according to the file table area to be updated in the first FAT area;

[0030] According to the file table area to be updated in the second FAT area, a third FAT area is established in the file table cache module, and a second mapping table is established, wherein the second mapping table is used to map a part of the address segments of the third FAT area to the second FAT area;

[0031] The third FAT area is updated in the file table cache module according to the read and write operation instructions.

[0032] Optionally, when the file table transfer condition is met, the step of the CPU module updating the file table area updated in the file table cache module to the DDR module, and transferring the updated file table area from the DDR module to the first FAT area of ​​the storage module includes:

[0033] When the file table transfer condition is met, the CPU module updates the file table area updated in bytes in the file table cache module to the DDR module, and transfers it from the DDR module to the first FAT area of ​​the storage module in sectors.

[0034] Optionally, the file table cache module is an STT-MRAM memory.

[0035] Optionally, the STT-MRAM memory includes an EMD4E001G16G2-115CAS2 chip.

[0036] To achieve the above objectives, the present invention also proposes an accelerated storage system for executing the method; the accelerated storage system includes a CPU module, and a DDR module, a storage module and a file table cache module respectively connected to the CPU module for communication; the storage module includes a first FAT area and a data storage area.

[0037] In the technical solution of the present invention, each time there is a read / write operation instruction, the file table area to be updated corresponding to the read / write operation instruction is determined from the DDR module, and the file table area to be updated is established in the file table cache module, so as to update the file table area to be updated in the file table cache module, thereby transferring the file table update operation that was originally frequently performed in the storage module to the file table cache module, significantly reducing the occupation of the transmission channel of the storage module by the file table update process. Therefore, the technical solution of the present invention can update the file table without frequently occupying the transmission channel of the storage module. Further, the conditions for transferring the file table from the file table cache module to the storage module are set, and when the transfer condition is met, the file table area updated in the file table cache module is updated to the DDR module, and transferred from the DDR module to the first FAT area of ​​the storage module. Therefore, in the period between two transfers, the transmission channel of the storage module can perform data read / write operations, avoiding the frequent occupation of the transmission channel of the storage module, resulting in the FAT file table update being unable to be performed simultaneously with data reading and writing, thereby causing the problem of low storage efficiency. Furthermore, the technical solution of the present invention ultimately stores the latest file table in the storage module, which does not affect the data storage and file table storage functions of the storage module. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a flow chart of a first embodiment of the present invention;

[0039] Figure 2 A corresponding relationship diagram between the first FAT area in the storage module and the file table buffer in the file table cache module;

[0040] Figure 3 The design schematic diagram of the chip in the STT-MRAM memory (I);

[0041] Figure 4 This is the design schematic diagram of the chip in the STT-MRAM memory (II);

[0042] Figure 5 This is the design schematic diagram of the chip in the STT-MRAM memory (III);

[0043] Figure 6 This is the design schematic diagram of the chip in the STT-MRAM memory (IV);

[0044] Figure 7 The design schematic diagram of the chip in the STT-MRAM memory (V);

[0045] Figure 8 It is a mapping relationship diagram of the first FAT area, the second FAT area, and the third FAT area in the present invention.

[0046] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0047] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0048] In the following description, suffixes such as "unit", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings. Therefore, "unit", "component" or "unit" can be used in a mixed manner.

[0049] See also Figures 1 to 8 In a first embodiment of the present invention, an accelerated storage method is provided. The accelerated storage system includes a CPU module, and a DDR module, a storage module and a file table cache module respectively connected to the CPU module for communication; the storage module includes a first FAT area and a data storage area; the method includes the following steps:

[0050] Step S10, when a read / write operation instruction is detected, the CPU module determines the file table area to be updated corresponding to the read / write operation instruction from the DDR module, and establishes the file table area to be updated in the file table cache module, so as to update the file table area to be updated in the file table cache module;

[0051] Step S20, according to the read-write operation instruction, the CPU module allocates a read-write address to the read-write operation instruction; it is easy to understand that when the read-write operation instruction is a read instruction, the read-write address allocated by the CPU module to the read-write operation instruction is a data read address, and when the read-write operation instruction is a write instruction, the read-write address allocated by the CPU module to the read-write operation instruction is a data write address.

[0052] Step S30, performing read and write operations on the data storage area of ​​the storage module according to the allocated read and write addresses;

[0053] Step S40, determining whether the file table transfer condition is met;

[0054] Step S50, when the file table transfer condition is met, the CPU module updates the file table area updated in the file table cache module to the DDR module, and transfers the updated file table area from the DDR module to the first FAT area of ​​the storage module.

[0055] In the technical solution of the present invention, each time there is a read / write operation instruction, the file table area to be updated corresponding to the read / write operation instruction is determined from the DDR module, and the file table area to be updated is established in the file table cache module, so as to update the file table area to be updated in the file table cache module, thereby transferring the file table update operation that was originally frequently performed in the storage module to the file table cache module, significantly reducing the occupation of the transmission channel of the storage module by the file table update process. Therefore, the technical solution of the present invention can update the file table without frequently occupying the transmission channel of the storage module. Further, the conditions for transferring the file table from the file table cache module to the storage module are set, and when the transfer condition is met, the file table area updated in the file table cache module is updated to the DDR module, and transferred from the DDR module to the first FAT area of ​​the storage module. Therefore, in the period between two transfers, the transmission channel of the storage module can perform data read / write operations, avoiding the frequent occupation of the transmission channel of the storage module, resulting in the FAT file table update being unable to be performed simultaneously with data reading and writing, thereby causing the problem of low storage efficiency. Furthermore, the technical solution of the present invention ultimately stores the latest file table in the storage module, which does not affect the data storage and file table storage functions of the storage module.

[0056] Furthermore, the file table is transferred to the storage module only when the file table transfer condition is met at regular intervals, which can also reduce frequent write operations to the storage module, thereby extending the service life of the storage module.

[0057] Specifically, the storage module may be an SSD. The file table cache module may be configured as required, for example, a hard disk may be used. In the present invention, the file table cache module is an STT-MRAM memory (Spin Transfer Torque-Magnetic Random Access Memory).

[0058] STT-MRAM memory has the following advantages:

[0059] STT-MRAM memory has excellent read and write performance, and its read and write speed is much higher than that of traditional storage devices. This enables it to quickly respond to read and write requests from the file system FAT file table area during file storage, reducing waiting time and improving storage efficiency.

[0060] The physical property of not losing data when power is off is another major advantage of STT-MRAM memory. In the event of an unexpected power outage, the FAT file table area data stored in the STT-MRAM memory will not be lost, ensuring the stability of the system and the security of the data.

[0061] Specifically, in the technical solution of the present invention, the FAT table will be cached in the DDR module. Considering that the FAT table in the DDR module will lose data if power is lost, the storage capacity of the STT-MRAM memory is generally small, and each read and write operation only needs to update a part of the file table area, rather than updating all the file table areas. Therefore, in the present invention, according to the read and write operation instructions, the file table area to be updated corresponding to the current read and write operation instructions is obtained; and the file table area to be updated is established in the STT-MRAM memory (implemented by address mapping, that is, mapping part of the address segment of the file table area in the STT-MRAM memory to the address segment of the file table area in the DDR module), and the file table area to be updated is updated in the STT-MRAM memory.

[0062] Therefore, within a period of time before the file table transfer condition is met, whenever there is a new read / write operation instruction, the file table area to be updated corresponding to the new read / write operation instruction will be established in the STT-MRAM memory and updated. Thus, within a period of time, all file table areas that need to be updated are stored in the STT-MRAM memory and have been updated. Even if the STT-MRAM memory loses power, the data therein will not be damaged or lost. Therefore, when the file table transfer condition is met, the file table area cached in the STT-MRAM memory is updated to the DDR module, and then updated from the DDR module to the first FAT area of ​​the storage module. Therefore, the technical solution of the present invention can ensure that the data is not lost when the power is off, thereby ensuring the security of the data.

[0063] Furthermore, the STT-MRAM memory includes an EMD4E001G16G2-115CAS2 chip.

[0064] See also Figures 3 to 7, STT-MRAM chip is selected as the file table storage location, which can quickly realize the query and access of the file table. The specific model of STT-MRAM chip is EMD4E001G16G2-115CAS2. This chip is compatible with 96-ball FBGADDR4 package and compatible with ordinary DDR4 SDRAM features and non-volatility. The capacity is 64Mb×16=1Gb, the page size is 2048bit×16, the working clock is 667MHz, the transmission rate is 1333MT / s, and the Bit Error Rate (BER) is 1×10 -11 The data retention time is 10 years at 85°C, and the number of repeated read and write times is 1×10 10 Second-rate.

[0065] Based on the first embodiment of the accelerated storage method of the present invention, in a second embodiment of the accelerated storage method of the present invention, the method further includes:

[0066] Step S60, detecting a file table access instruction;

[0067] Step S70, when the file table access instruction is detected, the CPU module reads the file table information corresponding to the file table access instruction from the file table cache module;

[0068] Step S80, determining whether the reading is successful;

[0069] If yes, executing step S90: returning the file table information corresponding to the file table access instruction read from the file table cache module to the user;

[0070] If not, execute step S100: the CPU module reads the file table information corresponding to the file table access instruction from the first FAT area of ​​the storage module, and returns the file table information corresponding to the file table access instruction read from the first FAT area of ​​the storage module to the user.

[0071] Furthermore, the file table cache module in the present invention can not only cache the file table area that needs to be updated within a period of time, and update the file table area that needs to be updated within this period of time, but also provide a fast access buffer for FAT access. Specifically, when the system or user initiates a file table access instruction, the corresponding file table information is first searched from the file table cache module. If the required file table information is found, the required file table information can be returned as a result without accessing the storage module, which greatly improves the access rate of FAT data and avoids frequent occupation of the transmission channel of the storage module when accessing FAT data. However, if the required file table information is not found from the file table cache module, it proves that the file table information has been transferred to the storage module, and then it can be read from the storage module.

[0072] Based on the second embodiment of the accelerated storage method of the present invention, in a third embodiment of the accelerated storage method of the present invention, the method further includes:

[0073] Step S110, establishing a file table buffer and a mapping table management area in the file table cache module, so as to update the file table area to be updated corresponding to the read and write operation instructions in the file table buffer, and managing the mapping relationship between the file table area updated in the file table buffer and the first FAT area in the storage module in the mapping table management area (i.e., the second mapping table in the following text).

[0074] In the technical solution of the present invention, the FAT table is address mapped twice.

[0075] The first address mapping is to map all file table areas in the first FAT area in the storage module to the second FAT area in the DDR module (ie, the first mapping table hereinafter) by means of address mapping.

[0076] The second address mapping is during the read and write operation process. When the FAT file table area needs to be read and written, part of the address segments of the file table area in the file table cache module are mapped to the file table area in the DDR module (i.e., the second mapping table in the following text) through secondary address mapping, so that the file table area to be updated is established in the file table cache module, which is convenient for the subsequent update of the file table area to be updated corresponding to the read and write operation. In this process, part of the space in the file table cache module is mapped to the file table area in the second FAT area of ​​the DDR module. Since all the file table areas in the first FAT area of ​​the storage module are also mapped to all the file table areas in the second FAT area of ​​the DDR module, part of the space in the file table cache module is also mapped to the file table area in the first FAT area.

[0077] This mapping method allows the system to directly access the file table area data in the file table cache module, just like accessing the first FAT area, without the need for complex address conversion, thereby improving access efficiency.

[0078] At the same time, through the secondary address mapping, the transmission channel of the storage module is released, so that the FAT table and data of the file system can be processed in parallel. For example, while reading and writing a large amount of data, the system can read and write and update the file table area of ​​the FAT area without interfering with each other, greatly improving the overall performance of the system.

[0079] See also Figure 2 In this embodiment, the file table area to be updated corresponding to the read and write operation instructions is updated in the file table buffer, and the mapping relationship between the file table area updated in the file table buffer and the second FAT area in the DDR module is managed in the mapping table management area, thereby managing the mapping relationship with the first FAT area in the storage module, thereby partitioning the file table area update and mapping table management.

[0080] When reading and writing updates to the FAT file table area of ​​the file system, the first FAT area must be associated with the cache space of the file table cache module (STT-MRAM memory) through the mapping table to implement the mapping management between physical addresses and virtual addresses. In order to prevent duplicate mapping addresses, the system will strictly manage and maintain the mapping table. Specifically, the system detects whether there are occupied physical addresses and virtual addresses in the mapping table. When it is detected that a physical address or virtual address is occupied, it is confirmed as a duplicate mapping address, and error correction processing is performed on the duplicate mapping address, such as updating the mapping table, clearing the old mapping relationship, etc., to ensure that the reading and writing updates of the FAT file table area are accurate.

[0081] Based on the first embodiment of the accelerated storage method of the present invention, in a fourth embodiment of the accelerated storage method of the present invention, step S40 includes:

[0082] Step S41, detecting whether the acceleration storage system is idle;

[0083] and / or

[0084] Step S42, detecting whether the amount of data written into the file table cache module reaches a preset threshold.

[0085] Specifically, the conditions for transferring the file table to the first FAT area of ​​the storage module can be set according to actual conditions. Specifically, the file table area in the file table cache module can be updated to the storage module during the system operation gap (i.e., the system's idle period). At this time, since there is no data being stored or read in the storage module, the transmission channel of the storage module is not occupied, so that the file table area in the file table cache module can be quickly updated to the storage module without affecting the data reading and writing process.

[0086] Furthermore, when the amount of data written in the file table cache module reaches a preset threshold (the preset threshold can be set as needed, for example, it can be any value between 50% and 80% of the total capacity of the file table cache module), the file table area in the file table cache module can be updated to the storage module, and the address mapping space in the file table cache module can be released at the same time. The system's file storage process can be accelerated through the FAT secondary cache parallel processing mechanism of the file table cache module.

[0087] Based on the first embodiment of the accelerated storage method of the present invention, in a fifth embodiment of the accelerated storage method of the present invention, before step S10, the following steps are included:

[0088] Step S120, establishing a first FAT area and a data storage area in the storage module, wherein the first FAT area includes a boot area, a file table area, and a file table backup area, and the data storage area is used to store write data;

[0089] Step S130: establishing a second FAT area and a first mapping table in the DDR module, wherein the first mapping table is used to record a mapping relationship between addresses in the first FAT area and the second FAT area.

[0090] Furthermore, the first FAT area in the storage module is mapped to the second FAT area in the DDR module in units of sectors.

[0091] Common file systems, such as NTFS, FAT32, EXFAT and other file systems, are mainly composed of a boot area, a file table area, a file table backup area and a data storage area. Furthermore, a reserved area can be set as needed.

[0092] The boot area is the first sector of the file system, which contains important information such as file system identification, file table entry address, sector size, cluster size, etc. The file table area contains the file attributes and corresponding data area, etc. The file table backup area is a backup of important information in the file table.

[0093] In the present invention, through the study of the general file system, the offset address size of the file table can reach GB level; however, the capacity of the STT-MRAM memory is limited, and it is impossible to establish a one-to-one correspondence with the file table in the general file system. Therefore, a file table buffer and a corresponding mapping table management area are established for the STT-MRAM memory with reference to the general file system, and a mapping management table is established in the mapping table management area; the corresponding block diagram of the file table buffer in the file table cache module and the first FAT area in the storage module is as shown in FIG. Figure 2 As shown. The second mapping table is used to manage the correspondence between the file table buffer of the STT-MRAM memory and the first FAT area in the storage module. The second mapping table also records the sector address of the file table of the first FAT area, the data length of the file table, and the update status of the file table.

[0094] Based on the first embodiment of the accelerated storage method of the present invention, in a sixth embodiment of the accelerated storage method of the present invention, step S10 includes:

[0095] Step S11, when a read / write operation instruction is detected, the CPU module obtains the file table area to be updated of the read / write operation instruction in the first FAT area;

[0096] Step S12, the CPU module determines the file table area to be updated in the second FAT area from the second FAT area of ​​the DDR module according to the file table area to be updated in the first FAT area;

[0097] Step S13, according to the file table area to be updated in the second FAT area, establishing a third FAT area in the file table cache module, and establishing a second mapping table, the second mapping table being used to map a part of the address segment of the third FAT area to the second FAT area;

[0098] Step S14: updating the third FAT area in the file table cache module according to the read and write operation instructions.

[0099] See also Figure 8 In this embodiment, the mapping process of the first FAT area in the storage module to the second FAT area in the DDR module is reflected, and the mapping process of the third FAT area in the file table cache module to the second FAT area in the DDR module is reflected.

[0100] Figure 8 In the second FAT table, the entire area of ​​the first FAT table is mapped (through Figure 8 The second FAT area includes several file table areas (only three are shown in the figure, but not limited to three), while the third FAT area only maps the file table area to be updated corresponding to the read and write operations (through Figure 8The area within the two dashed arrows in the figure is represented by ).

[0101] Based on the first embodiment of the accelerated storage method of the present invention, in a seventh embodiment of the accelerated storage method of the present invention, step S50 includes:

[0102] Step S51, when the file table transfer condition is met, the CPU module updates the file table area updated in bytes in the file table cache module to the DDR module, and transfers it from the DDR module to the first FAT area of ​​the storage module in sectors.

[0103] Furthermore, since the FAT file in the DDR module can only be updated in sectors when it is updated to the storage module, while in the STT-MRAM memory, the FAT file can be updated in bytes, thus, the FAT file update method of the present invention is also conducive to achieving more fine-grained update control, reducing the number of wear times of the storage module, and since the update in bytes only needs to write a smaller amount of data, the update process is also faster. At the same time, the byte-level update does not need to retain the data of the entire sector for each small change, which also saves the storage space of the STT-MRAM memory. Furthermore, the byte-level update also makes the amount of data written smaller, reducing the risk of data loss due to write failure.

[0104] To achieve the above objectives, the present invention also proposes an accelerated storage system for executing the method; the accelerated storage system includes a CPU module, and a DDR module, a storage module and a file table cache module respectively connected to the CPU module for communication; the storage module includes a first FAT area and a data storage area.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a computer-readable storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device to enter the method described in each embodiment of the present invention.

[0106] In the description of this specification, the description with reference to the terms "an embodiment", "another embodiment", "other embodiments", or "first embodiment to Xth embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, method steps or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0107] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0108] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0109] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for accelerating storage, characterized in that: The accelerated storage system includes a CPU module, and a DDR module, a storage module and a file table cache module respectively connected to the CPU module for communication; the storage module includes a first FAT area and a data storage area; the method includes the following steps: Establishing a first FAT area and a data storage area in the storage module, wherein the first FAT area includes a boot area, a file table area and a file table backup area, and the data storage area is used to store write data; Establishing a second FAT area and a first mapping table in the DDR module, wherein the first mapping table is used to record a mapping relationship between addresses in the first FAT area and the second FAT area; When a read / write operation instruction is detected, the CPU module determines the file table area to be updated corresponding to the read / write operation instruction from the DDR module, and establishes the file table area to be updated in the file table cache module, so as to update the file table area to be updated in the file table cache module, including: when a read / write operation instruction is detected, the CPU module obtains the file table area to be updated in the first FAT area of ​​the read / write operation instruction; the CPU module determines the file table area to be updated in the second FAT area of ​​the DDR module according to the file table area to be updated in the first FAT area; according to the file table area to be updated in the second FAT area, a third FAT area is established in the file table cache module, and a second mapping table is established, the second mapping table being used to map a part of the address segment of the third FAT area to the second FAT area; and the third FAT area is updated in the file table cache module according to the read / write operation instruction; According to the read-write operation instruction, the CPU module allocates a read-write address for the read-write operation instruction; Performing read and write operations on the data storage area of ​​the storage module according to the allocated read and write addresses; Determine whether the file table transfer conditions are met; When the file table transfer condition is met, the CPU module updates the file table area updated in the file table cache module to the DDR module, and transfers the updated file table area from the DDR module to the first FAT area of ​​the storage module.

2. The accelerated storage method according to claim 1, characterized in that: The method further comprises: Detect file table access instructions; When the file table access instruction is detected, the CPU module reads the file table information corresponding to the file table access instruction from the file table cache module; Determine whether the reading is successful; If so, the file table information corresponding to the file table access instruction read from the file table cache module is returned to the user; If not, the CPU module reads the file table information corresponding to the file table access instruction from the first FAT area of ​​the storage module, and returns the file table information corresponding to the file table access instruction read from the first FAT area of ​​the storage module to the user.

3. The accelerated storage method according to claim 2, characterized in that: The method further comprises: A file table buffer and a mapping table management area are established in the file table cache module to update the file table area to be updated corresponding to the read and write operation instructions in the file table buffer, and the mapping table management area manages the mapping relationship between the file table area updated in the file table buffer and the first FAT area in the storage module.

4. The accelerated storage method according to claim 1, characterized in that: The step of determining whether the file table transfer condition is met includes: Detecting whether the acceleration storage system is idle; and / or Detect whether the data writing amount in the file table cache module reaches a preset threshold.

5. The accelerated storage method according to claim 1, characterized in that: The step of the CPU module updating the updated file table area in the file table cache module to the DDR module and transferring the updated file table area from the DDR module to the first FAT area of ​​the storage module when the file table transfer condition is met includes: When the file table transfer condition is met, the CPU module updates the file table area updated in bytes in the file table cache module to the DDR module, and transfers it from the DDR module to the first FAT area of ​​the storage module in sectors.

6. The accelerated storage method according to any one of claims 1 to 5, characterized in that: The file table cache module is an STT-MRAM memory.

7. The accelerated storage method according to claim 6, characterized in that: The STT-MRAM memory includes an EMD4E001G16G2-115CAS2 chip.

8. An accelerated storage system, characterized in that: Used to execute the method as described in any one of claims 1 to 7; the accelerated storage system includes a CPU module, and a DDR module, a storage module and a file table cache module respectively connected to the CPU module for communication; the storage module includes a first FAT area and a data storage area.

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