Integrated circuit device

Abstract

An integrated circuit device includes a substrate, a fin-type active region extending in a first horizontal direction on a first surface of the substrate, a source / drain region on the fin-type active region, an active contact on the source / drain region and electrically connected to the source / drain region, a wiring extending at a higher vertical level than the source / drain region, a via contact penetrating the insulating layer on the source / drain region and serving as a medium of an electrical connection between the active contact and the wiring, and an adhesive layer between the wiring and the insulating layer and contacting the wiring, where the via contact includes a top via contact and a bottom via contact, the top via contact includes a metal different from a metal included in the bottom via contact, and the wiring and the top via contact are in direct contact with each other.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit device, and more particularly, to an integrated circuit device including a structure formed by a self-alignment method. Background Art

[0002] In the semiconductor industry, there is a continuous demand for reduced size, multifunctionality and high performance of electronic devices, high capacity and high integration of integrated circuit devices. Therefore, there is a need for a wiring structure that is effectively designed to improve high integration while ensuring functionality and operating speed. Summary of the invention

[0003] Generally, in some aspects, the subject matter of the present disclosure relates to an integrated circuit device including: a substrate, a fin-type active region extending in a first horizontal direction on a first surface of the substrate, a source / drain region on the fin-type active region, an active contact on the source / drain region and electrically connected to the source / drain region, a wiring extending at a higher vertical level than the source / drain region, a via contact penetrating an insulating layer on the source / drain region and configured to serve as a medium for electrical connection between the active contact and the wiring, and an adhesive layer between the wiring and the insulating layer and contacting the wiring, wherein the via contact includes a top via contact and a bottom via contact, the top via contact includes a metal different from a metal included in the bottom via contact, and the wiring and the top via contact are in direct contact with each other.

[0004] Generally, in some aspects, the subject matter of the present disclosure relates to an integrated circuit device comprising: a substrate, a fin-type active region extending in a first direction on a first surface of the substrate, a source / drain region on the fin-type active region, a gate line extending in a second horizontal direction intersecting the first horizontal direction on the fin-type active region, a wiring extending at a vertical level higher than the source / drain region, a gate contact penetrating an insulating layer on the gate line and serving as a medium for electrical connection between the gate line and the wiring, and an adhesive layer arranged between the wiring and the insulating layer and contacting the wiring, wherein the gate contact comprises a top gate contact and a bottom gate contact, the top gate contact comprises a metal different from a metal included in the bottom gate contact, and the wiring and the top gate contact are in direct contact with each other.

[0005] In general, in some aspects, the disclosed subject matter relates to an integrated circuit device including: a substrate, a fin-type active region extending in a first horizontal direction on a first surface of the substrate, a source / drain region on the fin-type active region, a gate line extending in a second horizontal direction intersecting the first horizontal direction on the fin-type active region, a wiring extending in the first horizontal direction at a higher vertical level than the source / drain region, an active contact on the source / drain region and electrically connected to the source / drain region, a via contact penetrating an insulating layer on the source / drain region and serving as a dielectric for electrical connection between the gate line and the wiring, and a via contact penetrating the insulating layer and serving as a dielectric for electrical connection between the gate line and the wiring. A gate contact of a dielectric electrically connected between the wiring and the insulating layer, and a titanium nitride (TiN) layer between the wiring and the insulating layer and in contact with the wiring, wherein the via contact includes a top via contact containing ruthenium (Ru) and a bottom via contact containing molybdenum (Mo), the gate contact includes a top gate contact containing Ru and a bottom gate contact containing Mo, the width of the top via contact in the second horizontal direction is greater than the width of the wiring in the second horizontal direction, the width of the top gate contact in the second horizontal direction is greater than the width of the wiring in the second horizontal direction, the wiring and the top via contact are in direct contact with each other, and the wiring and the top gate contact are in direct contact with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram showing a planar layout of an example of a unit block of an integrated circuit device.

[0007] Figure 2 is a plan layout diagram of an example of an integrated circuit device.

[0008] Figure 3 , Figure 4A , Figure 4B and Figure 5 is a cross-sectional view of an example of an integrated circuit device.

[0009] Figures 6 to 10 is a cross-sectional view of an example of an integrated circuit.

[0010] Fig.11 is a plan layout diagram of an example of an integrated circuit device.

[0011] Fig.12 , Fig.13 , Fig.14A and Fig. 14B is a cross-sectional view of an example of an integrated circuit device.

[0012] Figures 15 to 19 is a cross-sectional view of an example of an integrated circuit device.

[0013] Fig. 20 is a plan layout diagram of an example of an integrated circuit device.

[0014] Fig.21 and Fig. 22 is a cross-sectional view of an example of an integrated circuit device.

[0015] FIG. 23A to FIG. 23I are cross-sectional views shown in order of processes according to an example of a method of manufacturing an integrated circuit device.

[0016] FIG. 24A to FIG. 24J are cross-sectional views shown in order of processes according to an example of a method of manufacturing an integrated circuit device.

[0017] In the drawings, the same reference numerals will be assigned to the same components, and description thereof will not be given repeatedly. DETAILED DESCRIPTION

[0018] Figure 1 is a diagram showing an example plan layout of a unit block 12 of the integrated circuit device 10 .

[0019] Reference Figure 1 The cell block 12 of the integrated circuit device 10 includes a plurality of logic cells LC, and the logic cells LC include a plurality of circuit patterns for constructing various types of circuits. The plurality of logic cells LC may be arranged in the cell block 12 in the form of a matrix in the width direction (X direction) and the height direction (Y direction).

[0020] The plurality of logic cells LC may include a circuit pattern having a layout designed according to a layout and routing (PnR) method to perform at least one logic function. The plurality of logic cells LC may be configured to perform various logic functions. In some implementations, the plurality of logic cells LC may include a plurality of standard cells. In some implementations, at least some of the plurality of logic cells LC may be configured to perform the same logic function. In some implementations, at least some of the plurality of logic cells LC may be configured to perform different logic functions, respectively.

[0021] The plurality of logic cells LC may include various logic cells including a plurality of circuit elements. For example, the plurality of logic cells LC may each include AND, NAND, OR, NOR, XOR, XNOR, INV, ADD, BUF, DLY, FIL, MXT / MXIT, OAI, AO, AOI, D flip-flop, reset flip-flop, master-slave flip-flop, latch or a combination thereof, but other implementations are also possible.

[0022] In the cell block 12, at least some of the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 in the width direction (X direction) may have the same width. In addition, at least some of the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 may have the same height. However, other implementations are possible, and at least some of the plurality of logic cells LC forming the row R1, R2, R3, R4, R5, or R6 may have different widths and heights.

[0023] The area of ​​each of the plurality of logic cells LC included in the cell block 12 of the integrated circuit device 10 may be defined by a cell boundary CBD. A cell boundary contact CBC where the cell boundaries CBD of two logic cells LC meet each other is between two logic cells LC adjacent to each other in the width direction (X direction) or the height direction (Y direction) among the plurality of logic cells LC.

[0024] In some implementations, among the plurality of logic cells LC included in a row R1, R2, R3, R4, R5, or R6, two logic cells LC adjacent to each other in the width direction may contact each other in the cell boundary contact CBC without a distance therebetween. In some implementations, among the plurality of logic cells LC included in a row R1, R2, R3, R4, R5, or R6, two logic cells LC adjacent to each other in the width direction may be spaced apart from each other with a certain distance therebetween.

[0025] In some implementations, among the plurality of logic cells LC included in a row R1, R2, R3, R4, R5, or R6, two logic cells LC adjacent to each other may be configured to perform the same function. In this case, the two logic cells LC adjacent to each other may have the same structure. In some implementations, among the plurality of logic cells LC included in a row R1, R2, R3, R4, R5, or R6, two logic cells LC adjacent to each other may be configured to perform different functions.

[0026] In some implementations, the logic cell LC selected from the plurality of logic cells LC included in the unit block 12 of the integrated circuit device 10 and the logic cell LC in the height direction ( Figure 1 Another logic cell LC adjacent to the selected logic cell LC in the Y direction (in the Y direction shown in FIG. 1 ) may have a symmetrical structure with respect to the cell boundary contact CBC therebetween. For example, the reference logic cell LC_R in the third row R3 and the lower logic cell LC_L in the second row R2 may have a symmetrical structure with respect to the cell boundary contact CBC therebetween. In addition, the reference logic cell LC_R in the third row R3 and the upper logic cell LC_H in the fourth row R4 may have a symmetrical structure with respect to the cell boundary contact CBC therebetween.

[0027] although Figure 1 A cell block 12 including six rows R1, R2, R3, R4, R5 and R6 is shown, but this is only an example. The cell block 12 may include various numbers of rows selected as needed, and a row may include various numbers of logic cells selected for a particular application.

[0028] A line selected from among a plurality of ground lines VSS and a plurality of power lines VDD may be arranged between every two rows of a plurality of rows R1, R2, R3, R4, R5, and R6 including a plurality of logic cells LC arranged in series in a width direction (X direction). The plurality of ground lines VSS and the plurality of power lines VDD may extend in a first horizontal direction (X direction) and may be alternately arranged spaced apart from each other in a second direction (Y direction). Therefore, each of the plurality of ground lines VSS and the plurality of power lines VDD may be arranged to overlap with a cell boundary CBD in a second horizontal direction (Y direction) of the logic cell LC.

[0029] Figure 2 is a plan layout diagram for describing the integrated circuit device 100 . Figure 3 , Figure 4A , Figure 4B and Figure 5 is a cross-sectional view for describing the integrated circuit device 100. More specifically, Figure 3 is along Figure 2 A cross-sectional view taken along the line X1-X1 shown in FIG. Figure 4A is along Figure 2 A cross-sectional view taken along the line Y1-Y1 shown in FIG. Figure 4B yes Figure 4A An enlarged cross-sectional view of a region EX1 is shown in FIG. Figure 5 is along Figure 2 A cross-sectional view taken along the line Y2-Y2 shown in FIG.

[0030] Will refer to Figure 2 , Figure 3 , Figure 4A , Figure 4B and Figure 5 An integrated circuit device 100 is described that includes a field effect transistor having a gate-all-around structure including an active region in the form of a nanowire or nanosheet and a gate surrounding the active region. A plurality of logic cells LC may be constructed Figure 1 Some of the multiple logic cells LC shown in .

[0031] The integrated circuit device 100 may include a substrate 102 having a first surface 102_1 and a second surface 102_2 and a plurality of fin type active areas FA protruding on the first surface 102_1 of the substrate 102. The plurality of fin type active areas FA may extend along a first horizontal direction (X direction) and may extend parallel to each other.

[0032] The substrate 102 may include a semiconductor such as Si or Ge or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. In this specification, the terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" represent materials formed of the elements included in the terms, and do not include chemical formulas representing stoichiometric relationships. The substrate 102 may include a conductive region such as an impurity-doped well or an impurity-doped structure.

[0033] The device isolation film 112 may be arranged in a trench defining a plurality of fin-type active areas FA. The device isolation film 112 may cover a portion of a sidewall of each of the plurality of fin-type active areas FA. The device isolation film 112 may be formed of a silicon oxide film. The device isolation film 112 may include a material having an etching selectivity different from that of the material of the substrate 102.

[0034] The second surface 102_2 of the substrate 102 may be covered with a backside insulating film 109. The backside insulating film 109 may include a silicon oxide film, a silicon nitride film, a silicon carbide film, a low dielectric film, or a combination thereof. The low dielectric film may include fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon oxide, porous organic silicate glass, spin-coated organic polymer dielectrics, spin-coated silicon-based polymer dielectrics, or a combination thereof, but is not limited thereto.

[0035] like Figure 2 , Figure 3 and Figure 5 As shown, a plurality of gate lines 160 may be on a plurality of fin-type active areas FA. Each of the plurality of gate lines 160 may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). In the region where the plurality of fin-type active areas FA intersect with the plurality of gate lines 160, a plurality of nanosheet stacks NSS may be arranged on the fin top surfaces FT in the plurality of fin-type active areas FA. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing the fin top surface FT at a position separated from the fin top surface FT of the fin-type active area FA in a vertical direction (Z direction). In this specification, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. Nanosheets will be understood to include nanowires.

[0036] like Figure 3 and Figure 5As shown, each of the plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 overlapping each other in a vertical direction (Z direction) on the fin-type active area FA. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different vertical distances (distances in the Z direction) from the fin top surface FT of the fin-type active area FA. Each of the plurality of gate lines 160 may cover the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 overlapping each other in the vertical direction (Z direction) and included in the nanosheet stack NSS.

[0037] although Figure 2 It is shown that the shape of the flat surface of the nanosheet stack NSS is approximately square, but the example is not limited thereto. The nanosheet stack NSS may have a flat surface of various shapes according to the flat surface of the fin-type active area FA and the shape of the gate line 160. In this example, a plurality of nanosheet stacks NSS and a plurality of gate lines 160 are on one fin-type active area FA, and a plurality of nanosheet stacks NSS are arranged in a row in a first horizontal direction (X direction) on one fin-type active area FA. However, the number of nanosheet stacks NSS and gate lines 160 arranged on one fin-type active area FA is not limited to the example shown.

[0038] The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may each be used as a channel region. In some implementations, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have a thickness selected from a range of about 4 nm to about 6 nm, but the example is not limited thereto. In the present disclosure, the term "about" means (e.g., within 1%, 5%, or 10% of a disclosed value) almost equal to a disclosed value.

[0039] Here, the thickness of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 represents the size in the vertical direction (Z direction). In some implementations, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have substantially the same vertical thickness (Z direction). In some implementations, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different vertical thicknesses (Z direction). In some implementations, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may each include a Si layer, a SiGe layer, or a combination thereof.

[0040] like Figure 3 As shown in FIG. 1 , the sizes of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in a nanosheet stack NSS may be the same or similar to each other in the first horizontal direction (X direction). Figure 3Differently, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS may have different sizes in the first horizontal direction (X direction). Although the case where each of the plurality of nanosheet stacks NSS includes three nanosheets is described with reference to this example, other implementations are also possible. For example, the nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets included in the nanosheet stack NSS is not limited to this example.

[0041] like Figure 3 and Figure 5 As shown, each of the plurality of gate lines 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M may cover the top surface of the nanosheet stack NSS and extend in a second horizontal direction (Y direction). The plurality of sub-gate portions 160S may be integrally connected to the main gate portion 160M, and the plurality of sub-gate portions 160S may each be disposed between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and between the first nanosheet N1 and the fin-type active area FA. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 160S may be less than the thickness of the main gate portion 160M.

[0042] The plurality of gate lines 160 may each include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may include TiAlC. However, the materials included in the plurality of gate lines 160 are not limited thereto.

[0043] like Figure 3 and Figure 4A As shown in , a plurality of recesses R may be formed on the fin type active area FA. A vertical level of a bottom surface of each of the plurality of recesses R may be lower than a vertical level of a fin top surface FT of the fin type active area FA.

[0044] like Figure 3 and Figure 4AAs shown in , a plurality of source / drain regions 130 may be arranged in a plurality of recesses R. Each of the plurality of source / drain regions 130 may be arranged at a position adjacent to at least one gate line 160 selected from among a plurality of gate lines 160. The plurality of source / drain regions 130 may have a surface each facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS. Each of the plurality of source / drain regions 130 may contact the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS. In the implementation shown herein, the phrase "source / drain region" may be understood to mean a source terminal region and / or a drain terminal region of a transistor.

[0045] The gate dielectric film 152 may be arranged between the nanosheet stack NSS and the gate line 160. In some implementations, the gate dielectric film 152 may include a stacked structure including an interface dielectric film and a high dielectric film. The interface dielectric film may include a low dielectric material having a dielectric constant of about 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof. In some implementations, the interface dielectric film may be omitted. The high dielectric film may include a material having a dielectric constant greater than that of the silicon oxide film. For example, the high dielectric film may have a dielectric constant between about 10 and about 25. The high dielectric film may include hafnium oxide, but is not limited thereto.

[0046] like Figure 3 and Figure 5 As shown, top surfaces of the gate dielectric film 152 and the gate line 160 may be covered with a capping insulating pattern 168. The capping insulating pattern 168 may include a silicon nitride film.

[0047] Both sidewalls of each of the gate line 160 and the capping insulating pattern 168 may be covered by the outer insulating spacer 118. The outer insulating spacer 118 may cover both sidewalls of the main gate portion 160M on each top surface of the plurality of nanosheet stacks NSS. The outer insulating spacer 118 may be spaced apart from the gate line 160 with the gate dielectric film 152 therebetween.

[0048] like Figure 4A As shown in , a plurality of recess side insulating spacers 119 covering the sidewalls of the source / drain regions 130 may be disposed on the top surface of the device isolation film 112. In some implementations, each of the plurality of recess side insulating spacers 119 may be integrally connected to an outer insulating spacer 118 adjacent to the recess side insulating spacer 119.

[0049] The plurality of outer insulating spacers 118 and the plurality of recess side insulating spacers 119 may each include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. In this specification, the terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" represent materials including the elements included in the terms, and do not include chemical formulas representing stoichiometric relationships.

[0050] A metal silicide film 172 may be formed on the top surface of each source / drain region 130. The metal silicide film 172 may include a metal including Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 172 may include titanium silicide, but is not limited thereto.

[0051] On the substrate 102, the plurality of source / drain regions 130, the plurality of metal silicide films 172, and the plurality of outer insulating spacers 118 may be covered with an insulating liner 142. In some implementations, the insulating liner 142 may be omitted. An inter-gate insulating film 144 may be disposed on the insulating liner 142. When the insulating liner 142 is omitted, the inter-gate insulating film 144 may contact the plurality of source / drain regions 130.

[0052] The insulating liner 142 and the inter-gate insulating film 144 may be sequentially arranged on the plurality of source / drain regions 130 and the plurality of metal silicide films 172. The insulating liner 142 and the inter-gate insulating film 144 may form an insulating structure together. In some implementations, the insulating liner 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but is not limited thereto. The inter-gate insulating film 144 may include a silicon oxide film, but is not limited thereto.

[0053] Both sidewalls of each of the plurality of sub-gate portions 160S included in the plurality of gate lines 160 may be spaced apart from the source / drain region 130 with a gate dielectric film 152 therebetween. The gate dielectric film 152 may be disposed between the sub-gate portion 160S included in the gate line 160 and each of the first, second, and third nanosheets N1, N2, and N3 and between the sub-gate portion 160S included in the gate line 160 and the source / drain region 130.

[0054] A plurality of nanosheet stacks NSS may be arranged on the fin top surfaces FT of the plurality of fin active areas FA in the region where the plurality of fin active areas FA intersect the plurality of gate lines 160, and may face the fin top surfaces FT at a position spaced apart from the fin active areas FA. A plurality of nanosheet transistors may be formed in the region of the substrate 102 where the plurality of fin active areas FA intersect the plurality of gate lines 160.

[0055] like Figure 3 and Figure 4A As shown in , the active contact CA may be arranged on the source / drain region 130. The active contact CA may penetrate each of the inter-gate insulating film 144 and the insulating liner 142 in the vertical direction (Z direction) and contact the metal silicide film 172. The active contact CA may be electrically connected to the source / drain region 130 through the metal silicide film 172.

[0056] The active contact CA may include a conductive barrier pattern 174 and a contact plug 176 sequentially stacked on the source / drain region 130. The conductive barrier pattern 174 may cover and contact the bottom surface and sidewall of the contact plug 176. The active contact CA may penetrate the inter-gate insulating film 144 and the insulating liner 142 and extend in a vertical direction (e.g., Z direction). The conductive barrier pattern 174 may be arranged between the metal silicide film 172 and the contact plug 176. The conductive barrier pattern 174 may have a surface contacting the metal silicide film 172 and a surface contacting the contact plug 176. In some implementations, the conductive barrier pattern 174 may include a metal or a metal nitride. For example, the conductive barrier pattern 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto. The contact plug 176 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), combinations thereof, or alloys thereof, but is not limited thereto. Figure 4B Active contact CA is described in detail.

[0057] like Figure 3 , Figure 4A and Figure 5As shown, the top surface of each of the active contact CA, the cap insulating pattern 168, and the gate inter-insulating film 144 may be covered by a top insulating structure 180. The top insulating structure 180 may include an etch stop layer 182 and an interlayer insulating film 184 sequentially stacked on each of the active contact CA, the plurality of cap insulating patterns 168, and the gate inter-insulating film 144. The etch stop layer 182 may include silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating film 184 may include an oxide film, a nitride film, an ultra-low K (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating film 184 may include a tetraethyl orthosilicate (TEOS) film, a high density plasma (HDP) oxide film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, but is not limited thereto.

[0058] like Figure 3 and Figure 4A As shown in , the via contact VA may be arranged on the active contact CA. Each via contact VA may penetrate the top insulating structure 180 and contact the active contact CA. The source / drain region 130 may be electrically connected to the via contact VA through the metal silicide film 172 and the active contact CA. The bottom surface of each via contact VA may contact the top surface of the active contact CA. The via contact VA may include W, Mo and / or Ru, but is not limited thereto. Figure 4B Describe the via contact VA in detail.

[0059] The plurality of wirings M1 may be arranged to penetrate the top insulating film 192. Each of the plurality of wirings M1 may be connected to a via contact VA selected from among a plurality of via contacts VA below the plurality of wirings M1. In some implementations, the wiring M1 may extend in a first horizontal direction (X direction). In some implementations, the wiring M1 may include an extension M1_E extending in the first horizontal direction (X direction) and a connection M1_C arranged between the extension M1_E and the via contact VA. In some implementations, the connection M1_C may be arranged on a first portion M1_E1 of the extension M1_E.

[0060] The plurality of wirings M1 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof, but are not limited thereto. Figure 4B The wiring M1 is described in detail.

[0061] like Figure 3 and Figure 4AAs shown in , the adhesive layer 190 may be arranged on the area of ​​the wiring M1. The adhesive layer 190 may include titanium nitride (TiN). More specifically, the adhesive layer 190 may be arranged between the wiring M1 and the top insulating structure 180. More specifically, the adhesive layer 190 may be arranged between the wiring M1 and the interlayer insulating film 184. The adhesive layer 190 may contact the wiring M1 and the interlayer insulating film 184 between the wiring M1 and the interlayer insulating film 184. The adhesive layer 190 may overlap with the wiring M1 and the interlayer insulating film 184 in the vertical direction (Z direction). In some implementations, the wiring M1 may overlap with the top insulating structure 180 with the adhesive layer 190 therebetween. More specifically, the wiring M1 may be separated from the interlayer insulating film 184 with the adhesive layer 190 therebetween.

[0062] More specifically, the adhesive layer 190 may be disposed on the second portion M1_E2 of the extension M1_E. The second portion M1_E2 may include a portion of the surface of the extension M1_E other than the first portion M1_E1 that faces the top insulating structure 180. That is, in some implementations, the adhesive layer 190 is not disposed on the first portion M1_E1 of the extension M1_E.

[0063] In some implementations, the adhesive layer 190 is disposed between the extension portion M1_E of the wiring M1 and the top insulating structure 180, but is not disposed between the connection portion M1_C of the wiring M1 and the top insulating structure 180. More specifically, the adhesive layer 190 may be disposed between the extension portion M1_E of the wiring M1 and the interlayer insulating film 184, and may not be disposed between the extension portion M1_E and the connection portion M1_C of the wiring M1 and between the connection portion M1_C and the interlayer insulating film 184. More specifically, the adhesive layer 190 may not be disposed between the connection portion M1_C of the wiring M1 and the via contact VA.

[0064] In some implementations, the adhesive layer 190 may horizontally surround the connection portion M1_C of the wiring M1 between the extension portion M1_E of the wiring M1 and the interlayer insulating film 184 .

[0065] Combination Figure 4B , the wiring M1 may be connected to the active contact CA through the via contact VA.

[0066] As described above, the wiring M1 may include the extension portion M1_E extending in the first horizontal direction (X direction) and the connection portion M1_C disposed on the first portion M1_E1 of the extension portion M1_E.

[0067] In some implementations, the extension portion M1_E and the connection portion M1_C may include the same type of metal. For example, the extension portion M1_E and the connection portion M1_C may both include Ru. More specifically, the extension portion M1_E and the connection portion M1_C may be formed of the same type of metal. For example, the extension portion M1_E and the connection portion M1_C may both be formed of Ru.

[0068] In some implementations, the top surface of the connection portion M1_C may be at a vertical level higher than the top surface of the interlayer insulating film 184. More specifically, the top surface of the connection portion M1_C may be at the same vertical level as the top surface of the adhesive layer 190. For example, the top surface of the connection portion M1_C and the top surface of the adhesive layer 190 may both be at a first vertical level LV1.

[0069] In some implementations, a vertical thickness T11 of the extension portion M1_E may be greater than a vertical thickness T12 of the adhesive layer 190 .

[0070] In some implementations, the adhesive layer 190 may be disposed on the second portion M1_E2 (i.e., the portion of the extension portion M1_E where the connection portion M1_C is not disposed), and thus the extension portion M1_E and the connection portion M1_C may directly contact each other. In other words, the bottom surface of the extension portion M1_E may directly contact the top surface of the connection portion M1_C.

[0071] In some implementations, the angle θ11 formed by the outer sidewall of the wiring M1 and the top surface of the via contact VA may be 90° or greater. In this specification, the outer sidewall of the wiring M1 may refer to a sidewall directly contacting the top insulating film 192 surrounding the wiring M1. For example, the angle θ11 formed by the outer sidewall of the wiring M1 and the top surface of the via contact VA may be 90° or greater but not greater than 110°.

[0072] In some implementations, the adhesive layer 190 is not arranged on the contact portion of the wiring M1 with the via contact VA. More specifically, in some implementations, the adhesive layer 190 is not formed on the connection portion M1_C. More specifically, in some implementations, the adhesive layer 190 is not formed between the connection portion M1_C and the via contact VA. Therefore, the connection portion M1_C and the via contact VA can be in direct contact with each other. More specifically, the bottom surface of the connection portion M1_C and the top surface of the via contact VA can be in direct contact with each other. In some implementations, the wiring M1 and the top via contact VA_T can be formed integrally and in contact with each other.

[0073] In some implementations, the via contact VA may include a top via contact VA_T and a bottom via contact VA_B. In some implementations, the top via contact VA_T may be arranged between the wiring M1 and the bottom via contact VA_B. The top via contact VA_T may directly contact the wiring M1. More specifically, the top via contact VA_T may directly contact the connection portion M1_C of the wiring M1. For example, the top surface of the top via contact VA_T may directly contact the bottom surface of the connection portion M1_C. In some implementations, the bottom via contact VA_B may be arranged between the top via contact VA_T and the active contact CA. The bottom via contact VA_B may directly contact the active contact CA. For example, the bottom surface of the bottom via contact VA_B may directly contact the top surface of the active contact CA.

[0074] In some implementations, the top surface of the via contact VA may be at a vertical level lower than the top surface of the interlayer insulating film 184. That is, the top surface of the top via contact V_T may be at a vertical level lower than the top surface of the interlayer insulating film 184. The top surface of the top via contact V_T may be at a vertical level lower than the bottom surface of the adhesive layer 190. That is, the bottom surface of the connection portion M1_C may be at a vertical level lower than the bottom surface of the adhesive layer 190. Therefore, the vertical thickness T13 of the connection portion M1_C may be greater than the vertical thickness T12 of the adhesive layer 190.

[0075] In some implementations, the top via contact VA_T and the bottom via contact VA_B may include different kinds of metals, respectively. For example, the top via contact VA_T may include Ru, and the bottom via contact VA_B may include Mo. More specifically, the top via contact VA_T and the bottom via contact VA_B may be formed of different kinds of metals, respectively. For example, the top via contact VA_T may be formed of Ru, and the bottom via contact VA_B may be formed of Mo.

[0076] In some implementations, the top via contact VA_T may include a metal of the same type as the metal included in the wiring M1. For example, both the top via contact VA_T and the wiring M1 may include Ru. More specifically, the top via contact VA_T and the wiring M1 may be formed of the same type of metal. For example, both the top via contact VA_T and the wiring M1 may be formed of Ru. In some implementations, the bottom via contact VA_B may include a metal different from the metal included in the wiring M1. More specifically, the bottom via contact VA_B may be formed of a metal different from the metal included in the wiring M1.

[0077] In some implementations, a vertical thickness T14 of the top via contact VA_T may be smaller than a vertical thickness T15 of the bottom via contact VA_B.

[0078] In some implementations, an angle θ12 formed by the outer sidewall of the via contact VA and the top surface of the gate insulating film 144 surrounding the active contact CA may be 90° or less. In this specification, the outer sidewall of the via contact VA may refer to a sidewall directly contacting the top insulating structure 180 surrounding the via contact VA. For example, the angle θ12 formed by the outer sidewall of the via contact VA and the top surface of the gate insulating film 144 may be 70° or more but not more than 90°.

[0079] In some implementations, the bottom via contact VA_B and the active contact CA may include the same kind of metal. More specifically, the bottom via contact VA_B and the contact plug 176 may include the same kind of metal. For example, the bottom via contact VA_B and the contact plug 176 may include Mo. More specifically, the bottom via contact VA_B and the contact plug 176 may be formed of the same kind of metal. For example, the bottom via contact VA_B and the contact plug 176 may be formed of Mo. In some implementations, the top via contact VA_T and the active contact CA may include different kinds of metal. More specifically, the top via contact VA_T and the active contact CA may be formed of different kinds of metal.

[0080] In some implementations, the width of the wiring M1 in the second horizontal direction may be smaller than the width of the via contact VA in the second horizontal direction. More specifically, the average width of the wiring M1 in the second horizontal direction may be smaller than the average width of the via contact VA in the second horizontal direction. More specifically, at the contact portion between the wiring M1 and the via contact VA, the width of the wiring M1 in the second horizontal direction may be smaller than the width of the via contact VA in the second horizontal direction. For example, the width L11 in the second horizontal direction at the lowest vertical level of the wiring M1 may be smaller than the width L12 in the second horizontal direction at the highest vertical level of the via contact VA. For example, the width L11 on the bottom surface of the connection portion M1_C of the wiring M1 in the second horizontal direction may be smaller than the width L12 on the top surface of the top via contact VA_T in the second horizontal direction.

[0081] In some implementations, outer sidewalls of the wiring M1 and the via contact VA may have a step difference. More specifically, outer sidewalls of the wiring M1 and the via contact VA contacting each other may have a step difference at a boundary between the wiring M1 and the via contact VA.

[0082] In reference Figures 2 to 5In the described integrated circuit device 100, the adhesive layer 190 is not provided at the contact portion of the wiring M1 that contacts the via. In some implementations, the integrated circuit device 100 and the wiring M1 have reduced resistance due to the removal of the adhesive layer 190 at the contact portion with the via contact VA, compared to the wiring having the adhesive layer at the contact portion with the via.

[0083] Refer to above Figures 2 to 5 In the described integrated circuit device 100, the top via contact VA_T and the bottom via contact VA_B respectively include different types of metals. More specifically, in some implementations, the via contact VA has reduced resistance and improved controllability, wherein the via contact VA includes a top via contact VA_T, the top via contact VA_T includes Ru, and the bottom via contact VA_B includes a metal different from Ru.

[0084] Figures 6 to 10 100A, 100B, 101 , 101A, and 101B are cross-sectional views for describing examples of integrated circuit devices 100A, 100B, 101 , 101A, and 101B.

[0085] Reference Figures 6 to 10 , the main description and reference Figures 2 to 5 The differences in the integrated circuit device 100 are described.

[0086] Reference Figure 6 , the integrated circuit device 100A may include a wiring M1A and a via contact VA, and the wiring M1A may not be aligned with the via contact VA. More specifically, only a portion of the wiring M1A may overlap with the via contact VA contacting the wiring M1A in the vertical direction (Z direction), and another portion of the wiring M1A may not overlap with the via contact VA.

[0087] More specifically, the wiring M1A may extend in a first horizontal direction (X direction), and may include an extension portion M1A_E extending in the first horizontal direction (X direction) and a connection portion M1A_C disposed between the extension portion M1A_E and the via contact VA. The connection portion M1A_C may be disposed on a portion of the extension portion M1A_E overlapping with the via contact VA of the contact wiring M1A in the vertical direction (Z direction), and an adhesive layer 190 may be disposed on another portion of the extension portion M1A_E.

[0088] Reference Figure 7 , the integrated circuit device 100B may include a wiring M1B and a via contact VA, and the wiring M1B may not be aligned with the via contact VA. More specifically, only a portion of the wiring M1B may overlap with the via contact VA contacting the wiring M1B in the vertical direction (Z direction), and another portion of the wiring M1B may not overlap with the via contact VA.

[0089] The wiring M1B may include an extension portion M1B_E extending in the first horizontal direction (X direction) and a connection portion M1B_C arranged between the extension portion M1B_E and the via contact VA. More specifically, one via contact VA may be connected to at least one wiring M1B. For example, one via contact VA may be connected to two wirings M1B. More specifically, one via contact VA may be connected to the connection portion M1B_C of each of the two wirings M1B.

[0090] Reference Figures 8 to 10 , the integrated circuit devices 101, 101A, and 101B may include wirings M11, M11A, and M11B and via contacts VA1. The via contacts VA1 include top via contacts VA1_T and bottom via contacts VA1_B, and the wirings M11, M11A, and M11B include connection portions M11_C, M11A_C, and M11B_C and extension portions M11_E, M11A_E, and M11B_E, respectively. The top surface of the via contact VA1 may be at the same vertical level as the top surface of the interlayer insulating film 184. That is, the top surface of the top via contact VA1_T may be at the same vertical level as the top surface of the interlayer insulating film 184. That is, the top surface of the top via contact VA1_T may be at the same vertical level as the bottom surface of the adhesive layer 190. That is, the bottom surfaces of the connection portions M11_C, M11A_C, and M11B_C may be at the same vertical level as the bottom surface of the adhesive layer 190. Therefore, the vertical thickness of the connection parts M11_C, M11A_C, and M11B_C may be the same as the vertical thickness of the adhesive layer 190 .

[0091] Fig.11 is a plan layout diagram for describing an example of an integrated circuit device 200 . Fig.12 , Fig.13 , Fig.14A and Fig. 14B is a cross-sectional view for describing an integrated circuit device 200 according to other embodiments. More specifically, Fig.12 is along Fig.11 A cross-sectional view taken along the line X1-X1 shown in FIG. Fig.13 is along Fig.11 A cross-sectional view taken along the line Y1-Y1 shown in FIG. Fig.14A is along Figure 2 A cross-sectional view taken along the line Y2-Y2 shown in FIG. Fig. 14B yes Fig.14A An enlarged cross-sectional view of a region EX2 is shown in FIG.

[0092] Reference Fig.11 , Fig.13 and Fig.14A, the integrated circuit device 200 may include a substrate 202 having a first surface 202_1 and a second surface 202_2 and a plurality of fin type active areas FA protruding on the first surface 202_1 of the substrate 202. The plurality of fin type active areas FA may extend parallel to each other in a first horizontal direction (X direction) on the substrate 202.

[0093] The device isolation film 212 may be disposed in the trench defining the plurality of fin type active areas FA. The device isolation film 212 may cover a portion of the sidewall of each of the plurality of fin type active areas FA. The second surface 202_2 of the substrate 202 may be covered with a backside insulating film 209 .

[0094] like Fig.11 , Fig.12 and Fig.14A As shown, a plurality of gate lines 260 may be arranged on a plurality of fin-type active regions FA. Each of the plurality of gate lines 260 may extend in a second horizontal direction (Y direction). Each of the plurality of gate lines 260 may include a main gate portion 260M and a plurality of sub-gate portions 260S.

[0095] like Fig.12 and Fig.14A As shown in , a plurality of nanosheet stacks NSS may be arranged on a fin top surface FT of each of the plurality of fin type active areas FA in an area where the plurality of fin type active areas FA intersects the plurality of gate lines 260. The plurality of nanosheet stacks NSS may include at least one nanosheet facing the fin top surface FT at a position spaced apart from the fin top surface FT of the fin type active area FA in a vertical direction (Z direction).

[0096] The plurality of nanosheet stacks NSS may each include a first nanosheet N1 , a second nanosheet N2 , and a third nanosheet N3 , which may each serve as a channel region.

[0097] like Fig.12 and Fig.13 As shown in , a plurality of source / drain regions 230 may be arranged on a plurality of fin-type active regions FA. Each of the plurality of source / drain regions 230 may be arranged at a position adjacent to at least one gate line 260 selected from among a plurality of gate lines 260. Each of the source / drain regions 230 may contact the first nanosheet N1, the second nanosheet N2, and the third nanosheet included in the adjacent nanosheet stack NSS.

[0098] The gate dielectric film 252 may be between the nanosheet stack NSS and the gate line 260. A top surface of each of the gate dielectric film 252 and the gate line 260 may be covered by a capping insulating pattern 268. Both sidewalls of each of the gate line 260 and the capping insulating pattern 268 may be covered by an outer insulating spacer 218. A plurality of recess side insulating spacers 219 covering sidewalls of the plurality of source / drain regions 230 may be disposed on a top surface of the device isolation film 212.

[0099] A metal silicide film may be formed on a top surface of each of the source / drain regions 230. An insulating liner 242 and an inter-gate insulating film 244 may be sequentially disposed on the plurality of source / drain regions 230 and the plurality of metal silicide films.

[0100] like Fig.11 and Fig.14A As shown in , the gate contact CB may be arranged on the gate line 260. In this specification, it is shown that the gate contact CB is arranged between the plurality of fin-type active areas FA and the plurality of nanosheet stacks NSS, but this is only an example, and other implementations are possible. For example, in some implementations, the gate contact CB may overlap with the plurality of fin-type active areas FA and the plurality of nanosheet stacks NSS in the vertical direction (Z direction).

[0101] The gate contact CB may penetrate the top insulating structure 280 and the cap insulating pattern 268 in a vertical direction (Z direction) and may be connected to the gate line 260. A bottom surface of the gate contact CB may contact a top surface of the gate line 260. The gate contact CB may include a contact plug including molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the material included in the contact plug is not limited thereto.

[0102] In some implementations, the gate contact CB may further include a conductive barrier pattern surrounding a portion of the contact plug. The conductive barrier pattern included in the gate contact CB may include a metal or a metal nitride. For example, the conductive barrier pattern may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto. Fig. 14B The gate contact CB is described in detail.

[0103] The plurality of wirings M2 may be arranged to penetrate the upper insulating film 292. In the present specification, it is shown that the plurality of wirings M2 are arranged between the plurality of fin-type active areas FA and the plurality of nanosheet stacks NSS, respectively, but this is only an example, and other implementations are possible. For example, in some implementations, when the gate contact CB overlaps the plurality of fin-type active areas FA and the plurality of nanosheet stacks NSS in the vertical direction, the plurality of wirings M2 may overlap the plurality of fin-type active areas FA and the plurality of nanosheet stacks in the vertical direction (Z direction), respectively.

[0104] Each of the plurality of wirings M2 may be connected to a gate contact CB selected from a plurality of gate contacts below the plurality of wirings M2. In some implementations, the wiring M2 may extend in a first horizontal direction (X direction). In some implementations, the wiring M2 may include an extension M2_E extending in the first horizontal direction (X direction) and a connection M2_C arranged between the extension M2_E and the gate contact CB. In some implementations, the connection M2_C may be arranged on a first portion M2_E1 of the extension M2_E.

[0105] The plurality of wirings M2 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, a combination thereof, or an alloy thereof, but is not limited thereto. Figures 2 to 5 Description of the wiring M1.

[0106] like Fig.12 and Fig.13 As shown in , the adhesive layer 290 may be arranged on a portion of the wiring M2. The adhesive layer 290 may include titanium nitride (TiN). More specifically, the adhesive layer 290 may be arranged between the wiring M2 and the top insulating structure 280. More specifically, the adhesive layer 290 may be arranged between the wiring M2 and the interlayer insulating film 284. Between the wiring M2 and the interlayer insulating film 284, the adhesive layer 290 may contact the wiring M2 and the interlayer insulating film 284. The adhesive layer 290 may overlap with the wiring M2 and the interlayer insulating film 284 in the vertical direction (Z direction). In some implementations, the wiring M2 may be separated from the top insulating structure 280 with the adhesive layer 290 therebetween. More specifically, the wiring M2 may be separated from the interlayer insulating film 284 with the adhesive layer 290 therebetween.

[0107] More specifically, the adhesive layer 290 may be disposed in the second portion M2_E2 of the extension M2_E. The second portion M2_E2 may include an area other than the first portion M2_E1 in the surface of the extension M2_E facing the top insulating structure 280. That is, in some implementations, the adhesive layer 290 is not disposed on the first portion M2_E1 of the extension M2_E.

[0108] In some implementations, the adhesive layer 290 is disposed between the extension portion M2_E of the wiring M2 and the top insulating structure 280, but not between the connection portion M2_C of the wiring M2 and the top insulating structure 280. More specifically, in some implementations, the adhesive layer 290 is disposed between the extension portion M2_E of the wiring M2 and the interlayer insulating film 284, and not between the extension portion M2_E of the wiring M2 and the connection portion M2_C, and between the connection portion M2_C and the interlayer insulating film 284. More specifically, in some implementations, the adhesive layer 290 is not disposed between the connection portion M2_C of the wiring M2 and the gate contact CB.

[0109] In some implementations, the adhesive layer 290 may horizontally surround the connection portion M2_C of the wiring M2 between the extension portion M2_E of the wiring M2 and the interlayer insulating film 284 .

[0110] Reference Fig. 14B , the wiring M2 may be connected to the gate line 260 through the gate contact CB.

[0111] In some implementations, the extension portion M2_E and the connection portion M2_C may include the same type of metal. For example, the extension portion M2_E and the connection portion M2_C may both include Ru. More specifically, the extension portion M2_E and the connection portion M2_C may be formed of the same type of metal. For example, the extension portion M2_E and the connection portion M2_C may both be formed of Ru.

[0112] In some implementations, the top surface of the connection portion M2_C may be at a vertical level higher than the top surface of the interlayer insulating film 284. More specifically, the top surface of the connection portion M2_C may be at the same vertical level as the top surface of the adhesive layer 290. For example, both the top surface of the connection portion M2_C and the top surface of the adhesive layer 290 may be at the second vertical level LV2.

[0113] In some implementations, a vertical thickness T21 of the extension portion M2_E may be greater than a vertical thickness T22 of the adhesive layer 290 .

[0114] In some implementations, the adhesive layer 290 may be disposed on a portion of the extension portion M2_E where the connection portion M2_C is not disposed (i.e., the second portion M2_E2), and thus the extension portion M2_E and the connection portion M2_C may be in direct contact with each other. In other words, the bottom surface of the extension portion M2_E may be in direct contact with the top surface of the connection portion M2_C.

[0115] In some implementations, the angle θ21 formed by the outer sidewall of the wiring M2 and the top surface of the gate contact CB may be 90° or greater. In this specification, the outer sidewall of the wiring M2 may refer to a sidewall directly contacting the upper insulating film 292 surrounding the wiring M2. For example, the angle formed by the outer sidewall of the wiring M2 and the top surface of the gate contact CB may be 90° or greater but not greater than 110°.

[0116] In some implementations, the adhesive layer 290 is not arranged on the contact portion of the wiring M2 that contacts the gate contact CB. More specifically, in some implementations, the adhesive layer 290 is not formed on the connection portion M2_C. More specifically, in some implementations, the adhesive layer 290 is not formed between the connection portion M2_C and the gate contact CB. Therefore, the connection portion M2_C and the gate contact CB can be in direct contact with each other. More specifically, the bottom surface of the connection portion M2_C and the top surface of the gate contact CB can be in direct contact with each other. In some implementations, the wiring M2 and the top gate contact CB_T can be formed integrally and in direct contact with each other.

[0117] In some implementations, the gate contact CB may include a top gate contact CB_T and a bottom gate contact CB_B. In some implementations, the top gate contact CB_T may be arranged between the wiring M2 and the bottom gate contact CB_B. The top gate contact CB_T may directly contact the wiring M2. More specifically, the top gate contact CB_T may directly contact the connection portion M2_C of the wiring M2. For example, the top surface of the top gate contact CB_T may directly contact the bottom surface of the connection portion M2_C. In some implementations, the bottom gate contact CB_B may be arranged between the top gate contact CB_T and the gate line 260. The bottom gate contact CB_B may directly contact the gate line 260. For example, the bottom surface of the bottom gate contact CB_B may directly contact the top surface of the gate line 260.

[0118] In some implementations, the top surface of the gate contact CB may be at a vertical level lower than the top surface of the interlayer insulating film 284. That is, the top surface of the top gate contact CB_T may be at a vertical level lower than the top surface of the interlayer insulating film 284. That is, the top surface of the top gate contact CB_T may be at a vertical level lower than the bottom surface of the adhesive layer 290. That is, the bottom surface of the connection portion M2_C may be at a vertical level lower than the bottom surface of the adhesive layer 290. Therefore, the vertical thickness T23 of the connection portion M2_C may be greater than the vertical thickness T22 of the adhesive layer 290.

[0119] In some implementations, the top gate contact CB_T and the bottom gate contact CB_B may include different types of metals. For example, the top gate contact CB_T includes Ru, and the bottom gate contact CB_B may include Mo. More specifically, the top gate contact CB_T and the bottom gate contact CB_B may be formed of different types of metals. For example, the top gate contact CB_T is formed of Ru, and the bottom gate contact CB_B may be formed of Mo.

[0120] In some implementations, the top gate contact CB_T may include the same type of metal as the metal included in the wiring M2. For example, both the top gate contact CB_T and the wiring M2 may include Ru. More specifically, the top gate contact CB_T and the wiring M2 may be formed of the same type of metal. For example, both the top gate contact CB_T and the wiring M2 may be formed of Ru. In some implementations, the bottom gate contact CB_B and the wiring M2 may include different types of metals. More specifically, the bottom gate contact CB_B and the wiring M2 may be formed of different types of metals.

[0121] In some implementations, a thickness T25 of the top gate contact CB_T in the vertical direction (Z direction) may be smaller than a thickness T24 of the bottom gate contact CB_B in the vertical direction (Z direction).

[0122] In some implementations, the angle θ22 formed by the outer sidewall of the gate contact CB and the top surface of the gate line 260 may be 90° or less. In this specification, the outer sidewall of the gate contact CB may refer to a sidewall directly contacting the top insulating structure 280 and the cap insulating pattern 268 surrounding the gate contact CB. For example, the angle θ22 formed by the outer sidewall of the gate contact CB and the top surface of the gate line 260 may be 70° or more but not more than 90°.

[0123] In some implementations, the width of the wiring M2 in the second horizontal direction may be smaller than the width of the gate contact CB in the second horizontal direction. More specifically, the average width of the wiring M2 in the second horizontal direction may be smaller than the average width of the gate contact CB in the second horizontal direction. More specifically, at the contact portion between the wiring M2 and the gate contact CB, the width of the wiring M2 in the second horizontal direction may be smaller than the width of the gate contact CB in the second horizontal direction. For example, the width L21 of the wiring M2 in the second horizontal direction at the lowest vertical level may be smaller than the width L22 of the gate contact CB in the second horizontal direction at the highest vertical level. For example, the width L21 of the bottom surface of the connection portion M2_C of the wiring M2 in the second horizontal direction may be smaller than the width L22 of the top surface of the top gate contact CB_T in the second horizontal direction.

[0124] In some implementations, outer sidewalls of the wiring M2 and the gate contact CB in contact with each other may have a step difference. More specifically, outer sidewalls of the wiring M2 and the gate contact CB in contact with each other may have a step difference at a boundary between the wiring M2 and the gate contact CB.

[0125] In reference Figures 11 to 14B In the described integrated circuit device 200, the adhesive layer 290 is not disposed on the contact portion between the wiring M2 and the gate contact CB. In some implementations, the wiring M2 has a reduced resistance due to the removal of the adhesive layer 290 in the contact portion with the gate contact CB, compared to the wiring having the adhesive layer at the contact portion with the gate contact.

[0126] Refer to above Figures 11 to 14B In the described integrated circuit device 200, the gate contact CB may include a top gate contact CB_T and a bottom gate contact CB_B including different kinds of metals, respectively. More specifically, in some implementations, the gate contact CB may have reduced resistance and improved controllability compared to a gate contact that may be oxidized, wherein the gate contact CB includes a top gate contact CB_T including Ru and a bottom gate contact CB_B including a metal different from Ru.

[0127] Figures 15 to 19 are cross-sectional views of examples of integrated circuit devices 200A, 200B, 201, 201A, and 201B according to other embodiments.

[0128] Reference Figures 15 to 19 , the main description and reference Figures 11 to 14B The differences in the integrated circuit device 200 are described.

[0129] Reference Fig.15 and Fig.16 , the integrated circuit device 200A may include a wiring M2A and a gate contact CB; and the integrated circuit device 200B may include a wiring M2B and a gate contact CB, and the wirings M2A and M2B may not be aligned with the gate contact CB. The wiring M2A includes an extension portion M2A_E and a connection portion M2A_C, and the wiring M2B includes an extension portion M2B_E and a connection portion M2B_C. More specifically, only a portion of each of the wirings M2A and M2B may overlap with the gate contact CB in the vertical direction (Z direction) (the gate contact CB contacts the corresponding wirings M2A and M2B), and the other portion may not overlap with the gate contact CB.

[0130] Reference Figures 17 to 19, the integrated circuit device 201 may include a wiring M21 and a gate contact CB1; the integrated circuit device 201A may include a wiring M21A and a gate contact CB1; and the integrated circuit device 201B may include a wiring M21B and a gate contact CB1. The gate contact CB1 includes a top gate contact CB1_T and a bottom gate contact CB1_B. The wiring M21 includes an extension M21_E and a connection M21_C; the wiring M21A includes an extension M21A_E and a connection M21A_C; the wiring M21B includes an extension M21B_E and a connection M21B_C. The top surface of the gate contact CB1 may be at the same vertical level as the top surface of the interlayer insulating film 284. That is, the top surface of the top gate contact CB1_T may be at the same vertical level as the top surface of the interlayer insulating film 284. That is, the top surface of the top gate contact CB1_T may be at the same vertical level as the bottom surface of the adhesive layer 290. That is, the bottom surfaces of the connection parts M21_C, M21A_C, and M21B_C may be at the same vertical level as the bottom surface of the adhesive layer 290. Therefore, the vertical thickness of the connection parts M21_C, M21A_C, and M21B_C may be the same as that of the adhesive layer 290.

[0131] Fig. 20 is a plan layout diagram of an example of an integrated circuit device 300 . Fig.21 and Fig. 22 is a cross-sectional view of the integrated circuit device 300. More specifically, Fig.21 is along Fig. 20 A cross-sectional view taken along the line X1-X1 shown in FIG. Fig. 22 is along Fig. 20 A cross-sectional view taken along the line Y2-Y2 shown in FIG.

[0132] Reference Figure 20 to Figure 22 The integrated circuit device 300 includes a substrate 302 and a plurality of fin-type active areas FA protruding on a first surface 302_1 of the substrate 302 and extending in a first horizontal direction (X direction). A second surface 302_2 of the substrate 302 may be covered with a backside insulating film 309 .

[0133] A plurality of gate lines 360 may be arranged on the plurality of fin-type active areas FA. Each of the plurality of gate lines 360 may extend in the second horizontal direction (Y direction). Each of the plurality of gate lines 360 may include a main gate portion 360M and a plurality of sub-gate portions 360S.

[0134] In the region where the plurality of fin-type active areas FA intersect the plurality of gate lines 360, the plurality of nanosheet stacks NSS may be arranged on the fin top surfaces FT of the plurality of fin-type active areas FA. The plurality of nanosheet stacks NSS may include at least one nanosheet facing the fin top surface FT at a position spaced apart from the fin top surface FT of the fin-type active area FA in the vertical direction (Z direction). The gate dielectric film 352 may be arranged between the nanosheet stacks NSS and the gate lines 360.

[0135] The plurality of nanosheet stacks NSS may each include a first nanosheet N1 , a second nanosheet N2 , and a third nanosheet N3 , which may each serve as a channel region.

[0136] A plurality of source / drain regions 330 may be disposed on the fin-type active region FA. Each of the plurality of source / drain regions 330 may be disposed at a position adjacent to at least one gate line 360 ​​selected from among the plurality of gate lines 360. Each of the plurality of source / drain regions 330 may contact the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS.

[0137] The active contact CA2 may be disposed on the source / drain region 330. The active contact CA2 may include a conductive barrier pattern 374 and a contact plug 376 sequentially stacked on the source / drain region 330. The active contact CA2 may penetrate the inter-gate insulating film 344 and the insulating liner 342 in the vertical direction (Z direction) and contact the metal silicide film 372. The active contact CA2 may be electrically connected to the source / drain region 330 through the metal silicide film 372. For the active contact CA2, refer to the description of the embodiment of the present invention. Figures 2 to 5 Description of active contact CA.

[0138] The via contact VA2 may be disposed on the active contact CA2. The via contact VA2 may penetrate the top insulating structure 380 and contact the active contact CA2. Each of the plurality of source / drain regions 330 may be electrically connected to the via contact VA2 through the metal silicide film 372 and the active contact CA2.

[0139] In some implementations, the via contact VA2 may include a top via contact VA2_T and a bottom via contact VA2_B. The top via contact VA2_T and the bottom via contact VA2_B may include different types of metals, respectively. For example, the top via contact VA2_T may include Ru, and the bottom via contact VA2_B may include Mo. In some implementations, the top via contact VA2_T and the wiring M3 may include the same type of metal. Figures 2 to 5 Description of the access contact VA.

[0140] The gate contact CB2 may be disposed on the gate line 360. The gate contact CB2 may penetrate the top insulating structure 380 and the cap insulating pattern 368 in the vertical direction (Z direction) and may be connected to the gate line 360. The top insulating structure 380 may include an etch stop layer 382 and an interlayer insulating film 384. Both sidewalls of each of the gate line 360 ​​and the cap insulating pattern 368 may be covered by an outer insulating spacer 318.

[0141] In some implementations, the gate contact CB2 may include a top gate contact CB2_T and a bottom gate contact CB2_B. The top gate contact CB2_T and the bottom gate contact CB2_B may include different types of metals, respectively. For example, the top gate contact CB2_T may include Ru, and the bottom gate contact CB2_B may include Mo. In some implementations, the top gate contact CB2_T and the wiring M3 may include the same type of metal. Figures 11 to 14B Description of the gate contact CB.

[0142] The plurality of wirings M3 may be arranged to penetrate the top insulating film 392. Each of the plurality of wirings M3 may be connected to a via contact VA2 selected from a plurality of via contacts VA2 below the plurality of wirings M3. The plurality of wirings M3 may be connected to a gate contact CB2 selected from a plurality of gate contacts CB2 below the plurality of wirings M3. In some implementations, the wiring M3 may extend in a first horizontal direction (X direction). In some implementations, the wiring M3 may include: an extension portion M3_E extending in the first horizontal direction (X direction); a first connection portion M3_C1 arranged between the extension portion M3_E and the via contact VA2; and a second connection portion M3_C2 arranged between the extension portion M3_E and the gate contact CB2. Regarding the wiring M3, refer to Figures 2 to 5 Description of the wiring M1 and Figures 11 to 14B Description of the wiring M2.

[0143] The adhesive layer 390 may be arranged on a portion of the wiring M3. The adhesive layer 390 may include TiN. More specifically, the adhesive layer 390 may be arranged between the wiring M3 and the top insulating structure 380. More specifically, the adhesive layer 390 may be arranged between the wiring M3 and the interlayer insulating film 384. In some implementations, the adhesive layer 390 is not arranged on the contact portion of the wiring contacting the via contact VA2 and the contact portion of the wiring M3 contacting the gate contact CB2. That is, the wiring M3 may directly contact the via contact VA2 and the gate contact CB2. More specifically, the first connection portion M3_C1 of the wiring M3 may directly contact the via contact VA2. More specifically, the second connection portion M3_C2 of the wiring M3 may directly contact the gate contact CB2. In some implementations, the wiring M3, the top via contact VA2_T and the top gate contact CB2_T may be formed integrally and may be in direct contact with each other. Regarding the adhesive layer 390, refer to the description regarding Figures 2 to 5 Description of Adhesive Layer 190 and Related Figures 11 to 14B Description of Adhesive Layer 290 .

[0144] In reference Figure 20 to Figure 22 In the described integrated circuit device 300, the adhesive layer 390 is not arranged on the contact portion of the contact via contact VA2 and the contact portion of the contact gate contact CB2. In some implementations, due to the removal of the adhesive layer 390 from the contact portion of the contact via contact VA2 and the contact portion of the contact gate contact CB2, the wiring M3 (compared to the wiring in contact with the adhesive) can have a reduced resistance.

[0145] In reference Figure 20 to Figure 22 In the described integrated circuit device 300, the top via contact VA2_T and the bottom via contact VA2_B respectively include different types of metals. More specifically, in some implementations, the via contact VA2 can have reduced resistance and improved controllability compared to a via contact that may be oxidized, wherein the via contact VA2 includes a top via contact VA2_T including Ru and a bottom via contact VA2_B including a metal different from Ru.

[0146] Refer to above Figure 20 to Figure 22 In the described integrated circuit device 300, the top gate contact CB2_T and the bottom gate contact CB2_B may include different types of metals, respectively. More specifically, in some implementations, the gate contact CB2 may have reduced resistance and improved controllability compared to a gate contact that may be oxidized, wherein the gate contact CB2 includes a top gate contact CB2_T including Ru and a bottom gate contact CB2_B including a metal different from Ru.

[0147] FIG. 23A to FIG. 23I1 is a cross-sectional view showing a process sequence according to an example of a method of manufacturing an integrated circuit device 100. More specifically, FIG. 23A to FIG. 23I is corresponding to along Figure 2 A cross-sectional view of a cross section taken along the line Y1 - Y1 shown in FIG.

[0148] Reference Fig.23A , a plurality of fin-type active regions FA protrude on the first surface 102_1 of the substrate 102. The source / drain region 130 may be disposed on the fin-type active region FA. The active contact CA may be disposed on the source / drain region 130 and electrically connected to the source / drain region 130. The active contact CA may penetrate the inter-gate insulating film 144 and the insulating liner 142 in the vertical direction (Z direction) and contact the metal silicide film 172.

[0149] Reference Fig. 23B , a top insulating structure 180, a pre-adhesive layer P190, a first insulating film IL1, a first hard mask film HM1, a second insulating film IL2, and a first photoresist pattern PR1 are disposed on the inter-gate insulating film 144 and the active contact CA. For example, the top insulating structure 180 may include an etch stop layer 182 including SiN and an etch stop layer 183 including silicon oxide (SiO 2 ) interlayer insulating film 184. For example, the pre-adhesive layer P190 may include TiN. For example, the first insulating film IL1 and the second insulating film IL2 may include silicon oxynitride (SiON). For example, the first hard mask film HM1 may include a spin-on hard mask (SOH) film.

[0150] The first photoresist pattern PR1 may expose a portion of the second insulating film IL2. The first photoresist pattern PR1 may expose a portion of the second insulating film IL2 overlapping the active contact CA in a vertical direction (Z direction).

[0151] Reference Fig.23C , the second insulating film IL2, the first hard mask film HM1, and the first insulating film IL1 may be sequentially etched using the first photoresist pattern PR1 as a mask. More specifically, a portion of each of the second insulating film IL2, the first hard mask film HM1, and the first insulating film IL2 that overlaps with the active contact CA in the vertical direction (Z direction) may be sequentially etched. By doing so, a portion of the pre-adhesive layer P190 may be exposed. Next, the first photoresist pattern PR1, the second insulating film IL2, and the first hard mask film HM1 may be removed.

[0152] Reference Fig.23D, the pre-bonding layer P190, the interlayer insulating film 184, and the etching stop layer 182 may be sequentially etched using the first insulating film IL1, a portion of which has been etched, as a mask. More specifically, the pre-bonding layer P190, the interlayer insulating film 184, and the etching stop layer 182 overlapping the active contact CA may be sequentially etched. More specifically, the first hole H1 may be formed by etching the pre-bonding layer P190 using the first insulating film IL1 as a mask. Next, the via contact hole VAH may be formed by etching the top insulating structure 180 exposed by the first hole H1.

[0153] The top surface of the active contact CA may be exposed by the first hole H1 and the via contact hole VAH. Thereafter, the first insulating film IL1 may be removed.

[0154] Reference Fig.23E , an inhibitor layer 193 may be formed on the pre-bonding layer P190. More specifically, the inhibitor layer 193 may be selectively formed on the top surface of the pre-bonding layer P190 and the sidewalls of the first hole H1. For example, the inhibitor layer 193 may be selectively formed on the top surface of the pre-bonding layer P190 and the sidewalls of the first hole H1, and includes TiN. The inhibitor layer 193 may not be formed on the sidewalls of the via contact hole VAH and the top surface of the active contact CA.

[0155] Reference Fig.23F , a first metal layer ML_1 and a second metal layer ML_2 may be sequentially formed in the via contact hole VAH. The first metal layer ML_1 and the second metal layer ML_2 may include different kinds of metals. For example, the first metal layer ML_1 may include Mo. For example, the second metal layer ML_2 may include Ru.

[0156] In some implementations, the first metal layer ML_1 may be deposited on the top surface of the active contact CA. More specifically, the first metal layer ML_1 may be deposited by selectively using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD) on a metal. In some implementations, the first metal layer ML_1 may be conformally deposited on a non-metallic material by an ALD process and / or a CVD process. The top surface of the first metal layer ML_1 may have a vertical level lower than the top surface of the top insulating structure 180.

[0157] The second metal layer ML_2 may be deposited on the first metal layer ML_1 by an ALD process and / or a CVD process. After the second metal layer ML_2 has been deposited to a vertical level of the top surface of the top insulating structure 180, the deposition rate in the first hole H1 may be gradually reduced due to the inhibitor layer 193. As a result, the deposition of the second metal layer ML_2 in the first hole H1 may be completed. The top surface of the second metal layer ML_2 may have a vertical level higher than the top surface of the top insulating structure 180 and lower than the top surface of the pre-bonding layer P190.

[0158] Reference Figure 23G , the inhibitor layer 193 may be removed, and the first hole H1 may be filled with the same material as the pre-adhesion layer P190. Filling the first hole H1 may be performed using a physical vapor deposition (PVD) process, an ALD process, and / or a CVD process.

[0159] Thereafter, a portion of the pre-bonding layer P190 may be removed by using a chemical mechanical polishing (CMP) process. As a result, a top surface of the pre-bonding layer P190 may be at the same vertical level as a top surface of the second metal layer ML_2.

[0160] Reference Fig.23H , a third metal layer ML_3 may be formed on the top surface of the second metal layer ML_2 and the pre-bonding layer P190. The third metal layer ML_3 may include the same type of metal as the second metal layer ML_2. The third metal layer ML_3 and the second metal layer ML_2 may be formed integrally. For example, when the second metal layer ML_2 includes Ru, the third metal layer ML_3 may also include Ru. The third metal layer ML_3 may directly contact the second metal layer ML_2.

[0161] Reference Fig.23I , a plurality of wirings M1 may be formed by patterning the third metal layer ML_3. More specifically, the third metal layer ML_3 may be patterned so that the thickness of the wiring M1 in the second direction (Y direction) is less than the thickness of the via contact VA under the wiring M1 in the second horizontal direction (Y direction). For example, a subtractive etching scheme may be used.

[0162] In the process of patterning the third metal layer ML_3 to form the plurality of wirings M1, the top via contact VA_T may be formed by etching the second metal layer ML_2 at the same time. As a result, the vertical level of the top surface of the via contact VA may be lower than the vertical level of the top surface of the top insulating structure 180. That is, the third metal layer ML_3 and the second metal layer ML_2 may be integrally formed and then formed into the wirings M1 and the top via contact VA_T through a patterning process.

[0163] Next, a reference circuit can be manufactured by forming a top insulating film 192 surrounding the plurality of wirings M1. Figures 2 to 5 An integrated circuit device 100 is described.

[0164] According to reference FIG. 23A to FIG. 23I In the method of manufacturing the integrated circuit device 100 described above, the first metal layer ML_1 may include Mo, and the second metal layer ML_2 may include Ru. When the second metal layer ML_2 including Ru is disposed on the first metal layer ML_1 including Mo, the Fig.23I The etching gas that can be used in the process of patterning the third metal layer ML_3 described above causes the oxidation of Mo of the first metal layer ML_1 to increase the resistance. In addition, even when the third metal layer ML_3 is over-etched, the second metal layer ML_2 can be etched first on the first metal layer ML_1 and the etching margin can be increased, thereby improving process control.

[0165] Already referred to FIG. 23A to FIG. 23I An example of a method of manufacturing an integrated circuit device 100 is described. However, those skilled in the art will appreciate that Figures 6 to 10 The integrated circuit devices 100A, 100B, 101, 101A and 10B shown in Figure 20 to Figure 22 The integrated circuit device 300 shown in FIG. 1 and integrated circuit devices having various structures modified and changed therefrom can be constructed by referring to FIG. FIG. 23A to FIG. 23I Many modifications and variations of the description may be made without departing from the spirit of the disclosure.

[0166] FIG. 24A to FIG. 24J 2 is a cross-sectional view shown according to a process sequence to describe a method of manufacturing an integrated circuit device 200. More specifically, FIG. 24A to FIG. 24J is corresponding to along Fig.11 A cross-sectional view of a section taken along line Y2-Y2 shown in FIG.

[0167] Reference Fig.24A , a plurality of fin type active regions FA protrude on the first surface 202_1 of the substrate 202 . A plurality of gate lines 260 extending in the second horizontal direction (Y direction) may be arranged on the plurality of fin type active regions FA. A capping insulating pattern 268 is on the plurality of gate lines 260 .

[0168] Reference Fig. 24B A top insulating structure 280, a pre-adhesive layer P290, a third insulating film IL3, a second hard mask film HM2, a fourth insulating film IL4, and a second photoresist pattern PR2 are disposed on the capping insulating pattern 268. The second photoresist pattern PR2 may expose a region of the fourth insulating film IL4.

[0169] Reference Fig.24C, the fourth insulating film IL4, the second hard mask film HM2, and the third insulating film IL3 may be sequentially etched using the second photoresist pattern PR2 as a mask. By doing so, the region of the pre-adhesive layer P290 may be exposed. Next, the second photoresist pattern PR2, the fourth insulating film IL4, and the second hard mask film HM2 may be removed.

[0170] Reference Fig.24D , the pre-adhesive layer P290, the interlayer insulating film 284, the etching stop layer 282, and the cap insulating pattern 268 may be sequentially etched using the third insulating film IL3, in which the region thereof has been etched, as a mask. More specifically, the second hole H2 may be formed by etching the pre-adhesive layer P290 using the third insulating film IL3 as a mask. Next, the gate contact hole CBH may be formed by etching the top insulating structure 280 and the cap insulating pattern 268 exposed by the second hole H2. In some implementations, a portion of the gate line 260 may also be etched.

[0171] The gate line 260 may be exposed through the second hole H2 and the gate contact hole CBH. Thereafter, the third insulating film IL3 may be removed.

[0172] Reference Fig.24E , an inhibitor layer 293 may be formed on the pre-bonding layer P290. More specifically, the inhibitor layer 293 may be selectively formed on the top surface of the pre-bonding layer P290 and the sidewall of the second hole H2. For example, the inhibitor layer 293 may be selectively formed on the top surface of the pre-bonding layer P290 and the sidewall of the second hole H2, and includes TiN. The inhibitor layer 293 may not be formed on the sidewall of the gate contact hole CBH and on the gate line 260.

[0173] Reference Fig.24F , a fourth metal layer ML_4 and a fifth metal layer ML_5 may be sequentially formed in the gate contact hole CBH. The fourth metal layer ML_4 and the fifth metal layer ML_5 may include different kinds of metals. For example, the fourth metal layer ML_4 may include Mo. For example, the fifth metal layer ML_5 may include Ru. The top surface of the fourth metal layer ML_4 may have a vertical level lower than the vertical level of the top surface of the top insulating structure 280. The top surface of the fifth metal layer ML_5 may have a vertical level higher than the vertical level of the top surface of the top insulating structure 280 and lower than the vertical level of the top surface of the pre-bonding layer P290.

[0174] Reference Figure 24G and Fig.24H , the inhibitor layer 293 may be removed, and the second hole H2 may be filled with the same material as the pre-adhesion layer P290. The process of filling the second hole H2 may be performed using a PVD process, an ALD process, and / or a CVD process.

[0175] Next, a portion of the pre-bonding layer P290 may be removed using a CMP process. As a result, a top surface of the pre-bonding layer P290 may be at the same vertical level as that of a top surface of the fifth metal layer ML_5.

[0176] Reference Fig.24I , a sixth metal layer ML_6 may be formed on the top surface of the fifth metal layer ML_5 and the pre-bonding layer P290. The sixth metal layer ML_6 may include the same kind of metal as the fifth metal layer ML_5. The sixth metal layer ML_6 and the fifth metal layer ML_5 may be formed as one. For example, when the fifth metal layer ML_5 includes Ru, the sixth metal layer ML_6 may include Ru. The sixth metal layer ML_6 may directly contact the fifth metal layer ML_5.

[0177] Reference Fig.24J , a plurality of wirings M2 may be formed by patterning the sixth metal layer ML_6. More specifically, the sixth metal layer ML_6 may be patterned so that the thickness of the wiring M2 in the second horizontal direction (Y direction) is less than the thickness of the gate contact CB under the wiring M2 in the second horizontal direction (Y direction). For example, a subtractive etching scheme may be used.

[0178] In the process of patterning the sixth metal layer ML_6 to form a plurality of wirings M2, a top gate contact CB_T may be formed by simultaneously etching the fifth metal layer ML_5. As a result, the vertical level of the top surface of the gate contact CB may be lower than the vertical level of the top surface of the top insulating structure 280. That is, the sixth metal layer ML_6 and the fifth metal layer ML_5 may be formed as one, and then formed into the wirings M2 and the top gate contact CB_T through a patterning process.

[0179] Next, a reference circuit can be manufactured by forming an upper insulating film 292 surrounding the plurality of wirings M2. Figures 11 to 14B An integrated circuit device 200 is described.

[0180] Already referred to FIG. 24A to FIG. 24J An example of a method of manufacturing an integrated circuit device 200 is described. However, those skilled in the art will appreciate that without departing from the spirit of the present disclosure, Figures 15 to 19 The integrated circuit devices 200A, 200B, 201, 201A and 201B shown in Figure 20 to Figure 22 The integrated circuit device 300 shown in FIG. 1 and integrated circuit devices having various structures modified and changed therefrom can be constructed by referring to FIG. FIG. 24A to FIG. 24J Many modifications and variations of the description may be made.

[0181] Although the present disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the protection claimed. Certain features described in the context of separate implementations in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, one or more features from the combination may be removed from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0182] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0183] This application is based on and claims the priority benefit of Korean Patent Application No. 10-2023-0080636 filed in the Korean Intellectual Property Office on June 22, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: substrate; A fin-type active region extending in a first horizontal direction on a first surface of the substrate; a source / drain region on the fin-type active region; an active contact disposed on the source / drain region and electrically connected to the source / drain region; a wiring extending at a vertical level higher than a vertical level of said source / drain regions; a via contact penetrating the insulating layer on the source / drain region, wherein the active contact and the wiring are electrically connected through the via contact; as well as an adhesive layer between the wiring and the insulating layer, the adhesive layer directly contacting the wiring, wherein the via contacts include a top via contact and a bottom via contact, wherein the top via contact comprises a different metal than a metal included in the bottom via contact, and Wherein the wiring and the top via contact are in direct contact with each other. 2 . The integrated circuit device according to claim 1 , wherein the metal included in the bottom via contact is different from a metal included in the wiring. 3 . The integrated circuit device of claim 2 , wherein the metal of the top via contact and the metal included in the wiring both include the same first metal. 4 . The integrated circuit device of claim 1 , wherein a thickness of the top via contact along a vertical direction perpendicular to the first surface of the substrate is smaller than a thickness of the bottom via contact along the vertical direction.

5. The integrated circuit device according to claim 1, wherein the wiring includes an extension portion and a connection portion connecting the extension portion to the top via contact, and A thickness of the extension portion along a vertical direction perpendicular to the first surface of the substrate is greater than a thickness of the adhesive layer along the vertical direction.

6. The integrated circuit device of claim 1, wherein the metal of the top via contact is different from a metal included in the active contacts.

7. The integrated circuit device of claim 6, wherein the metal included in the bottom via contact and the metal included in the active contact both include the same metal.

8. The integrated circuit device according to claim 1, wherein the wiring includes an extension portion and a connection portion connecting the extension portion to the top via contact, and wherein the adhesive layer is arranged between the extension portion and the insulating layer, and Wherein the adhesive layer is not disposed between the extension portion and the connection portion and between the connection portion and the top via contact. 9 . The integrated circuit device of claim 1 , wherein a vertical level of a top surface of the top via contact is equal to or lower than a vertical level of a bottom surface of the adhesive layer.

10. The integrated circuit device according to claim 1, wherein the wiring extends in the first horizontal direction, and wherein a width of the via contact in the second horizontal direction is greater than a width of the wiring in the second horizontal direction.

11. An integrated circuit device comprising: substrate; A fin-type active region extending in a first horizontal direction on a first surface of the substrate; a source / drain region on the fin-type active region; a gate line extending on the fin-type active area in a second horizontal direction intersecting the first horizontal direction; a wiring extending at a vertical level higher than a vertical level of said source / drain regions; a gate contact penetrating the insulating layer on the gate line, wherein the gate line and the wiring are electrically connected through the gate contact; as well as an adhesive layer between the wiring and the insulating layer and in contact with the wiring, wherein the gate contact comprises a top gate contact and a bottom gate contact, The top gate contact comprises a different metal than a metal included in the bottom gate contact, and The wiring and the top gate contact are in direct contact with each other. 12 . The integrated circuit device according to claim 11 , wherein the metal included in the bottom gate contact is different from a metal included in the wiring. 13 . The integrated circuit device of claim 12 , wherein the metal of the top gate contact and the metal included in the wiring both include the same first metal. 14 . The integrated circuit device of claim 11 , wherein a thickness of the top gate contact along a vertical direction perpendicular to the first surface of the substrate is smaller than a thickness of the bottom gate contact along the vertical direction.

15. The integrated circuit device according to claim 11, wherein the wiring comprises an extension portion and a connection portion connecting the extension portion to the top gate contact, The extending portion and the connecting portion are in direct contact with each other, and The connection directly contacts the top gate contact. 16 . The integrated circuit device of claim 11 , wherein a vertical level of a top surface of the top gate contact is equal to or lower than a vertical level of a bottom surface of the adhesion layer.

17. The integrated circuit device according to claim 11, wherein the wiring extends in the first horizontal direction, and Wherein a width of the top gate contact in the second horizontal direction is greater than a width of the wiring in the second horizontal direction.

18. An integrated circuit device comprising: substrate; A fin-type active region extending in a first horizontal direction on a first surface of the substrate; a source / drain region on the fin-type active region; a gate line extending on the fin-type active area in a second horizontal direction intersecting the first horizontal direction; a wiring extending in the first horizontal direction at a vertical level higher than a vertical level of the source / drain regions; an active contact on and electrically connected to the source / drain region; a via contact penetrating the insulating layer on the source / drain region, wherein the active contact and the wiring are electrically connected through the via contact; a gate contact penetrating the insulating layer, wherein the gate line and the wiring are electrically connected through the gate contact; and a titanium nitride (TiN) layer between the wiring and the insulating layer and in contact with the wiring, wherein the via contacts include a top via contact comprising ruthenium (Ru) and a bottom via contact comprising molybdenum (Mo), wherein the gate contact comprises a top gate contact comprising Ru and a bottom gate contact comprising Mo, wherein the width of the top via contact in the second horizontal direction is greater than the width of the wiring in the second horizontal direction, wherein the width of the top gate contact in the second horizontal direction is greater than the width of the wiring in the second horizontal direction, wherein the wiring and the top via contact are in direct contact with each other, and Wherein the wiring and the top gate contact are in direct contact with each other.

19. The integrated circuit device according to claim 18, wherein the wiring includes an extension portion, a first connection portion connecting the extension portion to the top via contact, and a second connection portion connecting the extension portion to the top gate contact, wherein the TiN layer is arranged between the extension portion and the insulating layer, and The TiN layer is not disposed between the extension and the first connection, between the extension and the second connection, between the first connection and the top via contact, and between the second connection and the top gate contact. 20 . The integrated circuit device of claim 18 , wherein a thickness of the top via contact along a vertical direction perpendicular to the first surface of the substrate is smaller than a thickness of the bottom via contact along the vertical direction.

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