Test system and test method

Abstract

The invention relates to a test system and a test method. The test system comprises at least two output data source modules; the multiplexing selection module is connected with each output data source module and is used for switching and outputting a test pattern corresponding to the output data source module; the waveform synthesis module is connected with the multiplexing selection module and is used for performing waveform format synthesis on the test pattern output by the multiplexing selection module according to the configured waveform format and outputting a synthesized waveform; the time sequence generation module is connected with the waveform synthesis module and is used for carrying out delay processing on the synthesized waveform output by the waveform synthesis module and generating an output waveform; and the pin circuit module is connected with the time sequence generation module and the to-be-tested device, and is used for receiving the output waveform generated by the time sequence generation module and outputting an excitation signal to the to-be-tested device. The output waveform is obtained by adopting a processing mode of firstly performing waveform synthesis and then performing time sequence generation, the delay compensation error is reduced, a waveform output function can be realized by adopting a universal chip, and the design cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a testing system and a testing method. Background Art

[0002] Semiconductor automated testing refers to the use of test machines to test various parameters of the device under test (DUT) and eliminate defective products to control the factory quality of semiconductor devices. In traditional test machines, timing generation and waveform synthesis rely on dedicated IC (Integrated Circuit) chips, which have complex structures and high design complexity. Summary of the invention

[0003] Based on this, it is necessary to provide a test system and a test method that can reduce the design complexity in order to solve the above problems.

[0004] A testing system, comprising:

[0005] At least two output data source modules;

[0006] A multiplexing selection module, connected to each of the output data source modules, for switching and outputting the test pattern corresponding to the output data source module;

[0007] A waveform synthesis module (Format Controller, FC module), connected to the multiplexing selection module, is used to perform waveform format synthesis on the test pattern output by the multiplexing selection module according to the configured waveform format, and output a synthesized waveform;

[0008] A timing generator (TG module), connected to the waveform synthesis module, for performing delay processing on the synthesized waveform output by the waveform synthesis module to generate an output waveform;

[0009] A pin circuit module (Pin Electronics Driver / Comparator, PE module) is connected to the timing generation module and the device under test, and is used to receive the output waveform generated by the timing generation module and output an excitation signal to the device under test.

[0010] In one of the embodiments, the output data source module includes an algorithmic pattern generator module (ALPG module) and a pattern generator module (PG module).

[0011] In one of the embodiments, the test system further comprises a comparison processing module, wherein the comparison processing module is connected to the timing generation module and the waveform synthesis module;

[0012] The pin circuit module compares and judges the input signal fed back by the device under test according to a preset level threshold value, and outputs a comparison signal to the timing generation module;

[0013] The timing generation module performs delayed sampling on the comparison signal output by the pin circuit module, and outputs the sampling signal to the comparison processing module;

[0014] The comparison processing module analyzes and determines the actual sampling value according to the sampling signal output by the timing generation module, and compares and determines the actual sampling value with a preset expected value to obtain a comparison result.

[0015] In one of the embodiments, the test system further includes a timing control module (Timing Controller, TC module) for setting a delay time for the timing generation module, and the timing generation module is connected to the waveform synthesis module through the timing control module.

[0016] In one of the embodiments, the test system further includes an address failure memory module (Address Fail Memory, AFM module), which is connected to the comparison processing module and is used to receive the comparison result output by the comparison processing module and analyze the error address information corresponding to the error information according to the comparison result.

[0017] In one of the embodiments, the test system also includes a memory error repair analysis module (Memory Repair Analysis, MRA module), which is connected to the error address memory module and is used to analyze the distribution pattern of error bits according to the error address information fed into the error address memory module, and optimize the repair strategy to repair the memory of the device under test.

[0018] In one embodiment, the test system further includes a debugging module, which is connected to the comparison processing module and the waveform synthesis module and is used to record the theoretical synthesis waveform and the actual synthesis waveform, as well as the expected waveform and the actual waveform of the response of the device under test.

[0019] In one of the embodiments, the test system also includes a test unit processor (Test Unit Processor, TUP module), which is connected to the debugging module and is used to display the waveform data recorded by the debugging module through a GUI (Graphical User Interface).

[0020] A testing method comprising:

[0021] The multiplexing selection module switches and outputs the test pattern corresponding to the output data source module;

[0022] The waveform synthesis module synthesizes the waveform format of the test pattern output by the multiplexing selection module according to the configured waveform format, and outputs a synthesized waveform;

[0023] The timing generation module performs delay processing on the synthesized waveform output by the waveform synthesis module to generate an output waveform;

[0024] The pin circuit module receives the output waveform generated by the timing generation module, and outputs an excitation signal to the device under test.

[0025] In one embodiment, the method further comprises:

[0026] The pin circuit module compares and judges the input signal fed back by the device under test according to a preset level threshold value, and outputs a comparison signal;

[0027] The timing generation module performs delayed sampling on the comparison signal output by the pin circuit module and outputs a sampling signal;

[0028] The comparison processing module analyzes and determines the actual sampling value according to the sampling signal output by the timing generation module, and compares and determines the actual sampling value with a preset expected value to obtain a comparison result.

[0029] In one embodiment, the method further comprises:

[0030] The timing control module determines the output beat of the signal edge and the delay time within a single clock according to the output signal edge timing information fed into the waveform synthesis module;

[0031] The timing control module determines the sampling clock beat of the signal and the signal delay time information within a single clock according to the sampling position information of the input signal fed into the waveform synthesis module;

[0032] The timing control module feeds the output beat of the signal edge, the delay time within the single clock, the sampling clock beat and the signal delay time information within the single clock into the timing generation module.

[0033] In one of the embodiments, the method further includes: the waveform synthesis module determines the output signal edge timing information and the input signal sampling position information according to the graphic timing index, controls the processing speed of the waveform synthesis according to the feedback signal of the timing control module, and feeds back the output data source module to control the input data stream.

[0034] In one of the embodiments, the method further includes: the waveform synthesis module converts the received test pattern to obtain the expected value of each row sampled by the timing generation module, and feeds the expected value into the comparison processing module.

[0035] In one embodiment, the method further comprises:

[0036] The error address memory module receives the comparison result output by the comparison processing module, and analyzes the error address information corresponding to the error information according to the comparison result;

[0037] The memory error repair analysis module analyzes the distribution law of the error bits according to the error address information fed by the error address memory module, optimizes and obtains a repair strategy to repair the memory of the device under test.

[0038] In one embodiment, the method further comprises:

[0039] The debugging module records the theoretical synthesized waveform and the actual synthesized waveform, as well as the expected waveform and the actual waveform of the response of the device under test;

[0040] The test unit processor displays the waveform data recorded by the debugging module through a GUI.

[0041] In the above test system and test method, the multiplexing selection module selects the corresponding output data source module to output the test waveform, first receives the test pattern through the waveform synthesis module to synthesize the waveform to obtain the synthesized waveform, and then generates the output waveform through the timing generation module. Finally, the pin circuit module generates an excitation signal based on the received output waveform and sends it to the device to be tested. The output waveform is obtained by first synthesizing the waveform and then generating the timing, which reduces the delay compensation error, and the waveform output function can be realized by using a general chip, which reduces the design cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A structural schematic diagram of a test system in one embodiment;

[0043] Figure 2 The figure is a flow chart of a testing method in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0047] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0048] The functional architecture of current test machines is to first adjust the time delay of data, and then convert the adjusted signal into the required waveform format for output. This requires that the waveform format conversion circuit delay of each channel is as consistent as possible, or the circuit delay difference between channels is compensated to the data delay. In current test machines, timing generation and waveform synthesis rely on dedicated chips, which cannot be implemented using general-purpose FPGAs (Field Programmable Gate Arrays), and the dedicated chip implementation structure is complex.

[0049] Based on this, in order to solve the problem of equal delay requirements for waveform format conversion circuits between channels introduced by delaying data first and then performing waveform format conversion, or introducing additional circuit delay difference compensation, the present application provides a test system, in which a multiplexing selection module selects the corresponding output data source module to output a test waveform, first receives the test pattern through a waveform synthesis module to synthesize the waveform format to obtain a synthesized waveform, and then delays the synthesized waveform through a timing generation module to obtain an output waveform. Finally, the pin circuit module generates an excitation signal based on the received output waveform and sends it to the device to be tested. The output waveform is obtained by first synthesizing the waveform and then generating the timing, which is insensitive to the delay of the waveform format conversion part. When performing delay compensation between channels, the format conversion part does not need to be calculated, which reduces the delay compensation error. A general FPGA chip can be used to implement the waveform output function, reducing the design cost.

[0050] In one embodiment, Figure 1 As shown, a test system is provided, including an output data source module, a multiplexing selection module MUX, a waveform synthesis module FC, a timing generation module TG and a pin circuit module PE, the number of the output data source modules is at least two, the multiplexing selection module MUX is connected to each output data source module, the waveform synthesis module FC is connected to the multiplexing selection module MUX, the timing generation module TG is connected to the waveform synthesis module FC, and the pin circuit module PE is connected to the timing generation module TG and the device under test DUT.

[0051] Among them, the multiplexing selection module MUX switches and outputs the test pattern corresponding to the output data source module, the waveform synthesis module FC synthesizes the waveform format of the test pattern output by the multiplexing selection module MUX according to the configured waveform format, and outputs the synthesized waveform; the timing generation module TG delays the synthesized waveform output by the waveform synthesis module FC to generate an output waveform; the pin circuit module PE receives the output waveform generated by the timing generation module TG, outputs the excitation signal to the device under test DUT, and tests the device under test DUT. The device under test DUT can be a chip under test or other devices.

[0052] The types of the output data source modules can be the same or different. When the types of the output data source modules are the same, when one of the output data source modules fails, it can be switched to other spare output data source modules to ensure the normal operation of the test system; when the types of the output data source modules are different, the output data source modules of the corresponding types can be switched to output test graphics using the multiplexing selection module MUX according to actual needs to expand the application scenario. In this embodiment, the output data source module includes an algorithm graphics generation module ALPG and a graphics generation module PG, and the algorithm graphics generation module ALPG and the graphics generation module PG are both connected to the multiplexing selection module MUX.

[0053] Specifically, the algorithmic graph generation module ALPG automatically generates the original data stream according to the written program, the graph generation module PG generates the original data stream according to the specified test vector, and the multiplexing selection module MUX is used to select the algorithmic graph generation module ALPG or the graph generation module PG to generate the test graph. The waveform synthesis module FC synthesizes the waveform format of the test graph according to the configured waveform format to obtain a synthesized waveform. The types of waveform formats are not unique, for example, they may include NRZ, RZ, XORBC and other formats. The timing generation module TG performs delay processing on the input synthesized waveform to obtain an output waveform. The specific structure of the timing generation module TG is also not unique, and can be a combination of one or more of the IDELAY (input delay unit), ODELAY (output delay unit) and CARRY modules. Specifically, the delay width of the timing generation module TG covers the clock cycle, and the signal delay can be achieved through the dedicated resources inside the FPGA such as IDELAY, ODELAY, and CARRY. In other embodiments, the timing generation module TG can also use a digital control delay chain chip to achieve signal delay. The pin circuit module PE is responsible for the level control of the excitation signal, the input signal comparison threshold control, etc. Among them, the pin circuit module PE receives the output waveform generated by the timing generation module TG, converts it according to the set level threshold value (VIH\VIL) to obtain the excitation signal and sends it to the device under test DUT, and converts the level amplitude of the excitation signal to make it suitable for the device under test DUT. The pin circuit module PE also compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value, and outputs a comparison signal. Furthermore, the timing generation module TG also samples the comparison signal output by the pin circuit module PE based on the main sampling clock frequency of the system operation.

[0054] In one embodiment, the test system further includes a comparison processing module CP, and the comparison processing module CP is connected to the timing generation module TG and the waveform synthesis module FC. The pin circuit module PE compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value, and outputs the comparison signal to the timing generation module TG; the timing generation module TG performs delayed sampling on the comparison signal output by the pin circuit module PE, and outputs the sampling signal to the comparison processing module CP; the comparison processing module CP analyzes and determines the actual sampling value according to the sampling signal output by the timing generation module TG, and compares and judges the actual sampling value with the preset expected value to obtain the comparison result.

[0055] Specifically, the pin circuit module PE compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB. Among them, when the input signal is less than the threshold value VOL, the output signal CA is low level, and the output signal CB is low level; when the input signal is between the threshold value VOL and the threshold value VOH, the output signal CA is low level, and the output signal CB is high level; when the input signal is greater than the threshold value VOH, the output signal CA is high level, and the output signal CB is high level. The timing generation module TG samples the output signal CA\output signal CB, obtains the sampling signal and sends it to the comparison processing module CP. The comparison processing module CP can analyze the two sampling signals according to the set comparison truth table to determine the actual sampling value, and then judge according to the actual sampling value and the preset expected value, whether the sampling signal is consistent with the expectation, and obtain the comparison result.

[0056] In addition, the test system also includes a timing control module TC for setting the delay time of the timing generation module TG, and the timing generation module TG is connected to the waveform synthesis module FC through the timing control module TC. The timing control module TC is used to calculate according to the set position of the transmission signal edge and the sampling position, analyze the delay time of the timing generation module TG, and then realize the control of the signal edge position and the sampling position through the timing generation module TG, so as to realize the signal transmission and the sampling of the input signal that meet the timing. Among them, the timing control module TC determines the output beat of the signal edge and the delay time within a single clock according to the output signal edge timing information fed by the waveform synthesis module FC. The timing control module TC also determines the sampling clock beat of the signal and the signal delay time information within a single clock according to the input signal sampling position information fed by the waveform synthesis module FC, and feeds the output beat of the signal edge, the delay time within a single clock, the sampling clock beat and the signal delay time information within a single clock into the timing generation module TG. The timing generation module TG delays the output signal and delays the sampling of the input signal according to the beat information and delay information fed by the timing control module TC, thereby realizing the synthesis of the timing relationship of the output signal edge and the fine control of the sampling position of the input signal.

[0057] In one embodiment, the waveform synthesis module FC also determines the output signal edge timing information and the input signal sampling position information according to the graphic timing index, so as to serve as a reference for the timing control module TC to configure the output signal delay and input signal sampling of the timing generation module TG. In addition, the waveform synthesis module FC also controls the processing speed of the waveform synthesis according to the feedback signal of the timing control module TC, and feeds back the output data source module to control the input data flow.

[0058] In the above test system, the multiplexing selection module MUX selects the corresponding output data source module to output the test waveform, first receives the test pattern through the waveform synthesis module FC to synthesize the waveform to obtain the synthesized waveform, and then generates the output waveform through the timing generation module TG. Finally, the pin circuit module PE generates an excitation signal based on the received output waveform and sends it to the device under test DUT. The output waveform is obtained by first synthesizing the waveform and then generating the timing, which reduces the delay compensation error, and the waveform output function can be realized by using a general chip, which reduces the design cost.

[0059] In one embodiment, continue to refer to Figure 1 The test system also includes an error address memory module AFM, which is connected to the comparison processing module CP and is used to receive the comparison result output by the comparison processing module CP and analyze the error address information corresponding to the error information according to the comparison result. The error address memory module AFM records the error address information corresponding to the misaligned bit of the device under test DUT during the test process, so as to retest and repair the misaligned address after the test is completed.

[0060] In one embodiment, the test system further includes a memory error repair analysis module MRA, which is connected to the error address memory module AFM and is used to analyze the distribution law of error bits according to the error address information fed into the error address memory module AFM, and optimize and derive a repair strategy to repair the memory of the device under test DUT. The memory error repair analysis module MRA analyzes the error address information recorded by the error address memory module AFM, optimizes and derives the best repair strategy, and repairs the memory of the device under test DUT.

[0061] In one embodiment, the test system further includes a debugging module Debug, which is connected to the comparison processing module CP and the waveform synthesis module FC, and is used to record the theoretical synthesis waveform and the actual synthesis waveform, as well as the expected waveform and the actual waveform of the device under test DUT response. The debugging module Debug is used in conjunction with a software tool to capture the theoretical synthesis waveform and the actual synthesis waveform stimulated by the test system to the device under test DUT, and the expected waveform and the actual waveform fed back to the test system after the device under test DUT responds, so as to facilitate debugging and analyzing the running status of the debugging code and the working status of the device under test DUT.

[0062] In one embodiment, the test system further includes a test unit processor TUP, which is connected to a debug module Debug and is used to display the waveform data recorded by the debug module Debug through a GUI. Using the test unit processor TUP to run the software tool, the tester can analyze the stimulus waveform and the response waveform through the information displayed by the GUI.

[0063] Specifically, the execution process of the test system is as follows:

[0064] 1. The algorithm graphics generation module ALPG\Graphics generation module PG generates test graphics data stream and performs flow control according to the signal fed back by the waveform synthesis module FC to ensure that the waveform synthesis module FC has a continuous data stream supply.

[0065] 2. The multiplexing selection module MUX selects to use the test pattern generated by the algorithmic pattern generation module ALPG or the pattern generation module PG according to the setting.

[0066] 3. The waveform synthesis module FC synthesizes the waveform format according to the test pattern, and determines the timing information of each output signal and the sampling position information of the input signal according to the graphic timing index. It controls the processing speed of the waveform synthesis according to the feedback signal of the timing control module TC, and then feeds back to the algorithm graphic generation module ALPG\graphic generation module PG to control the input data flow.

[0067] 4. The timing control module TC decomposes and determines the beat of the output edge of the output synthesized waveform signal and the delay time within a single clock according to the output signal edge timing information and the input signal sampling position information fed by the waveform synthesis module FC, and decomposes and determines the sampling clock beat of the input sampling signal and the signal delay time information within a single clock, and feeds the above information into the timing generation module TG.

[0068] 5. The timing generation module TG delays the output signal and delays the sampling of the input signal according to the beat information and delay information fed into the timing control module TC, so as to realize the synthesis of the timing relationship of the output signal edge and the fine control of the sampling position of the input signal.

[0069] 6. The waveform synthesized by the timing generation module TG is fed into the pin circuit module PE. The pin circuit module PE synthesizes high and low level signals according to the set VIH\VIL level information and feeds them into the device under test DUT as an excitation signal.

[0070] 7. The device under test DUT responds to the input stimulus signal and outputs a signal to be fed into the pin circuit module PE.

[0071] 8. The pin circuit module PE compares the signal fed into the device under test DUT according to the set VOH\VOL level, obtains the output signal CA\output signal CB and transmits it to the timing generation module TG.

[0072] 9. The timing generation module TG performs fine sampling of the output signal CA\output signal CB fed into the pin circuit module PE according to the sampling time information transmitted by the timing control module TC, and outputs the sampling signal to the comparison processing module CP.

[0073] 10. The test graphics generated by the algorithm graphics generation module ALPG and the graphics generation module PG are converted into the expected value of each row of sampling by the timing generation module TG in the waveform synthesis module FC, and the expected value is fed to the comparison processing module CP so that the comparison processing module CP can compare and analyze the sampled signals; the waveform synthesis module FC also feeds the expected value of each row and the theoretical synthesis waveform of the original output into the debugging module Debug.

[0074] 11. The comparison processing module CP first performs a table lookup and matching comparison on the sampling signal output by the timing generation module TG, and obtains that the signal output by the device under test DUT is high level (High), low level (Low) or high impedance (HighZ), and uses the matching comparison result to compare with the expected value fed into the waveform synthesis module FC to determine whether the sampling value is consistent with the expected value. If they are consistent, True is output, otherwise False is output. The comparison result is fed into the error address memory module AFM.

[0075] 12. The error address memory module AFM records the corresponding error address information according to the error information fed by the comparison processing module CP, and feeds the error address information to the memory error repair analysis module MRA.

[0076] 13. The memory error repair analysis module MRA analyzes the distribution of error bits according to the error address information fed into the error address memory module AFM, and optimizes and obtains the best repair strategy to repair the memory of the device under test DUT.

[0077] 14. The debugging module Debug records the theoretical synthetic waveform of the transmitted waveform and the actual synthetic waveform sent to the device under test DUT according to the configuration, and records the expected waveform and the actual waveform of the response of the device under test DUT, and uploads the relevant waveform information to the software analysis tool of the test unit processor TUP.

[0078] 15. The test unit processor TUP runs the software analysis tool to collect the relevant waveform information captured by the debugging module Debug, and presents it to the tester in the form of GUI so that the tester can debug and analyze whether the running status of the test program is normal and whether the working status of the device under test DUT is normal.

[0079] In one embodiment, Figure 2 As shown, a testing method is also provided, including:

[0080] Step S110: the multiplexing selection module switches to output the test pattern corresponding to the output data source module.

[0081] Step S120: The waveform synthesis module synthesizes the waveform format of the test pattern output by the multiplexing selection module according to the configured waveform format, and outputs a synthesized waveform.

[0082] Step S130: the timing generation module performs delay processing on the synthesized waveform output by the waveform synthesis module to generate an output waveform.

[0083] Step S140: the pin circuit module receives the output waveform generated by the timing generation module, and outputs an excitation signal to the device under test.

[0084] In one embodiment, the method further includes: the pin circuit module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal; the timing generation module delays sampling the comparison signal output by the pin circuit module, and outputs a sampling signal; the comparison processing module analyzes and determines the actual sampling value according to the sampling signal output by the timing generation module, and compares and judges the actual sampling value with the preset expected value to obtain a comparison result.

[0085] In one embodiment, the method further includes: the timing control module determines the output beat of the signal edge and the delay time within a single clock according to the output signal edge timing information fed into the waveform synthesis module; the timing control module determines the sampling clock beat of the signal and the signal delay time information within a single clock according to the input signal sampling position information fed into the waveform synthesis module; the timing control module feeds the output beat of the signal edge, the delay time within a single clock, the sampling clock beat and the signal delay time information within a single clock into the timing generation module.

[0086] In one embodiment, the method further includes: the waveform synthesis module determines the output signal edge timing information and the input signal sampling position information according to the graphic timing index, controls the processing speed of the waveform synthesis according to the feedback signal of the timing control module, and feeds back the output data source module to control the input data flow.

[0087] In one embodiment, the method further includes: the waveform synthesis module converts the received test pattern to obtain the expected value of each row sampled by the timing generation module, and feeds the expected value into the comparison processing module.

[0088] In one embodiment, the method further includes: the error address memory module receives the comparison result output by the comparison processing module, and analyzes the error address information corresponding to the error information according to the comparison result; the memory error repair analysis module analyzes the distribution law of the error bit according to the error address information fed into the error address memory module, optimizes and derives the repair strategy to repair the memory of the device to be tested.

[0089] In one embodiment, the method further includes: a debugging module recording theoretical synthesized waveforms and actual synthesized waveforms, as well as expected waveforms and actual waveforms of responses of the device under test; and a test unit processor displaying the waveform data recorded by the debugging module through a GUI.

[0090] It can be understood that the specific implementation of the above-mentioned testing method has been explained in detail in the above-mentioned testing system, and will not be repeated here.

[0091] The above-mentioned test system and test method, in the process of waveform format synthesis and waveform timing synthesis, first synthesize the waveform format, then move the edge of the waveform format in timing, and finally synthesize the output waveform, which can be more easily implemented in FPGA devices, does not require phase switching of the clock, and reduces the complexity of the design. In the timing synthesis technology of the synthesized waveform, it is decomposed into two parts: timing calculation control and timing generation, which respectively realize the decomposition of the required timing parameters and the generation of timing delay. In the implementation technology of the timing synthesis of the synthesized waveform and the dynamic adjustment of the sampling position of the input signal, the flexibility of the timing synthesis is improved by moving the signal instead of adjusting the main clock frequency and phase.

[0092] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A testing system, characterized in that: include: At least two output data source modules; A multiplexing selection module, connected to each of the output data source modules, for switching and outputting the test pattern corresponding to the output data source module; A waveform synthesis module, connected to the multiplexing selection module, for synthesizing the waveform format of the test pattern output by the multiplexing selection module according to the configured waveform format, and outputting a synthesized waveform; A timing generation module, connected to the waveform synthesis module, for performing delay processing on the synthesized waveform output by the waveform synthesis module to generate an output waveform; The pin circuit module is connected to the timing generation module and the device to be tested, and is used to receive the output waveform generated by the timing generation module and output an excitation signal to the device to be tested.

2. The test system according to claim 1, characterized in that: The output data source module includes an algorithm graph generation module and a graph generation module.

3. The test system according to claim 1, characterized in that: It also includes a comparison processing module, which is connected to the timing generation module and the waveform synthesis module; The pin circuit module compares and judges the input signal fed back by the device under test according to a preset level threshold value, and outputs a comparison signal to the timing generation module; The timing generation module performs delayed sampling on the comparison signal output by the pin circuit module, and outputs the sampling signal to the comparison processing module; The comparison processing module analyzes and determines the actual sampling value according to the sampling signal output by the timing generation module, and compares and determines the actual sampling value with a preset expected value to obtain a comparison result.

4. The test system according to claim 3, characterized in that: It also includes a timing control module for setting the delay time of the timing generation module, and the timing generation module is connected to the waveform synthesis module through the timing control module.

5. The test system according to claim 3, characterized in that: It also includes an error address memory module, which is connected to the comparison processing module and is used to receive the comparison result output by the comparison processing module and analyze the error address information corresponding to the error information according to the comparison result.

6. The test system according to claim 5, characterized in that: It also includes a memory error repair analysis module, which is connected to the error address memory module and is used to analyze the distribution pattern of error bits according to the error address information fed into the error address memory module, and optimize the repair strategy to repair the memory of the device under test.

7. The test system according to claim 3, characterized in that: It also includes a debugging module, which is connected to the comparison processing module and the waveform synthesis module and is used to record the theoretical synthesis waveform and the actual synthesis waveform, as well as the expected waveform and the actual waveform of the response of the device to be tested.

8. The test system according to claim 7, characterized in that: It also includes a test unit processor, which is connected to the debugging module and is used to display the waveform data recorded by the debugging module in a GUI manner.

9. A testing method, characterized in that: include: The multiplexing selection module switches and outputs the test pattern corresponding to the output data source module; The waveform synthesis module synthesizes the waveform format of the test pattern output by the multiplexing selection module according to the configured waveform format, and outputs a synthesized waveform; The timing generation module performs delay processing on the synthesized waveform output by the waveform synthesis module to generate an output waveform; The pin circuit module receives the output waveform generated by the timing generation module, and outputs an excitation signal to the device under test.

10. The method according to claim 9, characterized in that Also includes: The pin circuit module compares and judges the input signal fed back by the device under test according to a preset level threshold value, and outputs a comparison signal; The timing generation module performs delayed sampling on the comparison signal output by the pin circuit module and outputs a sampling signal; The comparison processing module analyzes and determines the actual sampling value according to the sampling signal output by the timing generation module, and compares and determines the actual sampling value with a preset expected value to obtain a comparison result.

11. The method according to claim 10, characterized in that Also includes: The timing control module determines the output beat of the signal edge and the delay time within a single clock according to the output signal edge timing information fed into the waveform synthesis module; The timing control module determines the sampling clock beat of the signal and the signal delay time information within a single clock according to the sampling position information of the input signal fed into the waveform synthesis module; The timing control module feeds the output beat of the signal edge, the delay time within the single clock, the sampling clock beat and the signal delay time information within the single clock into the timing generation module.

12. The method according to claim 11, characterized in that Also includes: The waveform synthesis module determines the output signal edge timing information and the input signal sampling position information according to the graphic timing index, controls the processing speed of the waveform synthesis according to the feedback signal of the timing control module, and feeds back the output data source module to control the input data flow.

13. The method according to claim 10, characterized in that Also includes: The waveform synthesis module obtains the expected value of each row sampled by the timing generation module according to the received test pattern conversion, and feeds the expected value into the comparison processing module.

14. The method according to claim 10, characterized in that Also includes: The error address memory module receives the comparison result output by the comparison processing module, and analyzes the error address information corresponding to the error information according to the comparison result; The memory error repair analysis module analyzes the distribution law of the error bits according to the error address information fed by the error address memory module, optimizes and obtains a repair strategy to repair the memory of the device under test.

15. The method according to claim 10, characterized in that Also includes: The debugging module records the theoretical synthesized waveform and the actual synthesized waveform, as well as the expected waveform and the actual waveform of the response of the device under test; The test unit processor displays the waveform data recorded by the debugging module through a GUI.

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