Thread running method and device and electronic equipment

Abstract

The invention discloses a thread running method and device and electronic equipment, and belongs to the technical field of terminals. The method comprises the following steps: when an application program is in a scene switching state, determining a key thread associated with scene switching; distributing the key thread to a target processor core for operation; under the condition that the target processor core runs the key thread, the running frequency of the target processor core is adjusted from the first frequency to a second frequency, and the second frequency is larger than the first frequency.

Description

Technical Field

[0001] The present application belongs to the field of terminal technology, and specifically relates to a thread running method, device and electronic device. Background Art

[0002] Nowadays, when running applications containing multiple scenes on devices such as mobile phones and computers, due to technical and engine limitations, all scenes are usually not loaded at once, but only the scenes currently needed by the user are loaded. When the user needs to switch from the current scene to a new scene, the new scene is loaded. Since the new scene takes a relatively long time to load, the scene switching takes a long time, which will have a certain impact on the user experience of the application.

[0003] In order to solve the above problems, in the related art, whenever the application is in the state of scene switching, the frequency of all processor cores in the processor is increased to improve the processor performance and reduce the time consumption of scene switching. However, this method of reducing time consumption will increase additional power consumption. Therefore, how to balance performance and power consumption is a problem that needs to be solved. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a thread running method, device and electronic device to balance the performance and power consumption of an application program of an existing device during scene switching.

[0005] In a first aspect, an embodiment of the present application provides a thread running method, the method comprising:

[0006] When the application is in the state of scene switching, determine the key threads associated with the scene switching;

[0007] Allocating the critical thread to a target processor core for execution;

[0008] In a case where the target processor core runs the critical thread, the operating frequency of the target processor core is adjusted from a first frequency to a second frequency, wherein the second frequency is greater than the first frequency.

[0009] In a second aspect, an embodiment of the present application provides a thread running device, the device comprising:

[0010] A determination module, used for determining a key thread associated with a scene switch when the application is in a scene switch state;

[0011] An allocation module, used for allocating the key thread to a target processor core for execution;

[0012] An adjustment module is used to adjust the operating frequency of the target processor core from a first frequency to a second frequency when the target processor core runs the critical thread, wherein the second frequency is greater than the first frequency.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method provided in the first aspect are implemented.

[0014] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method provided in the first aspect are implemented.

[0015] In a fifth aspect, an embodiment of the present application provides a chip, the chip including a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the method provided in the first aspect.

[0016] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method provided in the first aspect.

[0017] In the thread operation method, device and electronic device of the present application, the key thread associated with the scene switching can be determined, and the key thread can be assigned to a suitable target processor core for operation, and when the key thread is running on the target processor core, the operating frequency of the target processor core is increased. In this way, it can be ensured that the key thread related to the scene switching runs on a high-performance processor core, and by adjusting the operating frequency of the processor core, it can be ensured that these key tasks can obtain sufficient processor resources during the scene switching process. At the same time, the present application only increases the operating frequency of the processor core where the key thread is located when the key thread is running, rather than increasing the operating frequency of all processor cores for a long time, which can improve the efficiency of scene switching with lower power consumption and reduce unnecessary power consumption overhead. Ultimately, a balance between performance and power consumption is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flowchart of a thread operation method provided by an embodiment of the present application;

[0019] Figure 2 is a structural schematic diagram of a thread running device provided by another embodiment of the present application;

[0020] Figure 3 is a structural schematic diagram of an electronic device provided by another embodiment of the present application;

[0021] Figure 4 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0023] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0024] In order to solve the above technical problems, the present application provides a thread operation method. The thread operation method provided by the embodiment of the present application is described in detail below through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0025] like Figure 1 As shown, Figure 1 : is a flowchart of a thread running method provided by an embodiment of the present application. The embodiment of the present application provides a thread running method, which may include:

[0026] S101, when the application is in a scene switching state, determining a key thread associated with the scene switching;

[0027] In this embodiment, the state of scene switching refers to the process of an application switching from one scene or view to another scene or view. In this process, the application needs to load and render new content, so this state involves a large amount of data processing and graphics rendering operations, and the scene switching takes a long time. For example, the application may be a game application, and a scene switching is required when switching from one game level to another game level in the game application; the application may also be a multimedia application, and a scene switching is required when switching from one video playback scene to another video playback scene in the multimedia application.

[0028] Critical threads are threads that carry the main workload in a system or application and have a direct impact on performance and response time. Such threads are usually given a higher priority to ensure that they can complete their tasks in a timely manner to avoid system bottlenecks or delays.

[0029] When the application is in a state associated with scene switching, the key thread can be the key task in scene switching, which can directly affect the efficiency and time consumption of scene switching. For example, the key thread can be the task of loading resources such as images, audio and model files required for the new scene, and the key thread can also be the task of rendering images in the new scene.

[0030] In some embodiments, S101 includes:

[0031] When the frame interval of the application is greater than a threshold, a critical thread associated with the scene switch is determined.

[0032] In this embodiment, the frame interval of the application refers to the interval between the generation time of two adjacent frames of images. The application can continuously monitor the interval between the generation time of two adjacent frames of images. Since more content needs to be loaded in the state of scene switching, the interval between the generation time of two adjacent frames of images will be larger. If the frame interval is monitored to be greater than the preset threshold, it can be considered that the application is in the state of scene switching; if the frame interval is monitored to be less than or equal to the preset threshold, it can be considered that the application is not in the state of scene switching.

[0033] In the above manner, it is possible to accurately determine whether the application is in a scene switching state.

[0034] In some embodiments, S101 includes:

[0035] The task of the rendering task that has woken up the application program within the target time period is determined as a key thread associated with the scene switch.

[0036] In this embodiment, in the process of determining the critical thread associated with the scene switch, the rendering task used to render the image in the application can be first determined, and then based on the determined rendering task, the task that has woken up the rendering task within the target time period can be determined. Specifically, the task that has woken up the rendering task is a task used to notify or activate the rendering task to start execution. The rendering task and the task that has woken up the rendering task within the target time period can be determined as the critical thread associated with the scene switch. The target time period can be a first duration before the current moment, and the first duration can be 1 second or 3 seconds.

[0037] For example, when the application is a game application, the rendering task is a task for rendering game scenes, characters and special effects. Then the task that wakes up the rendering task can be a task for processing user input, physics engine calculations or AI logic. After these tasks are completed, the rendering task will be woken up for image rendering.

[0038] Through the above method, all tasks directly and indirectly related to image rendering can be quickly identified and accurately determined as key threads.

[0039] In some embodiments, the number of critical threads is less than or equal to the number of processor cores.

[0040] In this embodiment, after the rendering task that has woken up the application within the target time period is determined as a critical thread, the number of critical threads at this time can be obtained, and the number of processor cores in the electronic device can be obtained, and the critical threads can be adjusted based on the number of processor cores so that the number of critical threads is less than or equal to the number of processor cores.

[0041] Specifically, since the critical thread is a critical task that needs to be optimized and has a greater impact on the efficiency of scene switching, each processor core can only be assigned at most one critical thread. Take the number of critical threads as N and the number of processor cores as M as an example, N and M are both positive integers. Then, when the number of critical threads N related to image rendering is greater than the number of processor cores M, it is necessary to select the tasks that have the greatest impact on system performance from the N critical threads for priority processing. In the case where one processor core corresponds to one critical thread, the M critical threads with the highest CPU utilization rate can be selected from the N critical threads as the critical threads that need to be prioritized, and tasks other than the M critical threads can be modified to non-critical threads.

[0042] When the number N of critical threads related to image rendering is less than or equal to the number M of processor cores, the task processor has sufficient resources to optimize all critical threads, so all N critical threads can be reserved as critical threads for optimization.

[0043] In this embodiment, through the above method, the critical thread with high CPU usage can be used as the key thread, which can ensure that system resources are preferentially allocated to the tasks related to image rendering that have the greatest impact on performance, thereby maximizing system performance and response speed, and improving the efficiency of image rendering and scene switching as much as possible.

[0044] S102, allocating the key thread to a target processor core for execution;

[0045] In an embodiment of the present application, after determining the critical thread, since the critical thread bears the main workload and has a direct impact on performance and response time, the priority of the critical thread is higher. In order to ensure that the critical thread is processed first, it needs to be allocated to the target processor core to run, where the target processor core can be the processor core with the best performance in the processor, or it can be the processor core with the lowest load status in the processor.

[0046] In some embodiments, the number of the critical threads is greater than 1, and S102 includes:

[0047] Assign critical threads with the highest CPU usage to the super-large core processor core for execution.

[0048] In this embodiment, a processor may include multiple processor cores, which may run independently, and different processor cores may have different performances. Based on the performances of different processor cores, the multiple processor cores may be divided into super-large core processor cores, large core processor cores, and small core processor cores. The performance of the super-large core processor core is higher than that of the large core processor core, and the performance of the large core processor core is higher than that of the small core processor core.

[0049] If there are multiple critical threads, then the CPU usage of the critical thread can be used. The CPU usage of a critical thread refers to the proportion of the total running time of the critical thread in a period of time. The CPU usage can characterize the actual load of the critical thread. After determining the CPU usage of the critical thread, the processor core can be allocated to the critical thread based on the CPU usage of the critical thread.

[0050] Specifically, if the CPU usage rate of a key thread is high, the key thread can be assigned to a processor core with better performance; if the CPU usage rate of a key thread is low, the key thread can be assigned to a processor core with poorer performance. Therefore, the key thread with the highest CPU usage rate can be assigned to run on the super-large core processor core with the best performance. In this way, the running efficiency of the thread can be guaranteed.

[0051] For example, when the processor includes P processor cores and there are also P critical threads, the P critical threads can be allocated to the P processor cores with performance from high to low in order of the CPU usage of the P critical threads from large to small, where each processor core is allocated one critical thread and P is a positive integer greater than 1.

[0052] In this embodiment, if the processor includes P processor cores and there are exactly P critical threads, then the P critical threads can be allocated to the P processor cores with performance from high to low in order of the CPU usage of the P critical threads from large to small.

[0053] For example, P can be 3, and the processor includes core 1, core 2 and core 3, among which core 1 is the processor core with the highest performance, that is, the super-large core processor core, core 2 is the processor core with the second highest performance, that is, the large-core processor core, and core 3 is the processor core with the lowest performance, that is, the small-core processor core; the three key threads include task A, task B and task C, among which the CPU utilization rate of task A is 70%, the CPU utilization rate of task B is 60%, and the CPU utilization rate of task C is 50%. Task A can be assigned to core 1, task B to core 2, and task C to core 3.

[0054] This ensures that high-load tasks are assigned to high-performance cores, thereby optimizing overall system performance and response speed. In this way, processor resources can be effectively utilized and system processing efficiency can be improved.

[0055] S103: When the target processor core runs the critical thread, adjust the operating frequency of the target processor core from a first frequency to a second frequency, wherein the second frequency is greater than the first frequency.

[0056] In this embodiment, the operating frequency of the processor core is the number of oscillation cycles executed by the processor core per second. Since the key thread is a key task related to the scene switching in the scene switching state, when the key thread is running on the target processor core, the operating frequency of the target processor core needs to be increased to speed up the processing speed of the key thread.

[0057] Specifically, when the critical thread is not running, the operating frequency of the target processor core is the initial first frequency. When it is detected that the critical thread is running on the target processor core, the operating frequency of the target processor core can be increased from the initial first frequency to the second frequency.

[0058] In some embodiments, adjusting the operating frequency of the target processor core from a first frequency to a second frequency includes:

[0059] The minimum constraint value of the task utilization corresponding to the critical thread is adjusted to a first ratio, and the maximum constraint value of the task utilization corresponding to the critical thread is adjusted to a second ratio, wherein the first ratio is greater than a first default ratio of the minimum constraint value, the second ratio is greater than a second default ratio of the maximum constraint value, and the operating frequencies corresponding to the first default ratio and the second default ratio are the first frequency;

[0060] The operating frequency of the target processor core is adjusted from the first frequency to the second frequency according to the adjusted first ratio and the second ratio.

[0061] In this embodiment, the task utilization is used to indicate the busyness of the processor. The minimum constraint value and the maximum constraint value of the task utilization together constitute the constraint condition of the proportion of the critical thread's running time to the total time, wherein the minimum constraint value of the task utilization corresponding to the critical thread is used to indicate that the critical thread obtains the least proportion of processor time during the execution process; the maximum constraint value of the task utilization corresponding to the critical thread is used to indicate that the critical thread obtains the greatest proportion of processor time during the execution process.

[0062] The application can adjust the operating frequency corresponding to the key thread based on the minimum constraint value and the maximum constraint value of the task utilization when the task is running. For example, when both the minimum constraint value and the maximum constraint value are increased, in order to ensure that the key thread can obtain more resources, the processor frequency can be dynamically increased to achieve the best balance between performance and energy efficiency.

[0063] Specifically, the first default ratio is the default ratio of the preset minimum constraint value of the task utilization, and the second default ratio is the default ratio of the preset maximum constraint value of the task utilization. After the critical thread is determined, the minimum constraint value and the maximum constraint value of the corresponding task utilization of the critical thread can be increased on the basis of the default ratio, and the minimum constraint value is adjusted from the first default ratio to the first ratio, and the maximum constraint value is adjusted from the second default ratio to the second ratio. In this way, the application can adjust the operating frequency of the target processor core from the initial first frequency to the second frequency when the critical thread is running based on the adjusted first ratio and second ratio.

[0064] For example, the first default ratio of task utilization is 30%, the second default ratio of task utilization is 50%, the first ratio is 40%, and the second ratio is 70%. Then, after determining the critical thread, the minimum constraint value of the task utilization of the critical thread can be increased from 30% to 40%, and the maximum constraint value of the task utilization of the critical thread can be increased from 50% to 70%. In this way, the operating frequency of the target processor core when the critical thread is running can be adjusted from the initial first frequency to the second frequency based on the adjusted first ratio and second ratio, thereby shortening the execution time of the critical thread.

[0065] In this way, by increasing the minimum and maximum constraints of task utilization, the processor frequency can be dynamically adjusted to achieve the best balance between performance and energy efficiency.

[0066] In some embodiments, the task information of the critical thread is stored in a critical thread list; if a critical thread is removed from the critical thread list, the minimum constraint value of the task utilization of the removed critical thread is adjusted to a first default ratio, and the maximum constraint value of the task utilization is adjusted to the second default ratio.

[0067] In this embodiment, the critical thread list is a data structure or set for storing critical tasks, i.e., critical threads, that are identified as being important to system performance and task execution in a specific scenario. Tasks stored in the critical thread list are critical tasks with higher priorities in the current scenario and need to be allocated more resources or be better optimized.

[0068] Then, when the application is in the state of scene switching, the tasks associated with image rendering can be first stored in the key thread list as relatively important key tasks, and then the number of key threads and the number of processor cores can be compared. If the number N of tasks related to image rendering is greater than the number M of processor cores, it is necessary to select M key threads that have the greatest impact on system performance from the N key threads as the final key threads, and remove the key threads other than the M key threads from the key thread list, and adjust the task utilization and allocate processor cores for the key threads in the key thread list.

[0069] At this time, the key thread in the key thread list is in a critical state. If the key thread is updated, there is a key thread that was originally in a critical state. After the update, the key thread is de-critical and is no longer a key thread. Then the key thread needs to be removed from the key thread list. After the removal, in order to avoid the de-critical key thread occupying too many processor resources, the minimum constraint value of the task utilization of the key thread needs to be reduced to the first default ratio, and the maximum constraint value of the task utilization needs to be reduced to the second default ratio.

[0070] Through the above method, it can be ensured that the processor resources are allocated to the most critical task in real time, avoiding the waste of processor resources and the increase of additional power consumption.

[0071] In this application, the key thread associated with the scene switching can be determined, and the key thread can be assigned to a suitable target processor core to run, and when the key thread runs on the target processor core, the operating frequency of the target processor core is increased. In this way, it can be ensured that the key thread related to the scene switching runs on a high-performance processor core, and by adjusting the operating frequency of the processor core, it can be ensured that these key tasks can obtain sufficient processor resources during the scene switching process. At the same time, this application only increases the operating frequency of the processor core where the key thread is located when the key thread is running, rather than increasing the operating frequency of all processor cores for a long time, which can improve the efficiency of scene switching with lower power consumption and reduce unnecessary power consumption overhead. Ultimately, a balance between performance and power consumption is achieved.

[0072] Figure 2 is a structural diagram of a thread running device provided by another embodiment of the present application, such as Figure 2 As shown, the running device of the thread may include:

[0073] A determination module 201, used for determining a key thread associated with a scene switching when the application is in a scene switching state;

[0074] An allocation module 202, configured to allocate the critical thread to a target processor core for execution;

[0075] The adjustment module 203 is used to adjust the operating frequency of the target processor core from a first frequency to a second frequency when the target processor core runs the critical thread, wherein the second frequency is greater than the first frequency.

[0076] In this application, the key thread associated with the scene switching can be determined, and the key thread can be assigned to a suitable target processor core to run, and when the key thread runs on the target processor core, the operating frequency of the target processor core is increased. In this way, it can be ensured that the key thread related to the scene switching runs on a high-performance processor core, and by adjusting the operating frequency of the processor core, it can be ensured that these key tasks can obtain sufficient processor resources during the scene switching process. At the same time, this application only increases the operating frequency of the processor core where the key thread is located when the key thread is running, rather than increasing the operating frequency of all processor cores for a long time, which can improve the efficiency of scene switching with lower power consumption and reduce unnecessary power consumption overhead. Ultimately, a balance between performance and power consumption is achieved.

[0077] In another optional example, the determining module 201 includes:

[0078] The first determining unit is used to determine a critical thread associated with the scene switching when a frame interval of the application is greater than a threshold.

[0079] In another optional example, the determining module 201 includes:

[0080] The second determining unit is used to determine the rendering task that has woken up the application program within the target time period as a key thread associated with the scene switch.

[0081] In another optional example, the number of the critical threads is less than or equal to the number of processor cores.

[0082] In another optional example, the number of the critical threads is greater than 1, and the allocation module 202 includes:

[0083] The allocation unit is used to allocate the key threads with the highest CPU usage to the super-large core processor core for operation.

[0084] The thread running device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a car-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the embodiment of the present application is not specifically limited.

[0085] The thread running device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0086] The thread running device provided in the embodiment of the present application can realize Figure 1 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0087] Alternatively, if Figure 3 As shown, an embodiment of the present application also provides an electronic device 100, including a processor 110, a memory 119, and a program or instruction stored in the memory 119 and executable on the processor 110. When the program or instruction is executed by the processor 110, each process of the above-mentioned thread running method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0088] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0089] Please refer to Figure 4 , Figure 4 The hardware structure diagram of an electronic device for implementing an embodiment of the present application is shown in FIG. The electronic device 100 includes, but is not limited to, a radio frequency unit 121, a network module 122, an audio output unit 123, an input unit 124, a sensor 125, a display unit 126, a user input unit 127, an interface unit 128, a memory 129, and a processor 120.

[0090] Those skilled in the art will appreciate that the electronic device 100 may also include a power source (such as a battery) for supplying power to various components, and the power source may be logically connected to the processor 120 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Figure 4 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0091] The processor 120 is used to determine a key thread associated with the scene switching when the application is in the scene switching state;

[0092] The processor 120 is used to allocate the critical thread to a target processor core for execution;

[0093] The processor 120 is configured to adjust the operating frequency of the target processor core from a first frequency to a second frequency when the target processor core runs the critical thread, wherein the second frequency is greater than the first frequency.

[0094] In this application, the key thread associated with the scene switching can be determined, and the key thread can be assigned to a suitable target processor core to run, and when the key thread runs on the target processor core, the operating frequency of the target processor core is increased. In this way, it can be ensured that the key thread related to the scene switching runs on a high-performance processor core, and by adjusting the operating frequency of the processor core, it can be ensured that these key tasks can obtain sufficient processor resources during the scene switching process. At the same time, this application only increases the operating frequency of the processor core where the key thread is located when the key thread is running, rather than increasing the operating frequency of all processor cores for a long time, which can improve the efficiency of scene switching with lower power consumption and reduce unnecessary power consumption overhead. Ultimately, a balance between performance and power consumption is achieved.

[0095] In another optional example, the processor 120 is further configured to:

[0096] When the frame interval of the application is greater than a threshold, a critical thread associated with the scene switch is determined.

[0097] In another optional example, the processor 120 is further configured to:

[0098] The task of the rendering task that has woken up the application program within the target time period is determined as a key thread associated with the scene switch.

[0099] In another optional example, the number of the critical threads is less than or equal to the number of processor cores.

[0100] In another optional example, the number of the critical threads is greater than 1, and the processor 120 is further configured to: allocate the critical thread with the highest CPU usage to the super-large core processor core for execution.

[0101] It should be understood that in the embodiment of the present application, the input unit 124 may include a graphics processor (Graphics Processing Unit, GPU) 1241 and a microphone 1242, and the graphics processor 1241 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 126 may include a display panel 1261, and the display panel 1261 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 127 includes a touch panel 1271 and at least one of other input devices 1272. The touch panel 1271 is also called a touch screen. The touch panel 1271 may include two parts: a touch detection device and a touch controller. Other input devices 1272 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0102] The memory 129 can be used to store software programs and various data. The memory 129 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 129 may include a volatile memory or a non-volatile memory, or the memory 129 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 129 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0103] The processor 120 may include one or more processing units; optionally, the processor 120 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 120.

[0104] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned thread running method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0105] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0106] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned thread running method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0107] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0108] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned thread running method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0109] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0110] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0111] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A thread running method, characterized in that: include: When the application is in the state of scene switching, determine the key threads associated with the scene switching; Allocating the critical thread to a target processor core for execution; In a case where the target processor core runs the critical thread, the operating frequency of the target processor core is adjusted from a first frequency to a second frequency, wherein the second frequency is greater than the first frequency.

2. The method according to claim 1, characterized in that The step of determining the key thread associated with the scene switching when the application is in the scene switching state includes: When the frame interval of the application is greater than a threshold, a critical thread associated with the scene switch is determined.

3. The method according to claim 1, characterized in that: The determining of the key threads associated with the scene switching includes: The task of the rendering task that has woken up the application program within the target time period is determined as a key thread associated with the scene switch.

4. The method according to claim 3, characterized in that The number of the key threads is less than or equal to the number of processor cores.

5. The method according to claim 1, characterized in that The number of the key threads is greater than 1, and the step of allocating the key threads to the target processor core for execution includes: Assign critical threads with the highest CPU usage to the super-large core processor core for execution.

6. A thread running device, characterized in that: include: A determination module, used for determining a key thread associated with a scene switch when the application is in a scene switch state; An allocation module, used for allocating the key thread to a target processor core for execution; An adjustment module is used to adjust the operating frequency of the target processor core from a first frequency to a second frequency when the target processor core runs the critical thread, wherein the second frequency is greater than the first frequency.

7. The device according to claim 6, characterized in that The determination module comprises: The first determining unit is used to determine a critical thread associated with the scene switching when a frame interval of the application is greater than a threshold.

8. The device according to claim 6, characterized in that The determination module comprises: The second determining unit is used to determine the rendering task that has woken up the application program within the target time period as a key thread associated with the scene switch.

9. The device according to claim 8, characterized in that The number of the key threads is less than or equal to the number of processor cores.

10. The device according to claim 6, characterized in that The number of the critical threads is greater than 1, and the allocation module includes: The allocation unit is used to allocate the key threads with the highest CPU usage to the super-large core processor core for operation.

11. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the thread running method according to any one of claims 1 to 5 are implemented.

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