Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps: acquiring quantitative evaluation information corresponding to each entity unit according to erasing counting information, reading counting information and effective counting information corresponding to each entity unit; determining a source unit from a plurality of entity units according to the quantitative evaluation information; and carrying out data migration on the effective data in the source unit. Therefore, the execution efficiency of the garbage collection operation and the maintenance and management efficiency of the storage device can be considered, and the service life of the storage device can be prolonged.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] When a storage device is shipped, some of the physical units (e.g., physical blocks) in the storage device are configured as idle physical units so that these idle physical units can be used to store new data. However, after the storage device has been used for a period of time, the number of idle physical units in the storage device will gradually decrease. Therefore, after the storage device has been used for a period of time, the storage device can perform a garbage collection (GC) operation to move valid data from the source unit to the target unit and erase the physical units belonging to the source unit to release new idle physical units.

[0003] Generally speaking, in a garbage collection operation, physical units storing relatively less valid data will be preferentially selected as source units to move valid data from. However, in some cases, simply using the amount of valid data stored as the basis for selecting source units may increase the difficulty of subsequent maintenance of the storage device (e.g., repeatedly performing garbage collection on a small number of physical units), and may even shorten the service life of the storage device.

[0004] Therefore, how to balance the execution performance of garbage collection operations and the maintenance and management performance of storage devices is a problem that urgently needs to be solved. Summary of the invention

[0005] The present invention provides a memory management method and a storage device, which can take into account both the execution performance of garbage collection operation and the maintenance management performance of the storage device, thereby increasing the service life of the storage device.

[0006] An embodiment of the present invention provides a memory management method for a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: obtaining quantitative evaluation information corresponding to each physical unit according to erase count information, read count information and valid count information corresponding to each physical unit in the plurality of physical units; determining a source unit from the plurality of physical units according to the quantitative evaluation information; and performing data migration on valid data in the source unit.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: obtain quantitative evaluation information corresponding to each physical unit in the plurality of physical units according to erase count information, read count information and valid count information corresponding to each physical unit in the plurality of physical units; determine a source unit from the plurality of physical units according to the quantitative evaluation information; and perform data migration on valid data in the source unit.

[0008] Based on the above, according to the erase count information, read count information and valid count information corresponding to each physical unit in the memory module, the quantitative evaluation information corresponding to each physical unit can be obtained; according to the quantitative evaluation information, the source unit can be determined from multiple physical units in the memory module, and then the valid data in the source unit can be moved. That is, by comprehensively considering a variety of information that is beneficial to the maintenance and management of the storage device (such as erase count information, read count information and valid count information) to select the source unit, the execution performance of the garbage collection operation and the maintenance and management performance of the storage device can be taken into account, thereby increasing the service life of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of a data sorting operation according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of obtaining quantitative evaluation information according to an embodiment of the present invention;

[0014] Figure 6 is a schematic diagram of determining a source unit according to quantitative evaluation information corresponding to a plurality of entity units according to an embodiment of the present invention;

[0015] Figure 7 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0019] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0020] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0021] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0022] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0026] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used to store data in a non-volatile manner.

[0027] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units. In one embodiment, a physical unit may include one or more virtual blocks. Each virtual block may include multiple physical erase units.

[0028] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0030] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0031] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0033] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0037] In one embodiment, the memory control circuit 23 may monitor the total number of physical units (i.e., idle physical units, such as physical units 301(A+1) to 301(B)) in the current idle area 32. The memory control circuit 23 may determine whether the total number of physical units in the idle area 32 is less than a critical value (also referred to as a first critical value). If the total number of physical units in the idle area 32 is less than the first critical value, the memory control circuit 23 may start or trigger a data sorting operation. For example, the data sorting operation is used to release new idle physical units to increase the total number of idle physical units. For example, the data sorting operation may include a garbage collection (GC) operation or a similar operation.

[0038] In one embodiment, during the data sorting operation, the memory control circuit 23 may select at least one physical cell from the data area 31 as a source cell. For example, the memory control circuit 23 may select at least one physical cell from the physical cells 301(1) to 301(A) in the data area 31 as a source cell. In addition, during the data sorting operation, the memory control circuit 23 may select at least one physical cell from the idle area 32 as a target cell. For example, the memory control circuit 23 may select at least one physical cell from the physical cells 301(A+1) to 301(B) in the idle area 32 as a source cell.

[0039] In the data arrangement operation, after determining the source unit, the memory control circuit 23 can instruct the memory module 122 to move or copy the valid data from the source unit to the target unit. If the valid data in a certain physical unit as the source unit has been completely moved or copied to the target unit, the memory control circuit 23 can associate this physical unit with the idle area 32 and instruct the memory module 122 to erase this physical unit. In this way, the purpose of releasing new idle physical units can be achieved to increase the total number of idle physical units.

[0040] Figure 4is a schematic diagram of a data sorting operation according to an embodiment of the present invention. Figure 4 In one embodiment, the memory control circuit 23 may determine the physical units 401(1)-401(D) as the source units 41, and the physical units 402(1)-402(E) as the target units 42. In the data cleanup operation, the memory control circuit 23 may instruct the memory module 122 to read the data 401 (i.e., valid data) from the source units 41 (i.e., the physical units 401(1)-401(D)) and store the read data 401 in the target units 42 (i.e., the physical units 402(1)-402(E)). In addition, if the valid data in the physical unit 401(i) has been completely moved or copied to the target unit 42, the memory control circuit 23 may associate the physical unit 401(i) with the idle area 32, and may instruct the memory module 122 to erase the physical unit 401(i).

[0041] In one embodiment, after starting or triggering the data cleanup operation, the memory control circuit 23 may determine whether the total number of physical cells in the idle area 32 is greater than a critical value (also referred to as a second critical value). If the total number of physical cells in the idle area 32 is greater than the second critical value, the memory control circuit 23 may stop the data cleanup operation. It should be noted that, in one embodiment, the data cleanup operation may also be started (or triggered) and / or stopped according to other conditions, and the present invention is not limited thereto.

[0042] In one embodiment, the memory control circuit 23 may obtain erase count information, read count information, and valid count information corresponding to each physical unit in the plurality of physical units in the memory module 122. Figure 3 Taking the physical unit 301(i) (also referred to as the first physical unit) as an example, the erase count information (also referred to as the first erase count information) corresponding to the physical unit 301(i) may reflect the total number of erase operations performed on the physical unit 301(i). The read count information (also referred to as the first read count information) corresponding to the physical unit 301(i) may reflect the total number of read operations performed on the physical unit 301(i). In addition, the first valid count information corresponding to the physical unit 301(i) reflects the total amount of valid data stored in the physical unit 301(i).

[0043] In one embodiment, the erase operation performed on the physical unit 301 (i) is used to erase the data stored in the physical unit 301 (i). In one embodiment, each time an erase operation is performed on the physical unit 301 (i), the memory control circuit 23 may update the erase count information (i.e., the first erase count information) corresponding to the physical unit 301 (i), for example, by adding "1" to the first erase count information.

[0044] In one embodiment, the read operation performed on the physical unit 301 (i) is used to read data from the physical unit 301 (i). In one embodiment, each time a read operation is performed on the physical unit 301 (i), the memory control circuit 23 may update the read count information (i.e., the first read count information) corresponding to the physical unit 301 (i), for example, by adding "1" to the first read count information.

[0045] In one embodiment, the total amount of valid data stored in the entity unit 301 (i) can be represented by the total number of sub-entity units (i.e., entity programming units) currently storing valid data in the entity unit 301 (i). For example, assuming that the valid count information (i.e., the first valid count information) corresponding to the entity unit 301 (i) is "20", it means that there are currently 20 sub-entity units (i.e., entity programming units) storing valid data in the entity unit 301 (i).

[0046] In one embodiment, the memory control circuit 23 can obtain the quantitative evaluation information corresponding to the physical unit 301 (i) according to the erase count information, read count information and valid count information corresponding to the physical unit 301 (i). It should be noted that in the following embodiments, the physical unit 301 (i) is used to represent any physical unit in the memory module 122 to illustrate how to obtain the corresponding quantitative evaluation information.

[0047] In one embodiment, based on the quantitative evaluation information corresponding to each physical unit, the memory control circuit 23 may determine the source unit from the plurality of physical units. For example, the memory control circuit 23 may determine at least one physical unit corresponding to the largest or relatively large quantitative evaluation information among the plurality of physical units as the source unit. Then, in the data sorting operation, the memory control circuit 23 may perform data migration on the valid data in the source unit. For details on the operation of the data sorting operation, please refer to Figure 4 The embodiments of the present invention will not be repeated here.

[0048] In one embodiment, the memory control circuit 23 may read a plurality of control information from a management table, and then the memory control circuit 23 may obtain the quantitative evaluation information corresponding to the physical unit 301 (i) according to the plurality of control information and the erase count information, read count information and valid count information corresponding to the physical unit 301 (i).

[0049] Figure 5 is a schematic diagram of obtaining quantitative evaluation information according to an embodiment of the present invention. Figure 5In one embodiment, the memory control circuit 23 may obtain erase count information 501, read count information 502, and valid count information 503. The erase count information 501 may reflect the total number of erase operations performed on the physical unit 301 (i). The read count information 502 may reflect the total number of read operations performed on the physical unit 301 (i). The valid count information 503 may reflect the total amount of valid data stored in the physical unit 301 (i). In addition, the memory control circuit 23 may read control information 511 (1) to 511 (F) from a management table.

[0050] In one embodiment, the memory control circuit 23 may run a calculator 51. For example, the calculator 51 may be implemented by software, firmware, or hardware. In one embodiment, the memory control circuit 23 may input the erase count information 501, the read count information 502, the valid count information 503, and the control information 511(1)-511(F) into the calculator 51. The calculator 51 may generate the quantitative evaluation information 52 corresponding to the physical unit 301(i) according to the erase count information 501, the read count information 502, the valid count information 503, and the control information 511(1)-511(F).

[0051] In one embodiment, the control information 511(1) to 511(F) includes weight control information. The weight control information may be used to adjust the calculation weight of at least one of the erase count information 501, the read count information 502, and the valid count information 503 on the quantitative evaluation information 52. For example, the control information 511(1) may include the weight control information We(i) corresponding to the erase count information 501, the control information 511(2) may include the weight control information Wr(i) corresponding to the read count information 502, and the control information 511(3) may include the weight control information Wp(i) corresponding to the valid count information 503. The weight control information We(i) is used to adjust the calculation weight of the erase count information 501 on the quantitative evaluation information 52. The weight control information Wr(i) is used to adjust the calculation weight of the read count information 502 on the quantitative evaluation information 52. The weight control information Wp(i) is used to adjust the calculation weight of the valid count information 503 on the quantitative evaluation information 52.

[0052] In one embodiment, the memory control circuit 23 may obtain the quantitative evaluation information corresponding to the physical unit 301 ( i ) according to the following formula (1).

[0053] S(i)=We(i)×E(i)+Wr(i)×R(i)+Wp(i)×P(i) (1)

[0054] In formula (1), S(i) represents the quantitative evaluation information corresponding to entity unit 301(i) (e.g. Figure 5 quantized evaluation information 52), E(i) represents the erase count information corresponding to the entity unit 301(i) (e.g. Figure 5 The erase count information 501 of the physical unit 301 (i) is represented by R(i), and the read count information corresponding to the physical unit 301 (i) is represented by R(i). Figure 5 502), P(i) represents the valid count information corresponding to the entity unit 301(i) (e.g. Figure 5 In addition, We(i), Wr(i) and Wp(i) are weight control information corresponding to E(i), R(i) and P(i), respectively (e.g. Figure 5 It should be noted that formula (1) can be adjusted according to practical requirements and the present invention is not limited thereto.

[0055] In one embodiment, We(i), Wr(i) and Wp(i) may be values ​​between "0" and "1", respectively, and the sum of W1(i), W2(i) and W3(i) may be "1". For example, in one embodiment, We(i), Wr(i) and Wp(i) may be "0.3", "0.4" and "0.3", respectively. It should be noted that We(i), Wr(i) and Wp(i) may be adjusted according to practical needs, and the present invention is not limited thereto.

[0056] In one embodiment, the memory control circuit 23 can adjust at least one of We(i), Wr(i) and Wp(i) (i.e. Figure 5 The memory control circuit 23 can adjust the influence (i.e., calculate the weight) of at least one of the erase count information 501, the read count information 502, and the valid count information 503 on the quantitative evaluation information 52 by increasing We(i). For example, by increasing We(i), the memory control circuit 23 can increase the influence (i.e., calculate the weight) of the erase count information 501 on the quantitative evaluation information 52. Alternatively, by increasing Wr(i), the memory control circuit 23 can increase the influence (i.e., calculate the weight) of the read count information 502 on the quantitative evaluation information 52. Alternatively, by increasing Wp(i), the memory control circuit 23 can increase the influence (i.e., calculate the weight) of the valid count information 503 on the quantitative evaluation information 52.

[0057] In other words, the memory control circuit 23 can dynamically adjust at least one of We(i), Wr(i) and Wp(i) (i.e., Figure 5At least one of the control information 511(1) to 511(F) of the memory module 122 is used to meet the current needs. For example, when the effect of the number of erase times on the memory module 122 is more important, the memory control circuit 23 can increase We(i). As a result, during the subsequent execution of the data cleanup operation, the memory control circuit 23 can increase the effect of the number of erase times on the maintenance of the memory module 122, thereby taking into account the execution performance of the data cleanup operation and the maintenance management performance of the storage device 12.

[0058] In one embodiment, the memory control circuit 23 may perform a normalization operation (also referred to as a normalization operation) on the erase count information, read count information, and valid count information corresponding to the physical unit 301 (i) according to the plurality of control information. Figure 5 For example, the control information 511 (1) to 511 (F) may include maximum erase count information, minimum erase count information, maximum read count information, minimum read count information, maximum valid count information, and minimum valid count information. The memory control circuit 23 may perform the normalization operation on the erase count information 501, the read count information 502, and the valid count information 503 according to the control information 511 (1) to 511 (F). The erase count information, the read count information, and the valid count information after the normalization operation may synchronously fall into a preset numerical range (also referred to as a target numerical range). In one embodiment, the normalization operation may improve the efficiency of comprehensive evaluation of management information of different scales (i.e., erase count information, read count information, and valid count information).

[0059] In one embodiment, the memory control circuit 23 may perform normalization operations on the erase count information, read count information, and valid count information corresponding to the physical unit 301 ( i ) according to the following formulas (2.1) to (2.3), respectively.

[0060] E(i)'=(E(i)-Emin) / (Emax-Emin)(2.1)

[0061] R(i)'=(R(i)-Rmin) / (Rmax-Rmin)(2.2)

[0062] P(i)'=(P(i)-Pmin) / (Pmax-Pmin)(2.3)

[0063] In formulas (2.1) to (2.3), E(i)', R(i)' and P(i)' respectively represent the normalized E(i), R(i) and P(i). In addition, Emax represents the maximum erase count information, Emin represents the minimum erase count information, Rmax represents the maximum read count information, Rmin represents the minimum read count information, Pmax represents the maximum valid count information, and Pmin represents the minimum valid count information. In one embodiment, E(i)', R(i)' and P(i)' can be substituted for E(i), R(i) and P(i) respectively and brought into the aforementioned formula (1) to obtain the quantitative evaluation information corresponding to the physical unit 301(i). It should be noted that formulas (2.1) to (2.3) can be adjusted according to practical needs and the present invention is not limited thereto.

[0064] In one embodiment, the memory control circuit 23 may use a polynomial function to calculate the quantitative evaluation information corresponding to the physical unit 301 (i). For example, the memory control circuit 23 may obtain the quantitative evaluation information corresponding to the physical unit 301 (i) according to the following formula (3).

[0065] S(i)=We(i)×E(i) 2 +Wr(i)×R(i) 2 +Wp(i)×P(i) 2 (3)

[0066] It should be noted that, in one embodiment, if formula 3 (i.e., a polynomial function) is used to calculate the quantitative evaluation information corresponding to the physical unit 301 (i), We(i), Wr(i), and Wp(i) can all be set to "1". Thus, by parameter amplification, the beneficial technical effect of ensuring that management information of different scales (i.e., erase count information, read count information, and valid count information) is comprehensively evaluated at almost the same scale can be achieved. However, in one embodiment, We(i), Wr(i), and Wp(i) used in formula 3 can also be set according to practical needs, and the present invention is not limited thereto. It should be noted that formula (3) can be adjusted according to practical needs, and the present invention is not limited thereto.

[0067] In one embodiment, the memory control circuit 23 may determine the management table from a plurality of candidate management tables based on the system information. For example, the system information may include a numerical value. This numerical value may change according to current needs. Different numerical values ​​may point to different candidate management tables. Each candidate management table may record a control information combination. Different candidate management tables may record different control information combinations. For example, the plurality of candidate management tables may include a first candidate management table and a second candidate management table. The first candidate management table may record a first control information combination. The second candidate management table may record a second control information combination. The first control information combination may be different from the second control information combination. After determining the management table, the memory control circuit 23 may read the plurality of control information (e.g. Figure 5 For example, the control information 511(1)-511(F) obtained from the first candidate management table may be at least partially different from the control information 511(1)-511(F) obtained from the second candidate management table. Thus, the memory control circuit 23 can automatically select the most appropriate control information combination according to the current demand.

[0068] Figure 6 FIG. 1 is a schematic diagram of determining a source unit according to quantitative evaluation information corresponding to a plurality of entity units according to an embodiment of the present invention. Figure 6 In one embodiment, the memory control circuit 23 can determine the quantitative evaluation information 602(1)-602(G) corresponding to the physical units 601(1)-601(G) respectively. For details on how to obtain the quantitative evaluation information, please refer to Figure 5 The embodiments of the present invention will not be repeated here.

[0069] In one embodiment, the memory control circuit 23 may determine that at least one of the physical units 601 (1) to 601 (G) is a source unit based on the quantitative evaluation information 602 (1) to 602 (G). For example, the memory control circuit 23 may compare the quantitative evaluation information 602 (1) to 602 (G) to obtain a comparison result. This comparison result may reflect the quantitative relationship between the quantitative evaluation information 602 (1) to 602 (G). Then, based on this comparison result, the memory control circuit 23 may determine at least one physical unit in the physical units 601 (1) to 601 (G) corresponding to the maximum or relatively large quantitative evaluation information as a source unit. Thereafter, in a data sorting operation, the memory control circuit 23 may perform data migration on the valid data in the source unit. For details on the operation of the data sorting operation, please refer to Figure 4In one embodiment, based on the quantitative evaluation information 602(1)-602(G), the memory control circuit 23 may also use other selection mechanisms to determine the source unit from the physical units 601(1)-601(G), and the present invention is not limited thereto.

[0070] Figure 7 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Figure 7 In step S701, quantitative evaluation information corresponding to each physical unit is obtained according to the erase count information, read count information and valid count information corresponding to each physical unit in the plurality of physical units. In step S702, a source unit is determined from the plurality of physical units according to the quantitative evaluation information. In step S703, data migration is performed on valid data in the source unit.

[0071] However, Figure 7 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 7 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 7 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0072] In summary, the memory management method and storage device proposed in the embodiments of the present invention can select source units for data sorting operations based on multiple types (and multiple scales) of management information (i.e., erase count information, read count information, and valid count information). In particular, through specially designed and / or dynamically selected control information, the calculation weights corresponding to different types of management information can be dynamically adjusted according to current needs, and / or management information of different scales can be integrated and calculated according to current needs. In this way, the execution performance of garbage collection operations and the maintenance and management performance of storage devices can be taken into account, thereby increasing the service life of storage devices.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity units, and the memory management method comprises: According to the erase count information, the read count information and the valid count information corresponding to each physical unit of the plurality of physical units, the quantitative evaluation information corresponding to each physical unit is obtained; Determining a source unit from the plurality of entity units according to the quantitative evaluation information; and The valid data in the source unit is moved.

2. The memory management method according to claim 1, wherein the plurality of physical units include a first physical unit, the first erase count information corresponding to the first physical unit reflects the total number of erase operations performed on the first physical unit, the first read count information corresponding to the first physical unit reflects the total number of read operations performed on the first physical unit, and the first valid count information corresponding to the first physical unit reflects the total amount of valid data stored in the first physical unit.

3. The memory management method according to claim 1, wherein the step of obtaining the quantitative evaluation information corresponding to each physical unit according to the erase count information, the read count information and the valid count information corresponding to each physical unit in the plurality of physical units comprises: Reading a plurality of control information from a management table; as well as The quantitative evaluation information corresponding to each physical unit is obtained according to the plurality of control information, the erase count information, the read count information and the valid count information.

4. The memory management method according to claim 3, wherein the plurality of control information includes weight control information, and the weight control information is used to adjust the calculation weight of at least one of the erase count information, the read count information and the valid count information on the quantitative evaluation information.

5. The memory management method according to claim 3, wherein the step of obtaining the quantitative evaluation information corresponding to each physical unit according to the plurality of control information, the erase count information, the read count information and the valid count information comprises: According to the plurality of control information, a normalization operation is performed on the erase count information, the read count information and the valid count information, so that the normalized erase count information, the read count information and the valid count information fall within a target value range. 6 . The memory management method according to claim 5 , wherein the plurality of control information comprises maximum erase count information, minimum erase count information, maximum read count information, minimum read count information, maximum valid count information, and minimum valid count information.

7. The memory management method according to claim 3, wherein the step of reading the plurality of control information from the management table comprises: determining the management table from a plurality of candidate management tables according to the system information, The plurality of candidate management tables include a first candidate management table and a second candidate management table, the first candidate management table records a first control information combination, and the second candidate management table records a second control information combination.

8. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: According to the erase count information, the read count information and the valid count information corresponding to each physical unit of the plurality of physical units, the quantitative evaluation information corresponding to each physical unit is obtained; Determining a source unit from the plurality of entity units according to the quantitative evaluation information; as well as The valid data in the source unit is moved.

9. The storage device according to claim 8, wherein the plurality of physical units include a first physical unit, a first erase count information corresponding to the first physical unit reflects a total number of erase operations performed on the first physical unit, a first read count information corresponding to the first physical unit reflects a total number of read operations performed on the first physical unit, and a first valid count information corresponding to the first physical unit reflects a total amount of valid data stored in the first physical unit.

10. The storage device according to claim 8, wherein the step of obtaining the quantitative evaluation information corresponding to each physical unit according to the erase count information, the read count information and the valid count information corresponding to each physical unit in the plurality of physical units comprises: Reading a plurality of control information from a management table; as well as The quantitative evaluation information corresponding to each physical unit is obtained according to the plurality of control information, the erase count information, the read count information and the valid count information.

11. The storage device according to claim 10, wherein the plurality of control information comprises weight control information, and the weight control information is used to adjust a calculation weight of at least one of the erase count information, the read count information and the valid count information on the quantitative evaluation information.

12. The storage device according to claim 10, wherein the step of obtaining the quantitative evaluation information corresponding to each physical unit according to the plurality of control information, the erase count information, the read count information and the valid count information comprises: According to the plurality of control information, a normalization operation is performed on the erase count information, the read count information and the valid count information, so that the normalized erase count information, the read count information and the valid count information fall within a target value range. 13 . The storage device according to claim 12 , wherein the plurality of control information comprises maximum erase count information, minimum erase count information, maximum read count information, minimum read count information, maximum valid count information, and minimum valid count information.

14. The storage device according to claim 10, wherein the step of reading the plurality of control information from the management table comprises: determining the management table from a plurality of candidate management tables according to the system information, The plurality of candidate management tables include a first candidate management table and a second candidate management table, the first candidate management table records a first control information combination, and the second candidate management table records a second control information combination.

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