Design method for Bump module at rear end of digital integrated circuit

Abstract

The invention provides a design method of a Bump module at the rear end of a digital integrated circuit, and belongs to the field of power consumption analysis of the rear end of a digital chip of the integrated circuit. The invention provides a Bump module design process for solving the problems of inaccurate power consumption analysis and low analysis efficiency caused by insufficient power supply points during voltage drop analysis. The method comprises the steps of preparing digital back-end layout wiring data, selecting a metal layer according to project indexes to create a power strip line, setting a power strip mode, opening holes and connecting the metal layer, creating Bump specific data information, selecting a corresponding Bump to connect a power line and a ground wire, exporting specific position information of the Bump and marking the specific position information to an AP layer, and creating Physic Pin and exporting a def.gz file. The method is mainly applied to providing a power supply point for voltage drop analysis after digital back-end layout wiring and before voltage drop analysis, facilitates subsequent RC parasitic parameter extraction, further reduces dynamic voltage drop through the power supply point, is more convenient to operate, reduces the design cycle of a digital integrated circuit, and shortens the sign-off time.

Description

Technical Field

[0001] The invention belongs to the technical field of digital chip back-end, and in particular relates to a Bump module design method for a digital integrated circuit back-end. Background Art

[0002] In modern large-scale integrated circuit design, the complexity of digital integrated circuits has increased rapidly, including the increase in the number of chip cores, the increase in frequency, the need to reduce power consumption, etc. This requires the back-end design to handle more logic units and complex electrical characteristics. The advancement of advanced process technology, such as 7nm and 5nm processes, has brought smaller feature sizes and higher integration, while also requiring back-end design tools to support higher precision and complexity, while meeting performance requirements while reducing power consumption as much as possible.

[0003] The continuous advancement of EDA (Electronic Design Automation) tools is the key to enabling back-end design to cope with complexity and challenges. The performance, accuracy and user-friendliness of the tools have a direct impact on design efficiency. Digital back-end design tools The digital back-end is an EDA tool developed by Cadence, which is specifically used for the physical design of digital integrated circuits. The digital back-end provides a range of functions to help engineers perform chip layout, routing, timing optimization, etc., to achieve high performance, low power consumption and area efficiency.

[0004] At present, the low-power design of integrated circuits has developed rapidly from the Moore's era to the nanometer level. Power consumption analysis has become a bottleneck problem in the development of large-scale integrated circuits. The logic signal complexity is high during power consumption analysis, and the physical layout and routing stages increase the internal blockage and density of the chip, making it more difficult to converge timing. As an important indicator of power consumption analysis, voltage drop analysis has been increasingly valued. The size of the voltage drop is determined by the size of the equivalent resistance from the power PAD to the calculated logic gate unit, which greatly affects the timing information and signal integrity analysis.

[0005] In digital backend design, Bump refers to a technology that can be used after layout and routing and before voltage drop analysis. Specifically, Bump refers to adding small metal balls or other shaped contact points on the circuit chip area of ​​the chip. Through Bump, thousands or even millions of tiny connection points can be arranged on the chip surface to effectively manage and transmit signals, power and ground connections. By adding the Bump module and then performing the voltage drop, a power supply point can be provided for subsequent analysis and optimization, so that physical layout optimization and voltage drop violation repair can be performed according to the voltage drop analysis results, the voltage drop of the integrated circuit can be reduced, and the dynamic voltage drop can be further reduced by providing a power supply point. In some integrated circuit designs, the design of the Bump module is relatively vague, and some generally applicable situations are less considered. Summary of the invention

[0006] The purpose of the present invention is to provide a Bump module design method for the back-end of a digital integrated circuit, aiming to solve the Bump module design problem between the layout and wiring stage and the voltage drop stage, reduce the complexity of the subsequent voltage drop analysis, and shorten the design cycle. At the same time, this method is suitable for most digital back-end design processes and has universal applicability.

[0007] To achieve the above objectives, the present invention proposes a Bump module design method for the back-end of a digital integrated circuit, which is suitable for a digital back-end layout and routing tool, including conventional digital back-end layout and routing data preparation, creating power lines in the corresponding metal layer according to project indicators, opening holes in the AP layer and connecting the underlying metal layer, creating a Bump, selecting a Bump connection line and exporting specific Bump information, creating a Physical Pin and exporting a def.gz file for voltage drop analysis and optimization.

[0008] The conventional digital back-end layout and routing data preparation includes a layout planning stage, a standard cell placement stage, a clock tree synthesis and optimization stage, and a routing and routing optimization result stage.

[0009] The method for creating a power strip creates a power strip in a corresponding metal layer according to project indicators, selects an AP layer and a second top layer, sets a horizontal direction; selects a top layer, sets a vertical direction; and sets a mode for adding a power strip.

[0010] The setting of adding a power strip mode includes selecting a corresponding power domain, generating a horizontal or vertical power strip according to the selected metal layer, setting power lines and ground lines, and setting width, length, spacing distance, and starting position.

[0011] The method for opening holes and connecting metal layers includes opening holes in the AP layer and connecting it to the metal layer below, setting Power Via power holes, constraining the position of the holes on the Pins so that they bypass the standard units; respectively selecting the power lines and ground lines of the top metal layer below the AP layer, setting the number of holes according to the area of ​​the module, and connecting them to the AP layer.

[0012] The method for creating a Bump includes selecting a corresponding unit according to a project indicator, setting the shape, starting position, and spacing of the Bump, setting the interleaving type to vertical arrangement, setting the interleaving offset value, setting the stacking mode and retaining the current Bump, and setting the full_chip mode.

[0013] The method for selecting a connection line of a Bump and deriving specific information of the Bump includes alternately selecting Bump information, connecting the Bump to an AP layer, and deriving specific location information of the Bump for subsequent voltage drop analysis and optimization.

[0014] Among them, the method of interleaving the selection of Bump information includes selecting even-numbered Bumps, such as Bump2, Bump4, and Bump6, and connecting them to the power line; selecting odd-numbered Bumps, such as Bump1, Bump3, and Bump5, and connecting them to the ground line, connecting the Bumps to the AP layer, and the even-numbered Bumps and the odd-numbered Bumps correspond to the power line and the ground line of the AP layer.

[0015] The method for creating a Physical Pin and exporting a def.gz file includes selecting the power lines and ground lines of the AP layer, the top layer, and the second top layer, setting the type to a special type, using the script dbget select.box to grab all the power lines and ground lines of the selected metal layer, obtaining their position and quantity information, using the script to create a Physical Pin, and exporting the def.gz file for subsequent voltage drop analysis and optimization.

[0016] The exported def.gz file includes all metal layer information, netlist information, layout planning information, and wiring information.

[0017] Beneficial effects:

[0018] In order to facilitate voltage drop analysis, the present invention proposes a Bump module design method for the back-end of a digital integrated circuit, which is mainly used in the stage after the digital back-end layout and routing and before the voltage drop analysis, to provide a power supply point for the voltage drop analysis, to facilitate the subsequent RC parasitic parameter extraction, and to further reduce the dynamic voltage drop through the power supply point, which makes the operation more convenient, reduces the difficulty of timing convergence, reduces the design cycle, and shortens the sign-off time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to further illustrate the contents described in the present invention, the specific embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. It should be understood that these drawings are only used as typical examples and should not be regarded as limiting the scope of the present invention.

[0020] Figure 1 The present invention is a flowchart of a method for designing a Bump module at the back end of a digital integrated circuit.

[0021] Figure 2 It is a schematic diagram of a method for creating a power supply line in a Bump module design method for a digital integrated circuit back end of the present invention.

[0022] Figure 3 It is a schematic diagram of a method for opening holes and connecting metal layers in a method for designing a Bump module at the back end of a digital integrated circuit of the present invention.

[0023] Figure 4 It is a schematic diagram of a method for creating a Bump module in a digital integrated circuit back-end design method of the present invention.

[0024] Figure 5 The present invention is a schematic diagram of a method for selecting a Bump connection line and deriving specific Bump information in a Bump module design method for a digital integrated circuit back end.

[0025] Figure 6 It is a schematic diagram of a method for creating a Physical Pin and exporting a def.gz file in a Bump module design method for a digital integrated circuit backend of the present invention.

[0026] 1-Digital backend layout and routing data preparation, 2-Create power strips, 3-Open holes and connect metal layers, 4-Create Bumps, 5-Select Bump connection lines and export Bump specific information, 6-Create Physical Pins and export def.gz files, 7-Create power strips in the corresponding metal layers according to project indicators, 8-Select metal layers, 9-Select AP layers and sub-top layers, set horizontal direction, 10-Select top layers, set vertical direction, 11-Set the mode of adding power strips, 12-Add power strips, select the corresponding power domain setting parameters, 13-Open holes in the AP layer and connect them to the metal layer below, 14-Set Power Via, constrain the position of the hole on the Pin so that it bypasses the standard unit, 15-Select the power line and ground line of the top metal below the AP layer, 16-Set the number of holes according to the area of ​​the module and connect to the AP layer, 17-Create Bump, 18-Select the corresponding unit according to the project indicators, 19-Set the shape and position of the Bump, 20-Set the specific arrangement type and mode, 21-Interlaced selection of Bump information, 22-Select even-numbered Bumps and connect to the power line, 23-Select odd-numbered Bumps and connect to the ground line, 24-Connect the Bump to the AP layer and correspond to the power line and ground line of the AP layer, 25-Export the specific location information of the Bump for subsequent voltage drop analysis and optimization, 26-Create Physical Pin, 27-Select power lines and ground lines of different metal layers and set the type, 28-Use the script to capture the power line and ground line information of the selected metal layer, 29-Export def.gz file, 30-Voltage drop analysis and optimization. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and beneficial effects of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present invention.

[0028] In order to illustrate the technical solution of the present invention, a specific embodiment is provided below for illustration.

[0029] See also Figure 1-Figure 6The present invention provides a Bump module design method for the back end of a digital integrated circuit. Step 1 is to prepare conventional digital back end layout and routing data. Step 2 is to create a power line and select the corresponding metal layer according to the data of step 1 and the project index. Step 3 is to open a hole and select the metal layer according to the data of step 2. Step 4 is to create a Bump method and create it according to the data of step 3. Step 5 is to select the Bump connection line and export the specific information of the Bump and implement it according to the data of step 4. Step 6 is to create a Physical Pin and export the def.gz file and create it according to the data of step 5, and then perform subsequent voltage drop analysis and optimization.

[0030] The step 1 of preparing conventional digital back-end layout and routing data includes layout planning, standard cell placement, clock tree synthesis and optimization, routing and routing optimization results, and saving the routing optimization result report.

[0031] The step 2 creates a power strip method, creates a power strip 7 in the corresponding metal layer according to the project indicators, selects the metal layer 8, and since the largest metal layer used in this embodiment is M13, the metal top layer is the M13 layer and the metal second top layer is the M12 layer, plus the AP layer above the metal top layer, selects the AP layer and the second top layer M12 to set the direction horizontal 9, selects the top layer M13 to set the direction vertical 10, sets the add power strip mode 11, and the instruction is AddStripeMode-stacked_via_top_layer-stacked_via_bottom_layer.

[0032] Among them, the creation of the power line 7 in the corresponding metal layer according to the project indicators includes setting the power domain, the instruction is -power_domains PD_CPU_SW_DIG; selecting the corresponding metal layer, the instruction is -layer M${layer}, and the metal layer selects M12 layer, M13 layer, and AP layer respectively; setting the M12 layer and the M13 layer includes selecting the power line and the ground line, the instruction is -nets{VDDVSS}, setting the width to 10um, the instruction is -width 10, setting the width to 2um, the instruction is -spacing 2, setting the spacing distance to 24um, and the instruction is -set_to_set_distance 24; setting the AP layer includes selecting the power line and the ground line respectively, the instructions are -nets{VDD VDD VDD}-nets{VSS VSS VSS}, setting the width to 20um, the instruction is -width 20, setting the width to 2um, the instruction is -spacing 2, setting the spacing distance to 24um, and the instruction is -set_to_set_distance 24.

[0033] In step 3, the metal layer is selected according to the data in step 2, and a hole is opened in the AP layer with the instruction -skip_via_on_pin Standardcell, and connected to the M13 metal layer with the instruction -bottom_layer M13-nets{VDD VSS}-add_vias 1-to_layer AP.

[0034] The step 4 creates a Bump method 17, selects a corresponding cell 18 according to the project indicator, and this embodiment selects PAD90UBMBOP, and the instruction is create_bump-cell PAD90UBMBOP. The specific parameter information of the Bump is set, including the interval size and the starting position. The instruction is -start_from lower left-loc{60 60}-pitch{81 216}, and the stagger type is set to vertical arrangement, the stacking mode is set and the current Bump is retained, the stagger offset value is set, and the full_chip mode is set 20. The instruction is -stagger_type odd_column-allow_overlap_control keep_exiting_bumps-pattern_full chip-edge_spacing{60 60 60 60}-stagger_offset 108.

[0035] The step 5 selects the Bump connection line and exports the Bump specific information. According to the Bump creation result in step 4, the Bump information 21 is selected in an interlaced manner. The even-numbered Bumps, such as Bump2, Bump4, and Bump6, are selected and connected to the power line 22. The instruction is select_bump-bumps Bump_2Bump_4...Bump_24assignPGbumps-selected-nets VDD. The odd-numbered Bumps, such as Bump1, Bump3, and Bump5, are selected and connected to the ground line 23. The instruction is select_bump-bumps Bump_1Bump_3...Bump_21assignPGbumps-selected-nets VSS. The Bump is connected to the AP layer, and the even-numbered Bumps and the odd-numbered Bumps correspond to the power line and the ground line 24 of the AP layer. The instruction is select-bump-nets "VDD" foreach name[dbget selected.name]net[deget selected.net.name]loc[dbgetselected.bump_shape_center]{echo$name$loc AP>>.VDD.pp}select-bump-nets "VSS"foreach name[dbget selected.name]net[deget selected.net.name]loc[dbgetselected.bump_shape_center]{echo$name$loc AP>>.VSS.pp}, export the specific location information of the Bump for subsequent voltage drop analysis 25.

[0036] The step 6 creates Physical Pin 26 and exports the def.gz file. According to step 2, select the AP layer, metal layer M13, and the power and ground lines of the metal layer M12, set the type to special type 27, and use the script dbget to grab all the power and ground lines of the selected metal layer to obtain their position and quantity information. Use the script to create Physical Pin 28. The instruction is set box[dbgetselect.box]foreach box$box{createPhysicalPin$VDD / VSS-net$VDD-layer$AP / M13 / M12-rect$box}. Export the def.gz file, which contains all metal layer information, layout planning information, netlist information, and routing information 29. The instruction is defOut-allLayer-floorplan-netlist-routing DATA / [deget top.name]_postRoute_IR.def.gz, and voltage drop analysis and optimization 30.

[0037] Among them, the voltage drop analysis and optimization 30 performs subsequent voltage drop analysis and optimization according to the Bump specific information exported in step 5 and the def.gz file exported in step 6, including but not limited to RC parasitic parameter extraction, PTPX power consumption analysis, generation of PTIAVG file for power consumption analysis, static voltage drop analysis, and dynamic voltage drop analysis.

[0038] The present invention proposes a Bump module design method for the back-end of a digital integrated circuit, which is applied to the back-end physical design of a high-speed chip with a 7nm process and a frequency of 1600MHz.

[0039] Finally, it should be noted that the above implementation examples are presented only to illustrate the present application and are not intended to be limiting. Those skilled in the relevant art can implement all or part of the above embodiments and make various combinations, modifications and changes thereto without departing from the spirit and scope of the present invention. Equivalent changes made in accordance with the claims of the present application are still within the scope of the present application.

Claims

1. A Bump module design method for a digital integrated circuit back end, characterized in that: The Bump module design method of the digital integrated circuit back end includes: 1) Digital back-end layout and routing data preparation; 2) using the digital backend layout and routing data, after layout, selecting the corresponding metal layer to create power strips according to project indicators, and setting the power strip mode; 3) Create power lines on the corresponding metal top layer according to the project indicators, open holes on the AP layer, constrain the location of the holes and connect them to the metal layer below; 4) Create Bump specific data information based on the information of opening a hole in the AP layer and connecting it to the metal layer below, and set the interleaving type, offset value, and stacking mode; 5) According to the specific data information of creating the Bump, select the corresponding Bump to connect to the power line and ground line, export the specific location information of the Bump and mark it to the AP layer for subsequent voltage drop analysis and optimization; 6) Create PhysicalPin based on the power line and ground line information of different metal layers and export the def.gz file for subsequent voltage drop analysis and optimization.

2. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 1, characterized in that: The digital back-end layout and routing data preparation includes a layout planning stage, a standard cell placement stage, a clock tree synthesis and optimization stage, and a routing and optimization routing result stage, which are performed in sequence.

3. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 1, characterized in that: Step 2) includes creating a power strip line on the corresponding metal layer according to the project indicators, selecting the AP layer and the second top layer, setting the horizontal direction; selecting the top layer, setting the vertical direction; and setting the mode of adding a power strip.

4. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 3, characterized in that: The setting of adding a power strip mode includes selecting a corresponding power domain, generating a horizontal or vertical power strip according to the selected metal layer, setting power lines and ground lines, and setting width, length, spacing distance, and starting position.

5. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 1, characterized in that: Step 3) includes opening a hole in the AP layer and connecting it to the metal layer below, setting a Power Via power hole, and constraining the position of the hole on the Pin so that it bypasses the standard unit; Select the power line and ground line of the top metal layer below the AP layer respectively, set the number of holes according to the area of ​​the module and connect them to the AP layer.

6. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 1, characterized in that: Step 4) includes selecting the corresponding unit according to the project indicators, setting the shape, starting position, and interval distance of the Bump, setting the interleaving type to vertical arrangement, setting the interleaving offset value, setting the stacking mode and retaining the current Bump, and setting the full_chip mode.

7. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 1, characterized in that: Step 5) includes interleaving and selecting Bump information, connecting the Bump to the AP layer, and deriving specific location information of the Bump for subsequent voltage drop analysis and optimization.

8. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 7, characterized in that: The method for interleaving the selection of Bump information includes selecting even-numbered Bumps, such as Bump2, Bump4, and Bump6, and connecting them to a power line; selecting odd-numbered Bumps, such as Bump1, Bump3, and Bump5, and connecting them to a ground line, connecting the Bump to an AP layer, and the even-numbered Bumps and the odd-numbered Bumps correspond to the power line and the ground line of the AP layer.

9. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 1, characterized in that: Step 6) includes selecting the power lines and ground lines of the AP layer, the top layer, and the second top layer, setting the type to special type, using the script dbget to grab all the power lines and ground lines of the selected metal layer, obtaining their position and quantity information, using the script to create Physical Pins, and exporting the def.gz file for subsequent voltage drop analysis and optimization.

10. The method for designing a Bump module of a digital integrated circuit back end as claimed in claim 9, characterized in that: The exported def.gz file includes all metal layer information, netlist information, layout planning information, and wiring information.

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