Semiconductor device preparation method, electrical performance adjustment method and semiconductor device

Abstract

The present application discloses a method for preparing a semiconductor device, a method for adjusting electrical properties, and a semiconductor device. The method for preparing the semiconductor device includes dividing a semiconductor wafer into a plurality of regions; selectively injecting a first type of dopant into the semiconductor wafer to form a first doping region of a first doping type in the semiconductor wafer; forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doping region; modifying the mask layer region by region to adjust the ion injection resistance of the mask layer region by region; and injecting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is injected into the semiconductor wafer exposed by the mask layer to form a second doping region of a second doping type, and part of the second type of dopant is injected into the first doping region covered by the mask layer to adjust the doping concentration of the first doping region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a method for preparing a semiconductor device, a method for adjusting electrical properties, and a semiconductor device. Background Art

[0002] A plurality of semiconductor devices with the same structure are formed in a conventional semiconductor wafer. The electrical performance of the same semiconductor device varies within the semiconductor wafer surface. Generally, the electrical performance difference between semiconductor devices in the center area of ​​the semiconductor wafer and the edge area of ​​the semiconductor wafer is particularly obvious.

[0003] The difference in electrical performance of the same semiconductor wafer mainly comes from the final result of multiple process factors, such as the difference in doping concentration within the surface during ion implantation, the difference in thermal process within the surface, and the difference in gate line width. The current method of adjusting the electrical performance of semiconductor wafers is ion implantation of the entire surface of the wafer, which cannot eliminate the difference in electrical performance within the wafer surface. And without adding a new photolithography mask, it is impossible to achieve differential adjustment of any semiconductor device in the wafer. Summary of the invention

[0004] In view of the above problems, the purpose of the present application is to provide a method for preparing a semiconductor device, a method for adjusting electrical properties, and a semiconductor device, so as to achieve regional adjustment of the doping concentration of the first doping region in the same semiconductor wafer without adding photolithography and ion implantation steps.

[0005] According to one aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising: dividing a semiconductor wafer into a plurality of regions; selectively injecting a first type of dopant into the semiconductor wafer to form a first doping region of a first doping type in the semiconductor wafer; forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doping region; modifying the mask layer region by region to adjust the ion injection resistance of the mask layer region by region; and injecting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is injected into the semiconductor wafer exposed by the mask layer to form a second doping region of a second doping type, and part of the second type of dopant is injected into the first doping region covered by the mask layer to adjust the doping concentration of the first doping region.

[0006] Optionally, the mask layer is a photoresist mask, and the mask layer is exposed to light with a light beam corresponding to a photosensitivity wavelength of the mask layer to perform a modification process on the mask layer.

[0007] Optionally, when the mask layer is modified by exposing the mask layer with a light beam, the ion implantation resistance of the mask layer is controlled by adjusting the exposure time of the mask layer.

[0008] Optionally, when the mask layer is modified by exposing the mask layer with a light beam, the single exposure time of the light beam is constant, and the ion implantation resistance of the mask layer is related to the number of exposure times of the mask layer. By adjusting the number of exposure times of the mask layer, the ion implantation resistance of the mask layer can be controlled.

[0009] Optionally, when the mask layer is modified by exposing the mask layer with a light beam, as the number of times the mask layer is exposed increases, the ion implantation resistance of the mask layer first gradually decreases and then tends to be stable.

[0010] According to another aspect of the present invention, a method for adjusting the electrical properties of a semiconductor device is provided, wherein the electrical properties of the semiconductor device are related to the number of exposure times of a mask layer, and the method for adjusting the electrical properties comprises: obtaining a fitting curve of the electrical properties of the semiconductor device and the number of exposure times of the mask layer; forming a first doping region of a first doping type in a semiconductor wafer; forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doping region; exposing the mask layer with a light beam to achieve mask layer modification, wherein the single exposure time of the light beam is constant, adjusting the number of exposure times of the mask layer by region according to the fitting curve, modifying the mask layer by region, and adjusting the ion implantation resistance of the mask layer by region; injecting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is injected into the semiconductor wafer exposed by the mask layer to form a second doping region of a second doping type, and part of the second type of dopant is injected into the first doping region covered by the mask layer, and the doping concentration of the first doping region is adjusted, thereby adjusting the electrical properties of the semiconductor device.

[0011] Optionally, the fitting curve of the electrical performance of the semiconductor device and the exposure times of the mask layer includes an adjustment region where the electrical performance changes with an increase in the exposure times and a stable region close to a stable value.

[0012] Optionally, the exposure times of the mask layer in different regions are adjusted so that the electrical performance of the same semiconductor device in different regions of the same semiconductor wafer is consistent, thereby eliminating the difference in electrical performance of the same semiconductor device in different regions of the same semiconductor wafer.

[0013] Optionally, the exposure times of the mask layer in different regions are adjusted so that the electrical properties of the same semiconductor device in different regions of the same semiconductor wafer are different, so as to form semiconductor devices with different electrical properties in different regions of the same semiconductor wafer.

[0014] According to another aspect of the present invention, a semiconductor device formed by the above method is provided, the semiconductor device comprising: a semiconductor wafer, the semiconductor wafer comprising a plurality of regions; a first doping region of a first doping type located in the semiconductor wafer; and a second doping region of a second doping type located in the semiconductor wafer; wherein the doping concentration of the first doping region is adjusted while forming the second doping region, and the doping concentrations of the first doping regions in different regions are the same or different.

[0015] The unexpected technical effects of this application are:

[0016] The present application performs regional modification treatment on the same mask layer to adjust the ion injection resistance of the mask layer in different regions, thereby achieving regional control of the doping concentration of the first doping region of the same semiconductor wafer without increasing the photolithography and ion injection steps.

[0017] In the process of forming the second doping region, the present application adjusts the doping concentration of the first doping region without adding additional photolithography and ion implantation steps.

[0018] The mask layer described in the present application is a photoresist mask layer, and the ion injection resistance of the mask layer is controlled by controlling the exposure time of the mask layer, thereby facilitating the control of the ion injection resistance of the mask layer.

[0019] The single exposure time of the light beam in the present application is constant. By controlling the number of exposures of the mask layer, the ion implantation resistance of the mask layer is controlled, and the corresponding relationship between the number of exposures of the mask layer and the electrical performance of the semiconductor device is obtained, thereby optimizing the electrical performance of the semiconductor device.

[0020] The present application controls the ion implantation resistance of the mask layer in different regions to make the electrical performance of the same semiconductor device in different regions of the same semiconductor wafer consistent, thereby eliminating the difference in electrical performance of the same semiconductor device in different regions of the same semiconductor wafer.

[0021] The present application controls the ion implantation resistance of the mask layer in different regions so that the electrical properties of the same semiconductor device in different regions of the same semiconductor wafer differ, thereby forming semiconductor devices with different electrical properties in different regions of the same semiconductor wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0023] Figure 1A flow chart showing a method for preparing a semiconductor device according to an embodiment of the present application is shown;

[0024] Figure 2a-1 A schematic diagram of a top view of a semiconductor wafer according to an embodiment of the present application is shown;

[0025] Figure 2a-2 Shows Figure 2a-1 A partial cross-sectional view of a semiconductor device;

[0026] Figure 2b A cross-sectional view after forming a first doped region in a semiconductor wafer according to an embodiment of the present application is shown;

[0027] Figure 2c A cross-sectional view after forming a second mask layer PR2 on a semiconductor wafer according to an embodiment of the present application is shown;

[0028] Figure 2d A cross-sectional view showing the modification of the second mask layer PR2 according to an embodiment of the present application is shown;

[0029] Figure 2e A cross-sectional schematic diagram of the second ion implantation in an embodiment of the present application is shown;

[0030] Figure 3 A schematic diagram showing the distribution of the threshold voltage Vth of the same semiconductor device within the semiconductor wafer surface in one embodiment is shown;

[0031] Figure 4 shows the sensitometric curves of different photoresist masks;

[0032] Figure 5 The diagram shows a region division form of a semiconductor wafer in one embodiment;

[0033] Figure 6 Shows Figure 5 A partial schematic diagram of the threshold voltage of the same semiconductor device in the semiconductor wafer shown;

[0034] Figure 7 A fitting curve between the threshold voltage of a semiconductor device and the number of exposure times is shown;

[0035] Figure 8 The fitting curve between the drain saturation current and the exposure times of the semiconductor device is shown;

[0036] Fig. 9 The diagram shows the area division form of a semiconductor wafer in another embodiment of the present application. DETAILED DESCRIPTION

[0037] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0038] This application may be presented in a variety of forms, some examples of which are described below.

[0039] Figure 1 A flow chart of a method for preparing a semiconductor device according to an embodiment of the present application is shown. Figure 1 As shown, the method for preparing a semiconductor device includes:

[0040] S110: Dividing the semiconductor wafer into a plurality of regions;

[0041] S120: selectively injecting a first type of dopant into the semiconductor wafer to form a first doping region of a first doping type in the semiconductor wafer;

[0042] S130: forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doped region;

[0043] S140: performing modification processing on the mask layer in different regions to adjust the ion implantation resistance of the mask layer in different regions; and

[0044] S150: Injecting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is injected into the semiconductor wafer exposed by the mask layer to form a second doping region of a second doping type, and part of the second type of dopant is injected into the first doping region covered by the mask layer to adjust the doping concentration of the first doping region.

[0045] Figure 2a-1 to Figure 2e The structure diagram of each stage in the preparation process of the semiconductor device of the embodiment of the present application is shown. Figure 2a-1 to Figure 2e A method for manufacturing the semiconductor device of the present application is described.

[0046] Figure 2a-1 FIG. 1 shows a schematic diagram of a top view of a semiconductor wafer 10 according to an embodiment of the present application. Figure 2a-2 Shows Figure 2a-1 A partial cross-sectional view of a semiconductor device in FIG.

[0047] like Figure 1 , Figure 2a-1 and Figure 2a-2 As shown, the semiconductor wafer 10 is divided into a plurality of regions 110 .

[0048] The semiconductor wafer 10 includes a plurality of basic operation units (shots) 10a, each of which includes one or more chips (chips), and each of which includes one or more semiconductor devices. In this embodiment, the semiconductor device is, for example, a MOSFET (metal oxide semiconductor field effect transistor), but is not limited thereto. The electrical properties of the semiconductor device include the threshold voltage Vth, drain saturation current Ids, breakdown voltage BVD, leakage current I off And on-resistance R, etc.

[0049] Figure 3 FIG. 1 shows a schematic diagram of the threshold voltage Vth distribution of the same semiconductor device in a semiconductor wafer in an embodiment. Figure 3 As shown, the semiconductor wafer 10 includes a plurality of basic operation units 10a, each of which includes at least one semiconductor device with the same structure, such as a MOSFET device. The threshold voltage Vth of the same semiconductor devices in the semiconductor wafer 10 is different. Specifically, the absolute value of the threshold voltage Vth of the same semiconductor devices in the semiconductor wafer increases gradually from the center of the semiconductor wafer 10 to the edge of the semiconductor wafer 10.

[0050] The difference in electrical performance of the same semiconductor devices in the same semiconductor wafer 10 is mainly the final result caused by multiple process aspects such as the difference in in-plane doping concentration during ion implantation, the difference in in-plane thermal process and the difference in gate line width. This embodiment adjusts the electrical performance of the device by adjusting the in-plane doping concentration.

[0051] In the embodiment of the present application, the semiconductor wafer 10 is divided into a plurality of regions 110, so that the doping concentrations of the body regions (first doping regions) of different regions are adjusted respectively in subsequent steps, so as to realize the regional control of the doping concentration of the body region (first doping region) of the same semiconductor wafer 10, and then adjust the doping concentration of the body region (first doping region) in different regions of the same semiconductor wafer, and then adjust the electrical performance of the device. In this embodiment, for example, the doping concentration of the body region (first doping region) in different regions of the same semiconductor wafer is adjusted, so that the electrical performance of the semiconductor device in different regions of the same semiconductor wafer remains consistent.

[0052] like Figure 2a-1 As shown, in the application embodiment, the semiconductor wafer 10 is divided into a first area 110a, a second area 110b and a third area 110c, and the first area 110a, the second area 110b and the third area 110c are distributed in sequence from the inside to the outside. The first area 110a is a circular area located in the center area of ​​the semiconductor wafer 10, the second area 110b is an annular area surrounding the first area 110a, and the third area 110c is an annular area surrounding the second area 110b.

[0053] Figure 2b FIG. 4 shows a cross-sectional view of an embodiment of the present application after a first doped region is formed in a semiconductor wafer, as shown in FIG. Figure 1 and Figure 2b As shown, a first doping region 111 of a first doping type is formed in the semiconductor wafer 10 .

[0054] In this step, a first mask layer PR1 is formed on the semiconductor wafer 10, for example, the first mask layer PR1 is patterned by a photolithography process, and the semiconductor wafer 10 is subjected to a first ion implantation through the patterned first mask layer PR1 to form a first doped region 111 in the semiconductor wafer 10, wherein during the first ion implantation process, a first type of dopant is implanted into the semiconductor wafer 10. In one embodiment, the first mask layer PR1 is, for example, a photoresist mask, and the first doping type is, for example, N-type doping.

[0055] Furthermore, at least one first doping region 111 is formed in each of the plurality of regions 110 .

[0056] Figure 2c FIG. 4 shows a cross-sectional view of an embodiment of the present application after a second mask layer PR2 is formed on a semiconductor wafer. Figure 1 and Figure 2c As shown, a patterned second mask layer PR2 is formed on the semiconductor wafer, wherein the patterned second mask layer PR2 covers the first doping region 111 .

[0057] In this step, a second mask layer PR2 is formed in the semiconductor wafer. For example, the second mask layer PR2 is patterned by a photolithography process to form a patterned second mask layer PR2 . The patterned second mask layer PR2 covers the first doping region 111 .

[0058] Figure 2d FIG. 4 shows a cross-sectional view of the modification of the second mask layer PR2 according to an embodiment of the present application. Figure 1 and Figure 2d As shown, the patterned second mask layer PR2 is modified to adjust the ion implantation resistance of the second mask layer PR2, wherein the ion implantation resistance of the second mask layer PR2 is the same or different in different regions.

[0059] The second mask layer PR2 is, for example, a photoresist mask, and the second mask layer PR2 is modified by exposing the second mask layer PR2 to light.

[0060] Different photoresist masks have different light-sensitive wavelengths. The mask layer is exposed to light using a light beam corresponding to the light-sensitive wavelength of the mask layer to perform a modification process on the mask layer. Figure 4The sensitivity curves of different photoresist masks are shown, where the horizontal axis of the sensitivity curve is wavelength (nanometers) and the vertical axis is absorbance. The greater the absorbance, the stronger the photosensitivity. Figure 4 As shown, the light-sensitive wavelength of the first photoresist mask is 200 nanometers to 300 nanometers, and the light-sensitive wavelength of the second photoresist mask is 240 nanometers to 260 nanometers.

[0061] Furthermore, a light beam with a corresponding wavelength is selected according to the type of photoresist to expose it. For example, a light beam with a wavelength range of 200 nanometers to 300 nanometers is used to expose the first photoresist mask, and a light beam with a wavelength range of 240 nanometers to 260 nanometers is used to expose the second photoresist mask.

[0062] In other embodiments, a corresponding type of photoresist mask may be selected according to the wavelength of the light beam. Existing machines have the function of light beam scanning, such as KLA wafer defect scanning machines, photolithography machines, UV irradiation machines, etc., and corresponding types of photoresist masks may be selected according to the wavelength of the light beam of the above existing machines.

[0063] After the second mask layer PR2 is scanned by light of the corresponding wavelength, its molecular weight becomes smaller, thereby weakening the ion injection resistance of the second mask layer PR2. Furthermore, the ion injection resistance of the second mask layer PR2 varies with the exposure time. Specifically, the ion injection resistance of the second mask layer PR2 weakens as the exposure time of the second mask layer PR2 increases. When the exposure time reaches a certain time length, as the exposure time of the second mask layer PR2 increases, the ion injection resistance of the second mask layer PR2 tends to be stable and no longer changes.

[0064] The exposure time length of each of the multiple regions can be controlled to control the ion injection resistance of the second mask layer PR2 in each of the multiple regions, thereby adjusting the doping concentration of the first doping region 111 by region. In one embodiment, the single exposure time of the light beam is constant, and the ion injection resistance of the second mask layer PR2 can be adjusted by controlling the number of exposures. In the process of adjusting the doping concentration of the first doping region 111, as the number of exposures of the second mask layer PR2 increases, the doping concentration of the first doping region 211 gradually decreases first and then tends to be stable.

[0065] In the present embodiment, in the first region 110a, the second mask layer PR2 is exposed for a first time length; in the second region 110b, the second mask layer PR2 is exposed for a second time length; in the third region 110c, the second mask layer PR2 is exposed for a third time length, and the first time length, the second time length and the third time length are different. In one embodiment, the first time length is less than the second time length, and the second time length is less than the third time length. The ion injection resistance of the second mask layer PR2 in the first region 110a is greater than that in the second region 110b, and the ion injection resistance of the second mask layer PR2 in the second region 110b is greater than that in the third region 110c.

[0066] Figure 2e FIG. 4 shows a cross-sectional schematic diagram of the second ion implantation in an embodiment of the present application. Figure 1 and Figure 2e As shown, the semiconductor wafer 10 is subjected to a second ion implantation through the modified second mask layer PR2 to form a second doping region 112 of a second doping type in the semiconductor wafer 10, wherein, during the formation of the second doping region 112, the second ion implantation simultaneously adjusts the doping concentration of the first doping region 111 in different regions so that the doping concentrations of the first doping regions 111 in different regions are the same or different.

[0067] In this step, the semiconductor wafer 10 is subjected to a second ion implantation through the modified second mask layer PR2, wherein during the second ion implantation, a second type of dopant is implanted into the semiconductor wafer 10. The second type of dopant is of the opposite type to the first type of dopant. Since the ion implantation resistance of the modified second mask layer PR2 is weakened, during the second ion implantation, the second type of dopant is implanted into the semiconductor wafer 10 exposed by the second mask layer PR2 to form a second doping region 112 of a second doping type, and part of the second type of dopant will also enter the first doping region 111 through the modified second mask layer PR2, and part of the first type of dopant in the first doping region 111 is neutralized, thereby adjusting the doping concentration of the first doping region 111.

[0068] Furthermore, in this embodiment, the second mask layer PR2 in different regions has different ion injection resistance, so in different regions, the second ion injection changes the doping concentration of the first doping region 111 to different degrees. By controlling the ion injection resistance of the second mask layer PR2 in different regions, the doping concentration of the first doping region 111 in different regions can be controlled, thereby eliminating the difference in doping concentration of the first doping region 111 in different regions.

[0069] In this embodiment, since the ion injection resistance of the second mask layer PR2 in the first region 110a is greater than that of the second mask layer PR2 in the second region 110b, more second-type dopants enter the first doping region 111 in the second region 110b relative to the first region 110a, and the first-type dopants in the first doping region 111 in the second region 110b are more neutralized, thereby reducing or even eliminating the difference in doping concentration between the first doping region 111 in the first region 110a and the first doping region 111 in the second region 110b. Similarly, the ion injection resistance of the second mask layer PR2 in the second region 110b is greater than that of the second mask layer PR2 in the third region 110c, and the difference in doping concentration between the first doping region 111 in the second region 110b and the first doping region 111 in the third region 110cb is reduced or even eliminated.

[0070] Furthermore, the method for forming a semiconductor device also includes forming an active region, a source region, a drain region, and a gate stack structure, etc., so as to finally form a plurality of semiconductor devices in the semiconductor wafer 10 .

[0071] Through the above method, the difference in electrical performance of the same semiconductor device in different regions of the same semiconductor wafer 10 is eliminated by adjusting the ion implantation resistance of the second mask layer PR2 in different regions. In other embodiments, semiconductor devices with different electrical performance can be formed in different regions of the same semiconductor wafer 10 by adjusting the ion implantation resistance of the second mask layer PR2 in different regions.

[0072] In the above embodiment, the semiconductor wafer is divided into a plurality of regions arranged sequentially from the inside to the outside. It should be noted that the shape, number and arrangement of the plurality of regions are not limited thereto, and other forms of region division may also be provided. Figure 5 FIG. 4 shows a semiconductor wafer region division form in an embodiment, such as Figure 5 As shown, the semiconductor wafer 20 is divided into a plurality of regions 210 sequentially distributed from top to bottom, each of the plurality of regions 210 is rectangular. The plurality of regions, for example, include a first region 210a to an eighth region 210h sequentially arranged from top to bottom.

[0073] In the process of modifying the second mask layer PR2 of different areas, the first area 210a is exposed 12 times, the second area 210b is exposed 6 times, the third area 210c is exposed 4 times, the fourth area 210d is exposed 2 times, the fifth area 210e is exposed 1 time, the sixth area 210f is exposed 2 times, the seventh area 210g is exposed 4 times, and the eighth area 210h is exposed 20 times.

[0074] Figure 6 Shows Figure 5 A partial schematic diagram of the threshold voltage of the same semiconductor device in multiple regions of a semiconductor wafer is shown, such as Figure 6 As shown, the fifth region 210e has the least number of exposures, and the threshold voltage (absolute value) of the semiconductor device 210a in the fifth region 210e is the highest. From the fifth region 210e toward the first region 210a, the number of exposures of each region gradually increases, and accordingly, the threshold voltage (absolute value) of the semiconductor device 210a in each region gradually decreases. Similarly, from the fifth region 210e toward the eighth region 210h, the number of exposures of each region gradually increases, and accordingly, the threshold voltage (absolute value) of the semiconductor device 210a in each region gradually decreases.

[0075] Furthermore, the number of exposure times of the first region 210a is much smaller than the number of exposure times of the eighth region 210h. However, compared with the threshold voltage (absolute value) of the semiconductor device 210a in the first region 210a, the threshold voltage (absolute value) of the semiconductor device 210a in the eighth region 210h is not significantly reduced.

[0076] It can be seen from the above embodiments that the electrical performance of the semiconductor device is related to the number of exposures of the second mask layer. This embodiment obtains a fitting curve of the electrical performance of the semiconductor device and the number of exposures of the second mask layer, and then adjusts the electrical performance of the semiconductor device according to the fitting curve. Specifically, the following steps are included:

[0077] S200: Obtaining a fitting curve between the electrical performance of the semiconductor device and the number of exposure times of the second mask layer;

[0078] S210: Dividing the semiconductor wafer into a plurality of regions;

[0079] S220: forming a first doping region of a first doping type in the semiconductor wafer;

[0080] S230: forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doped region;

[0081] S240: exposing the mask layer with a light beam to achieve mask layer modification, wherein a single exposure time of the light beam is constant, and the number of exposure times of the mask layer is adjusted regionally according to the fitting curve, and the mask layer is modified regionally to adjust the ion implantation resistance of the mask layer regionally;

[0082] S250: injecting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is injected into the semiconductor wafer exposed by the mask layer to form a second doping region of a second doping type, and part of the second type of dopant is injected into the first doping region covered by the mask layer, and the doping concentration of the first doping region is adjusted, thereby adjusting the electrical performance of the semiconductor device;

[0083] By adjusting the exposure times of the mask layer in different areas, the electrical properties of the same semiconductor device in different areas of the same semiconductor wafer are made consistent, so as to eliminate the difference in electrical properties of the same semiconductor device in different areas of the same semiconductor wafer; or by adjusting the exposure times of the mask layer in different areas, the electrical properties of the same semiconductor device in different areas of the same semiconductor wafer are made different, so as to form semiconductor devices with different electrical properties in different areas of the same semiconductor wafer.

[0084] Furthermore, the fitting curve of the electrical performance of the semiconductor device and the exposure times of the mask layer includes an adjustment region where the electrical performance changes with an increase in the exposure times and a stable region close to a stable value. Figure 7 The fitting curve between the threshold voltage of the semiconductor device and the exposure times is shown in FIG. Figure 7 As shown in FIG. 1 , the fitting curve includes an adjustment region where the threshold voltage (absolute value) of the semiconductor device decreases as the number of exposures increases, and a stable region close to a stable value. That is, as the number of exposures increases, the threshold voltage (absolute value) of the semiconductor device first gradually decreases and then tends to be stable.

[0085] Figure 8 The fitting curve between the drain saturation current of the semiconductor device and the exposure times is shown in FIG. Figure 8 As shown in FIG. 1 , the fitting curve between the drain saturation current (absolute value) of the semiconductor device and the exposure times includes an adjustment region that increases with the increase of the exposure times, and a stable region close to the stable value. That is, as the exposure times increase, the drain saturation current (absolute value) of the semiconductor device first gradually increases and then tends to be stable.

[0086] In the above embodiment, in order to eliminate the difference in electrical properties of the same semiconductor device in different regions of the semiconductor wafer, the second mask layer PR2 in different regions is modified to different degrees, and the doping concentration of the first doping region in different regions is adjusted respectively, thereby eliminating the difference in doping concentration of the body region (first doping region) in different regions of the same semiconductor wafer.

[0087] In other embodiments, the semiconductor wafer may be divided into multiple regions, and the doping concentration of the body region (first doping region) of the same semiconductor wafer may be controlled by region, so as to form semiconductor devices with different electrical properties in different regions of the same semiconductor wafer.

[0088] In the above embodiments, the semiconductor wafer is divided into regions as a whole, and the semiconductor wafer also includes multiple basic operation units (shots), each basic operation unit (shot) includes multiple chips (chips), and each chip (chip) includes multiple semiconductor devices. Each chip (chip) can also be further divided into regions.

[0089] Fig. 9 FIG. 4 shows the area division form of the conductor substrate in another embodiment of the present application, such as Fig. 9 As shown, the semiconductor wafer 30 includes a plurality of identical basic operation units 30-1, each of which includes a plurality of identical chips 30-2, and each of which includes a plurality of semiconductor devices 30a. In this embodiment, the chip 30-2 is divided into a plurality of regions. In this embodiment, for example, the chip 30-2 is divided into a first region 30-2a, a second region 30-2b, a third region 30-2c, and a fourth region 30-2d. The region sizes and numbers of the plurality of regions can be set as required, and the position distribution of the plurality of regions can also be arbitrarily set as required, which is not limited in this embodiment.

[0090] Further, the number of exposure times for each of the multiple regions can be set as needed, and this embodiment does not limit this. In one embodiment, the doping concentration of the first doping region in the first region 30-2a, the second region 30-2b, the third region 30-2c, and the fourth region 30-2d decreases in sequence. In this embodiment, a chip 30-2 is divided into multiple regions, and the doping concentration of the first doping region of the chip 30-2 is adjusted by region to form a semiconductor device with different electrical properties in the same chip 30-2.

[0091] The unexpected technical effects of this application are:

[0092] The present application performs regional modification treatment on the same mask layer to adjust the ion injection resistance of the mask layer in different regions, thereby adjusting the doping concentration of the first doping region in different regions separately. Without adding photolithography and ion injection steps, the doping concentration of the first doping region of the same semiconductor wafer can be controlled in different regions.

[0093] In the process of forming the second doping region, the present application adjusts the doping concentration of the first doping region without adding additional photolithography and ion implantation steps.

[0094] The mask layer described in the present application is a photoresist mask layer, and the ion injection resistance of the mask layer is controlled by controlling the exposure time of the mask layer, thereby facilitating the control of the ion injection resistance of the mask layer.

[0095] The single exposure time of the light beam in the present application is constant. By controlling the number of exposure times of the mask layer, the ion implantation resistance of the mask layer is controlled, and the corresponding relationship between the number of exposure times of the mask layer and the electrical performance of the semiconductor device is obtained, so as to optimize the electrical performance of the semiconductor device.

[0096] The present application controls the ion implantation resistance of the mask layer in different regions so that the doping concentrations of the first doping regions in different regions are consistent, thereby eliminating the differences in electrical performance of the same semiconductor device in different regions of the same semiconductor wafer.

[0097] The present application controls the ion implantation resistance of the mask layer in different regions so that the doping concentrations of the first doping regions in different regions are different, so as to form semiconductor devices with different electrical properties in different regions of the same semiconductor wafer.

[0098] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A method for preparing a semiconductor device, comprising: dividing a semiconductor wafer into a plurality of regions; selectively implanting a first type of dopant into the semiconductor wafer to form a first doping region of a first doping type in the semiconductor wafer; forming a patterned mask layer on the semiconductor wafer, wherein the mask layer covers the first doped region; Performing modification treatment on the mask layer in different regions to adjust the ion implantation resistance of the mask layer in different regions; and Injecting a second type of dopant opposite to the first type into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is injected into the semiconductor wafer exposed by the mask layer to form a second doping region of the second doping type, and part of the second type of dopant is injected into the first doping region covered by the mask layer to adjust the doping concentration of the first doping region; The mask layer is a photoresist mask, and the mask layer is exposed to light by a light beam corresponding to the photosensitivity wavelength of the mask layer to perform a modification process on the mask layer.

2. The method according to claim 1, wherein: When the mask layer is modified by exposing the mask layer with a light beam, the ion implantation resistance of the mask layer is controlled by adjusting the exposure time of the mask layer.

3. The method according to claim 1, wherein: When the mask layer is modified by using a light beam to expose the mask layer, the single exposure time of the light beam is constant, and the ion injection resistance of the mask layer is related to the number of exposure times of the mask layer. The ion injection resistance of the mask layer is controlled by adjusting the number of exposure times of the mask layer.

4. The method according to claim 3, wherein: When the mask layer is modified by exposing the mask layer with a light beam, as the number of times the mask layer is exposed increases, the ion implantation resistance of the mask layer first gradually decreases and then tends to be stable.

5. A method for adjusting the electrical properties of a semiconductor device, wherein: The electrical performance of the semiconductor device is related to the number of exposure times of the mask layer, and the electrical performance adjustment method includes: Obtaining a fitting curve of the electrical performance of the semiconductor device and the number of exposure times of the mask layer; forming a first doped region of a first doping type in a semiconductor wafer; forming a patterned mask layer on a semiconductor wafer, wherein the mask layer covers the first doped region; The mask layer is exposed to light by a light beam corresponding to the photosensitivity wavelength of the mask layer to achieve modification of the mask layer, the single exposure time of the light beam is constant, the exposure times of the mask layer are adjusted regionally according to the fitting curve, and the mask layer is modified regionally to adjust the ion implantation resistance of the mask layer regionally; A second type of dopant opposite to the first type is injected into the semiconductor wafer through the modified mask layer, wherein the second type of dopant is injected into the semiconductor wafer exposed by the mask layer to form a second doping region of the second doping type, and part of the second type of dopant is injected into the first doping region covered by the mask layer to adjust the doping concentration of the first doping region, thereby adjusting the electrical properties of the semiconductor device.

6. The method according to claim 5, wherein: The fitting curve of the electrical performance of the semiconductor device and the exposure times of the mask layer includes an adjustment region where the electrical performance changes with the increase of the exposure times and a stable region close to a stable value.

7. The method according to claim 5, wherein: The exposure times of the mask layer in different regions are adjusted so that the electrical performance of the same semiconductor device in different regions of the same semiconductor wafer is consistent, thereby eliminating the difference in electrical performance of the same semiconductor device in different regions of the same semiconductor wafer.

8. The method according to claim 5, wherein: The exposure times of the mask layer in different regions are adjusted so that the electrical properties of the same semiconductor device in different regions of the same semiconductor wafer are different, so as to form semiconductor devices with different electrical properties in different regions of the same semiconductor wafer.

9. A semiconductor device formed by the method according to any one of claims 1 to 8, the semiconductor device comprising: A semiconductor wafer, wherein the semiconductor wafer comprises a plurality of regions; a first doping region of a first doping type located in the semiconductor wafer; as well as a second doping region of a second doping type located in the semiconductor wafer; Wherein, the doping concentration of the first doping region is adjusted while the second doping region is formed, and the doping concentrations of the first doping region in different regions are the same or different.

Images