Preparation method of semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure, which is applied to the technical field of semiconductors. According to the invention, by removing the closed-loop line pattern, the grid-shaped pattern, the columnar array pattern and the part of the pad structure corresponding to the surrounding pattern, the pad structure defects of the semiconductor structure caused by continuous increase of the density of the storage unit are overcome, and the pad structure is prevented from collapsing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor memory structure. Background Art

[0002] As various electronic products develop towards miniaturization, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the DRAM cell with only a planar gate structure under the current mainstream development trend. Generally speaking, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage component to receive voltage signals from the bit line and the word line. However, due to the limitations of process technology, the existing DRAM cell with a recessed gate structure still has many defects, and further improvements are needed to effectively improve the performance and reliability of the relevant memory components. Summary of the invention

[0003] The object of the present invention is to provide a method for preparing a semiconductor structure, by removing part of the columnar array pattern and part of the surrounding pattern on the first area and part of the closed-loop line pattern on the second area used to form the corresponding pad structure, so as to improve the pad structure defects of the semiconductor structure derived from the continuous increase in the density of storage units, thereby improving the technical problem of partial pad structure collapse.

[0004] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor structure, which may at least include:

[0005] providing a substrate comprising a first region and a second region;

[0006] forming a target layer on the first region and the second region of the substrate;

[0007] forming a hard mask layer on the target layer;

[0008] forming a first pattern located on the first region of the hard mask layer, wherein the first pattern includes a plurality of columnar array patterns and a surrounding pattern surrounding the columnar array patterns;

[0009] forming a second pattern on the second region of the hard mask layer, wherein the second pattern comprises a plurality of closed loop line patterns;

[0010] forming a barrier layer on the first pattern and the second pattern;

[0011] Using the barrier layer as a mask, cutting the closed loop line pattern of the second pattern into a single line pattern;

[0012] The first pattern and the second pattern after being cut are used as masks to form the first pattern and the second pattern in the target layer.

[0013] In some optional examples, ends of the plurality of closed-loop line patterns are connected.

[0014] In some optional examples, the second pattern further includes: a plurality of grid-bar patterns, and one of the grid-bar patterns is located in a gap in a closed area surrounded by the closed-loop line pattern.

[0015] In some optional examples, the step of forming the second pattern may include:

[0016] forming a first transition layer on the hard mask layer;

[0017] forming the plurality of grid-shaped patterns on the second region of the first transition layer;

[0018] forming a partition wall wrapped on the side wall of the grid strip pattern;

[0019] forming a second transition layer on the first transition layer in the second region, wherein the second transition layer wraps the partition wall;

[0020] The partition wall is removed, and a closed loop line pattern is formed on the second transition layer on the second region, surrounding the outer side of the grid strip pattern and having a gap therebetween;

[0021] The second transition layer is used as a mask to form the gate stripe pattern and the closed loop line pattern on the second region of the hard mask layer.

[0022] In some optional examples, the first transition layer located on the first region may further include a rectangular block pattern.

[0023] In some optional examples, the partition walls may also be formed on side walls of the rectangular block pattern.

[0024] In some optional examples, a third pattern is formed on the second region of the barrier layer, and the third pattern may include a plurality of grid-shaped opening patterns exposing ends of the plurality of closed-loop line patterns.

[0025] In some optional examples, the third pattern may further include: a plurality of rectangular block opening patterns that expose a portion of the closed-loop line pattern and a portion of the grid strip pattern of the second pattern.

[0026] In some optional examples, a fourth pattern is formed on the first area of ​​the barrier layer, and the fourth pattern includes an irregular closed pattern that shields a portion of the columnar array pattern and a ring-shaped frame pattern located outside the irregular closed pattern and shielding a portion of the surrounding pattern.

[0027] In some optional examples, the width of the grid-shaped opening pattern may be greater than the sum of the widths of the ends of the multiple closed-loop line patterns after being connected.

[0028] In the preparation method of the semiconductor structure provided by the present invention, on the one hand, a closed-loop line pattern and a grid-shaped pattern located in the internal gap of the second area of ​​the substrate are formed to form a partition wall to fill the gap and use it to remove the pad structure corresponding to the partition wall on the second area, and a barrier layer with an opening pattern and a shielding pattern is formed and used to remove part of the closed-loop line pattern and part of the grid-shaped pattern on the second area. The pad structure corresponding to the pattern is removed to achieve the purpose of removing part of the pad structure with defects on the second area (for example, the structure size does not meet the design requirements); on the other hand, a barrier layer with an opening pattern and a shielding pattern is formed on the first area of ​​the substrate to remove part of the columnar array pattern and the pad structure corresponding to the surrounding pattern close to the second area on the first area, so as to achieve the purpose of removing part of the pad structure with defects on the first area, and also to achieve the purpose of improving the pad structure defects derived from the continuous increase in the density of storage units in the semiconductor structure and avoiding the collapse of the pad structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0030] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in one embodiment of the present invention;

[0031] Figure 2 to Figure 16 The method for preparing a semiconductor structure provided in one embodiment of the present invention includes: Figure 2 The top view obtained in the direction of the CC tangent line.

[0032] Figures 17 to 24 The figure is a schematic structural diagram of a method for preparing a semiconductor structure during the preparation process provided in one embodiment of the present invention.

[0033] Wherein, the accompanying drawings are marked as follows:

[0034] 100-substrate, 100A-first region, 100B-second region, 110-target layer, 111.1-column array pattern located in the target layer, 111.2-annular frame pattern located in the target layer, 112.1-single line pattern located in the target layer, 120-hard mask layer, 121-first pattern, 121.1-column array pattern located in the hard mask layer, 121.2-enclosing pattern located in the hard mask layer, 121.3-first stripe pattern, 121.4-second stripe pattern, 122-second pattern, 122.1- A gate stripe pattern located in the hard mask layer, 122.2-a closed loop line pattern located in the hard mask layer, 130-a first transition layer, 131-a rectangular block pattern, 132-a gate stripe pattern located in the first transition layer, 140-a partition wall, 150-a second transition layer, 160-a third transition layer, 170-a barrier layer, 171-a third pattern, 171.1-a gate stripe opening pattern, 171.2-a rectangular block opening pattern, 172-a fourth pattern, 172.1-an irregular closed pattern, 172.2-a ring frame pattern located in the barrier layer.

[0035] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0036] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0037] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0038] In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be combined arbitrarily without conflict.

[0039] For ease of understanding, a first direction D1, a second direction D2, a third direction D3 and a fourth direction D4 are defined below, wherein the first direction D1 is a direction parallel to the surface of the substrate 100; the second direction D2 is a direction perpendicular to the first direction D1 and located in the same horizontal plane; the third direction D3 is a direction located in the same horizontal plane as the first direction D1 and the second direction D2 and has an inclination angle with the first direction D1 and the second direction D2; and the fourth direction D4 is a direction perpendicular to the surface of the substrate 100.

[0040] Please refer to Figure 1 , Figure 1 Schematic diagram of the process of preparing the semiconductor structure provided in this embodiment. Figure 1 As shown, the method for preparing the semiconductor structure provided in this embodiment at least includes the following steps:

[0041] Step S101 , providing a substrate, wherein the substrate includes a first region and a second region.

[0042] Step S102 , forming a target layer on the first area and the second area of ​​the substrate.

[0043] Step S103 , forming a hard mask layer on the target layer.

[0044] Step S104 , forming a first pattern on the first region of the hard mask layer, wherein the first pattern includes a plurality of columnar array patterns and a surrounding pattern surrounding the columnar array patterns.

[0045] Step S105 , forming a second pattern on the second region of the hard mask layer, wherein the second pattern includes a plurality of closed loop line patterns.

[0046] Step S106: forming a barrier layer on the first pattern and the second pattern.

[0047] Step S107 , using the barrier layer as a mask, cutting the closed loop line pattern of the second pattern into a single line pattern.

[0048] Step S108 , using the first pattern and the cut second pattern as masks, forming the first pattern and the second pattern in the target layer.

[0049] In order to enable a general technician in the technical field to which the present invention belongs to easily understand the method for preparing the semiconductor structure in the embodiment of the present invention, the following will further illustrate the method for preparing the semiconductor structure proposed in the present invention in combination with various structural schematic diagrams of the preparation method during the preparation process and the corresponding top view and local enlarged view.

[0050] Figure 2 to Figure 16 The method for preparing a semiconductor structure provided in one embodiment of the present invention includes: Figure 2 The top view obtained in the direction of the CC tangent line; Figures 17 to 24 The figure is a schematic structural diagram of a method for preparing a semiconductor structure during the preparation process provided in one embodiment of the present invention.

[0051] Please refer to Figure 2 and Fig.17, perform the above steps S101 to S104: provide a substrate 100 as a setting basis for the semiconductor structure in the embodiment of the present invention, and divide the substrate 100 into a first area 100A and a second area 100B surrounding the first area 100A. In one embodiment, the substrate 100 is any suitable substrate material known in the art, for example, it can be a silicon substrate, a silicon-containing substrate or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto. Then, a target layer 110 and a hard mask layer 120 stacked in sequence are formed on the first area 100A and the second area 100B of the substrate 100 by using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. In one embodiment, the material of the hard mask layer 120, for example, includes at least one of silicon nitride (SiN) or silicon oxynitride (SiON), and the material of the target layer 110, for example, includes at least one of conductive barrier materials such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), but not limited thereto. Next, a first pattern 121 is formed on the first region 100A of the hard mask layer 120, and the first pattern 121 includes a plurality of columnar array patterns 121.1 and a surrounding pattern 121.2 surrounding the columnar array pattern 121.1. In one embodiment, the plurality of columnar array patterns 121.1 of the first pattern 121 are specifically used to form a plurality of storage node pad (SNpad) structures as a semiconductor device (not shown, for example, a dynamic random access memory device), and are located in the middle area of ​​the first region 100A and are separated from each other along the first direction D1 and the third direction D3 that are staggered and not perpendicular to each other, and are arranged in multiple rows in the third direction D3, and the surrounding pattern 121.2 is specifically used to form a pad boundary structure that ensures the contact range between the pad 111 and the corresponding plug (not shown) and is arranged on the outside of the storage node pad structure corresponding to all the columnar array patterns 121.1, and extends along the first direction D1 and the second direction D2 on the second region 100B. In detail, the first pattern 121 located on the first area 100A may also include a plurality of first strip patterns 121.3 and a plurality of second strip patterns 121.4 arranged between the plurality of columnar array patterns 121.1 and the surrounding pattern 121.2; in one embodiment, the plurality of first strip patterns 121.3 are spaced apart from each other along the first direction D1 or the second direction D2, and the plurality of second strip patterns 121.4 are spaced apart from each other along the second direction D2, and are in direct contact with the surrounding pattern 121.2 located in the first area 100A, so as to serve as branch patterns of the surrounding pattern 121.2 extending along the third direction D3, and the first strip patterns 121.3 and the second strip patterns 121.4 are specifically used to form a surrounding pad structure for adjusting the density of the pad structure.

[0052] It should be understood that since the surrounding pattern 121.2 located on the first area 100A will extend to the second area 100B, Figure 2 The CC tangent in Fig.17 When observing the cross-sectional view of FIG. 1 , the surrounding pattern 121.2 and the second strip pattern 121.4 are continuous structures, while the plurality of columnar array patterns 121.1 are independent structures that are separated from each other.

[0053] Please refer to Figure 3 and Fig.18 , and combined with Figure 4 , following the above step S104: forming a first transition layer 130 on the first area 100A and the second area 100B of the hard mask layer 120, and the first transition layer 130 has different patterns on the first area 100A and the second area 100B. In one embodiment, the portion of the first transition layer 130 located in the first area 100A has a rectangular block pattern 131, and the portion of the first transition layer 130 located in the second area 100B has a plurality of gate strip patterns 132; the rectangular block pattern 131 covers the first pattern 121 located on the hard mask layer 120 in the first area 100A, and the edge of the rectangular block pattern 131 is flush with the edge of the surrounding pattern 121.2 of the first pattern 121; the plurality of gate strip patterns 132 located in the first transition layer 130 are arranged on the outside of the rectangular block pattern 131 and are separated from each other along the first direction D1 and the second direction D2; the first transition layer 130 may be made of the same material as the hard mask layer 120, for example, silicon nitride (SiN) or silicon oxynitride (SiON), but is not limited thereto.

[0054] It should be understood that Figure 4 for Figure 3 A partial enlarged view of the semiconductor structure at the position of the dotted ellipse. Figure 4 As shown, the shape of the grid bar pattern 132 located in the first transition layer 130 in the embodiment of the present invention can be a grid bar extending along the second direction D2, and its width along the second direction D2 is greater than its width along the first direction D1, but is not limited thereto.

[0055] Please refer to Figure 5 and Fig.19 , and combined with Figure 6, following the above step S104: forming a partition wall 140 on the sidewalls of the rectangular block pattern 131 and the plurality of grid-shaped patterns 132 located in the first transition layer 130. In one embodiment, the partition wall 140 wraps around each grid-shaped pattern 132 located in the first transition layer 130 and each sidewall of the rectangular block pattern 131, thereby forming a Figure 5 And the corresponding partial enlarged image Figure 6 The illustrated closed rectangular frame pattern is formed by four spacers 140. In addition, the material of the spacers 140 and the material of the first transition layer 130 have a high etching selectivity ratio.

[0056] Please refer to Figure 7 and Fig. 20 , and combined with Figure 8 , following the above step S104: forming a second transition layer 150 that fills the gaps between the rectangular block pattern 131 formed in the first transition layer 130 in the second area 100B and the gate strip pattern 132 located in the first transition layer 130 and the multiple gate strip patterns 132 located in the first transition layer 130; in one embodiment, the material of the second transition layer 150 may also be the same as that of the first transition layer 130, such as silicon nitride (SiN) or silicon oxynitride (SiON), but is not limited thereto.

[0057] Please refer to Fig. 9 and Fig.21 , and combined with Fig.10 , following the above step S104: performing a removal process such as at least one of a dry etching process or a wet etching process, the corresponding film layers of all the partition walls 140 spaced in the first transition layer 130 and the second transition layer 150 can be removed to form a Fig. 9 And its corresponding partial enlarged image Fig.10 The second pattern in the above step S105 is formed by the gaps between the plurality of the grid-shaped patterns 132 in the second transition layer 150 and the first transition layer 130 as shown in FIG. 1 . However, at this time, the second pattern is formed in the first transition layer 130 and the second transition layer 150. Specifically, the second pattern in the first transition layer 130 and the second transition layer 150 may include a plurality of closed-loop line patterns (such as Fig. 9 or Fig.10 The second transition layer 150 outside the interval described in the figure and the grid strip pattern 132 located in the first transition layer 130 in the gap of the closed area surrounded by each closed loop line pattern.

[0058] Please continue to refer to Fig. 9 and Fig.10 , and combined with Fig. 22 , execute the above step S105: using the multiple closed-loop line patterns connected at the ends of the first transition layer 130 and the second transition layer 150 and the multiple grid-shaped patterns 132 located in the first transition layer 130 as masks, the multiple grid-shaped patterns 132 located in the first transition layer 130 and the closed-loop line patterns are transferred to the second area 100B of the hard mask layer 120. At this time, in order to facilitate distinction, the embodiment of the present invention marks the second pattern located in the second area 100B of the hard mask layer 120 with the attachment mark 122, and marks the grid-shaped pattern in the second pattern 122 with the reference mark 122.1, and marks its closed-loop line pattern with the reference mark 122.2.

[0059] Please refer to Fig.11 and Fig.23 , and combined with Fig.12 , perform the above step S106: first form a third transition layer 160 and a barrier layer 170 stacked in sequence, and use photolithography and etching processes to form a third pattern 171 on the second area 100B of the barrier layer 170, and form a fourth pattern 172 on the first area 100A thereof; it should be understood that if the third transition layer 160 is a transparent material, then the third pattern 171 and the fourth pattern 172 formed on the barrier layer 170 can use the relationship between the third pattern 171 and the fourth pattern 172 formed on the barrier layer 170 and the first pattern 121 and the second pattern 122 in the hard mask layer 120 located below the third transition layer 160 to describe the specific positions of the third pattern 171 and the fourth pattern 172.

[0060] In one embodiment, the third pattern 171 includes a plurality of grid-shaped opening patterns 171.1 that expose the ends of the plurality of closed-loop line patterns 122.2; the fourth pattern 172 includes an irregular closed pattern 172.1 that shields a portion of the columnar array pattern 121.1 and a ring-shaped frame pattern 172.2 that is located outside the irregular closed pattern 172.1 and shields a portion of the surrounding pattern 121.2 (the portion located in the first area 100A); in detail, the grid-shaped opening pattern 171.1 of the third pattern 171 located in the second area 100B extends along the first direction D1 or the second direction D2, and its width is greater than the sum of the widths of the ends of the plurality of closed-loop line patterns 122.2 connected along their respective directions, for example Fig.11 A partial enlarged view of the semiconductor structure described in Fig.12As shown, two grid-shaped opening patterns 171.1 are opposite to each other along the second direction D2 and are respectively arranged at two ends of the connected multiple closed-loop line patterns 122.2, and the width of each of the grid-shaped opening patterns 171.1 along the first direction D1 is greater than the sum of the widths of the ends of the connected multiple closed-loop line patterns 122.2 along the first direction D1, so as to ensure that when executing step S107, all the ends of the connected multiple closed-loop line patterns 122.2 can be removed, so as to cut the closed-loop line pattern 122.2 of the second pattern 122 into a single line pattern, as shown in FIG. Fig.14 As shown; the irregular closed pattern 172.1 of the fourth pattern 172 may specifically only cover a portion of the plurality of columnar array patterns 121.1 located in the middle area on the first area 100A, and expose the remaining portion of the columnar array pattern 121.1 on the first area 100A, so that when etching downward along the fourth direction D4 using the barrier layer 170 as a mask, the plurality of columnar array patterns 121.1 not covered by the irregular closed pattern 172.1 of the fourth pattern 172 can be removed, thereby achieving the removal of the pad structure corresponding to the portion of the columnar array pattern 121.1 on the first area 100A close to the second area 100B.

[0061] In another embodiment, please refer to Fig.13 In addition to the plurality of grid-shaped opening patterns 171.1 exposing the ends of the plurality of closed-loop line patterns 122.2, the third pattern 171 also includes a plurality of rectangular block opening patterns 171.2 exposing a portion of the closed-loop line patterns 122.2 and a portion of the grid-shaped patterns 122.1 of the second pattern 122; under this arrangement, a portion of the plurality of grid-shaped patterns 122.1 extending along the second direction D2 with a longer length can be removed in a subsequent etching process along the second direction D2 to form a pattern Fig.15 The pattern shown is not limited thereto, and the fourth pattern 172 formed by the barrier layer 170 in this embodiment is the same as the pattern and position in the aforementioned embodiment, and will not be repeated here.

[0062] Please refer to Fig.14 and Fig.15 , and combined with Fig.23 , perform the above step S107: an etching process may be performed downward along the fourth direction D4, so as to use the third pattern 171 and the fourth pattern 172 formed in the barrier layer 170 as a mask to transfer the pattern downward, and in this process, the closed loop line pattern 122.2 of the second pattern 122 is cut into a single line pattern by the third pattern 171, such as Fig.14 Shown or Fig.15As shown, the portion of the columnar array pattern 121.1 on the first area 100A that is not covered by the fourth pattern 172 and the portion of the surrounding pattern 121.2 located outside thereof are removed.

[0063] Please refer to Fig.16 and Fig.24 , perform the above step S108: use the multiple columnar array patterns 121.1 of the first pattern 121 remaining in the hard mask layer 120 and the single line pattern of the second pattern 122 after being cut off as masks, and transfer the patterns of the first pattern 121 and the second pattern 122 to the target layer 110. At this time, in order to facilitate distinction, the multiple columnar array patterns located in the first area 100A of the target layer 110 are exemplarily identified by reference numeral 111.1, the annular frame pattern located in the first area 100A of the target layer 110 is identified by reference numeral 111.2, and the multiple single line patterns located in the second area 100B of the target layer 110 and dividedly arranged along the first direction D1 and the second direction D2 are identified by reference numeral 112.1.

[0064] To summarize, in the method for preparing a semiconductor structure provided by the present invention, on the one hand, a closed-loop line pattern and a gate-shaped pattern located in the internal gap are formed on the second area of ​​the substrate, an interval wall is formed to fill the gap and the pad structure corresponding to the interval wall on the second area is removed by using the interval wall, a barrier layer having an opening pattern and a shielding pattern is formed and the pad structure corresponding to part of the closed-loop line pattern and part of the gate-shaped pattern on the second area is removed by using the barrier layer, so as to achieve the purpose of removing part of the pad structure with defects on the second area (for example, the structure size does not meet the design requirements); on the other hand, a barrier layer having an opening pattern and a shielding pattern is formed on the first area of ​​the substrate to remove part of the columnar array pattern and the pad structure corresponding to the surrounding pattern close to the second area on the first area, so as to achieve the purpose of removing part of the pad structure with defects on the first area, and also to achieve the purpose of improving the pad structure defects derived from the continuous increase in the density of the storage unit of the semiconductor structure and avoiding the collapse of the pad structure.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate comprising a first region and a second region; forming a target layer on the first region and the second region of the substrate; forming a hard mask layer on the target layer; forming a first pattern located on the first region of the hard mask layer, wherein the first pattern includes a plurality of columnar array patterns and a surrounding pattern surrounding the columnar array patterns; forming a second pattern on the second region of the hard mask layer, wherein the second pattern comprises a plurality of closed loop line patterns; forming a barrier layer on the first pattern and the second pattern; Using the barrier layer as a mask, cutting the closed loop line pattern of the second pattern into a single line pattern; The first pattern and the second pattern after being cut are used as masks to form the first pattern and the second pattern in the target layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Ends of the plurality of closed-loop line patterns are connected.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The second pattern further includes: a plurality of grid-bar patterns, and one of the grid-bar patterns is located in a gap in a closed area surrounded by the closed-loop line pattern.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The step of forming the second pattern comprises: forming a first transition layer on the hard mask layer; forming the plurality of grid-shaped patterns on the second region of the first transition layer; forming a partition wall wrapped on the side wall of the grid strip pattern; forming a second transition layer on the first transition layer in the second region, wherein the second transition layer wraps the partition wall; The partition wall is removed, and a closed loop line pattern is formed on the second transition layer on the second region, surrounding the outer side of the grid strip pattern and having a gap therebetween; The second transition layer is used as a mask to form the gate stripe pattern and the closed loop line pattern on the second region of the hard mask layer.

5. The method for preparing a semiconductor memory according to claim 4, wherein: The first transition layer located on the first region further includes a rectangular block pattern.

6. The method for preparing a semiconductor memory according to claim 5, wherein: The partition walls are also formed on side walls of the rectangular block pattern.

7. The method for preparing a semiconductor memory according to claim 2, wherein: A third pattern is formed on the second region of the barrier layer, and the third pattern includes a plurality of grid-shaped opening patterns exposing ends of the plurality of closed-loop line patterns.

8. The method for preparing a semiconductor memory according to claim 7, wherein: The third pattern further includes: a plurality of rectangular block opening patterns that expose a portion of the closed-loop line pattern and a portion of the grid strip pattern of the second pattern.

9. The method for preparing a semiconductor memory according to claim 2, wherein: A fourth pattern is formed on the first region of the barrier layer, and the fourth pattern includes an irregular closed pattern that shields a portion of the columnar array pattern and a ring frame pattern located outside the irregular closed pattern and shielding a portion of the surrounding pattern.

10. The method for preparing a semiconductor structure according to claim 7, characterized in that: The width of the grid-shaped opening pattern is greater than the sum of the widths of the ends of the multiple closed-loop line patterns after being connected.

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