Pixel structure
By introducing a adjusting gate into the pixel structure and changing the charge distribution in the photodiode, the problem of low charge transfer rate in the traditional pixel structure is solved, and more efficient charge transfer is achieved.
Patent Information
- Application Number
- CN202310760616.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-26
- Publication Date
- 2024-12-27
AI Technical Summary
The charge transfer rate of traditional pixel structures is low during exposure, resulting in electron residue problems.
The adjusting gate is introduced into the pixel structure, and the multiple sub-gate regions are arranged in sequence in the direction of the transmission transistor to form a local high potential region, changing the distribution of photogenerated charges in the photodiode, so that it gathers on the side close to the transmission gate, and shortening charge transmission path.
It improves the charge transmission rate of pixels, reduces the transmission time, and effectively solves the problem of electron residue.
Smart Images
Figure CN119208338A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of image sensors and relates to a pixel structure. Background Art
[0002] Image sensors are functional devices that use the photoelectric conversion function of photoelectric devices to convert the light image on the photosensitive surface into an electrical signal that is proportional to the light image. Image sensors include two types: CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCD (Charged Coupled Device) image sensors, which can be widely used in digital cameras, mobile phones, medical devices, automobiles and other applications.
[0003] CCD image sensors and CMOS image sensors have their own advantages in different application scenarios. However, with the rapid development and continuous improvement of CMOS image sensor manufacturing processes and technologies, as well as the continuous decline in the price of high-end CMOS, CMOS has occupied an increasingly important position, and people have higher requirements for the image quality output of CMOS image sensors.
[0004] In the CMOS image sensor, a photosensitive pixel array is provided to collect the photoelectric signal information of the image. When external light shines on the pixel array, a photoelectric effect occurs, generating corresponding charges in the pixel unit to collect the image signal.
[0005] In the traditional pixel structure, during the exposure process, the photogenerated charges are collected and distributed in the doped area of the photodiode (PD for short). When the transfer gate is turned on for charge transfer, the photogenerated charges distributed on the side of the PD close to the transfer gate are first transferred to the FD, but the photogenerated charges distributed at the bottom of the PD need to be moved to the area close to the transfer gate before they can be transferred and output. When the signal reading time is short, due to the slow charge transfer rate at the bottom of the PD, incomplete transfer is prone to occur, resulting in residual electrons.
[0006] Therefore, how to improve the pixel structure to increase the charge transfer rate has become an important technical problem that needs to be solved urgently by those skilled in the art.
[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a pixel structure for solving the problem of low charge transfer rate in the prior art.
[0009] To achieve the above objectives and other related objectives, the present invention provides a pixel structure, comprising:
[0010] A photodiode, comprising a P-type doped region and an N-type doped region located on an upper surface of the P-type doped region;
[0011] A transfer transistor, wherein a source terminal of the transfer transistor is connected to an N-type doped region of the photodiode;
[0012] a reset transistor, wherein a source terminal of the reset transistor is connected to a drain terminal of the transfer transistor;
[0013] An adjustment gate is located above the photodiode, and the adjustment gate includes a plurality of sub-gate regions, wherein the plurality of sub-gate regions are arranged in sequence in the direction from the transfer transistor to the photodiode so as to make the potential of the side of the photodiode close to the transfer transistor higher than the potential of the side of the photodiode away from the transfer transistor during pixel exposure.
[0014] Optionally, a plurality of the sub-gate regions are joined together as one, and for any two adjacent sub-gate regions, a doping concentration of a sub-gate region close to the transfer transistor is higher than a doping concentration of a sub-gate region far from the transfer transistor.
[0015] Optionally, a ratio of a vertical projection area of the regulating gate on a horizontal plane to a vertical projection area of the N-type doping region on a horizontal plane is greater than 0.7.
[0016] Optionally, a plurality of the sub-grid regions are disposed separately.
[0017] Optionally, for any two adjacent sub-gate regions, during pixel exposure, a voltage connected to a sub-gate region close to the transfer transistor is higher than a voltage connected to a sub-gate region far from the transfer transistor.
[0018] Optionally, the doping concentrations of the plurality of sub-gate regions are the same, or the doping concentrations of at least two of the sub-gate regions are different.
[0019] Optionally, for any two adjacent sub-gate regions, the doping concentration of one of the sub-gate regions close to the transfer transistor is higher than the doping concentration of one of the sub-gate regions far from the transfer transistor.
[0020] Optionally, during a pixel exposure period, a plurality of the sub-gate regions are connected to the same voltage, or at least two of the sub-gate regions are connected to different voltages.
[0021] Optionally, the number of the sub-gate regions ranges from 2 to 5.
[0022] Optionally, the material of the regulating gate includes any one of polysilicon or metal material.
[0023] As described above, the pixel structure of the present invention includes a photodiode, a transfer transistor, a reset transistor and an adjustment gate, wherein the photodiode includes a P-type doped region and an N-type doped region located on the upper surface of the P-type doped region, the source terminal of the transfer transistor is connected to the N-type doped region of the photodiode, the source terminal of the reset transistor is connected to the drain terminal of the transfer transistor, the adjustment gate is located above the photodiode, and the adjustment gate includes a plurality of sub-gate regions, and the plurality of sub-gate regions are arranged in sequence in the direction of the transfer transistor pointing to the photodiode so that during the exposure of the pixel, the potential of the side of the photodiode close to the transfer transistor is higher than the potential of the side of the photodiode away from the transfer transistor. The pixel structure of the present invention adds an adjustment gate above the doped region of the photodiode, and a local high potential region is manufactured on the top of the photodiode region through the adjustment gate, thereby changing the distribution of the photogenerated charge in the photodiode region, so that the photogenerated charge is gathered on the side of the photodiode region close to the transfer gate, which can shorten the transmission path of the photogenerated charge and reduce the transmission time, thereby equivalently improving the charge transmission rate of the pixel. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is a schematic diagram showing an exemplary planar layout structure of the pixel structure of the present invention in the first embodiment.
[0025] Figure 2 It is a schematic diagram showing an exemplary timing control of the pixel structure of the present invention in the first embodiment.
[0026] Figure 3 It is a schematic diagram showing an exemplary planar layout structure of the pixel structure of the present invention in the second embodiment.
[0027] Figure 4 It is a schematic diagram showing an exemplary timing control of the pixel structure of the present invention in the second embodiment.
[0028] Component number description
[0029] 101 N-type doping region
[0030] 102 Transmission grid
[0031] 103 Reset Gate
[0032] 104 Adjustment grid
[0033] 104a First sub-gate region
[0034] 104b Second sub-gate region
[0035] 201 N-type doping region
[0036] 202 Transmission grid
[0037] 203 Reset Gate
[0038] 204 Adjustment grid
[0039] 204a First sub-gate region
[0040] 204b Second sub-gate region DETAILED DESCRIPTION
[0041] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0042] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0043] Embodiment 1
[0044] A pixel structure is provided in this embodiment, which includes a photodiode, a transfer transistor, a reset transistor and an adjustment gate, wherein the photodiode includes a P-type doped region and an N-type doped region located on the upper surface of the P-type doped region, the transfer transistor has a transfer gate, and the reset transistor has a reset gate.
[0045] See also Figure 1 , which is a schematic diagram of an exemplary planar layout structure of the pixel structure, showing an N-type doping region 101 of the photodiode, a transfer gate 102 of the transfer transistor, a reset gate 103 of the reset transistor, and an adjustment gate 104.
[0046] Specifically, the source terminal of the transfer transistor is connected to the N-type doping region 101 of the photodiode, the source terminal of the reset transistor is connected to the drain terminal of the transfer transistor, and the regulating gate 104 is located above the photodiode.
[0047] Specifically, the adjustment gate 104 includes a plurality of sub-gate regions, and the plurality of sub-gate regions are arranged sequentially in the direction from the transfer transistor to the photodiode so that during pixel exposure, the potential of the side of the photodiode close to the transfer transistor is higher than the potential of the side of the photodiode away from the transfer transistor.
[0048] In this embodiment, the multiple sub-gate regions of the adjustment gate 104 are joined together as one body, and for any two adjacent sub-gate regions, the doping concentration of the sub-gate region close to the transfer transistor is higher than the doping concentration of the sub-gate region far from the transfer transistor. In other words, the adjustment gate 104 is integrated as a whole, and its multiple sub-gate regions are distinguished by doping concentrations. The potential gradient is formed on the top of the photodiode by the non-uniformity of doping, thereby changing the distribution of photogenerated charges in the photodiode region.
[0049] As an example, the ratio of the vertical projection area of the integrally formed regulating gate 104 on the horizontal plane to the vertical projection area of the N-type doping region on the horizontal plane is greater than 0.7. Figure 1 In the example presented, the area of the adjustment gate 104 almost covers the entire photodiode area, so that the distribution of photogenerated charges can be regulated in a larger area.
[0050] As an example, in Figure 1 In the example presented, the regulating gate 104 includes a first sub-gate region 104 a and a second sub-gate region 104 b that are integrally connected, and the doping concentration of the first sub-gate region 104 a is higher than the doping concentration of the second sub-gate region 104 b.
[0051] It should be pointed out that, in other examples, there may be no clear physical boundaries between the multiple sub-gate regions of the adjustment gate 104, that is, in the direction in which the photodiode points to the transfer transistor, the doping concentration of the adjustment gate 104 may be gradually increased. For example, in the actual manufacturing process, a partial area of the area where the adjustment gate 104 is located is injected, that is, only the side of the area where the adjustment gate 104 is located close to the transfer gate 102 is doped with a preset concentration, and the doping of the side of the area where the adjustment gate 104 is located away from the transfer gate 102 is completed by diffusion, thereby obtaining a non-uniformly doped adjustment gate 104, that is, the doping concentration of the end of the adjustment gate 104 close to the transfer gate 102 is the highest, and the doping concentration of the end away from the transfer gate 102 is the lowest.
[0052] It should be pointed out that in Figure 1In the presented planar layout example, the N-type doping region 101 of the photodiode is roughly square, and the adjustment gate 104 is octagonal. However, in other examples, the shape of the N-type doping region 101 of the photodiode and the shape of the adjustment gate 104 can be adjusted as needed, and the source and drain region layouts of the transfer transistor and the reset transistor can also be adjusted as needed, without being limited to this embodiment.
[0053] As an example, the material of the regulating gate 104 includes polysilicon.
[0054] The principle of achieving photogenerated charge distribution regulation by the non-uniformly doped regulating gate 104 in this embodiment is: Figure 2 , which is a schematic diagram of an example timing control of the pixel structure, wherein AVDD represents the operating voltage, RST represents the gate terminal of the reset transistor, TX represents the gate terminal of the transmission transistor, Gate1 represents the gate terminal of the adjustment gate 104, and RS represents the gate terminal of the row selection transistor.
[0055] Specifically, when the pixel is reset and the exposure period begins, the gate terminal Gate1 of the adjustment gate 104 is connected to a high level. Due to the uneven conductivity caused by its non-uniform doping, the potential of the photodiode region close to the transmission gate 102 is higher, and the potential of the side away from the transmission gate 102 is lower, which drives the photogenerated charges collected by the photodiode during the exposure period to move and gather to the side close to the transmission gate 102. When the exposure is completed and the transmission gate 102 is turned on, the adjustment gate 104 is connected to a low level, and the transmission path of the photogenerated charges is greatly shortened, and the transmission of all the photogenerated charges can be completed in a short time.
[0056] Embodiment 2
[0057] A pixel structure is provided in this embodiment, which includes a photodiode, a transfer transistor, a reset transistor and an adjustment gate, wherein the photodiode includes a P-type doped region and an N-type doped region located on the upper surface of the P-type doped region, the transfer transistor has a transfer gate, and the reset transistor has a reset gate.
[0058] See also Figure 3 , showing an example planar layout structure schematic diagram of the pixel structure, which shows the N-type doping region 201 of the photodiode, the transfer gate 202 of the transfer transistor, the reset gate 203 of the reset transistor, and the adjustment gate 204.
[0059] Specifically, the source terminal of the transfer transistor is connected to the N-type doping region 201 of the photodiode, the source terminal of the reset transistor is connected to the drain terminal of the transfer transistor, and the regulating gate 204 is located above the photodiode.
[0060] Specifically, the adjustment gate 204 includes a plurality of sub-gate regions, which are arranged sequentially in the direction from the transfer transistor to the photodiode so that during pixel exposure, the potential of the side of the photodiode close to the transfer transistor is higher than the potential of the side of the photodiode away from the transfer transistor.
[0061] In this embodiment, the multiple sub-gate regions of the adjustment gate 104 are arranged separately. For any two adjacent sub-gate regions, during pixel exposure, the voltage connected to a sub-gate region close to the transfer transistor is higher than the voltage connected to a sub-gate region far away from the transfer transistor. By applying different voltages to the multiple sub-gate regions, an electric potential gradient is formed on the top of the photodiode, thereby changing the distribution of photogenerated charges in the photodiode area.
[0062] As an example, in Figure 3 In the example presented, the adjustment gate 204 includes a first sub-gate region 204a and a second sub-gate region 204b that are separately arranged. In other examples, the number of separately arranged sub-gate regions included in the adjustment gate 204 can be adjusted as needed, for example, it can be but not limited to 3-5. The more sub-gate regions there are, the higher the degree of adjustment precision is, but the higher the manufacturing process requirements are.
[0063] It should be pointed out that in Figure 3 In the presented planar layout example, the N-type doped region 201 of the photodiode is roughly square, and each of the sub-gate regions is in the shape of a long strip. The extension directions of each of the sub-gate regions are parallel to each other and perpendicular to the direction of the transfer transistor pointing to the photodiode. However, in other examples, the shape of the N-type doped region 101 of the photodiode and the shape of the adjustment gate 104 can be adjusted as needed, and the layout of the source and drain regions of the transfer transistor and the source and drain regions of the reset transistor can also be adjusted as needed, without being limited to this embodiment.
[0064] In addition, the width of each of the sub-gate regions and the width of the gap between two adjacent sub-gate regions may also be adjusted as required, and are not particularly limited here.
[0065] As an example, the material of the regulating gate 204 includes any one of polysilicon or metal material, and the metal material may include aluminum or other suitable metals. When the material of the regulating gate 204 is polysilicon, the doping concentrations of the multiple sub-gate regions included in the regulating gate 204 may be the same, or at least two of the sub-gate regions may have different doping concentrations.
[0066] The principle of this embodiment to achieve photogenerated charge distribution control through the adjustment gate 204 is: Figure 4 , which is a schematic diagram of an example timing control of the pixel structure, wherein AVDD represents the operating voltage, RST represents the gate terminal of the reset transistor, TX represents the gate terminal of the transfer transistor, Gate1 represents the gate terminal of the first sub-gate region 204a, Gate2 represents the gate terminal of the second sub-gate region 204b, and RS represents the gate terminal of the row selection transistor.
[0067] Specifically, when the pixel is reset and begins to be exposed, the gate terminal Gate1 of the first sub-gate region 204a is connected to a slightly higher positive voltage, and the gate terminal Gate2 of the second sub-gate region 204b is connected to a slightly lower positive voltage, and the voltage difference between the two sub-gate regions is used to form a lateral potential difference inside the photodiode, thereby causing the photogenerated charges to gather on one side of the photodiode close to the transmission gate 202. When the exposure is completed and the transmission gate 202 is turned on, the regulating gate 204 is connected to a low level, and the transmission path of the photogenerated charges is greatly shortened, and the transmission of all the photogenerated charges can be completed in a short time.
[0068] Embodiment 3
[0069] A pixel structure is provided in the present embodiment, which is similar to the pixel structure in the second embodiment. The pixel structure in the present embodiment includes a photodiode, a transfer transistor, a reset transistor and an adjustment gate, wherein the photodiode includes a P-type doped region and an N-type doped region located on the upper surface of the P-type doped region, the transfer transistor has a transfer gate, the reset transistor has a reset gate, the source terminal of the transfer transistor is connected to the N-type doped region of the photodiode, the source terminal of the reset transistor is connected to the drain terminal of the transfer transistor, and the adjustment gate is located above the photodiode.
[0070] Specifically, the adjustment gate includes a plurality of sub-gate regions, and the plurality of sub-gate regions are arranged sequentially in the direction from the transfer transistor to the photodiode so that during pixel exposure, the potential of the side of the photodiode close to the transfer transistor is higher than the potential of the side of the photodiode away from the transfer transistor.
[0071] In this embodiment, the multiple sub-gate regions of the regulating gate are separately arranged. For any two adjacent sub-gate regions, the doping concentration of the sub-gate region close to the transfer transistor is higher than the doping concentration of the sub-gate region far from the transfer transistor.
[0072] As an example, the material of the regulating gate includes polysilicon.
[0073] In one application example, during the pixel exposure period, the multiple sub-gate regions are connected to the same voltage, and only the doping concentration difference of the multiple sub-gate regions of the adjustment gate is used to achieve a higher potential on the side of the photodiode region close to the transmission gate and a lower potential on the side away from the transmission gate, thereby driving the photogenerated charges collected by the photodiode during the exposure period to move and gather toward the side close to the transmission gate. When the exposure is completed and the transmission gate is turned on, the adjustment gate is connected to a low level, and the transmission path of the photogenerated charges is greatly shortened, and the transmission of all photogenerated charges can be completed in a short time.
[0074] In another application example, during the pixel exposure period, at least two of the plurality of sub-gate regions are connected to different voltages, so that based on the difference in doping concentration of the plurality of sub-gate regions, a more refined adjustment of the photogenerated charge distribution can be achieved through the difference in voltage.
[0075] In another application example, for any two adjacent sub-gate regions with different doping concentrations, one of the sub-gate regions close to the transfer transistor is connected to a relatively higher voltage, and one of the sub-gate regions far from the transfer transistor is connected to a relatively lower voltage, so that the difference in applied voltage and the difference in doping concentration can add to the regulating effect on the photogenerated charge distribution, thereby achieving more efficient regulation of the photogenerated charge distribution.
[0076] In summary, the pixel structure of the present invention includes a photodiode, a transfer transistor, a reset transistor and an adjustment gate, wherein the photodiode includes a P-type doped region and an N-type doped region located on the upper surface of the P-type doped region, the source terminal of the transfer transistor is connected to the N-type doped region of the photodiode, the source terminal of the reset transistor is connected to the drain terminal of the transfer transistor, the adjustment gate is located above the photodiode, and the adjustment gate includes a plurality of sub-gate regions, and the plurality of sub-gate regions are arranged in sequence in the direction of the transfer transistor pointing to the photodiode so that during the pixel exposure period, the potential of the side of the photodiode close to the transfer transistor is higher than the potential of the side of the photodiode away from the transfer transistor. The pixel structure of the present invention adds an adjustment gate above the doped region of the photodiode, and a local high potential region is manufactured on the top of the photodiode region through the adjustment gate, thereby changing the distribution of the photogenerated charge in the photodiode region, so that the photogenerated charge is gathered on the side of the photodiode region close to the transfer gate, which can shorten the transmission path of the photogenerated charge and reduce the transmission time, thereby equivalently improving the charge transmission rate of the pixel. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0077] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A pixel structure, characterized in that: include: A photodiode, comprising a P-type doped region and an N-type doped region located on an upper surface of the P-type doped region; A transfer transistor, wherein a source terminal of the transfer transistor is connected to an N-type doped region of the photodiode; a reset transistor, wherein a source terminal of the reset transistor is connected to a drain terminal of the transfer transistor; An adjustment gate is located above the photodiode, and the adjustment gate includes a plurality of sub-gate regions, wherein the plurality of sub-gate regions are arranged in sequence in the direction from the transfer transistor to the photodiode so as to make the potential of the side of the photodiode close to the transfer transistor higher than the potential of the side of the photodiode away from the transfer transistor during pixel exposure.
2. The pixel structure according to claim 1, characterized in that: The plurality of sub-gate regions are joined together as a whole. For any two adjacent sub-gate regions, the doping concentration of the sub-gate region close to the transfer transistor is higher than the doping concentration of the sub-gate region far from the transfer transistor.
3. The pixel structure according to claim 1, characterized in that: The ratio of the vertical projection area of the regulating gate on the horizontal plane to the vertical projection area of the N-type doping region on the horizontal plane is greater than 0.
7.
4. The pixel structure according to claim 1, characterized in that: The plurality of sub-grid regions are disposed separately.
5. The pixel structure according to claim 4, characterized in that: For any two adjacent sub-gate regions, during pixel exposure, a voltage connected to a sub-gate region close to the transfer transistor is higher than a voltage connected to a sub-gate region far from the transfer transistor.
6. The pixel structure according to claim 5, characterized in that: The doping concentrations of the plurality of sub-gate regions are the same, or the doping concentrations of at least two of the sub-gate regions are different.
7. The pixel structure according to claim 4, characterized in that: For any two adjacent sub-gate regions, the doping concentration of one of the sub-gate regions close to the transfer transistor is higher than the doping concentration of one of the sub-gate regions far from the transfer transistor.
8. The pixel structure according to claim 7, characterized in that: During the pixel exposure period, the plurality of sub-gate regions are connected to the same voltage, or at least two of the sub-gate regions are connected to different voltages.
9. The pixel structure according to claim 4, characterized in that: The number of the sub-gate regions ranges from 2 to 5.
10. The pixel structure according to claim 1, characterized in that: The material of the regulating gate includes any one of polysilicon and metal material.