Array substrate and preparation method thereof

Abstract

The invention relates to an array substrate and a preparation method thereof, and belongs to the technical field of display. A barrier layer is formed on the side wall of a gate, and the size of a gate dielectric layer formed by etching a dielectric layer is increased, so that a source contact region and a drain contact region which are formed by conducting a metal oxide semiconductor active layer extend to the lower part of the gate dielectric layer and do not extend to the lower part of the gate, thereby ensuring that a channel region has a relatively large size; the short-channel effect of the transistor can be reduced, and the switching performance of the transistor is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof. Background Art

[0002] With the development of information society, display devices are widely used, including liquid crystal display devices, plasma display panel devices, organic light emitting diode display devices, etc.

[0003] Liquid crystal display devices and organic light emitting diode display devices include thin film transistors for electrically connecting pixel regions, and the thin film transistors are used to drive the pixel regions to display images.

[0004] However, the reliability of oxide semiconductor thin film transistors is currently poor. Summary of the invention

[0005] Based on this, it is necessary to provide an array substrate and a preparation method thereof that can improve the problem of poor reliability of oxide semiconductor thin film transistors in response to the above technical problems.

[0006] In a first aspect, the present application provides an array substrate, comprising:

[0007] substrate substrate;

[0008] A transistor disposed on the substrate, the transistor comprising:

[0009] A metal oxide semiconductor active layer is disposed on the substrate, wherein the metal oxide semiconductor active layer comprises a channel region and a source contact region and a drain contact region respectively disposed on both sides of the channel region;

[0010] A gate dielectric layer is disposed on the channel region, and two side edges of an orthographic projection of the gate dielectric layer formed on the substrate have a first overlapping region and a second overlapping region with the orthographic projections of the source contact region and the drain contact region formed on the substrate, respectively;

[0011] A gate is disposed on the gate dielectric layer, wherein an orthographic projection of the gate on the substrate has no overlapping portion with an orthographic projection of the source contact region and an orthographic projection of the drain contact region on the substrate;

[0012] The barrier layer at least covers a portion of the sidewall of the gate.

[0013] In the above-mentioned array substrate, a gate and a barrier layer covering the side wall of the gate are arranged on the gate dielectric layer, so that the size of the gate dielectric layer is larger than the size of the gate, and the orthographic projection formed by the gate dielectric layer on the base substrate and the orthographic projection formed by the source contact area and the drain contact area on the base substrate have a first overlapping area and a second overlapping area, and the orthographic projection formed by the gate on the base substrate and the orthographic projection formed by the source contact area and the drain contact area on the base substrate have no overlapping part, ensuring that the channel area between the source contact area and the drain contact area has a larger size, which can reduce the short channel effect of the transistor and improve the switching performance of the transistor.

[0014] In one embodiment, the size of the first overlapping area in the horizontal direction is not less than a preset value; the size of the second overlapping area in the horizontal direction is not less than the preset value;

[0015] Preferably, the preset value ranges from 0.6 μm to 1 μm;

[0016] Preferably, along the horizontal direction, the maximum size of the gate has a first size, the maximum size of the blocking layer has a second size; the first overlapping region has a third size; the second overlapping region has the third size; the channel region has a fourth size; the third size is equal to the second size, and the fourth size is equal to the first size;

[0017] Preferably, the orthographic projection of the barrier layer on the base substrate coincides with the first overlapping region and the second overlapping region.

[0018] In this way, the dimensional accuracy of the channel region of the transistor is high, and the size of the channel region is consistent with the design size, avoiding the problem of the small size of the channel region caused by the extension of the source contact area and the drain contact area below the gate dielectric layer, avoiding the adverse effects of the short channel effect on the transistor, improving the switching performance of the transistor, and improving the yield rate of the array substrate.

[0019] In one embodiment, the side wall of the gate is an inclined surface, and there is a first angle between the side wall of the gate and the top surface of the gate, and the first angle is 75°-80°;

[0020] Preferably, a second angle is formed between the side wall of the gate and the top surface of the gate, and the second angle is smaller than the first angle;

[0021] Preferably, the side wall of the gate comprises a first inclined surface and a second inclined surface which are connected in sequence along a direction away from the base substrate, and the second inclined surface is connected to the top surface of the gate and has the second included angle with the top surface of the gate.

[0022] In this way, by designing the side wall of the gate to be a slope and setting a barrier layer on the side wall of the gate, the sizes of the first overlapping area and the second overlapping area are defined by the barrier layer, and the size of the channel area is accurately defined by the size of the gate, ensuring that the channel area has high dimensional accuracy, is suitable for transistors with smaller channel lengths, and can effectively avoid the problem of switching performance failure of transistors with small-size channels caused by the short channel effect.

[0023] In one embodiment, the array substrate further includes:

[0024] an interlayer dielectric layer, covering the metal oxide semiconductor active layer, the gate and the barrier layer, wherein a top surface of the interlayer dielectric layer is higher than a top surface of the gate;

[0025] The transistor further comprises:

[0026] A source electrode, penetrating through the interlayer dielectric layer and contacting and connecting with the source contact region;

[0027] A drain electrode, penetrating through the interlayer dielectric layer and contacting and connecting with the drain contact region;

[0028] Preferably, the array substrate further includes:

[0029] A passivation layer is disposed on the interlayer dielectric layer. The passivation layer is provided with vias. The vias are correspondingly disposed on the source electrode and the drain electrode. The vias expose the top surfaces of the source electrode and the drain electrode.

[0030] In this way, it is easy to wire the source electrode and the drain electrode, reducing the wiring difficulty.

[0031] In a second aspect, the present application provides a method for preparing an array substrate, comprising:

[0032] providing a substrate base plate;

[0033] forming a metal oxide semiconductor active layer on the substrate;

[0034] sequentially forming a dielectric layer and a metal layer covering the metal oxide semiconductor active layer;

[0035] Etching the metal layer to form a gate of a transistor on the metal oxide semiconductor active layer;

[0036] forming a barrier layer covering a sidewall of the gate;

[0037] The dielectric layer is etched using the gate electrode and the barrier layer as masks to form a gate dielectric layer, and the metal oxide semiconductor active layer is subjected to conductor processing to form a source contact region and a drain contact region, wherein the metal oxide semiconductor active layer between the source contact region and the drain contact region forms a channel region of the transistor;

[0038] Among them, the two side edges of the orthographic projection formed by the gate dielectric layer on the substrate have a first overlapping area and a second overlapping area with the orthographic projections formed by the source contact area and the drain contact area on the substrate, respectively, and the orthographic projection formed by the gate on the substrate has no overlapping part with the orthographic projections formed by the source contact area and the drain contact area on the substrate.

[0039] The preparation method of the above-mentioned array substrate forms a barrier layer on the side wall of the gate and increases the size of the gate dielectric layer formed by etching the dielectric layer, so that the source contact area and the drain contact area formed by the conductor-treated metal oxide semiconductor active layer extend to the bottom of the gate dielectric layer instead of extending to the bottom of the gate, thereby ensuring that the channel area has a larger size, which can reduce the short channel effect of the transistor and improve the switching performance of the transistor.

[0040] In one embodiment, the sidewall of the gate is an inclined surface, and the maximum dimension of the gate in the horizontal direction has a first dimension;

[0041] Preferably, a first angle is formed between the side wall of the gate and the top surface of the gate, and the first angle is 75°-80°.

[0042] In this way, by designing the side wall of the gate to be a slope and setting a barrier layer on the side wall of the gate, the sizes of the first overlapping area and the second overlapping area are defined by the barrier layer, and the size of the channel area is accurately defined by the size of the gate, ensuring that the channel area has high dimensional accuracy, is suitable for transistors with smaller channel lengths, and can effectively avoid the problem of switching performance failure of transistors with small-size channels caused by the short channel effect.

[0043] In one embodiment, forming a barrier layer covering the sidewall of the gate includes:

[0044] Depositing to form a barrier material layer covering the gate, wherein the thickness of the barrier material layer on the sidewall of the gate is greater than the thickness of the barrier material layer in other areas;

[0045] The barrier material layer is etched with the gate as a stop layer to expose the top surface of the gate and the top surface of the dielectric layer, and a portion of the barrier material layer covering the side wall of the gate is etched away to form the barrier layer;

[0046] Preferably, the barrier material layer is etched using an anisotropic dry process;

[0047] Preferably, the maximum dimension of the barrier layer in the horizontal direction has a second dimension.

[0048] In this way, the barrier material layer is etched with the gate as a stop layer, and there is no need to perform a coating and exposure process, and no need to add a mask process. The barrier material layer can be etched to obtain a barrier layer covering the side wall of the gate, which is beneficial to the control of production costs.

[0049] In one embodiment, the dielectric layer is etched using the gate and the barrier layer as masks to form a gate dielectric layer, and the metal oxide semiconductor active layer is subjected to conductor processing to form a source contact region and a drain contact region, including:

[0050] Etching and removing the dielectric layer exposed by the gate and the barrier layer to form the gate dielectric layer;

[0051] Doping conductive ions into the metal oxide semiconductor active layer on both sides of the gate dielectric layer to form the source contact region and the drain contact region, respectively, wherein the source contact region and the drain contact region extend below the gate dielectric layer respectively;

[0052] Preferably, at least one of bromine plasma, fluorine plasma or helium plasma is used to etch the dielectric layer and to conduct the metal oxide semiconductor active layer;

[0053] Preferably, in the horizontal direction, the first overlapping area has a third size, the second overlapping area has the third size, and the channel area has a fourth size; the third size is equal to the second size, and the fourth size is equal to the first size; wherein the third size is not less than a preset value;

[0054] Preferably, the preset value ranges from 0.6 μm to 1 μm;

[0055] Preferably, the orthographic projection of the barrier layer on the base substrate coincides with the first overlapping region and the second overlapping region.

[0056] In this way, the dielectric layer is etched using the gate and the barrier layer as masks and the metal oxide semiconductor active layer is conductorized so that the first overlapping area and the second overlapping area are located below the barrier layer, ensuring that the metal oxide semiconductor active layer located below the gate forms a channel region, ensuring that the channel region has high dimensional accuracy, is suitable for transistors with smaller channel lengths, and can effectively avoid the problem of failure of switching performance of transistors with small-size channels caused by short channel effects.

[0057] In one embodiment, in the process of etching the dielectric layer to form a gate dielectric layer using the gate and the barrier layer as masks, part of the barrier layer and part of the gate covered by the barrier layer are etched away, and after etching, a second angle is formed between the side wall of the gate and the top surface of the gate, and the second angle is smaller than the first angle;

[0058] Preferably, after etching, the side wall of the gate comprises a first inclined surface and a second inclined surface sequentially connected in a direction away from the substrate, and the second inclined surface is connected to the top surface of the gate and has the second angle with the top surface of the gate.

[0059] In this way, the angle between the side wall of the gate and the top surface of the gate is reduced, and the connection between the side wall of the gate and the top surface of the gate is smoother, which can avoid charge accumulation at the angle between the side wall of the gate and the top surface of the gate, and is beneficial to improving the electrical performance of the transistor.

[0060] In one embodiment, the preparation method further comprises:

[0061] forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the metal oxide semiconductor active layer, the gate and the barrier layer, and the top surface of the interlayer dielectric layer is higher than the top surface of the gate;

[0062] forming a source electrode and a drain electrode penetrating the interlayer dielectric layer, wherein the source electrode is in contact with the source contact region, and the drain electrode is in contact with the drain contact region;

[0063] Preferably, the preparation method further comprises:

[0064] forming a passivation layer on the interlayer dielectric layer;

[0065] The passivation layer is patterned, and via holes are formed on the source electrode and the drain electrode respectively, wherein the via holes expose the top surfaces of the source electrode and the drain electrode.

[0066] In this way, it is easy to wire the source electrode and the drain electrode, reducing the wiring difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0068] FIG1 is a schematic diagram of a related solution 1 after a gate is formed;

[0069] FIG2 is a schematic diagram of a related solution 1 after the active layer is conductively formed using the gate electrode as a mask to form a source region and a drain region;

[0070] FIG3 is a schematic diagram of a related scheme 2 after ion implantation to form a region and a drain region;

[0071] FIG4 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0072] FIG5 is a schematic diagram of a process of preparing an array substrate according to an embodiment of the present application;

[0073] FIG6 is a schematic diagram of an embodiment of the present application after a metal oxide semiconductor active layer is formed on a substrate;

[0074] FIG7 is a schematic diagram of a gate after forming a gate according to an embodiment of the present application;

[0075] FIG8 is a schematic diagram of an embodiment of the present application after a barrier material layer is formed;

[0076] FIG9 is a schematic diagram of an embodiment of the present application after a barrier layer is formed on the sidewall of the gate;

[0077] 10 is a schematic diagram of an embodiment of the present application after etching the dielectric layer using the gate and the barrier layer as masks to form a gate dielectric layer, and conducting the metal oxide semiconductor active layer to form a source contact region and a drain contact region;

[0078] FIG. 11 is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present application.

[0079] Description of reference numerals:

[0080] 11. substrate; 12. isolation buffer layer; 20. transistor; 21. metal oxide semiconductor active layer; 211. source contact region; 212. drain contact region; 213. channel region; 22. gate dielectric layer; 23. gate; 30. barrier layer; 41. interlayer dielectric layer; 42. passivation layer; 421. via; 51. source electrode; 52. drain electrode; 61. dielectric layer; 62. barrier material layer; 171. first overlapping region; 271. second overlapping region;

[0081] 203', active layer; 204', dielectric layer; 205', gate; 206', source region; 207', drain region; 208', channel region. DETAILED DESCRIPTION

[0082] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0083] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0084] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0085] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0086] As described in the background technology, the reliability of oxide semiconductor thin film transistors in the prior art is poor. The resolution of display products is getting higher and higher, and the requirements for the screen pixel density (Pixels Per Inch, PPI) of display panels are getting higher and higher. The size of oxide semiconductor thin film transistors is constantly decreasing, and the difficulty of manufacturing oxide semiconductor thin film transistors is increasing, especially the size accuracy of the channel region is difficult to control, which affects the reliability of oxide semiconductor thin film transistors and product yield.

[0087] Related technology 1, as shown in FIG. 1 and FIG. 2, in the process of forming an oxide semiconductor thin film transistor, after forming the gate 205' of the transistor, the length L of the gate 205' is the designed length of the channel region 208', and the dielectric layer 204' below the gate 205' is etched with the gate 205' as a mask, and at the same time, the ion conductor active layer 203' of the etched dielectric layer 204' is used to form the source region 206' and the drain region 207'. However, in this process, the ions generated by the excited plasma collide and scatter with the atoms of the active layer 203', causing the source region 206' and the drain region 207' to extend to the active layer 203' below the gate 205', and the extension length is △L, resulting in a reduction in the effective length of the channel region 208' of the transistor, and the actual length L of the channel region 208' is △L. eff Less than the design length L. L eff =L-2△L.

[0088] In the same process, the length of △L is relatively fixed, usually 0.6um~1um. Therefore, the shorter the designed length L of the channel region 208' is, the more serious the adverse effect of △L on the transistor is. When the size of the transistor is reduced to a certain extent, that is, when preparing a short-channel transistor device, the actual length L of the actual channel region 208' is effIt will be much smaller than the designed length L, resulting in an unnecessary short channel effect, which is manifested in that the characteristic curve of the transistor device will be severely negatively biased or even completely turned on, thus losing its switching function.

[0089] Related technology 2, in the process of forming an oxide semiconductor thin film transistor, as shown in FIG. 3, after forming the gate 205' of the transistor, the length L of the gate 205' is the designed length of the channel region 208', and then the active layer 203' is conductively formed to form the source region 206' and the drain region 207' using the side wall of the gate 205' as the boundary by ion implantation. Ion implantation has a high degree of directional accuracy, and can reduce the length △L of the source region 206' and the drain region 207' extending to the active layer 203' below the gate 205' to 0, so that the actual length L of the channel region 208' eff Equal to the design length L, avoiding the short channel effect of the transistor.

[0090] However, ion implantation to conduct the active layer to form the source region 206' and the drain region 207' requires additional ion implantation equipment, which is costly. The applicable size of the ion implantation equipment is limited and cannot process the process of transistors with smaller sizes.

[0091] In view of this, the present application provides an array substrate and a method for manufacturing the same, by forming a barrier layer on the side wall of the gate and increasing the size of the gate dielectric layer formed by etching the dielectric layer, so that the source contact area and the drain contact area formed by the conductor-treated metal oxide semiconductor active layer extend to the bottom of the gate dielectric layer instead of extending to the bottom of the gate, thereby ensuring that the channel area has a larger size, which can reduce the short channel effect of the transistor and improve the switching performance of the transistor.

[0092] In the first aspect, the present application provides an array substrate, as shown in FIG. 4, the array substrate includes a base substrate 11 and a transistor 20 disposed on the base substrate 11. The base substrate 11 may be a transparent substrate, such as a glass substrate, or the base substrate 11 may be a semiconductor substrate, such as a silicon substrate. The base substrate 11 may be a flexible or rigid substrate. A plurality of transistors 20 arranged in an array are disposed on the base substrate 11, and the transistors 20 are metal oxide semiconductor transistors 20. It can be understood that an isolation buffer layer 12 is also provided on the base substrate 11 for isolating the transistor 20 from the base substrate 11, and the material of the isolation buffer layer 12 may include silicon oxide.

[0093] The transistor 20 includes a metal oxide semiconductor active layer 21, a gate dielectric layer 22, a gate 23 and a barrier layer 30; the metal oxide semiconductor active layer 21 is arranged on the base substrate 11, and the metal oxide semiconductor active layer 21 includes a channel region 213 and a source contact region 211 and a drain contact region 212 respectively arranged on both sides of the channel region 213; the gate dielectric layer 22 is arranged on the channel region 213, and the edges on both sides of the orthographic projection of the gate dielectric layer 22 on the base substrate 11 respectively have a first overlapping region 171 and a second overlapping region 271 with the orthographic projections of the source contact region 211 and the drain contact region 212 on the base substrate 11; the gate 23 is arranged on the gate dielectric layer 22, and the orthographic projection of the gate 23 on the base substrate 11 has no overlapping part with the orthographic projections of the source contact region 211 and the drain contact region 212 on the base substrate 11; the barrier layer 30 at least covers a part of the side wall of the gate 23.

[0094] In the above-mentioned array substrate, a gate 23 and a barrier layer 30 covering the side wall of the gate 23 are arranged on the gate dielectric layer 22, so that the size of the gate dielectric layer 22 is larger than the size of the gate 23, and the orthographic projection formed by the gate dielectric layer 22 on the base substrate 11 and the orthographic projection formed by the source contact area 211 and the drain contact area 212 on the base substrate 11 have a first overlapping area 171 and a second overlapping area 271, and the orthographic projection formed by the gate 23 on the base substrate 11 and the orthographic projection formed by the source contact area 211 and the drain contact area 212 on the base substrate 11 have no overlapping part, ensuring that the channel area 213 between the source contact area 211 and the drain contact area 212 has a larger size, which can reduce the short channel effect of the transistor 20 and improve the switching performance of the transistor 20.

[0095] In one embodiment, as shown in FIG. 4 , the size of the first overlapping area 171 in the horizontal direction X is not less than a preset value; the size of the second overlapping area 271 in the horizontal direction X is not less than a preset value.

[0096] It should be noted that the horizontal direction X refers to a direction parallel to the array substrate 11 .

[0097] It should be noted that the preset value is the length of the source contact region 211 and the drain contact region 212 extending toward the inner side of the gate 23 in actual production.

[0098] Preferably, the preset value ranges from 0.6 μm to 1 μm. For example, the size of the first overlapping area 171 and the second overlapping area 271 in the horizontal direction X may be 1.1 μm, 1.2 μm, 1.3 μm, or 1.4 μm.

[0099] It can be understood that the preset value is used to compensate for the length of the source contact area 211 and the drain contact area 212 diffusing and extending below the gate 23. The inventor of the present application has conducted multiple experiments and found that the length of the source contact area 211 and the drain contact area 212 diffusing and extending below the gate 23 is relatively fixed, usually 0.6um~1um. In this embodiment, the size of the first overlapping area 171 and the second overlapping area 271 in the horizontal direction X is set to be not less than the preset value, and the first overlapping area 171 and the second overlapping area 271 are used to compensate for the length of the source contact area 211 and the drain contact area 212 extending to the gate 23, so as to increase the size of the channel area 213, reduce the short channel effect of the transistor 20, and improve the switching performance of the transistor 20.

[0100] In one embodiment, as shown in FIG. 4 , along the horizontal direction X, the maximum dimension of the gate 23 has a first dimension L, and the maximum dimension of the barrier layer 30 has a second dimension L2.

[0101] The first overlapping region 171 has a third size ΔL; the second overlapping region 271 has a third size ΔL; the channel region 213 has a fourth size L eff .

[0102] It can be understood that the first dimension L of the gate 23 is the designed length of the channel region 213. The fourth dimension L of the channel region 213 is eff is the actual effective length of the channel region 213.

[0103] The gate 23 and the barrier layer 30 are disposed on the gate dielectric layer 22. The barrier layer 30 is disposed on both sidewalls of the gate 23. Thus, the horizontal dimension L1 of the gate dielectric layer 22 is L+2L2. eff +2ΔL. Therefore, the closer the second dimension L2 is to the third dimension ΔL, the greater the actual effective length L of the channel region 213 is. eff The closer the length L is to the design length L of the channel region 213 , the higher the dimensional accuracy of the channel region 213 .

[0104] In some embodiments, as shown in FIG. 4 , the third dimension ΔL is equal to the second dimension L2, and the fourth dimension L eff It is equal to the first dimension L. The orthographic projection of the barrier layer 30 on the base substrate 11 overlaps with the first overlapping region 171 and the second overlapping region 271 .

[0105] Thus, the actual effective length L of the channel region 213 is effThe channel region 213 of the transistor 20 has a high dimensional accuracy, which is the same as the design length L of the channel region 213. The size of the channel region 213 is consistent with the design size, avoiding the problem of the small size of the channel region 213 caused by the extension of the source contact region 211 and the drain contact region 212 below the gate dielectric layer 22, avoiding the short channel effect from having an adverse effect on the transistor 20, improving the switching performance of the transistor 20, and improving the yield rate of the array substrate.

[0106] In one embodiment, the sidewall of the gate 23 is an inclined surface, and there is a first angle α1 between the sidewall of the gate 23 and the top surface of the gate 23 (refer to FIG. 7 ), and the first angle α1 is 75°-80°. For example, the first angle α1 can be 75°, 76°, 77°, 78°, 79° or 80. In this way, by designing the sidewall of the gate 23 to be an inclined surface, a barrier layer 30 is set on the sidewall of the gate 23, and the size of the first overlapping area 171 and the second overlapping area 271 is defined by the barrier layer 30, and the size of the channel area 213 is accurately defined by the size of the gate 23, ensuring that the channel area 213 has high dimensional accuracy, which is suitable for transistors 20 with smaller channel lengths, and can effectively avoid the problem of failure of switching performance of transistors 20 with small-sized channels caused by short channel effects.

[0107] In one embodiment, referring to FIG. 4 , there is a second angle α2 between the side wall of the gate 23 and the top surface of the gate 23 , and the second angle α2 is less than the first angle α1. For example, the second angle α2 may be 30°-75°. For example, the second angle α2 may be 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70° or 75. In this way, the angle between the side wall of the gate 23 and the top surface of the gate 23 is smaller, and the connection between the side wall of the gate 23 and the top surface of the gate 23 is smoother, which can avoid the charge accumulation at the angle between the side wall of the gate 23 and the top surface of the gate 23, which is beneficial to improve the electrical performance of the transistor 20.

[0108] In one embodiment, referring to FIG. 4 , the sidewall of the gate 23 includes a first inclined surface and a second inclined surface sequentially connected in a direction away from the substrate 11, and the second inclined surface is connected to the top surface of the gate 23 and has a second angle α2 with the top surface of the gate 23. The barrier layer 30 only covers the first inclined surface, and the second inclined surface is connected to the top surface of the gate 23, so that the charge can be prevented from accumulating at the angle between the sidewall of the gate 23 and the top surface of the gate 23, which is beneficial to improving the electrical performance of the transistor 20.

[0109] In one embodiment, referring to FIG. 4 , the array substrate further includes an interlayer dielectric layer 41 covering the metal oxide semiconductor active layer 21 , the gate 23 and the barrier layer 30 , and the top surface of the interlayer dielectric layer 41 is higher than the top surface of the gate 23 .

[0110] The interlayer dielectric layer 41 may be a single layer or a multi-layer structure. For example, the interlayer dielectric layer 41 may include multiple insulating film layers stacked in sequence. The material of the interlayer dielectric layer 41 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0111] 4 , the transistor 20 further includes a source electrode 51 and a drain electrode 52. The source electrode 51 penetrates the interlayer dielectric layer 41 and contacts and connects with the source contact region 211; the drain electrode 52 penetrates the interlayer dielectric layer 41 and contacts and connects with the drain contact region 212. The source electrode 51 and the drain electrode 52 are respectively in contact and connected with the source contact region 211 and the drain contact region 212, so as to lead out the source contact region 211 and the drain contact region 212 of the transistor 20, so as to facilitate the wiring of the array substrate and connect the source electrode 51 and the drain electrode 52 with other devices or structures.

[0112] The source electrode 51 and the drain electrode 52 may be made of a conductive metal. For example, the source electrode 51 and the drain electrode 52 may be made of at least one of Ti, Al, Mo, and Cu.

[0113] In one embodiment, referring to FIG. 4 , the array substrate further includes a passivation layer 42 disposed on the interlayer dielectric layer 41, and the passivation layer 42 is provided with a via 421, and the via 421 is correspondingly disposed on the source electrode 51 and the drain electrode 52, and the via 421 exposes the top surface of the source electrode 51 and the drain electrode 52. In this way, the source electrode 51 and the drain electrode 52 can be wired through the via 421, for example, the source electrode 51 and the drain electrode 52 can be connected to the signal line through the via 421, thereby reducing the wiring difficulty.

[0114] Based on the same inventive concept, an embodiment of the present application provides a method for preparing an array substrate. As shown in FIG5 , the method for preparing the array substrate includes the following steps:

[0115] Step S11: providing a substrate 11;

[0116] Step S12: forming a metal oxide semiconductor active layer 21 on the base substrate 11;

[0117] Step S13: sequentially forming a dielectric layer and a metal layer covering the metal oxide semiconductor active layer 21;

[0118] Step S14: etching the metal layer to form a gate 23 of the transistor 20 on the metal oxide semiconductor active layer 21;

[0119] Step S15: forming a barrier layer 30 covering the sidewall of the gate 23;

[0120] Step S16: using the gate 23 and the barrier layer 30 as masks, etching the dielectric layer to form a gate dielectric layer 22, and conducting the metal oxide semiconductor active layer 21 to form a source contact region 211 and a drain contact region 212, the metal oxide semiconductor active layer 21 between the source contact region 211 and the drain contact region 212 forms a channel region 213 of the transistor 20. The edges of the orthographic projection of the gate dielectric layer 22 formed on the substrate 11 respectively overlap with the orthographic projections of the source contact region 211 and the drain contact region 212 on the substrate 11 in a first overlapping region 171 and a second overlapping region 271, and the orthographic projection of the gate 23 formed on the substrate 11 has no overlapping portion with the orthographic projections of the source contact region 211 and the drain contact region 212 on the substrate 11.

[0121] In step S11, as shown in Fig. 6, the base substrate 11 may be a transparent substrate, such as a glass substrate, or the base substrate 11 may be a semiconductor substrate, such as a silicon substrate. The base substrate 11 may be a flexible or rigid substrate.

[0122] In this embodiment, after providing the base substrate 11, a chemical vapor deposition process (CVD) is used to deposit an isolation buffer layer 12 on the base substrate 11. The isolation buffer layer 12 may be a single layer or a multi-layer structure, and the isolation buffer layer 12 may include a single layer of SiOx, SiNx, or SiON, or a stacked combination of these films. The thickness of the isolation buffer layer 12 may be 2000A to 3000A.

[0123] In step S12, a metal oxide semiconductor layer (not shown) is deposited on the isolation buffer layer 12 by chemical vapor deposition, and the thickness of the metal oxide semiconductor layer is 300A-500A. The material of the metal oxide semiconductor layer may include at least one of IGZO, ILZO, ITZO, and ITGO.

[0124] Then, referring to FIG. 6 , the metal oxide semiconductor layer is pattern-etched to form a metal oxide semiconductor active layer 21 of a plurality of transistors 20 arranged in an array on the base substrate 11 .

[0125] In step S13, first, referring to Fig. 7, a chemical vapor deposition process is used to deposit and form a dielectric layer 61. In this embodiment, the thickness of the dielectric layer 61 is 1200 Å-1400 Å, and the material of the dielectric layer includes SiOx.

[0126] Then, a physical vapor deposition process (PVD) is used to deposit a metal layer (not shown in the figure), and the metal layer may be a single layer structure or a stacked layer structure. For example, the metal layer may include a single layer or multiple layers of metal materials such as Ti, Al, Mo, and Cu.

[0127] In step S14, referring to FIG7 , the metal layer is patterned and etched to form a gate 23 of the transistor 20 on each metal oxide semiconductor active layer 21 . The horizontal dimension of the gate 23 of the transistor 20 is used to define the design length of the channel region 213 .

[0128] In step S15 , referring to FIG. 9 , a barrier layer 30 covering the sidewall of the gate 23 may be formed by a combination of deposition and etching processes to increase the horizontal dimension defined by the gate 23 and the barrier layer 30 .

[0129] In step S16, referring to FIG. 10, the dielectric layer 61 below the gate 23 is etched using the gate 23 and the barrier layer 30 as masks, and the plasma used to etch the dielectric layer 61 is used to conduct the metal oxide semiconductor active layer 21 to form a source contact region 211 and a drain contact region 212. The metal oxide semiconductor active layer 21 between the source contact region 211 and the drain contact region 212 is a channel region 213, and the actual length of the channel region 213 is.

[0130] In the process of etching the dielectric layer 61 and the conductive metal oxide semiconductor active layer 21 below the gate 23, the plasma generated by the excited plasma collides and scatters with the atoms of the metal oxide semiconductor active layer 21, causing the source contact region 211 and the drain contact region 212 to extend below the gate dielectric layer 22. As a result, the edges of the two sides of the orthographic projection of the gate dielectric layer 22 on the substrate 11 respectively overlap with the orthographic projections of the source contact region 211 and the drain contact region 212 on the substrate 11 in a first overlapping region 171 and a second overlapping region 271. Since the size of the mask formed by the gate 23 and the barrier layer 30 is larger than the size of the gate 23, the length of the source contact region 211 and the drain contact region 212 extending to the gate dielectric layer 22 is less than or equal to the size of the barrier layer 30, the orthographic projections of the source contact region 211 and the drain contact region 212 on the substrate 11 have no overlapping area with the orthographic projection of the gate 23 on the substrate 11, and the actual effective size of the channel region 213 between the source contact region 211 and the drain contact region 212 is close to the designed size.

[0131] The method for preparing the above-mentioned array substrate forms a barrier layer 30 on the side wall of the gate electrode 23, increases the size of the gate dielectric layer 22 formed by etching the dielectric layer, so that the source contact area 211 and the drain contact area 212 formed by the conductor-treated metal oxide semiconductor active layer 21 extend to the bottom of the gate dielectric layer 22 instead of extending to the bottom of the gate electrode 23, thereby ensuring that the channel area 213 has a larger size, which can reduce the short channel effect of the transistor 20 and improve the switching performance of the transistor 20.

[0132] In one embodiment, referring to FIG. 7 , the sidewall of the gate 23 is an inclined surface, and the maximum dimension of the gate 23 along the horizontal direction X has a first dimension L. In the process of etching the metal layer to form the gate 23 of the transistor 20 , the parameters and conditions of the etching process are controlled so that the dimension of the gate 23 along the horizontal direction X gradually decreases in the direction away from the substrate 11 , and the sidewall of the gate 23 forms an inclined surface, so as to form a barrier layer 30 on the sidewall of the gate 23 .

[0133] The maximum dimension of the gate 23 along the horizontal direction X has a first dimension L. It can be understood that the first dimension L is the designed length of the channel region 213 .

[0134] In one embodiment, referring to FIG. 7 , there is a first angle α1 between the sidewall of the gate 23 and the top surface of the gate 23 , and the first angle α1 is 75°-80°. For example, the first angle α1 can be 75°, 76°, 77°, 78°, 79° or 80°. In this way, by designing the sidewall of the gate 23 to be an inclined surface, a barrier layer 30 is set on the sidewall of the gate 23, and the size of the first overlapping area 171 and the second overlapping area 271 is defined by the barrier layer 30, and the size of the channel area 213 is precisely defined by the size of the gate 23, ensuring that the channel area 213 has high dimensional accuracy, which is suitable for transistors 20 with smaller channel lengths, and can effectively avoid the problem of failure of the switching performance of transistors 20 with small-sized channels caused by the short channel effect.

[0135] In one embodiment, step S15 forms a barrier layer 30 covering the sidewall of the gate 23, including:

[0136] Step S151: using a chemical vapor deposition process to deposit a barrier material layer 62 covering the gate 23, wherein the thickness of the barrier material layer 62 on the sidewall of the gate 23 is greater than the thickness of the barrier material layer 62 in other areas;

[0137] Step S152 : etching the barrier material layer 62 with the gate 23 as the stop layer to expose the top surface of the gate 23 and the top surface of the dielectric layer, and a portion of the barrier material layer 62 covering the sidewall of the gate 23 is etched away to form a barrier layer 30 .

[0138] In step S151, referring to FIG7 and FIG8, a chemical vapor deposition process is used to deposit and form a barrier material layer 62, and the barrier material layer 62 may include a single layer or a stacked layer of SiOx or SiON. The barrier material layer 62 forms good step coverage at the top surface and the steps of the side walls of the gate 23, and the thickness of the barrier material layer 62 is adjusted by adjusting the deposition parameters and conditions so that its lateral width at the step is the second size L2.

[0139] The second dimension L2 of the barrier material layer 62 is used to compensate for the length of the subsequent source contact region 211 and the drain contact region 212 diffusing and extending below the gate 23. Since the length of the source contact region 211 and the drain contact region 212 diffusing and extending below the gate 23 is relatively fixed, usually 0.6um~1um, in this embodiment, the thickness of the barrier material layer 62 is adjusted by adjusting the deposition parameters and conditions so that its second lateral dimension L2 at the step is 0.6um~1um.

[0140] In step S152, referring to FIG8 and FIG9, an anisotropic dry process is used to etch the barrier material layer 62. The etching rate of the etching process in the direction perpendicular to the substrate 11 is much greater than the etching rate in the direction parallel to the substrate 11. The etching is stopped after the top surface of the gate 23 is exposed. The barrier material layer 62 on the top surface of the gate 23 and the barrier layer 30 material layer on the dielectric layer are all etched away. Since the etching rate in the direction parallel to the substrate 11 is relatively low, the barrier material layer 62 covering the side wall of the gate 23 is etched and retained to form the barrier layer 30.

[0141] In this embodiment, the horizontal dimension of the barrier layer 30 gradually decreases in a direction away from the base substrate 11 , and the maximum dimension of the barrier layer 30 in the horizontal direction X has a second dimension L2 , and the second dimension L2 is 0.6 um-1 um.

[0142] In this way, the barrier material layer 62 is etched with the gate 23 as a stop layer, and there is no need to perform a coating and exposure process, and no need to add a mask process. The barrier material layer 62 can be etched to obtain the barrier layer 30 covering the side wall of the gate 23, which is beneficial to the control of production costs.

[0143] In one embodiment, step S16 is to etch the dielectric layer 61 using the gate 23 and the barrier layer 30 as a mask to form the gate dielectric layer 22, and to perform conductor processing on the metal oxide semiconductor active layer 21 to form the source contact region 211 and the drain contact region 212, including:

[0144] Step S161: etching and removing the dielectric layer exposed by the gate 23 and the barrier layer 30 to form a gate dielectric layer 22;

[0145] Step S162 : doping conductive ions into the metal oxide semiconductor active layer 21 on both sides of the gate dielectric layer 22 to form a source contact region 211 and a drain contact region 212 , respectively. The source contact region 211 and the drain contact region 212 extend below the gate dielectric layer 22 .

[0146] In this embodiment, referring to FIGS. 9 and 10 , at least one of bromine plasma Ar+, fluorine plasma F+ or helium plasma He+ is used to etch the dielectric layer and to conduct the metal oxide semiconductor active layer 21.

[0147] Due to the collision and scattering of Ar+, F+, He+ ions with atoms in the metal oxide semiconductor active layer 21, Ar+, F+, He+ ions are injected into the metal oxide semiconductor active layer 21 below the gate dielectric layer 22, and the source contact region 211 and the drain contact region 212 extend to below the gate dielectric layer 22. The edges on both sides of the orthographic projection of the gate dielectric layer 22 on the substrate 11 respectively overlap with the orthographic projections of the source contact region 211 and the drain contact region 212 on the substrate 11 in a first overlapping region 171 and a second overlapping region 271.

[0148] Along the horizontal direction X, the first overlapping region 171 has a third size ΔL; the second overlapping region 271 has a third size ΔL; and the channel region 213 has a fourth size L eff . Fourth size L eff is the actual size of the channel region 213. The third size ΔL is equal to the second size L2, and the fourth size L eff is equal to the first size L; wherein the third size is not less than a preset value.

[0149] The preset value is the length of the source contact region 211 and the drain contact region 212 extending toward the inner side of the gate 23 in actual production.

[0150] In one embodiment, the preset value ranges from 0.6 μm to 1 μm.

[0151] Due to the size compensation of the barrier layer 30 during the process of conducting the metal oxide semiconductor active layer 21, the first overlapping region 171 and the second overlapping region 271 are both located below the barrier layer 30. The actual length L of the channel region 213 is eff Close to the design length L.

[0152] Further, referring to FIG. 10 , the gate 23 and the barrier layer 30 are disposed on the gate dielectric layer 22, and the barrier layer 30 is disposed on both sidewalls of the gate 23, so that the horizontal dimension L1 of the gate dielectric layer 22 is L1=L+2L2. eff +2ΔL. Therefore, the closer the second dimension L2 is to the third dimension ΔL, the greater the actual effective length L of the channel region 213 is. eff The closer the length L is to the design length L of the channel region 213 , the higher the dimensional accuracy of the channel region 213 .

[0153] In this way, the dielectric layer is etched using the gate 23 and the barrier layer 30 as masks and the metal oxide semiconductor active layer 21 is conductorized so that the first overlapping region 171 and the second overlapping region 271 are located below the barrier layer 30, ensuring that the metal oxide semiconductor active layer 21 located below the gate 23 forms a channel region 213, ensuring that the channel region 213 has high dimensional accuracy, is suitable for transistors 20 with smaller channel lengths, and can effectively avoid the problem of switching performance failure of transistors 20 with small-size channels caused by short channel effects.

[0154] In one embodiment, referring to FIG. 10 , the orthographic projection of the barrier layer 30 on the base substrate 11 overlaps with the first overlapping region 171 and the second overlapping region 271 .

[0155] Thus, the actual effective length L of the channel region 213 is eff The channel region 213 of the transistor 20 has a high dimensional accuracy, which is the same as the design length L of the channel region 213. The size of the channel region 213 is consistent with the design size, avoiding the problem of the small size of the channel region 213 caused by the extension of the source contact region 211 and the drain contact region 212 below the gate dielectric layer 22, avoiding the short channel effect from having an adverse effect on the transistor 20, improving the switching performance of the transistor 20, and improving the yield rate of the array substrate.

[0156] In one embodiment, referring to FIG. 9 and FIG. 10, in the process of etching the dielectric layer to form the gate dielectric layer 22 using the gate 23 and the barrier layer 30 as a mask, part of the barrier layer 30 and part of the gate 23 covered by the barrier layer 30 are etched away, and after etching, a second angle α2 is provided between the side wall of the gate 23 and the top surface of the gate 23, and the second angle α2 is smaller than the first angle α1.

[0157] For example, the second angle α2 may be 30°-75°. For example, the second angle α2 may be 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70° or 75. In this way, the angle between the side wall of the gate 23 and the top surface of the gate 23 is reduced, and the connection between the side wall of the gate 23 and the top surface of the gate 23 is smoother, which can avoid the charge accumulation at the angle between the side wall of the gate 23 and the top surface of the gate 23, which is beneficial to improve the electrical performance of the transistor 20.

[0158] In one embodiment, referring to FIG. 10 , the sidewall of the gate 23 after etching includes a first inclined surface and a second inclined surface sequentially connected in a direction away from the substrate 11 , and the second inclined surface is connected to the top surface of the gate 23 and has a second angle α2 with the top surface of the gate 23 .

[0159] During the process of etching the dielectric layer, the top barrier layer 30 and the portion of the gate 23 covered by the top barrier layer 30 are etched away, and the side wall of the gate 23 forms a first inclined surface and a second inclined surface sequentially connected in a direction away from the substrate 11, thereby reducing the angle between the side wall of the gate 23 and the top surface of the gate 23, and the connection between the side wall of the gate 23 and the top surface of the gate 23 is smoother; at the same time, the bottom barrier layer 30 arranged close to the substrate 11 is etched and retained to compensate for the length of the source contact area 211 and the drain contact area 212 extending below the gate dielectric layer 22.

[0160] In one embodiment, after step S16, the preparation method further includes:

[0161] Step S17: forming an interlayer dielectric layer 41, wherein the interlayer dielectric layer 41 covers the metal oxide semiconductor active layer 21, the gate 23 and the barrier layer 30, and the top surface of the interlayer dielectric layer 41 is higher than the top surface of the gate 23;

[0162] Step S18 : forming a source electrode 51 and a drain electrode 52 penetrating the interlayer dielectric layer 41 , wherein the source electrode 51 is in contact with and connected to the source contact region 211 , and the drain electrode 52 is in contact with and connected to the drain contact region 212 .

[0163] In step S17, referring to Fig. 4, a chemical vapor deposition process is used to deposit and form an interlayer dielectric layer 41, and the thickness of the interlayer dielectric layer 41 is 5000 Å-6000 Å. The interlayer dielectric layer 41 can be a single layer or a stacked layer film of SiOx, SiNx or SiON.

[0164] When chemical vapor deposition is used to deposit SiOx, SiNx, and SiON film layers, gases such as SiH4 and NH3 are usually required as reactants. A large amount of H+ will be generated during the reaction. Under high temperature conditions, these H+ may diffuse into the channel region 213 as impurity elements and affect the electrical properties of the channel region 213, causing the size of the channel region 213 to decrease.

[0165] In the present application, referring to FIG. 4 , after the barrier layer 30 is added to the sidewall of the gate 23, the barrier layer 30 blocks the H+ generated during the deposition of the interlayer dielectric layer 41 from diffusing to the channel region 213, thereby preventing the H+ diffusion from affecting the electrical properties and size of the channel region 213, so that the actual effective length L of the channel region 213 is eff The channel region 213 of the transistor 20 has a high dimensional accuracy, which is the same as the designed length L of the channel region 213 .

[0166] In step S18 , first, referring to FIG. 4 , the interlayer dielectric layer 41 is patterned and etched to form through holes penetrating the interlayer dielectric layer 41 on the source contact region 211 and the drain contact region 212 .

[0167] Then, referring to FIG. 4 , a conductive metal is deposited to fill the through hole of the interlayer dielectric layer 41 by a physical vapor deposition process to form a source electrode 51 and a drain electrode 52 penetrating the interlayer dielectric layer 41 , and the source electrode 51 and the drain electrode 52 are respectively in contact with the source contact region 211 and the drain contact region 212 .

[0168] The material of the source electrode 51 and the drain electrode 52 may include at least one of Ti, Al, Mo, and Cu.

[0169] In this way, the source contact region 211 and the drain contact region 212 of the transistor 20 are led out by forming the source electrode 51 and the drain electrode 52 to facilitate wiring of the array substrate and connect the source electrode 51 and the drain electrode 52 to other devices or structures.

[0170] In one embodiment, after step S18, the preparation method further comprises:

[0171] Step S19: forming a passivation layer 42 on the interlayer dielectric layer 41; the passivation layer 42 is formed by deposition using a chemical vapor deposition process, the thickness of the passivation layer 42 is 2000A~5000A, and the passivation layer 42 includes a single layer or a stacked film of SiOx, SiNx or SiON.

[0172] Step S20: patterning the passivation layer 42, forming via holes 421 on the source electrode 51 and the drain electrode 52, respectively, and exposing the top surfaces of the source electrode 51 and the drain electrode 52 through the via holes 421. In this way, the source electrode 51 and the drain electrode 52 can be wired through the via holes 421, for example, the source electrode 51 and the drain electrode 52 can be connected to the signal line through the via holes 421, reducing the wiring difficulty.

[0173] In the method for preparing the array substrate of the present embodiment, a barrier layer 30 is formed on the side wall of the gate electrode 23. The barrier layer 30 and the gate electrode 23 are used together as a mask to conduct the metal oxide semiconductor active layer 21 to form a source contact area 211 and a drain contact area 212. The horizontal size of the barrier layer 30 compensates for the extension length of the source contact area 211 and the drain contact area 212 below the gate electrode 23, so that the actual length of the channel area 213 is the same as the designed length. The channel area 213 has high dimensional accuracy. The barrier layer 30 can prevent the H+ diffusion in the process of depositing the interlayer dielectric layer 41 from affecting the electrical properties and size of the channel area 213, thereby ensuring the actual effective length L of the channel area 213. eff The length L is the same as the designed length of the channel region 213, and is suitable for preparing a metal oxide semiconductor TFT device with a shorter channel region 213 length; at the same time, the preparation method of the array substrate of this embodiment has a simple manufacturing process and low manufacturing cost.

[0174] Based on the description of the above embodiments, more specific embodiments are proposed below for detailed description.

[0175] 11 , the method for preparing the array substrate of this embodiment includes:

[0176] Step S101: providing a base substrate 11;

[0177] Step S102: forming a metal oxide semiconductor active layer 21 on the base substrate 11;

[0178] Step S103: sequentially forming a dielectric layer and a metal layer covering the metal oxide semiconductor active layer 21;

[0179] Step S104: etching the metal layer to form a gate 23 of the transistor 20 on the metal oxide semiconductor active layer 21, wherein the sidewall of the gate 23 is an inclined surface, the maximum dimension of the gate 23 along the horizontal direction X has a first dimension L, and a first angle α1 is formed between the sidewall of the gate 23 and the top surface of the gate 23, and the first angle α1 is 75°-80°;

[0180] Step S105: depositing and forming a barrier material layer 62 covering the gate 23, wherein the thickness of the barrier material layer 62 on the sidewall of the gate 23 is greater than the thickness of the barrier material layer 62 in other regions;

[0181] Step S106: etching the barrier material layer 62 with the gate 23 as a stop layer, exposing the top surface of the gate 23 and the top surface of the dielectric layer, and a portion of the barrier material layer 62 covering the sidewall of the gate 23 is etched away to form a barrier layer 30, wherein the maximum dimension of the barrier layer 30 along the horizontal direction X has a second dimension L2, and the second dimension L2 is 0.6 um to 1 um;

[0182] Step S107: using the gate 23 and the barrier layer 30 as masks, etching the dielectric layer to form a gate dielectric layer 22, and conducting the metal oxide semiconductor active layer 21 to form a source contact region 211 and a drain contact region 212, the metal oxide semiconductor active layer 21 between the source contact region 211 and the drain contact region 212 forms a channel region 213 of the transistor 20; the edges on both sides of the orthographic projection of the gate dielectric layer 22 formed on the substrate 11 respectively overlap with the orthographic projections of the source contact region 211 and the drain contact region 212 formed on the substrate 11 in a first overlapping region 171 and a second overlapping region 271, the first overlapping region 171 and the second overlapping region 271 have a third size △L, and the channel region 213 has a fourth size L eff， The third dimension △L is equal to the second dimension L2;

[0183] Step S108: forming an interlayer dielectric layer 41, wherein the interlayer dielectric layer 41 covers the metal oxide semiconductor active layer 21, the gate 23 and the barrier layer 30, and the top surface of the interlayer dielectric layer 41 is higher than the top surface of the gate 23;

[0184] Step S109: forming a source electrode 51 and a drain electrode 52 penetrating the interlayer dielectric layer 41 , wherein the source electrode 51 is in contact with and connected to the source contact region 211 , and the drain electrode 52 is in contact with and connected to the drain contact region 212 ;

[0185] Step S110: forming a passivation layer 42 on the interlayer dielectric layer 41;

[0186] Step S111 : patterning the passivation layer 42 , forming via holes 421 on the source electrode 51 and the drain electrode 52 , respectively, wherein the via holes 421 expose the top surfaces of the source electrode 51 and the drain electrode 52 .

[0187] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0188] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An array substrate, characterized in that: include: substrate substrate; A transistor disposed on the substrate, the transistor comprising: A metal oxide semiconductor active layer is disposed on the substrate, wherein the metal oxide semiconductor active layer comprises a channel region and a source contact region and a drain contact region respectively disposed on both sides of the channel region; A gate dielectric layer is disposed on the channel region, and two side edges of an orthographic projection of the gate dielectric layer formed on the substrate have a first overlapping region and a second overlapping region with the orthographic projections of the source contact region and the drain contact region formed on the substrate, respectively; A gate is arranged on the gate dielectric layer, and an orthographic projection of the gate on the substrate has no overlapping part with an orthographic projection of the source contact region and the drain contact region on the substrate; The barrier layer at least covers a portion of the sidewall of the gate.

2. The array substrate according to claim 1, characterized in that: The size of the first overlapping area in the horizontal direction is not less than a preset value; the size of the second overlapping area in the horizontal direction is not less than the preset value; Preferably, the preset value ranges from 0.6 μm to 1 μm; Preferably, along the horizontal direction, the maximum size of the gate has a first size, the maximum size of the blocking layer has a second size; the first overlapping area has a third size; the second overlapping area has the third size; and the channel region has a fourth size; The third size is equal to the second size, and the fourth size is equal to the first size; Preferably, the orthographic projection of the barrier layer on the base substrate coincides with the first overlapping region and the second overlapping region.

3. The array substrate according to claim 1, characterized in that: The side wall of the gate is an inclined surface, and a first angle is formed between the side wall of the gate and the top surface of the gate, and the first angle is 75°-80°; Preferably, a second angle is formed between the side wall of the gate and the top surface of the gate, and the second angle is smaller than the first angle; Preferably, the side wall of the gate comprises a first inclined surface and a second inclined surface which are connected in sequence along a direction away from the base substrate, and the second inclined surface is connected to the top surface of the gate and has the second included angle with the top surface of the gate.

4. The array substrate according to claim 1, characterized in that: The array substrate further includes: an interlayer dielectric layer, covering the metal oxide semiconductor active layer, the gate and the barrier layer, wherein a top surface of the interlayer dielectric layer is higher than a top surface of the gate; The transistor further comprises: A source electrode, penetrating through the interlayer dielectric layer and contacting and connecting with the source contact region; A drain electrode, penetrating through the interlayer dielectric layer and contacting and connecting with the drain contact region; Preferably, the array substrate further includes: A passivation layer is disposed on the interlayer dielectric layer. The passivation layer is provided with vias. The vias are correspondingly disposed on the source electrode and the drain electrode. The vias expose the top surfaces of the source electrode and the drain electrode.

5. A method for preparing an array substrate, characterized in that: include: providing a substrate base plate; forming a metal oxide semiconductor active layer on the substrate; sequentially forming a dielectric layer and a metal layer covering the metal oxide semiconductor active layer; Etching the metal layer to form a gate of a transistor on the metal oxide semiconductor active layer; forming a barrier layer covering a sidewall of the gate; The dielectric layer is etched using the gate electrode and the barrier layer as masks to form a gate dielectric layer, and the metal oxide semiconductor active layer is subjected to conductor processing to form a source contact region and a drain contact region, wherein the metal oxide semiconductor active layer between the source contact region and the drain contact region forms a channel region of the transistor; Among them, the two side edges of the orthographic projection formed by the gate dielectric layer on the substrate have a first overlapping area and a second overlapping area with the orthographic projections formed by the source contact area and the drain contact area on the substrate, respectively, and the orthographic projection formed by the gate on the substrate has no overlapping part with the orthographic projections formed by the source contact area and the drain contact area on the substrate.

6. The method for preparing an array substrate according to claim 5, characterized in that: The sidewall of the gate is an inclined surface, and the maximum dimension of the gate along the horizontal direction has a first dimension; Preferably, a first angle is formed between the side wall of the gate and the top surface of the gate, and the first angle is 75°-80°.

7. The method for preparing an array substrate according to claim 6, characterized in that: forming a barrier layer covering a sidewall of the gate, comprising: A barrier material layer covering the gate is formed by depositing using a chemical vapor deposition process, wherein the thickness of the barrier material layer on the sidewall of the gate is greater than the thickness of the barrier material layer in other areas; The barrier material layer is etched with the gate as a stop layer to expose the top surface of the gate and the top surface of the dielectric layer, and a portion of the barrier material layer covering the side wall of the gate is etched away to form the barrier layer; Preferably, the barrier material layer is etched using an anisotropic dry process; Preferably, the maximum dimension of the barrier layer in the horizontal direction has a second dimension.

8. The method for preparing an array substrate according to claim 7, characterized in that: The gate and the barrier layer are used as masks to etch the dielectric layer to form a gate dielectric layer, and the metal oxide semiconductor active layer is subjected to conductor processing to form a source contact region and a drain contact region, including: Etching and removing the dielectric layer exposed by the gate and the barrier layer to form the gate dielectric layer; Doping conductive ions into the metal oxide semiconductor active layer on both sides of the gate dielectric layer to form the source contact region and the drain contact region, respectively, wherein the source contact region and the drain contact region extend below the gate dielectric layer respectively; Preferably, at least one of bromine plasma, fluorine plasma or helium plasma is used to etch the dielectric layer and to conduct the metal oxide semiconductor active layer; Preferably, along the horizontal direction, the first overlapping area has a third size, the second overlapping area has the third size, and the channel area has a fourth size; the third size is equal to the second size, and the fourth size is equal to the first size; wherein the third size is not less than a preset value; Preferably, the preset value ranges from 0.6 μm to 1 μm; Preferably, the orthographic projection of the barrier layer on the base substrate coincides with the first overlapping region and the second overlapping region.

9. The method for preparing an array substrate according to claim 6, characterized in that: In the process of etching the dielectric layer to form a gate dielectric layer using the gate and the barrier layer as masks, part of the barrier layer and part of the gate covered by the barrier layer are removed by etching, and after etching, a second angle is formed between the side wall of the gate and the top surface of the gate, and the second angle is smaller than the first angle; Preferably, after etching, the side wall of the gate comprises a first inclined surface and a second inclined surface sequentially connected in a direction away from the substrate, and the second inclined surface is connected to the top surface of the gate and has the second angle with the top surface of the gate.

10. The method for preparing an array substrate according to any one of claims 5 to 9, characterized in that: The preparation method further comprises: forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the metal oxide semiconductor active layer, the gate and the barrier layer, and the top surface of the interlayer dielectric layer is higher than the top surface of the gate; forming a source electrode and a drain electrode penetrating the interlayer dielectric layer, wherein the source electrode is in contact with the source contact region, and the drain electrode is in contact with the drain contact region; Preferably, the preparation method further comprises: forming a passivation layer on the interlayer dielectric layer; The passivation layer is patterned, and via holes are formed on the source electrode and the drain electrode respectively, wherein the via holes expose the top surfaces of the source electrode and the drain electrode.

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