BUS management method

Abstract

The invention relates to a BUS bus management method, which is characterized in that at least two groups of capacitor banks connected in series are connected between positive and negative electrode lines of a BUS bus, a push-pull circuit is arranged between two adjacent capacitor banks, and half-bus voltage is acquired through a partial voltage acquisition module; comparing the voltage at the two ends of the half-bus capacitor with the acquired half-bus voltage to obtain a voltage difference between the two voltages, if the voltage difference between the base electrode of the positive bus transistor and the midpoint of the two capacitor banks is greater than a threshold voltage, conducting the positive bus transistor, and discharging the positive bus capacitor bank through a voltage-sharing resistor; and if the voltage difference between the midpoint of the two capacitor banks and the base electrode of the negative bus transistor is greater than the threshold voltage, the negative bus transistor is conducted, and the negative bus capacitor bank is discharged through the voltage-sharing resistor. According to the invention, discharging of the bus capacitor can be realized, then dynamic voltage-sharing processing of the bus capacitor is realized, the voltage-sharing effect is good, and the safety and reliability of equipment work are improved.

Description

Technical Field

[0001] The invention relates to the technical field of safety circuits, and in particular to a method for managing a BUS busbar. Background Art

[0002] In multi-level circuits, half-bridge circuits or high-voltage circuits, capacitors of the same specification and capacitance are often used in series to divide the bus voltage of the BUS bus. However, in actual situations, due to the differentiation of electrolytic capacitors in the production process, the electrical parameters of each electrolytic capacitor cannot be completely consistent when leaving the factory, resulting in certain differences in capacitance, equivalent series resistance and leakage current of capacitors of the same specification, resulting in the bus voltage cannot be completely divided. If the voltage unevenness causes some capacitors to withstand a voltage greater than their own withstand voltage value, the capacitors are prone to breakdown and burn, which in turn causes the inverter to fail to work properly. In response to this situation, a variety of voltage equalization processing methods have emerged, such as connecting resistors in parallel to capacitors for voltage equalization, compensating for the difference in parallel resistors, and making the leakage currents close to each other. However, this processing method reduces the energy utilization rate of the system circuit due to the high energy consumption of the resistors. In view of this, a switch device is further added to the parallel circuit of each resistor, and the voltage equalization resistor is connected only when necessary through the logic control of the switch device, but this brings new problems. The control logic of the switch device is complex, and the cost of voltage equalization control is also higher.

[0003] Therefore, a method for adjusting the voltage balancing of the BUS bus voltage is needed to overcome the above-mentioned defects. Summary of the invention

[0004] A main purpose of the present invention is to overcome at least one of the above-mentioned defects, and to provide a method for managing a BUS bus, which can achieve effective management of the bus voltage and dynamic voltage balancing of the bus capacitors, while simplifying the circuit structure and reducing cost investment.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is: The present invention provides a method for managing a BUS bus, wherein at least two groups of capacitor groups connected in series are connected between the positive and negative lines of the BUS bus, a push-pull circuit is arranged between two adjacent capacitor groups, and a voltage-equalizing resistor is respectively connected in series on the collectors of two transistors in the push-pull circuit, a voltage-dividing acquisition module is arranged between the bases of the two transistors and the positive and negative electrodes of the bus, a half-bus voltage is collected by the voltage-dividing acquisition module, and the voltage between the bases of the two transistors and a connection point A of the voltage-dividing acquisition module and a midpoint C of the two capacitor groups is compared; if the voltage difference between the connection point A and the midpoint C of the two capacitor groups is greater than the threshold voltage, the positive bus transistor is turned on, and the positive bus capacitor group is discharged through the voltage-equalizing resistor; if the voltage difference between the midpoint C of the two capacitor groups and the connection point A is greater than the threshold voltage, the negative bus transistor is turned on, and the negative bus capacitor group is discharged through the voltage-equalizing resistor.

[0006] According to one embodiment of the present invention, the push-pull circuit includes at least two transistors, the emitters of adjacent transistors are connected, the transistor whose collector is connected to the positive electrode of the bus is recorded as a positive bus transistor, and the transistor whose collector is connected to the negative electrode of the bus is recorded as a negative bus transistor.

[0007] According to one embodiment of the present invention, one side of the voltage grading resistor is connected to the collector of the transistor, and the other side is connected to the BUS busbar.

[0008] According to one embodiment of the present invention, a voltage regulator is provided between the base of each transistor and the sampling resistor in the push-pull circuit.

[0009] According to one embodiment of the present invention, a positive bus capacitor group and a negative bus capacitor group connected in series are connected between the positive and negative lines of the BUS bus, the push-pull circuit includes a positive bus transistor and a negative bus transistor, the positive bus transistor is an NPN tube, the negative bus transistor is a PNP tube, the collector of the positive bus transistor is connected to the positive bus electrode of the BUS bus after being connected in series with a first equalizing resistor, one end of the positive bus capacitor group is connected to the positive bus electrode of the BUS bus, the emitter of the positive bus transistor is connected to the other end of the positive bus capacitor group, the emitter of the negative bus transistor, and one end of the negative bus capacitor group, the other end of the negative bus capacitor group is connected to the negative bus electrode of the BUS bus, and the collector of the negative bus transistor is connected to the negative bus electrode of the BUS bus after being connected in series with a second equalizing resistor.

[0010] According to one embodiment of the present invention, a first voltage-dividing acquisition module and a second voltage-dividing acquisition module are included. The first voltage-dividing acquisition module and the second voltage-dividing acquisition module are connected in series to form a sampling circuit, which is then arranged between the positive and negative lines of the BUS bus. The base of the positive bus transistor is connected to the base of the negative bus transistor and then connected to the midpoint of the sampling circuit. Each voltage-dividing acquisition module is used to detect the half-bus voltage.

[0011] According to one embodiment of the present invention, two voltage regulator tubes are included, the two voltage regulator tubes are connected in series and placed in reverse, and the series circuit formed by the two voltage regulator tubes is arranged between the bases of the two transistors and the midpoint of the sampling circuit, and is used to compare the breakdown voltage of the voltage regulator tube, the half bus voltage and the voltage difference between the positive and negative bus capacitor groups, wherein: When the capacitor voltage of the positive bus capacitor group is higher than the half bus voltage, and the voltage difference is greater than the breakdown voltage of the voltage regulator tube, one voltage regulator tube is broken down and turned on, and the other voltage regulator tube is forward-conducted, and the positive bus transistor is further turned on, and the positive bus capacitor group is discharged through the first voltage-equalizing resistor; Similarly, when the capacitor voltage of the negative bus capacitor group is higher than the half bus voltage and the voltage difference is greater than the breakdown voltage of the Zener diode, one Zener diode is forward-conducted, the other Zener diode is broken down and turned on, the negative bus transistor is then turned on, and the negative bus capacitor group is discharged through the second equalizing resistor.

[0012] According to one embodiment of the present invention, a bidirectional voltage regulator is included, and the bidirectional voltage regulator is arranged between the bases of the two transistors and the midpoint of the sampling circuit.

[0013] According to one embodiment of the present invention, a current-limiting protection resistor is connected in series in the connection path between the base of the transistor and the voltage-dividing acquisition module.

[0014] According to one embodiment of the present invention, a voltage dividing protection resistor is connected in parallel at both ends of each capacitor group.

[0015] According to one embodiment of the present invention, each capacitor group includes at least one capacitor, and the capacitors in each capacitor group are connected in series. The capacitor group whose one side is connected to the positive electrode of the bus is recorded as the positive bus capacitor group, and the capacitor group whose one side is connected to the negative electrode of the bus is recorded as the negative bus capacitor group.

[0016] Compared with the prior art, the advantages and beneficial effects of the BUS busbar management method of the patent application of the present invention are: The BUS bus management method of the present application collects the half-bus voltage. Through the design of a push-pull circuit, the voltage difference between the base of the transistor and the midpoint of the bus capacitor of the BUS bus, that is, the voltage across the half-bus capacitor is compared with the collected half-bus voltage to obtain the voltage difference between the two. When the voltage difference between the base of the two transistors and the connection point A of the voltage divider acquisition module and the midpoint C of the two capacitor groups is greater than the threshold voltage, the transistor is turned on. After the transistor is turned on, the equalizing resistor connected to the collector of the transistor can be connected in parallel with the bus capacitor to realize the discharge of the bus capacitor, thereby realizing dynamic equalizing processing of the BUS bus capacitor, with good equalizing effect, thereby improving the safety and reliability of equipment operation.

[0017] In addition, the present application can realize that the transistor will only be turned on under a certain voltage difference, and then the voltage equalization resistor and the bus capacitor are connected in parallel to realize discharge, so that the voltage equalization will not start until the voltage difference between the bus capacitor and the transistor is greater than the threshold voltage, effectively avoiding the high-frequency repeated opening of the transistor and affecting its service life, thereby enhancing the robustness of the voltage equalization circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings: Figure 1 is a circuit structure diagram of a BUS bus management method according to Embodiment 1 of the present invention; Figure 2 is a circuit structure diagram of a BUS bus management method according to Embodiment 2 of the present invention; Figure 3 is a circuit structure diagram of a BUS bus management method according to Embodiment 3 of the present invention; Figure 4 is a circuit structure diagram of a BUS bus management method according to Embodiment 4 of the present invention; Figure 5 Schematic diagram of the circuit structure of the BUS bus management method according to Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0019] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0021] Embodiment 1: This embodiment describes a method for managing a BUS bus, wherein the circuit architecture is as follows: Figure 1 As shown, two groups of capacitors connected in series are connected between the positive and negative lines of the BUS bus as bus capacitors, each capacitor group includes at least one capacitor, and the capacitors in each capacitor group are connected in series or connected. The capacitor group connected to the positive pole of the bus on one side is recorded as the positive bus capacitor group C1, and the capacitor group connected to the negative pole of the bus on one side is recorded as the negative bus capacitor group C2. Generally speaking, the positive bus capacitor group C1 or the negative bus capacitor group C2 can include one capacitor, or two or more capacitors, but it is necessary to ensure that the capacitance of each capacitor group is equal to divide the bus voltage of the BUS bus equally.

[0022] A push-pull circuit is set between two capacitor groups, and a voltage-equalizing resistor is connected in series on the collectors of the two transistors in the push-pull circuit respectively, and a voltage-dividing acquisition module is set between the bases of the two transistors and the positive and negative electrodes of the busbar, and the half-busbar voltage is collected by the voltage-dividing acquisition module, where the half-busbar voltage corresponds to half of the busbar voltage. The voltage difference between two points is compared with the threshold voltage, one of which is the connection point A between the bases of the two transistors and the voltage-dividing acquisition module, and the other is the midpoint C of the two capacitor groups. The voltage difference between the connection point A and the midpoint C of the two capacitor groups is compared with the threshold voltage, and the voltage difference between the connection point A and the midpoint C of the two capacitor groups corresponds to the voltage difference between the capacitor voltage of the capacitor group on the same side and the voltage-dividing acquisition module.

[0023] In this embodiment, the threshold voltage is theoretically 0V, but here it is actually the voltage drop between the collector and emitter of the transistor, which is usually 0.7V. Because its absolute value is small, it can generally be regarded as 0V, so this is specially explained.

[0024] In this embodiment, if the voltage difference U between the base of the positive bus transistor Q1 (directly connected to the connection point A) and the midpoint C of the two capacitor groups is AC (That is, Figure 1 If the voltage between the midpoints A and C in the middle of the two capacitor groups is greater than the threshold voltage, the positive bus transistor Q1 is turned on to discharge the positive bus capacitor group C1 through the voltage balancing resistor R1; if the voltage difference U between the midpoint C of the two capacitor groups and the base of the positive bus transistor Q1 (directly connected to the connection point A) is CA (That is, Figure 1When the voltage between points C and A in the circuit is greater than the threshold voltage, the negative bus transistor Q2 is turned on, and the negative bus capacitor group C2 is discharged through the voltage-equalizing resistor R2. The push-pull circuit includes two transistors, the emitters of adjacent transistors are connected, the transistor whose collector is connected to the positive electrode of the bus is denoted as the positive bus transistor Q1, and the transistor whose collector is connected to the negative electrode of the bus is denoted as the negative bus transistor Q2. The transistor can be a semiconductor device with a controllable switch such as a MOS tube or a triode. In this embodiment, the positive bus transistor Q1 is an NPN tube, and the negative bus transistor Q2 is a PNP tube.

[0025] For ease of description, the voltage-equalizing resistor connected to the positive bus transistor Q1 is recorded as the first voltage-equalizing resistor R1, and the voltage-equalizing resistor connected to the negative bus transistor Q2 is recorded as the second voltage-equalizing resistor R2. The collector of the positive bus transistor Q1 is connected to the positive bus electrode of the BUS bus after being connected in series with the first voltage-equalizing resistor R1, one end of the positive bus capacitor group C1 is connected to the positive bus electrode of the BUS bus, the emitter of the positive bus transistor Q1 is connected to the other end of the positive bus capacitor group C1, the emitter of the negative bus transistor Q2, and one end of the negative bus capacitor group C2, the other end of the negative bus capacitor group C2 is connected to the negative bus electrode of the BUS bus, and the collector of the negative bus transistor Q2 is connected to the negative bus electrode of the BUS bus after being connected in series with the second voltage-equalizing resistor R2.

[0026] This embodiment includes a first voltage-dividing acquisition module R3 and a second voltage-dividing acquisition module R4. The first voltage-dividing acquisition module R3 and the second voltage-dividing acquisition module R4 are connected in series to form a voltage acquisition circuit and are arranged between the positive and negative lines of the BUS bus. The base of the positive bus transistor Q1 is connected to the base of the negative bus transistor Q2 and then connected to the midpoint of the sampling circuit. Each voltage-dividing acquisition module is used to detect the half-bus voltage. The half-bus voltage is the voltage from the positive pole of the bus to the connection midpoint between the first voltage-dividing acquisition module R3 and the second voltage-dividing acquisition module R4 or the connection midpoint between the first voltage-dividing acquisition module R3 and the second voltage-dividing acquisition module R4 to the negative pole of the bus, which is half of the bus voltage.

[0027] In this embodiment, the half-bus voltage is collected by the voltage division collection module. Through the design of the push-pull circuit, the voltage difference between the base of the transistor and the midpoint of the bus capacitor of the BUS bus, that is, the voltage at both ends of the half-bus capacitor is compared with the half-bus voltage obtained by collection to obtain the voltage difference between the two. The voltage difference corresponds to the voltage difference between the connection point A and the midpoint C of the two capacitor groups, which is an absolute value. When the voltage at both ends of each bus capacitor group is greater than the half-bus voltage obtained by collection, the transistor is turned on. In this embodiment, the transistor is turned on when the voltage difference between the connection point A and the midpoint C of the two capacitor groups is approximately greater than zero (or 0.7V). After the transistor is turned on, the voltage-equalizing resistor connected to the collector of the transistor can be connected in parallel with the bus capacitor to discharge the bus capacitor, thereby realizing dynamic voltage-equalizing processing of the BUS bus capacitor, with good voltage-equalizing effect, which improves the safety and reliability of the equipment.

[0028] Embodiment 2: The BUS bus management method of this embodiment is improved on the basis of embodiment 1, and the improvement lies in that a voltage regulator is provided between the base of each transistor and the sampling resistor in the push-pull circuit, and through the design of the voltage regulator, the voltage difference between the connection point A and the midpoint C of the two capacitor groups can be compared with the threshold voltage (the breakdown voltage of the voltage regulator) through the design of the hardware circuit, and the transistor is turned on when it is greater than the threshold voltage. In other words, the BUS bus management method of this embodiment can realize the turning on of the transistor under a certain voltage difference, and then the voltage balancing resistor is connected in parallel with the bus capacitor to realize discharge, so that the voltage balancing is started only when the voltage difference between the bus capacitor and the transistor is greater than the threshold voltage, effectively avoiding the high-frequency repeated opening of the transistor and affecting its service life, and enhancing the robustness of the voltage balancing circuit.

[0029] Specifically in this embodiment, the circuit architecture is as follows: Figure 2 As shown, this embodiment includes a voltage regulator tube Z1 and a voltage regulator tube Z2, the two voltage regulator tubes are connected in series and placed in reverse, and the series circuit formed by the two voltage regulator tubes is arranged between the bases of the two transistors and the midpoint of the sampling circuit, and is used to compare the breakdown voltage of the voltage regulator tube, the half bus voltage and the voltage difference between the positive and negative bus capacitor groups C2, wherein, When the capacitor voltage across the positive bus capacitor group C1 is higher than the half bus voltage, and the voltage difference (the voltage U between points A and C) is AC ) is greater than the breakdown voltage of the voltage regulator tube, the first voltage regulator tube Z1 is broken down and turned on, the second voltage regulator tube Z2 is forward-conducted, the positive bus transistor Q1 is then turned on, and the positive bus capacitor group C1 is discharged through the first voltage-equalizing resistor R1; Similarly, when the capacitor voltage of the negative bus capacitor group C2 is higher than the half bus voltage, and the voltage difference (the voltage U between points C and A) isCA ) is greater than the breakdown voltage of the voltage regulator tube, the first voltage regulator tube Z1 is forward-conducted, the second voltage regulator tube Z2 is broken down and turned on, the negative bus transistor Q2 is then turned on, and the negative bus capacitor group C2 is discharged through the second balancing resistor R2.

[0030] Embodiment 3: The BUS busbar management method of this embodiment is adjusted on the basis of the embodiment 1, and the improvement is that a bidirectional voltage regulator Z3 is used to replace the two back-to-back voltage regulators Z1 and Z2 in the embodiment 2. Figure 3 As shown, the bidirectional voltage regulator Z3 is arranged between the bases of the two transistors and the midpoint of the sampling circuit.

[0031] Embodiment 4: The BUS busbar management method of this embodiment is improved on the basis of Embodiment 2. The improvement is as follows: Figure 4 As shown, a current limiting protection resistor R5 is connected in series in the connection path between the base of the transistor and the voltage dividing acquisition module, and the current limiting protection resistor R5 is connected in series with the voltage regulator tubes Z1 and Z2.

[0032] Embodiment 5: The BUS busbar management method of this embodiment is improved on the basis of Embodiment 2. The improvement is as follows: Figure 5 As shown, a current limiting protection resistor R5 is connected in series in the connection path between the base of the transistor and the voltage dividing acquisition module, and the current limiting protection resistor R5 is connected in series with the bidirectional voltage regulator Z3.

[0033] In each of the above embodiments, a voltage-dividing protection resistor may be connected in parallel at both ends of each capacitor group, so that each capacitor group can be basically protected by the voltage-dividing protection resistor.

[0034] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with this technology to understand the contents of the present invention and implement them accordingly. They cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for managing a BUS bus, characterized in that: At least two groups of capacitor groups connected in series are connected between the positive and negative lines of the BUS bus, a push-pull circuit is arranged between two adjacent capacitor groups, and equalizing resistors are respectively connected in series on the collectors of the two transistors in the push-pull circuit, and a voltage dividing acquisition module is arranged between the bases of the two transistors and the positive and negative poles of the bus. The half-bus voltage is collected by the voltage dividing acquisition module, and the voltage between the bases of the two transistors and the connection point A of the voltage dividing acquisition module and the midpoint C of the two capacitor groups is compared. If the voltage difference between the connection point A and the midpoint C of the two capacitor groups is greater than a threshold voltage, the positive bus transistor is turned on, and the positive bus capacitor group is discharged through the equalizing resistor; if the voltage difference between the midpoint C of the two capacitor groups and the connection point A is greater than the threshold voltage, the negative bus transistor is turned on, and the negative bus capacitor group is discharged through the equalizing resistor.

2. The method for managing a BUS bus according to claim 1, characterized in that: The push-pull circuit includes at least two transistors, the emitters of adjacent transistors are connected, the transistor whose collector is connected to the positive electrode of the bus is recorded as a positive bus transistor, and the transistor whose collector is connected to the negative electrode of the bus is recorded as a negative bus transistor.

3. The method for managing a BUS bus according to claim 1, characterized in that: One side of the voltage-equalizing resistor is connected to the collector of the transistor, and the other side is connected to the BUS bus.

4. The method for managing a BUS bus according to claim 1 or 3, characterized in that: A voltage regulator tube is arranged between the base of each transistor and the sampling resistor in the push-pull circuit.

5. The method for managing a BUS bus according to claim 1, characterized in that: A positive bus capacitor group and a negative bus capacitor group connected in series are connected between the positive and negative lines of the BUS bus. The push-pull circuit includes a positive bus transistor and a negative bus transistor. The positive bus transistor is an NPN tube, and the negative bus transistor is a PNP tube. The collector of the positive bus transistor is connected to the positive bus electrode of the BUS bus after being connected in series with the first equalizing resistor. One end of the positive bus capacitor group is connected to the positive bus electrode of the BUS bus. The emitter of the positive bus transistor is connected to the other end of the positive bus capacitor group, the emitter of the negative bus transistor, and one end of the negative bus capacitor group. The other end of the negative bus capacitor group is connected to the negative bus electrode of the BUS bus. The collector of the negative bus transistor is connected to the negative bus electrode of the BUS bus after being connected in series with the second equalizing resistor.

6. The method for managing a BUS bus according to claim 5, characterized in that: It includes a first voltage-dividing acquisition module and a second voltage-dividing acquisition module. The first voltage-dividing acquisition module and the second voltage-dividing acquisition module are connected in series to form a sampling circuit, which is then arranged between the positive and negative lines of the BUS bus. The base of the positive bus transistor is connected to the base of the negative bus transistor and then connected to the midpoint of the sampling circuit. Each voltage-dividing acquisition module is used to collect half-bus voltage.

7. The method for managing a BUS bus according to claim 6, characterized in that: It includes two voltage regulator tubes, which are connected in series and placed in reverse. The series circuit formed by the two voltage regulator tubes is arranged between the bases of the two transistors and the midpoint of the sampling circuit, and is used to compare the breakdown voltage of the voltage regulator tube, the half bus voltage and the voltage difference between the positive and negative bus capacitor groups, wherein: When the capacitor voltage of the positive bus capacitor group is higher than the half bus voltage, and the voltage difference is greater than the breakdown voltage of the voltage regulator tube, one voltage regulator tube is broken down and turned on, and the other voltage regulator tube is forward-conducted, and the positive bus transistor is further turned on, and the positive bus capacitor group is discharged through the first voltage-equalizing resistor; Similarly, when the capacitor voltage of the negative bus capacitor group is higher than the half bus voltage and the voltage difference is greater than the breakdown voltage of the Zener diode, one Zener diode is forward-conducted, the other Zener diode is broken down and turned on, the negative bus transistor is then turned on, and the negative bus capacitor group is discharged through the second equalizing resistor.

8. The method for managing a BUS bus according to claim 6, characterized in that: It comprises a bidirectional voltage regulator tube, which is arranged between the bases of the two transistors and the midpoint of the sampling circuit.

9. The method for managing a BUS bus according to claim 1, 7 or 8, characterized in that: A current-limiting protection resistor is connected in series in a connection path between the base of the transistor and the voltage-dividing acquisition module.

10. The method for managing a BUS bus according to claim 1, characterized in that: A voltage dividing protection resistor is connected in parallel at both ends of each capacitor group.

11. The method for managing a BUS bus according to claim 1, characterized in that: Each capacitor group includes at least one capacitor, and the capacitors in each capacitor group are connected in series. The capacitor group with one side connected to the positive electrode of the bus is recorded as the positive bus capacitor group, and the capacitor group with one side connected to the negative electrode of the bus is recorded as the negative bus capacitor group.

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