Semiconductor device and electronic system including the same

Abstract

The present disclosure relates to a semiconductor device and an electronic system including the same, the semiconductor device including: a first substrate; a wiring layer on the first substrate; a second substrate on the wiring layer and including a conductive material; a first horizontal conductive layer and a second horizontal conductive layer sequentially stacked on the second substrate and connected to the second substrate; a gate stack structure including interlayer insulating layers and gate electrodes alternately stacked on the second horizontal conductive layer; a channel structure passing through the gate stack structure and connected to the second substrate; a first capacitor electrode on the same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; and a first dielectric layer between the first capacitor electrode and the second capacitor electrode, where the second capacitor electrode is on the same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer, and the gate electrode.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an electronic system including the semiconductor device. Background Art

[0002] Semiconductor is a material belonging to the middle area between conductor and insulator, and refers to a material that conducts electricity under predetermined conditions. Various semiconductor devices such as memory devices can be manufactured using such semiconductor materials. Memory devices can be divided into volatile memory devices and non-volatile memory devices. In the case of non-volatile memory devices, the content may not be deleted when the power is turned off. Both volatile memory devices and non-volatile memory devices can be used in various electronic devices such as portable phones, digital cameras, and PCs.

[0003] According to the recent trend of increasing storage capacity, it is expected to improve the integration of non-volatile memory devices. The integration of memory devices arranged two-dimensionally on a plane may be limited. Therefore, vertical non-volatile memory devices arranged three-dimensionally have been proposed. Summary of the invention

[0004] The present disclosure aims to provide a semiconductor device for simplifying a process and improving integration, and an electronic system including the semiconductor device.

[0005] An example embodiment of the present disclosure provides a semiconductor device, which includes: a first substrate; a wiring layer on the first substrate; a second substrate on the wiring layer and including a conductive material; a first horizontal conductive layer and a second horizontal conductive layer, which are sequentially stacked on the second substrate and connected to the second substrate; a gate stack structure, including an interlayer insulating layer and a gate electrode alternately stacked on the second horizontal conductive layer; a channel structure passing through the gate stack structure and connected to the second substrate; a first capacitor electrode, which is on the same layer as the second substrate; a second capacitor electrode, which overlaps with the first capacitor electrode; and a first dielectric layer, between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on the same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer, and the gate electrode.

[0006] Another example embodiment of the present disclosure provides a semiconductor device, which includes: a first substrate; a second substrate facing the first substrate and including a conductive material; a wiring layer between the first substrate and the second substrate; a gate stack structure including an interlayer insulating layer and a gate electrode alternately stacked between the wiring layer and the second substrate; a channel structure passing through the gate stack structure and connected to the second substrate; a first capacitor electrode on the same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; and a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on the same layer as at least one of the wiring layer, the second substrate and the gate electrode.

[0007] Another example embodiment of the present disclosure provides an electronic system, which includes a main substrate, a semiconductor device on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device includes: a first substrate; a wiring layer on the first substrate; a second substrate on the wiring layer and including a conductive material; a gate stack structure including interlayer insulating layers and gate electrodes alternately stacked on the second substrate; a channel structure passing through the gate stack structure and connected to the second substrate; a first capacitor electrode on the same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; and a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on the same layer as at least one of the wiring layer, the second substrate, and the gate electrode.

[0008] In an example embodiment where the second capacitor electrode is on the same layer as the second substrate, the sum of the thickness of the first capacitor electrode and the thickness of the second capacitor electrode corresponds to the thickness of the second substrate. For example, the sum of the thickness of the first capacitor electrode and the thickness of the second capacitor electrode can be the same, substantially the same, or equal to the thickness of the second substrate.

[0009] According to example embodiments, a semiconductor device and an electronic system including the semiconductor device may simplify a manufacturing process and may improve integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A cross-sectional view of a semiconductor device according to example embodiments is shown.

[0011] Figure 2A and Figure 2B Shows Figure 1 Cross-sectional views of various examples of channel structures in semiconductor devices are shown.

[0012] Figure 3 Shows Figure 1 Cross-sectional view of an enlarged area of ​​.

[0013] Figure 4 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0014] Figure 5 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0015] Figure 6 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0016] Figure 7 A cross-sectional view of a semiconductor device according to example embodiments is shown.

[0017] Figure 8 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0018] Figures 9 to 12 Process cross-sectional views of parts of a method of manufacturing a semiconductor device according to example embodiments are sequentially shown.

[0019] Fig.13 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0020] Fig.14 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0021] Figures 15 to 19 Process cross-sectional views of parts of a method of manufacturing a semiconductor device according to example embodiments are sequentially shown.

[0022] Fig. 20 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0023] Fig.21 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0024] Fig. 22 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0025] Fig.23 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0026] Fig.24 A top view of some constituent elements of a semiconductor device according to example embodiments is shown.

[0027] Fig.25 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0028] Figures 26 to 30 Process cross-sectional views of parts of a method of manufacturing a semiconductor device according to example embodiments are sequentially shown.

[0029] Fig.31 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0030] Fig.32 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0031] Fig.33 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0032] Figure 34 to Figure 39 Process cross-sectional views of parts of a method of manufacturing a semiconductor device according to example embodiments are sequentially shown.

[0033] Fig.40 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0034] Fig.41 An electronic system including a semiconductor device according to example embodiments is illustrated.

[0035] Fig.42 A perspective view of an electronic system including a semiconductor device according to example embodiments is shown.

[0036] Fig.43 and Fig.44 A cross-sectional view of a semiconductor package according to example embodiments is shown. DETAILED DESCRIPTION

[0037] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. As those skilled in the art will realize, the described example embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0038] The drawings and description are to be regarded as illustrative in nature and not restrictive.Throughout the specification, like reference numerals refer to like elements.

[0039] For better understanding and ease of description, the size and thickness of each structure shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. In the drawings, for clarity, the thickness of layers, films, panels, regions, etc. are exaggerated. For ease of description, the thickness of some layers and regions is exaggerated.

[0040] It will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, it can be directly on the other element, or there can also be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "on" or "above" describe a position relative to a target portion, and do not necessarily mean being positioned "on" or "above" the upper side of a target portion based on the direction of gravity.

[0041] Unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0042] The phrase "on a plane" means observing the target portion from the top, and the phrase "on a cross section" means observing a cross section vertically cutting the target portion from the side.

[0043] Now refer to Figure 1 , Figure 2A , Figure 2B and Figure 3 A semiconductor device according to example embodiments is described.

[0044] Figure 1 shows a cross-sectional view of a semiconductor device according to an example embodiment, Figure 2A and Figure 2B Shows Figure 1 Cross-sectional views of various examples of channel structures in semiconductor devices are shown. Figure 3 Shows Figure 1 Cross-sectional view of an enlarged area of ​​. Figure 3 Shows Figure 1 An enlarged portion of the capacitor area.

[0045] Reference Figure 1 and Figure 2A , the semiconductor device 10 according to the example embodiment may include a cell region 100 in which a memory cell structure is installed, a circuit region 200 in which a peripheral circuit structure for controlling the operation of the memory cell structure is installed, and a capacitor region 106. For example, the circuit region 200 and the cell region 100 may correspond to a capacitor region 106 included in Fig.41 The first structure 1100F and the second structure 1100S of the semiconductor device 1100 in the electronic system 1000 are shown. In another way, the circuit region 200 and the unit region 100 may correspond to Fig.43 The first structure 3100 and the second structure 3200 of the semiconductor chip 2200 are shown. Fig.41 and Fig.43 , the portion corresponding to the capacitor region 106 is not shown, Fig.41 The first structure 1100F and Fig.43 The first structure 3100 and Fig.41 The second structure 1100S and Fig.43 A predetermined area of ​​the edge of the second structure 3200 may correspond to the capacitor region 106 .

[0046] Here, the circuit region 200 may include a peripheral circuit structure disposed on a first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH as a memory cell structure disposed in a cell array region 102 of a second substrate 110. A first wiring portion 230 electrically connected to the peripheral circuit structure may be disposed in the circuit region 200, and a second wiring portion 180 electrically connected to the memory cell structure may be disposed in the cell region 100.

[0047] In example embodiments, the cell region 100 may be disposed in the circuit region 200. Accordingly, there is no need to ensure an area corresponding to the circuit region 200 separately from the cell region 100, and thus the area of ​​the semiconductor device 10 may be reduced. However, example embodiments are not limited thereto, and the circuit region 200 may be disposed adjacent to the cell region 100. Other various variations are possible.

[0048] The circuit region 200 may include a first substrate 210 , and a circuit element 220 and a first wiring portion 230 disposed on the first substrate 210 .

[0049] The first substrate 210 may be a semiconductor substrate including a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate made of a semiconductor material, and may be a semiconductor substrate produced by forming a semiconductor layer on a base substrate. For example, the first substrate 210 may be made of silicon, epitaxial silicon, germanium, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0050] The circuit element 220 formed on the first substrate 210 may include various types of circuit elements for controlling the operation of the memory cell structure installed in the cell region 100. For example, the circuit element 220 may configure a peripheral circuit structure such as Fig.41 The decoder circuit 1110, Fig.41 The page buffer 1120 or Fig.41 Logic circuit 1130.

[0051] For example, the circuit element 220 may include a transistor, and is not limited thereto. For example, the circuit element 220 may include an active element (such as a transistor) and a passive element (such as a capacitor, a resistor, or an inductor). Some capacitors may be arranged in the circuit region 200, and other capacitors may be arranged in the capacitor region 106. The capacitor region 106 may be arranged near the circuit region 200 and the unit region 100. The capacitor arranged in the capacitor region 106 may be connected to the circuit element 220 arranged in the circuit region 200.

[0052] The first wiring portion 230 disposed on the first substrate 210 may be electrically connected to the circuit element 220. In example embodiments, the first wiring portion 230 may include wiring layers 236 that are spaced apart with the first insulating layer 232 therebetween and connected by contact vias 234 to form a predetermined path. The wiring layers 236 or the contact vias 234 may include various types of conductive materials, and the first insulating layer 232 may include various types of insulating materials.

[0053] The cell region 100 may include a cell array region 102 and a connection region 104. A gate stack structure 120 and a channel structure CH may be disposed on a second substrate 110 in the cell array region 102. A structure for connecting the gate stack structure 120 and / or the channel structure CH disposed in the cell array region 102 to the circuit region 200 or an external circuit may be disposed in the connection region 104.

[0054] In example embodiments, the second substrate 110 may include a semiconductor material. For example, the second substrate 110 may include polysilicon doped with impurities. The second substrate 110 may be used as a common source line. The second substrate 110 may be used as a source region for supplying current to a memory cell disposed on the second substrate 110. The second substrate 110 may have a plate shape. That is, the second substrate 110 may be made of a plate-shaped common source line.

[0055] The insulating layer 240 may be disposed between the second substrate 110 and the first wiring portion 230. The insulating layer 240 may be a single layer or multiple layers. For example, the insulating layer 240 may include a lower insulating layer 242 and an upper insulating layer 244 disposed on the lower insulating layer 242. The insulating layer 240 may include various types of insulating materials. For example, the lower insulating layer 242 may include silicon nitride, and the upper insulating layer 244 may include silicon oxide.

[0056] The first wiring portion 230 may further include a floating electrode 230a. In this case, the floating electrode 230a may include a layer disposed on the same layer as the wiring layer 236 and the contact path 234. However, not limited thereto, the floating electrode 230a may be disposed on the same layer as some of the wiring layer 236 and the contact path 234. The floating electrode 230a may include a conductive material. The floating electrode 230a may be connected to the second substrate 110. The insulating layer 240 disposed between the second substrate 110 and the first wiring portion 230 may include an opening OP. That is, an opening OP passing through the insulating layer 240 may be formed. The opening OP may overlap with the floating electrode 230a. The second substrate 110 may be connected to the floating electrode 230a through the opening OP formed in the insulating layer 240.

[0057] No additional signal is applied to the floating electrode 230a, and the floating electrode 230a may float. Since the floating electrode 230a is electrically connected to the second substrate 110, in the process of manufacturing the semiconductor device 10 according to the example embodiment, the plasma charges stored on the second substrate 110 may be removed. For example, the floating electrode 230a may be connected to the first substrate 210, and the stored charges may be released to the first substrate 210 through the floating electrode 230a.

[0058] A gate stack structure 120 including a cell insulating layer 132 and a gate electrode 130 alternately stacked on a first side (e.g., a front side or an upper side) of a second substrate 110, and a channel structure CH passing through the gate stack structure 120 and extending in a direction intersecting the second substrate 110 can be formed in the cell array region 102.

[0059] Horizontal conductive layers 112 and 114 may be provided between the second substrate 110 and the gate stack structure 120 in the cell array region 102. The horizontal conductive layers 112 and 114 may electrically connect the channel structure CH and the second substrate 110. For example, the horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 disposed on the first surface of the second substrate 110, and may further include a second horizontal conductive layer 114 disposed on the first horizontal conductive layer 112. That is, the first horizontal conductive layer 112 may be disposed between the second substrate 110 and the second horizontal conductive layer 114. The first horizontal conductive layer 112 may not be provided, but a horizontal insulating layer 116 may be provided between the second substrate 110 and the gate stack structure 120 in at least a predetermined region of the connection region 104. In the manufacturing process, a portion of the horizontal insulating layer 116 may be replaced by the first horizontal conductive layer 112, and another portion of the horizontal insulating layer 116 may remain in the connection region 104. The horizontal insulating layer 116 may be a single layer or multiple layers. For example, the horizontal insulating layer 116 may include a lower layer 116a, an intermediate layer 116b, and an upper layer 116c. In this case, the intermediate layer 116b may be disposed between the lower layer 116a and the upper layer 116c. The horizontal insulating layer 116 may include various insulating materials. For example, the lower layer 116a and the upper layer 116c may include silicon oxide, and the intermediate layer 116b may include silicon nitride.

[0060] The first horizontal conductive layer 112 may be used as part of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 may be used as a common source line together with the second substrate 110. Figure 2AAs shown in the enlarged view of , the channel structure CH extends to pass through the horizontal conductive layers 112 and 114 and reaches the second substrate 110, and the gate dielectric layer 150 is removed from the portion on which the first horizontal conductive layer 112 is disposed, so the first horizontal conductive layer 112 can be directly connected to the channel layer 140 on the periphery of the channel layer 140. Therefore, the first horizontal conductive layer 112 can electrically connect the second substrate 110 and the channel layer 140.

[0061] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may include a semiconductor material (e.g., polysilicon). For example, the first horizontal conductive layer 112 may include polysilicon doped with impurities, and the second horizontal conductive layer 114 may include polysilicon doped with impurities, or may include impurities diffused from the first horizontal conductive layer 112. However, example embodiments are not limited thereto, and the second horizontal conductive layer 114 may include an insulating material. Alternatively, the second horizontal conductive layer 114 may not be provided separately.

[0062] The gate stack structure 120 in which the cell insulating layers 132 and the gate electrodes 130 are alternately stacked may be disposed on the second substrate 110 (eg, on the first horizontal conductive layer 112 and the second horizontal conductive layer 114 formed on the second substrate 110 ).

[0063] In an example embodiment, the gate stack structure 120 may include gate stack structures 120a and 120b sequentially stacked on the second substrate 110. As a result, the number of stacked gate electrodes 130 may increase, and thus the number of memory cells may increase in a stable structure. For example, the gate stack structure 120 may include a first gate stack structure 120a and a second gate stack structure 120b, and the structure may be simplified while increasing the data storage capacity. However, example embodiments are not limited thereto, and the gate stack structure 120 may be made of one gate stack structure, or may include three or more gate stack structures.

[0064] The gate electrode 130 may include a lower gate electrode 130L, a memory cell gate electrode 130M, and an upper gate electrode 130U sequentially disposed on the second substrate 110 in the gate stack structure 120. The lower gate electrode 130L may be used as a gate electrode of a ground selection transistor, the memory cell gate electrode 130M may configure a memory cell, and the upper gate electrode 130U may be used as a gate electrode of a string selection transistor. The number of memory cell gate electrodes 130M may be determined by the data storage capacity of the semiconductor device 10. According to example embodiments, one or more lower gate electrodes 130L and upper gate electrodes 130U may be installed and may have the same or different structures as the memory cell gate electrode 130M. Portions of the gate electrode 130, such as the memory cell gate electrode 130M disposed close to the lower gate electrode 130L and the upper gate electrode 130U, may be dummy gate electrodes.

[0065] The unit insulating layer 132 may include an interlayer insulating layer 132m disposed at the lower portion of the gate electrode 130 or between two adjacent gate electrodes 130 in the first gate stack structure 120a and the second gate stack structure 120b, and upper insulating layers 132a and 132b disposed at the upper portion of the first gate stack structure 120a and the second gate stack structure 120b. For example, the upper insulating layers 132a and 132b may include a first upper insulating layer 132a disposed at the upper portion of the first gate stack structure 120a and a second upper insulating layer 132b disposed at the upper portion of the second gate stack structure 120b. In this case, the first upper insulating layer 132a is an intermediate insulating layer disposed between the first gate stack structure 120a and the second gate stack structure 120b, and the second upper insulating layer 132b is an uppermost insulating layer disposed at the uppermost portion of the gate stack structure 120. The second upper insulating layer 132b may configure part or all of the unit region insulating layer disposed at the upper portion of the unit region 100. In example embodiments, all thicknesses of the unit insulating layer 132 may be unequal to each other. For example, the upper insulating layers 132a and 132b may be thicker than the interlayer insulating layer 132m. However, according to example embodiments, the form or structure of the unit insulating layer 132 may be modified in various ways.

[0066] For ease of explanation, the drawings show that the unit insulating layer 132 has a boundary between the first gate stack structure 120a and the second gate stack structure 120b in the connection region 104. However, example embodiments are not limited thereto. The insulating layer may have various types of stacking structures in the connection region 104, and example embodiments are not limited thereto.

[0067] The gate electrode 130 may include various types of conductive materials. For example, the gate electrode 130 may include a metal material such as tungsten (W), copper (Cu) or aluminum (Al). For another example, the gate electrode 130 may include polysilicon, a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a combination thereof. Although not shown, an insulating layer made of an insulating material may be disposed on the outside of the gate electrode 130, or a portion of the gate dielectric layer 150 may be disposed on the outside of the gate electrode 130. The cell insulating layer 132 may include various types of insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) material having a dielectric constant lower than that of silicon oxide, or a combination thereof.

[0068] In example embodiments, a channel structure CH is formed extending in a direction (eg, a vertical direction perpendicular to the second substrate 110 ) (Z-axis direction in the drawing) that passes through the gate stack structure 120 and crosses the second substrate 110 .

[0069] In more detail, the channel structure CH may include a channel layer 140 and a gate dielectric layer 150 disposed on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may further include a core insulating layer 142 disposed inside the channel layer 140, and may further include a channel pad 144 disposed on the channel layer 140 and / or the gate dielectric layer 150.

[0070] Each of the channel structures CH forms a memory cell string, and the channel structures CH may form rows and columns and may be spaced apart from each other in a plan view. For example, in a plan view, the channel structure CH may be arranged in various forms, such as a lattice form or a zigzag form. The channel structure CH may have a columnar shape. For example, the channel structure CH may have an inclined side so that the width of the channel structure CH narrows as it approaches the second substrate 110 according to the aspect ratio in the cross-sectional view. However, example embodiments are not limited thereto, and the channel structure CH may have various arrangements, structures, and shapes.

[0071] The core insulating layer 142 may be provided in the central region of the channel structure CH, and the channel layer 140 may be formed while surrounding the sidewall of the core insulating layer 142. For example, the core insulating layer 142 may have a columnar shape (e.g., a cylindrical shape or a polygonal columnar shape), and the channel layer 140 may have a planar shape such as a ring shape. However, example embodiments are not limited thereto, and the core insulating layer 142 may not be provided, and the channel layer 140 may have a columnar shape (e.g., a cylindrical shape or a polygonal columnar shape).

[0072] The channel layer 140 may include a semiconductor material, such as polysilicon. The core insulating layer 142 may include various types of insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the materials of the channel layer 140 and the core insulating layer 142 are not limited thereto.

[0073] The gate dielectric layer 150 disposed between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152 , a charge storage layer 154 , and a blocking layer 156 sequentially stacked on the channel layer 140 .

[0074] In this case, the tunneling layer 152 may allow charge tunneling according to a voltage applied to the gate electrode 130, and may include an insulating material that allows charge tunneling. The tunneling layer 152 may include a material such as silicon oxide or silicon oxynitride. For example, the tunneling layer 152 may be formed by stacking a layer including silicon oxide and a layer including silicon nitride.

[0075] The charge storage layer 154 disposed between the tunneling layer 152 and the blocking layer 156 may be used as a data storage area. For example, the charge storage layer 154 may include silicon nitride for capturing charges. When the charge storage layer 154 is made of silicon nitride, the charge storage layer 154 may have excellent retention compared to the case where it is made of polysilicon, and may be beneficial to integration. However, the material of the charge storage layer 154 is not limited thereto.

[0076] The blocking layer 156 may be disposed between the charge storage layer 154 and the gate electrode 130. The blocking layer 156 may include an insulating material for preventing charges from undesirably flowing into the gate electrode 130. For example, the blocking layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material, or a combination thereof.

[0077] Here, the high dielectric constant material refers to a dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high dielectric constant material may include aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), praseodymium oxide (Pr 2 O 3 ) or a combination thereof.

[0078] The channel pad 144 may be disposed on the channel layer 140 and / or the gate dielectric layer 150. The channel pad 144 may be disposed to cover the upper surface of the core insulating layer 142 and be electrically connected to the channel layer 140. The channel pad 144 is shown as covering the upper surface of the gate dielectric layer 150, but is not limited thereto. For example, the channel pad 144 may not cover the upper surface of the gate dielectric layer 150. In this case, the side of the channel pad 144 may be surrounded by the gate dielectric layer 150. The side of the channel pad 144 may contact the tunneling layer 152. The channel pad 144 may include a conductive material, such as doped polysilicon. However, the material of the channel pad 144 is not limited thereto and may be modified in a variety of ways.

[0079] When the gate stack structure 120 includes the stacked gate stack structures 120a and 120b as described above, the channel structure CH may have channel structures CH1 and CH2 that pass through the gate stack structures 120a and 120b, respectively. For example, when the gate stack structure 120 includes a first gate stack structure 120a and a second gate stack structure 120b, the channel structure CH may include a first channel structure CH1 extending through the first gate stack structure 120a and a second channel structure CH2 extending through the second gate stack structure 120b.

[0080] The first channel structure CH1 may be connected to the second channel structure CH2. The first channel structure CH1 and the second channel structure CH2 may each have an inclined side surface such that the width becomes narrower as approaching the second substrate 110 according to the aspect ratio in the cross-sectional view. Figure 2A As shown, due to the difference in width, a bent portion may be provided at a portion where the first channel structure CH1 is connected to the second channel structure CH2. Figure 2B As shown, the first channel structure CH1 and the second channel structure CH2 may have inclined sides that are continuously connected without a bent portion. However, the shapes of the first channel structure CH1 and the second channel structure CH2 are not limited thereto and may be modified in various ways.

[0081] Figure 1The gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the first channel structure CH1 and the second channel structure CH2 are shown to extend from each other to form an integral structure. When forming a first penetration portion for the first channel structure CH1 and a second penetration portion for the second channel structure CH2, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 are formed in the first penetration portion and the second penetration portion to form the above structure. However, the embodiment is not limited thereto. For another example, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the first channel structure CH1 and the second channel structure CH2 may be formed separately from each other and may be electrically connected to each other. For example, when forming a first penetration portion for the first channel structure CH1, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 may be formed in the first penetration portion, and when forming a second penetration portion for the second channel structure CH2, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 may be formed in the second penetration portion. Various other variations are possible.

[0082] In example embodiments, the channel pad 144 may provide an upper portion of a channel structure CH (e.g., a second channel structure CH2) provided in a gate stack structure 120 (e.g., a second gate stack structure 120b) disposed at an upper portion among the gate stack structures 120. Differently, the channel pad 144 may be provided at upper portions of the first channel structure CH1 and the second channel structure CH2, respectively. In this case, the channel pad 144 of the first channel structure CH1 may be connected to the channel layer 140 of the second channel structure CH2.

[0083] In an example embodiment, the gate stack structure 120 may extend in a direction intersecting the second substrate 110 (eg, a vertical direction, a Z-axis direction in the drawings), and may be divided into a plurality of partitions by a separation structure 146 penetrating the gate stack structure 120 in a plan view.

[0084] For example, the separation structure 146 may penetrate the gate electrode 130 and the cell insulating layer 132, and may extend to the second substrate 110. The separation structure 146 may be provided in plurality, so that the plurality of separation structures 146 may extend in one direction (the Y-axis direction in the drawings), and may be spaced apart from each other at a predetermined interval in a plan view along a cross direction (the X-axis direction in the drawings) that crosses the one direction. Therefore, in a plan view, the gate stack structures 120 may extend in one direction (the Y-axis direction in the drawings), respectively, and may be spaced apart from each other at a predetermined interval in a cross direction (the X-axis direction in the drawings). The gate stack structures 120 divided by the separation structures 146 may constitute a memory cell block. However, the example embodiments are not limited thereto, and the scope of the memory cell block is not limited thereto.

[0085] For example, the separation structure 146 may have an inclined side whose width decreases toward the second substrate 110 due to a high aspect ratio when viewed in a cross-sectional view. However, example embodiments are not limited thereto, and the side of the separation structure 146 may be perpendicular to the second substrate 110. Figure 1 The separation structure 146 is shown to have continuous inclined side surfaces in the first gate stack structure 120a and the second gate stack structure 120b, and has no curved portion in the cross-sectional view. However, example embodiments are not limited thereto, and the separation structure 146 may have a curved portion at a boundary between the first gate stack structure 120a and the second gate stack structure 120b.

[0086] The separation structure 146 may be filled with various types of insulating materials. For example, the separation structure 146 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, example embodiments are not limited thereto, and the structure, shape, and material of the separation structure 146 may be changed in various ways.

[0087] The upper separation pattern 148 may be formed at an upper portion of the gate stack structure 120. The upper separation pattern 148 may be provided in plurality, such that the plurality of upper separation patterns 148 may extend in one direction (the Y-axis direction in the drawing) and may be spaced apart from each other at a predetermined interval in a crossing direction (the X-axis direction in the drawing) crossing the one direction.

[0088] The upper separation pattern 148 may be formed by passing through one or more gate electrodes 130, the one or more gate electrodes 130 including an upper gate electrode 130U disposed between the separation structures 146. The upper separation pattern 148 may, for example, separate the three gate electrodes 130 from each other in the cross direction (the X-axis direction in the drawings). However, the number of gate electrodes 130 separated by the upper separation pattern 148 is not limited thereto and may be modified in various ways. The upper separation pattern 148 may be filled with an insulating material. For example, the upper separation pattern 148 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, example embodiments are not limited thereto, and the structure, shape, and material of the upper separation pattern 148 may be modified in various ways.

[0089] In order to connect the gate stack structure 120 and the channel structure CH provided in the cell array region 102 to the circuit region 200 or an external circuit, a connection region 104 and a second wiring portion 180 may be provided.

[0090] Here, the second wiring portion 180 may include a member for electrically connecting the gate electrode 130, the channel structure CH, the horizontal conductive layers 112 and 114, and / or the second substrate 110 to the circuit region 200 or an external circuit. For example, the second wiring portion 180 may include a bit line 182, a gate contact portion 184, a source contact portion 186, a penetration plug 188, contact vias 180a respectively connected thereto, and a connection wiring 190 for connecting them.

[0091] The bit line 182 may be disposed on the cell insulating layer 132 of the gate stack structure 120 formed in the cell array region 102. The bit line 182 may extend in a crossing direction (X-axis direction in the drawing) that crosses one direction in which the gate electrode 130 extends. The bit line 182 may be electrically connected to the channel structure CH (e.g., the channel pad 144) through a contact via 180a (e.g., a bit line contact via).

[0092] The connection region 104 may be disposed around the cell array region 102. A portion of the second wiring portion 180 may be disposed in the connection region 104. A member for connecting with the gate electrode 130, the horizontal conductive layers 112 and 114, and / or the second substrate 110, and the circuit region 200 may be provided in the connection region 104. In addition, the connection region 104 may include a portion on which an input / output pad and an input / output connection wiring are formed.

[0093] In more detail, the gate electrode 130 may extend in one direction (the Y-axis direction in the drawing) in the connection region 104, and the extension length of the gate electrode 130 may be sequentially reduced in the connection region 104 according to the distance from the second substrate 110. For example, the gate electrode 130 may be arranged in a stepped shape in the connection region 104. In this case, the gate electrode 130 may have a stepped shape in one direction or in multiple directions. In the connection region 104, the gate contact portion 184 may pass through the cell insulating layer 132 and may be electrically connected to each gate electrode 130 extending to the connection region 104.

[0094] In the connection area 104, the source contact portion 186 can penetrate the unit insulation layer 132 and can be electrically connected to the horizontal conductive layers 112 and 114 and / or the second substrate 110, and the penetration plug 188 can penetrate the gate stack structure 120, or can be arranged outside the gate stack structure 120, and can be electrically connected to the first wiring portion 230 of the circuit area 200.

[0095] The connection wiring 190 may be provided in the cell array region 102 and / or the connection region 104. The bit line 182, the gate contact portion 184, the source contact portion 186, and / or the penetration plug 188 may be electrically connected to the connection wiring 190. For example, the gate contact portion 184, the source contact portion 186, and / or the penetration plug 188 may be connected to the connection wiring 190 through the contact via 180a.

[0096] Figure 1 It is shown that the connection wiring 190 is provided as a single layer disposed on the same plane as the bit line 182, and the second insulating layer 192 is disposed on a portion other than the second wiring portion 180. However, this is briefly shown for the sake of convenience. Therefore, the connection wiring 190 includes a wiring layer for electrically connecting to the bit line 182, the gate contact portion 184, the source contact portion 186, and / or the penetration plug 188, and may further include a contact via.

[0097] As described above, the bit line 182 connected to the channel structure CH, the gate electrode 130 , the horizontal conductive layers 112 and 114 , and / or the second substrate 110 may be electrically connected to the circuit element 220 of the circuit region 200 through the second wiring portion 180 and the first wiring portion 230 .

[0098] Reference Figure 1 , in a cross-sectional view, the gate contact portion 184, the source contact portion 186, and / or the penetration plug 188 have inclined sides so that, according to the aspect ratio, their widths become narrower as they approach the second substrate 110, and a curved portion is provided at the boundary between the first gate stack structure 120a and the second gate stack structure 120b. However, example embodiments are not limited thereto. For example, the gate contact portion 184, the source contact portion 186, and / or the penetration plug 188 may not have a curved portion at the boundary between the first gate stack structure 120a and the second gate stack structure 120b. Various other variations are possible.

[0099] Figure 1 It is shown that the gate contact portion 184 passes through the cell insulating layer 132, reaches the gate electrode 130, and is connected to the gate electrode 130 in the connection region 104. However, not limited thereto, the gate contact portion 184 may pass through the cell insulating layer 132 and the gate electrode 130, and may extend to the first wiring portion 230 provided in the circuit region 200. In this case, the gate contact portion 184 includes a pad corresponding to the gate electrode 130 to be connected among the gate electrodes 130 included in the gate stack structure 120, and may be insulated from the other gate electrodes 130 by an insulating material.

[0100] Cst provided in the capacitor region 106 will now be described.

[0101] like Figure 1 and Figure 3 As shown, the capacitor Cst disposed in the capacitor region 106 may include a first capacitor Cst1 and a second capacitor Cst2. The semiconductor device further includes a first capacitor electrode 510 and a second capacitor electrode 520 disposed in the capacitor region 106. The first capacitor electrode 510 may overlap with the second capacitor electrode 520 to configure the first capacitor Cst1. The semiconductor device may further include a third capacitor electrode 530 disposed in the capacitor region 106. The second capacitor electrode 520 may overlap with the third capacitor electrode 530 to configure the second capacitor Cst2.

[0102] The first capacitor electrode 510 may be disposed on the same layer as the second substrate 110. The first capacitor electrode 510 may include the same material as the second substrate 110 and may be formed in the same process as the second substrate 110. For example, the first capacitor electrode 510 may include polysilicon doped with impurities. The first capacitor electrode 510 may have substantially the same thickness as the second substrate 110. The first capacitor electrode 510 may not be connected to the second substrate 110. That is, the first capacitor electrode 510 may be separated from the second substrate 110. Different voltages may be applied to the first capacitor electrode 510 and the second substrate 110.

[0103] The semiconductor device may further include a first voltage line 551 disposed in the capacitor region 106. The first voltage line 551 may be disposed on the same layer as the first wiring portion 230. For example, the first voltage line 551 may be disposed on the same layer as the wiring layer 236 and the floating electrode 230a. The first voltage line 551 may include the same material as the wiring layer 236 and the floating electrode 230a, and may be formed in the same process as the wiring layer 236 and the floating electrode 230a. For example, the first voltage line 551 may include a conductive material. The first voltage line 551 may be electrically connected to a predetermined circuit element and may receive a predetermined first voltage. The first capacitor electrode 510 may be connected to the first voltage line 551. The first capacitor electrode 510 may receive a first voltage through the first voltage line 551. The first voltage may be a constant voltage.

[0104] The insulating layer 560 may be disposed between the first capacitor electrode 510 and the first voltage line 551. The insulating layer 560 disposed between the first capacitor electrode 510 and the first voltage line 551 may be disposed on the same layer as the insulating layer 240 disposed between the second substrate 110 and the first wiring portion 230. The insulating layer 560 disposed between the first capacitor electrode 510 and the first voltage line 551 may include the same material as the insulating layer 240 disposed between the second substrate 110 and the first wiring portion 230, and may be formed in the same process as the insulating layer 240. The insulating layer 560 may be a single layer or multiple layers. For example, the insulating layer 560 may include a lower insulating layer 562 and an upper insulating layer 564 disposed on the lower insulating layer 562. The insulating layer 560 may include various types of insulating materials. For example, the lower insulating layer 562 may include silicon nitride, and the upper insulating layer 564 may include silicon oxide.

[0105] An opening is formed in the insulating layer 560 disposed between the first capacitor electrode 510 and the first voltage line 551. The first capacitor electrode 510 may be connected to the first voltage line 551 through the opening.

[0106] The second capacitor electrode 520 may be disposed on the same layer as the first horizontal conductive layer 112. The second capacitor electrode 520 may be disposed on the same layer as a portion of the first horizontal conductive layer 112. The second capacitor electrode 520 may be thinner than the first horizontal conductive layer 112. The second capacitor electrode 520 may not be connected to the first horizontal conductive layer 112. That is, the second capacitor electrode 520 may be separated from the first horizontal conductive layer 112. Different voltages may be applied to the second capacitor electrode 520 and the first horizontal conductive layer 112. The second capacitor electrode 520 may be disposed on the same layer as the horizontal insulating layer 116. The second capacitor electrode 520 may be disposed on the same layer as a portion of the horizontal insulating layer 116. For example, the second capacitor electrode 520 may be disposed on the same layer as the middle layer 116b of the horizontal insulating layer 116. The thickness of the second capacitor electrode 520 may be substantially equal to the thickness of the middle layer 116b of the horizontal insulating layer 116. The second capacitor electrode 520 may include a conductive material. For example, the second capacitor electrode 520 may include tungsten and polysilicon doped with impurities.

[0107] The semiconductor device may further include a first dielectric layer 542 disposed between the first capacitor electrode 510 and the second capacitor electrode 520. The first dielectric layer 542 may be disposed on the same layer as the first horizontal conductive layer 112. The first dielectric layer 542 may be disposed on the same layer as another portion of the first horizontal conductive layer 112. The first dielectric layer 542 may be thinner than the first horizontal conductive layer 112. In addition, the first dielectric layer 542 may be disposed on the same layer as the horizontal insulating layer 116. The first dielectric layer 542 may be disposed on the same layer as another portion of the horizontal insulating layer 116. For example, the first dielectric layer 542 may be disposed on the same layer as the lower layer 116a of the horizontal insulating layer 116. The thickness of the first dielectric layer 542 may be substantially equal to the thickness of the lower layer 116a of the horizontal insulating layer 116. The first dielectric layer 542 may include an insulating material. For example, the first dielectric layer 542 may include silicon oxide.

[0108] The semiconductor device may further include a second voltage line 553 disposed in the capacitor region 106. The second voltage line 553 may be disposed on the same layer as the second wiring portion 180. The second voltage line 553 may include the same material as the second wiring portion 180 and may be formed in the same process as the second wiring portion 180. For example, the second voltage line 553 may include a conductive material. The second voltage line 553 may be electrically connected to a predetermined circuit element and may receive a predetermined second voltage. The second capacitor electrode 520 may be connected to the second voltage line 553. The second capacitor electrode 520 may receive a second voltage through the second voltage line 553. The second voltage may be a constant voltage.

[0109] The semiconductor device may further include a connection structure 555 for connecting the second capacitor electrode 520 and the second voltage line 553. The connection structure 555 may extend in the same direction as the channel structure CH (Z-axis direction in the drawings). The connection structure 555 may also extend in the same direction as the gate contact portion 184, the source contact portion 186, and the penetration plug 188. The connection structure 555 may include a conductive material. For example, the connection structure 555 may include tungsten. The second capacitor electrode 520 may be connected to the second voltage line 553 through the connection structure 555.

[0110] The third capacitor electrode 530 may be disposed on the same layer as the second horizontal conductive layer 114. The third capacitor electrode 530 may include the same material as the second horizontal conductive layer 114 and may be formed in the same process as the second horizontal conductive layer 114. For example, the third capacitor electrode 530 may include polysilicon doped with impurities. The third capacitor electrode 530 may have a thickness substantially equal to that of the second horizontal conductive layer 114. The third capacitor electrode 530 may not be connected to the second horizontal conductive layer 114. That is, the third capacitor electrode 530 may be separated from the second horizontal conductive layer 114. Different voltages may be applied to the third capacitor electrode 530 and the second horizontal conductive layer 114.

[0111] The third capacitor electrode 530 may be connected to the first capacitor electrode 510. The third capacitor electrode 530 may be connected to the first voltage line 551 through the first capacitor electrode 510. The third capacitor electrode 530 may receive the first voltage through the first capacitor electrode 510 and the first voltage line 551.

[0112] The third capacitor electrode 530 may include an open region. The connection structure 555 may be disposed in the open region of the third capacitor electrode 530. Therefore, the connection structure 555 may not be connected to the third capacitor electrode 530.

[0113] The semiconductor device may further include a second dielectric layer 544 disposed between the second capacitor electrode 520 and the third capacitor electrode 530. The second dielectric layer 544 may be disposed on the same layer as the first horizontal conductive layer 112. The second dielectric layer 544 may be disposed on the same layer as another portion of the first horizontal conductive layer 112. The second dielectric layer 544 may be thinner than the first horizontal conductive layer 112. The second dielectric layer 544 may also be disposed on the same layer as the horizontal insulating layer 116. The second dielectric layer 544 may be disposed on the same layer as another portion of the horizontal insulating layer 116. For example, the second dielectric layer 544 may be disposed on the same layer as the upper layer 116c of the horizontal insulating layer 116. The thickness of the second dielectric layer 544 may be substantially equal to the thickness of the upper layer 116c of the horizontal insulating layer 116. The second dielectric layer 544 may include an insulating material. For example, the second dielectric layer 544 may include silicon oxide.

[0114] The semiconductor device may include a first capacitor Cst1 configured with a first capacitor electrode 510 and a second capacitor electrode 520, which overlap each other with a first dielectric layer 542 therebetween. The semiconductor device may include a second capacitor Cst2 configured with a second capacitor electrode 520 and a third capacitor electrode 530, which overlap each other with a second dielectric layer 544 therebetween. The respective electrodes configuring the capacitor, the dielectric layer disposed between the electrodes, and the voltage lines connected to the electrodes may be disposed on the same layer as the constituent elements disposed in the circuit region 200 and the cell region 100. That is, by forming the capacitor Cst in the capacitor region 106 by using the constituent elements disposed in the circuit region 200 and the cell region 100, the process may be simplified and the integration may be improved.

[0115] The shapes and arrangements of the first capacitor electrode, the second capacitor electrode, and the third capacitor electrode and the positions and shapes of the wiring for transmitting voltage to the electrodes can be modified in a variety of ways, some of which will now be described. However, these ways are not limited thereto, and a person of ordinary skill in the art can expect many variations.

[0116] Now refer to Figure 4 A semiconductor device according to example embodiments is described.

[0117] Figure 4 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown. Figure 4 A portion of a capacitor region of a semiconductor device according to example embodiments is shown.

[0118] according to Figure 4 The semiconductor device of the exemplary embodiment shown corresponds largely to the Figures 1 to 3 The semiconductor device of the example embodiment shown in the figure is not a semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. This example embodiment is partially different from the previous example embodiment in that the third capacitor electrode is not directly connected to the first capacitor electrode, which will be described below.

[0119] A semiconductor device may include a cell region, a circuit region, and a capacitor region. Figure 4 As shown, the semiconductor device may include a capacitor Cst disposed in a capacitor region. The capacitor Cst may include a first capacitor Cst1 and a second capacitor Cst2.

[0120] The semiconductor device includes a first capacitor electrode 1510 and a second capacitor electrode 1520 disposed in a capacitor region. The first capacitor electrode 1510 and the second capacitor electrode 1520 may overlap each other to configure a first capacitor Cst1. The semiconductor device may further include a third capacitor electrode 1530 disposed in the capacitor region. The second capacitor electrode 1520 and the third capacitor electrode 1530 may overlap each other to configure a second capacitor Cst2.

[0121] The semiconductor device may further include a first voltage line 1551 disposed in the capacitor region. The first capacitor electrode 1510 may be connected to the first voltage line 1551. The first capacitor electrode 1510 may receive a first voltage through the first voltage line 1551. An insulating layer 1560 may be disposed between the first capacitor electrode 1510 and the first voltage line 1551. The insulating layer 1560 may include a lower insulating layer 1562 and an upper insulating layer 1564. An opening may be formed in the insulating layer 1560, and the first capacitor electrode 1510 may be connected to the first voltage line 1551 through the opening.

[0122] The semiconductor device may further include a first dielectric layer 1542 disposed between the first capacitor electrode 1510 and the second capacitor electrode 1520. The first capacitor electrode 1510 and the second capacitor electrode 1520 overlap each other with the first dielectric layer 1542 therebetween to configure a first capacitor Cst1.

[0123] The semiconductor device may further include a connection structure 1555 connected to the second capacitor electrode 1520. The connection structure 1555 may extend in a direction perpendicular to the first substrate (Z-axis direction in the drawing). Although not shown, the connection structure 1555 may be connected to a second voltage line. The second capacitor electrode 1520 may be connected to the second voltage line through the connection structure 1555 and may receive a second voltage from the second voltage line.

[0124] The semiconductor device may further include a third voltage line 1557 disposed in the capacitor region. The third voltage line 1557 may be disposed on the same layer as the first voltage line 1551. The third voltage line 1557 may include the same material as the first voltage line 1551 and may be formed in the same process as the first voltage line 1551. The third voltage line 1557 may be electrically connected to a predetermined circuit element and may receive a predetermined third voltage. The third capacitor electrode 1530 may be connected to the third voltage line 1557. The third capacitor electrode 1530 may receive a third voltage through the third voltage line 1557. The third voltage may be a constant voltage. In this case, the third voltage may be equal to / different from the first voltage. That is, the same voltage / different voltage may be applied to the first capacitor electrode 1510 and the third capacitor electrode 1530. The insulating layer 1560 may be disposed between the third capacitor electrode 1530 and the third voltage line 1557. An opening may be formed in the insulating layer 1560, and the third capacitor electrode 1530 may be connected to the third voltage line 1557 through the opening.

[0125] The semiconductor device may further include a second dielectric layer 1544 disposed between the second capacitor electrode 1520 and the third capacitor electrode 1530. The second capacitor electrode 1520 and the third capacitor electrode 1530 may overlap each other with the second dielectric layer 1544 therebetween to configure a second capacitor Cst2.

[0126] The respective electrodes of the capacitor disposed in the capacitor region of the semiconductor device, the dielectric layer disposed between the electrodes, and the voltage lines connected to the electrodes may be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming the capacitor Cst in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process may be simplified and the integration may be improved.

[0127] Now refer to Figure 5 A semiconductor device according to example embodiments is described.

[0128] Figure 5 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown. Figure 5 A portion of a capacitor region of a semiconductor device according to example embodiments is shown.

[0129] according to Figure 5 The semiconductor device of the exemplary embodiment shown corresponds largely to the Figures 1 to 3The semiconductor device of the example embodiment shown in the figure is not limited to the semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. In this example embodiment, it is partially different from the previous example embodiment in that it further includes structures connected to the first capacitor electrode and the third capacitor electrode, respectively.

[0130] A semiconductor device may include a cell region, a circuit region, and a capacitor region. Figure 5 As shown, the semiconductor device may include a capacitor Cst disposed in a capacitor region. The capacitor Cst may include a first capacitor Cst1 and a second capacitor Cst2.

[0131] The semiconductor device may include a first capacitor electrode 2510 and a second capacitor electrode 2520 disposed in a capacitor region and a first dielectric layer 2542 disposed therebetween. The first capacitor electrode 2510 and the second capacitor electrode 2520 may overlap each other with the first dielectric layer 2542 therebetween to configure a first capacitor Cst1. The semiconductor device may further include a third capacitor electrode 2530 disposed in the capacitor region and a second dielectric layer 2544 disposed between the second capacitor electrode 2520 and the third capacitor electrode 2530. The second capacitor electrode 2520 and the third capacitor electrode 2530 may overlap each other with the second dielectric layer 2544 therebetween to configure a second capacitor Cst2.

[0132] The semiconductor device may further include a first connection structure 2555a connected to the first capacitor electrode 2510. The first connection structure 2555a may extend in a direction perpendicular to the first substrate (Z-axis direction in the drawing). Although not shown, the semiconductor device may further include a first voltage line for applying a first voltage, and the first connection structure 2555a may be connected to the first voltage line. The first capacitor electrode 2510 may be connected to the first voltage line through the first connection structure 2555a, and may receive a first voltage from the first voltage line.

[0133] The semiconductor device may further include a second connection structure 2555b connected to the second capacitor electrode 2520. The second connection structure 2555b may extend in a direction perpendicular to the first substrate (Z-axis direction in the drawings). Although not shown, the semiconductor device may further include a second voltage line for applying a second voltage, and the second connection structure 2555b may be connected to the second voltage line. The second capacitor electrode 2520 may be connected to the second voltage line through the second connection structure 2555b, and may receive a second voltage from the second voltage line.

[0134] The semiconductor device may further include a third connection structure 2555c connected to the third capacitor electrode 2530. The third connection structure 2555c may extend in a direction perpendicular to the first substrate (Z-axis direction in the drawing). Although not shown, the semiconductor device may further include a third voltage line for applying a third voltage, and the third connection structure 2555c may be connected to the third voltage line. The third capacitor electrode 2530 may be connected to the third voltage line through the third connection structure 2555c, and may receive a third voltage from the third voltage line.

[0135] The respective electrodes of the capacitor disposed in the capacitor region of the semiconductor device, the dielectric layer disposed between the electrodes, and the voltage lines connected to the electrodes may be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming the capacitor Cst in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process may be simplified and the integration may be improved.

[0136] Now refer to Figure 6 A semiconductor device according to example embodiments is described.

[0137] Figure 6 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown. Figure 6 A portion of a capacitor region of a semiconductor device according to example embodiments is shown.

[0138] according to Figure 6 The semiconductor device of the exemplary embodiment shown corresponds largely to the Figure 5 The semiconductor device of the example embodiment shown in the figure is not a semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. In this example embodiment, the position and shape of the second capacitor electrode and the third capacitor electrode are partially different from the previous example embodiment, which will be described below.

[0139] A semiconductor device may include a cell region, a circuit region, and a capacitor region. Figure 6 As shown, the semiconductor device may include a capacitor Cst disposed in a capacitor region. The capacitor Cst may include a first capacitor Cst1 and a second capacitor Cst2.

[0140] The semiconductor device includes a first capacitor electrode 3510 and a second capacitor electrode 3520 disposed in a capacitor region and a first dielectric layer 3542 disposed therebetween. The first capacitor electrode 3510 and the second capacitor electrode 3520 may overlap each other with the first dielectric layer 3542 therebetween to configure a first capacitor Cst1. The first capacitor electrode 3510 may be connected to a first connection structure 3555a, and the second capacitor electrode 3520 may be connected to a second connection structure 3555b. The semiconductor device may further include a third capacitor electrode 3530 disposed in the capacitor region and a second dielectric layer 3544 disposed between the second capacitor electrode 3520 and the third capacitor electrode 3530. The second capacitor electrode 3520 and the third capacitor electrode 3530 may overlap each other with the second dielectric layer 3544 therebetween to configure a second capacitor Cst2.

[0141] In the previous example embodiment, at least a portion of the third capacitor electrode 2530 may be disposed at a lower level than the second capacitor electrode 2520. In this case, an insulating layer may be disposed between the side of the second capacitor electrode 2520 and the third capacitor electrode 2530. In the present example embodiment, the third capacitor electrode 3530 may be disposed at a higher level than the second capacitor electrode 3520. In this case, the third capacitor electrode 3530 may face the upper face of the second capacitor electrode 3520, and may not face the side of the second capacitor electrode 3520.

[0142] The respective electrodes of the capacitor disposed in the capacitor region of the semiconductor device, the dielectric layer disposed between the electrodes, and the voltage lines connected to the electrodes may be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming the capacitor Cst in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process may be simplified and the integration may be improved.

[0143] Now refer to Figure 7 A semiconductor device according to example embodiments is described.

[0144] Figure 7 A cross-sectional view of a semiconductor device according to example embodiments is shown.

[0145] Figure 7 The example embodiments shown correspond largely to Figures 1 to 3The example embodiment shown in the figure is not shown, so its description will be omitted, and the differences will be mainly described. In addition, the same or similar reference numerals are used for the same or similar components as the components of the previous example embodiment. This example embodiment is partially different from the previous example embodiment in that the unit area is inverted, which will now be described.

[0146] Reference Figure 7 , the semiconductor device 20 may have a chip-to-chip (C2C) structure bonded by a wafer bonding method. That is, a lower chip including a circuit region 200a formed on a first substrate 210 is manufactured, an upper chip including a cell region 100a formed on a second substrate 110 is manufactured, and they may be bonded to manufacture the semiconductor device 20. The semiconductor device 20 may further include a capacitor region 106, a portion of the capacitor region 106 may be included in the lower chip, and another portion of the capacitor region 106 may be included in the upper chip.

[0147] The circuit region 200 a may have a first bonding structure 238 on the first substrate 210 , the circuit element 220 , and the first wiring portion 230 on a face facing the cell region 100 a .

[0148] The cell region 100 a may have a second bonding structure 194 on the second substrate 110 , the gate stack structure 120 , the channel structure CH, and the second wiring portion 180 on a face facing the circuit region 200 a .

[0149] The semiconductor device includes a first capacitor electrode 4510 and a second capacitor electrode 4520 disposed in the capacitor region 106 and a first dielectric layer 4542 disposed therebetween. The first capacitor electrode 4510 and the second capacitor electrode 4520 may overlap each other with the first dielectric layer 4542 therebetween to configure a first capacitor. The semiconductor device may further include a third capacitor electrode 4530 disposed in the capacitor region and a second dielectric layer 4544 disposed between the second capacitor electrode 4520 and the third capacitor electrode 4530. The second capacitor electrode 4520 and the third capacitor electrode 4530 may overlap each other with the second dielectric layer 4544 therebetween to configure a second capacitor.

[0150] The semiconductor device may further include a first voltage line 4551 disposed in the capacitor region 106. The semiconductor device may further include a first connection structure 4555a connected to the first voltage line 4551. The first capacitor electrode 4510 may be connected to the third capacitor electrode 4530. The third capacitor electrode 4530 may be connected to the first voltage line 4551 through the first connection structure 4555a. The first capacitor electrode 4510 and the third capacitor electrode 4530 may receive a first voltage from the first voltage line 4551.

[0151] The semiconductor device may further include a second voltage line 4553 disposed in the capacitor region 106. The semiconductor device may further include a second connection structure 4555b connected to the second voltage line 4553. The second capacitor electrode 4520 may be connected to the second voltage line 4553 through the second connection structure 4555b. The second capacitor electrode 4520 may receive a second voltage from the second voltage line 4553.

[0152] Regarding the gate stack structure 120, the gate electrode 130 may run from the second substrate 110 to the circuit region 200a, and may include a lower gate electrode 130L, a memory cell gate electrode 130M, and an upper gate electrode 130U sequentially disposed on the second substrate 110. Figure 7 As shown, the gate stack structure 120 can be sequentially stacked below the second substrate 110, so Figures 1 to 2B The gate stack structure 120 shown may be arranged upside down.

[0153] Therefore, the channel pad 144 and the second wiring portion 180 disposed on the gate stack structure 120 can be disposed close to the circuit region 200a. The second bonding structure 194 electrically connected to the second wiring portion 180 can be provided on the face opposite to the circuit region 200a. Other regions except the second bonding structure 194 can be covered by the insulating layer 196. As described, in the cell region 100a, the second wiring portion 180 and the second bonding structure 194 can be opposite to the circuit region 200a.

[0154] For example, the second bonding structure 194 of the cell region 100a and the first bonding structure 238 of the circuit region 200a may be made of aluminum, copper, tungsten or alloys thereof. For example, the first bonding structure 238 and the second bonding structure 194 may include copper, so that the cell region 100a and the circuit region 200a may be connected by copper-to-copper bonding (e.g., may be in direct contact with each other and may be bonded).

[0155] Figure 7 The gate stack structure 120 is shown as a single gate stack structure. Figure 1As shown, the gate stack structure 120 may include a plurality of gate stack structures. Figures 1 to 2B Description of the configurations of the gate stack structure 120 and the channel structure CH are described. Figure 7 The electrical connection configuration of the channel structure CH to the horizontal conductive layers 112 and 114 and / or the second substrate 110 corresponds to the reference Figure 1 Example embodiments are not limited thereto, and the electrical connection configuration of the channel structure CH to the horizontal conductive layers 112 and 114 and / or the second substrate 110 may be modified in various ways. For example, in a manner similar to that described below Fig.33 In a similar manner, the channel layer of the channel structure CH may protrude compared to the gate dielectric layer and may contact the second substrate 110 .

[0156] The semiconductor device 20 may include an input / output pad 198 and an input / output connection wiring 198a electrically connected thereto. The input / output connection wiring 198a may be electrically connected to a portion of the second bonding structure 194. The input / output pad 198 may be, for example, disposed on an insulating layer 198b for covering an outer face of the second substrate 110. According to example embodiments, an additional input / output pad electrically connected to the circuit region 200a may be provided.

[0157] For example, the circuit region 200a and the unit region 100a may correspond to Fig.41 The first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 are shown. Optionally, the circuit region 200a and the unit region 100a may correspond to Fig.44 The semiconductor chip 2200 is shown with a first structure 4100 and a second structure 4200 .

[0158] Now refer to Figure 8 A semiconductor device according to example embodiments is described.

[0159] Figure 8 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown. Figure 8 1 shows a boundary between a circuit region and a cell region and a portion of a capacitor region of a semiconductor device according to an example embodiment. Figure 8 , the left area may correspond to the boundary between the circuit area and the unit area, and the right area may correspond to the capacitor area.

[0160] according to Figure 8 The semiconductor device of the exemplary embodiment shown corresponds largely to the Figures 1 to 3The semiconductor device of the example embodiment shown in the figure is not limited to the semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. The present example embodiment is partially different from the previous example embodiment in that the second capacitor electrode can be provided on the same layer as the first wiring portion, which will be described below.

[0161] like Figure 8 As shown, the semiconductor device includes a second substrate 110 and a floating electrode 230a connected to the second substrate 110. An insulating layer 240 may be disposed between the second substrate 110 and the floating electrode 230a. The insulating layer 240 may include a lower insulating layer 242, an upper insulating layer 244, and a dummy insulating layer 246. An opening may be formed in the insulating layer 240, and the second substrate 110 may be connected to the floating electrode 230a through the opening.

[0162] The semiconductor device includes a first capacitor electrode 5510, a second capacitor electrode 5520, and a first dielectric layer 5542 disposed therebetween. The first capacitor electrode 5510 and the second capacitor electrode 5520 may overlap each other with the first dielectric layer 5542 therebetween to configure a capacitor. The first dielectric layer 5542 may be disposed on the same layer as the dummy insulating layer 246. The first dielectric layer 5542 may include the same material as the dummy insulating layer 246 and may be formed in the same process as the dummy insulating layer 246.

[0163] The first capacitor electrode 5510 may be disposed on the same layer as the second substrate 110. The first capacitor electrode 5510 may include the same material as the second substrate 110 and may be formed in the same process as the second substrate 110. The first capacitor electrode 5510 may have a thickness substantially equal to that of the second substrate 110. The first capacitor electrode 5510 may not be connected to the second substrate 110. That is, the first capacitor electrode 5510 may be separated from the second substrate 110. Different voltages may be applied to the first capacitor electrode 5510 and the second substrate 110.

[0164] The semiconductor device may further include a first voltage line 5551. The first voltage line 5551 may be disposed on the same layer as the first wiring portion (e.g., the floating electrode 230a). The first voltage line 5551 may include the same material as the floating electrode 230a and may be formed in the same process as the floating electrode 230a. The first capacitor electrode 5510 may be connected to the first voltage line 5551. The first capacitor electrode 5510 may receive a first voltage through the first voltage line 5551.

[0165] The insulating layer 5560 and the first dielectric layer 5542 may be disposed between the first capacitor electrode 5510 and the first voltage line 5551. The insulating layer 5560 disposed between the first capacitor electrode 5510 and the first voltage line 5551 may be disposed on the same layer as at least a portion of the insulating layer 240 disposed between the second substrate 110 and the floating electrode 230a. The insulating layer 5560 may be a single layer or multiple layers. For example, the insulating layer 5560 may include a lower insulating layer 5562 and an upper insulating layer 5564. An opening is formed in the insulating layer 5560 and the first dielectric layer 5542, and the first capacitor electrode 5510 may be connected to the first voltage line 5551 through the opening.

[0166] The second capacitor electrode 5520 may be disposed on the same layer as the first wiring portion (e.g., the floating electrode 230a). The second capacitor electrode 5520 may include the same material as the floating electrode 230a and may be formed in the same process as the floating electrode 230a. The insulating layer 5560 may include an opening overlapping with the second capacitor electrode 5520, and the first dielectric layer 5542 and the first capacitor electrode 5510 may be disposed in the opening. In the opening, the first capacitor electrode 5510 may overlap with the second capacitor electrode 5520 with the first dielectric layer 5542 therebetween.

[0167] The respective electrodes of the capacitor disposed in the capacitor region of the semiconductor device, the dielectric layer disposed between the electrodes, and the voltage lines connected to the electrodes can be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming a capacitor in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process can be simplified and the integration can be improved.

[0168] Now refer to Figures 9 to 12 A method of manufacturing a semiconductor device according to example embodiments is described.

[0169] Figures 9 to 12 Process cross-sectional views of parts of a method of manufacturing a semiconductor device according to example embodiments are sequentially shown. Figures 9 to 12 Shows the manufacturing method Figure 8 A process for a semiconductor device according to an example embodiment is shown.

[0170] like Fig. 9As shown, the floating electrode 230a, the first voltage line 5551 and the second capacitor electrode 5520 are formed by using a conductive material. For example, the floating electrode 230a, the first voltage line 5551 and the second capacitor electrode 5520 may be formed by depositing a conductive material and patterning the conductive material. The floating electrode 230a, the first voltage line 5551 and the second capacitor electrode 5520 may be spaced apart from each other. Although not shown, various constituent elements included in the first wiring portion and the floating electrode 230a may be formed together.

[0171] The lower insulating layers 242 and 5562 and the upper insulating layers 244 and 5564 may be sequentially formed on the floating electrode 230a, the first voltage line 5551, and the second capacitor electrode 5520 by using an insulating material. In this case, the lower insulating layers 242 and 5562 may include silicon nitride, and the upper insulating layers 244 and 5564 may include silicon oxide. However, the materials of the lower insulating layers 242 and 5562 and the upper insulating layers 244 and 5564 are not limited thereto and may be modified in various ways.

[0172] The opening 5561 is formed by patterning the insulating layer 5560 covering the second capacitor electrode 5520. At least a portion of an upper face of the second capacitor electrode 5520 may be exposed through the opening 5561 formed in the insulating layer 5560.

[0173] like Fig.10 As shown, a first dielectric layer 5542 is formed on an insulating layer 5560 in which an opening 5561 is formed by using an insulating material. For example, the first dielectric layer 5542 may be formed by depositing silicon oxide. The first dielectric layer 5542 may be formed in the opening 5561 of the insulating layer 5560. The first dielectric layer 5542 may be disposed on the second capacitor electrode 5520 in the opening 5561. In this case, the first dielectric layer 5542 may have a conformal shape in the opening 5561.

[0174] When forming the first dielectric layer 5542, a dummy insulating layer 246 may be formed. The dummy insulating layer 246 may form the insulating layer 240 together with the lower insulating layer 242 and the upper insulating layer 244. The dummy insulating layer 246 may include the same material as the first dielectric layer 5542 and may have a thickness substantially equal to that of the first dielectric layer 5542.

[0175] like Fig.11As shown, openings 241 and 5563 are formed by patterning the insulating layers 240 and 5560 and the first dielectric layer 5542. At least a portion of the upper surface of the floating electrode 230a may be exposed through the opening 241 formed in the insulating layer 240. At least a portion of the upper surface of the first voltage line 5551 may be exposed through the opening 5563 formed in the insulating layer 5560.

[0176] like Fig.12 As shown, the second substrate 110 and the first capacitor electrode 5510 are formed on the insulating layers 240 and 5560 and the first dielectric layer 5542 by using a conductive material. For example, the second substrate 110 and the first capacitor electrode 5510 can be formed by using polysilicon. In this case, the second substrate 110 can fill the opening 241. The second substrate 110 can be connected to the floating electrode 230a through the opening 241. In addition, the first capacitor electrode 5510 can fill the opening 5563. The first capacitor electrode 5510 can be connected to the first voltage line 5551 through the opening 5563.

[0177] The first capacitor electrode 5510 and the second capacitor electrode 5520 may overlap each other in the opening 5561 with the first dielectric layer 5542 therebetween to configure a capacitor.

[0178] Now refer to Fig.13 A semiconductor device according to example embodiments is described.

[0179] Fig.13 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0180] according to Fig.13 The semiconductor device of the exemplary embodiment shown corresponds largely to the Figure 8 The semiconductor device of the example embodiment shown in the figure is not limited to the semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. This example embodiment is partially different from the previous example embodiment in that the barrier layer is provided under the first capacitor electrode, which will be described below.

[0181] like Fig.13 As shown, the semiconductor device includes a first capacitor electrode 5510, a second capacitor electrode 5520, and a first dielectric layer 5542 disposed therebetween. A barrier layer 5510s may be further disposed below the first capacitor electrode 5510. The barrier layer 5510s may include a conductive material, for example, it may include a metal nitride. For example, the barrier layer 5510s may include titanium nitride.

[0182] In the previous example embodiment, the first capacitor electrode 5510 may contact the first voltage line 5551, and in the present example embodiment, the first capacitor electrode 5510 may not contact the first voltage line 5551. In the present example embodiment, a barrier layer 5510s may be disposed between the first capacitor electrode 5510 and the first voltage line 5551. The barrier layer 5510s may be disposed between the first capacitor electrode 5510 and the first dielectric layer 5542.

[0183] A dummy barrier layer 110s may be further disposed under the second substrate 110. The dummy barrier layer 110s may be disposed on the same layer as the barrier layer 5510s. The dummy barrier layer 110s may include the same material as the barrier layer 5510s and may be formed in the same process as the barrier layer 5510s. The dummy barrier layer 110s may be disposed between the second substrate 110 and the floating electrode 230a. The dummy barrier layer 110s may be disposed between the second substrate 110 and the insulating layer 240.

[0184] Now refer to Fig.14 A semiconductor device according to example embodiments is described.

[0185] Fig.14 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0186] according to Fig.14 The semiconductor device of the exemplary embodiment shown corresponds largely to the Figures 1 to 3 The semiconductor device of the example embodiment shown in the figure is not limited to the semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. This example embodiment is partially different from the previous example embodiment in that the second capacitor electrode can be provided on the same layer as the second substrate, which will be described below.

[0187] like Fig.14 As shown, the semiconductor device includes a second substrate 110 and a floating electrode 230a connected to the second substrate 110. An insulating layer 240 may be disposed between the second substrate 110 and the floating electrode 230a. The insulating layer 240 may include a lower insulating layer 242 and an upper insulating layer 244. An opening may be formed in the insulating layer 240, and the second substrate 110 may be connected to the floating electrode 230a through the opening.

[0188] The second substrate 110 may include a first layer 110a and a second layer 110b stacked in sequence. The second layer 110b may be disposed on the first layer 110a. That is, the bottom surface of the second layer 110b may contact the upper surface of the first layer 110a. The first layer 110a and the second layer 110b of the second substrate 110 may include a conductive material. The first layer 110a and the second layer 110b may include the same material, or may include different materials. The thickness of the first layer 110a may be substantially equal to the thickness of the second layer 110b. However, not limited thereto, the thickness of the first layer 110a may be different from the thickness of the second layer 110b.

[0189] The semiconductor device includes a first capacitor electrode 6510, a second capacitor electrode 6520, and a first dielectric layer 6542 disposed therebetween. The first capacitor electrode 6510 and the second capacitor electrode 6520 may overlap each other with the first dielectric layer 6542 therebetween to configure a capacitor.

[0190] The first capacitor electrode 6510 may be disposed on the same layer as the first layer 110a of the second substrate 110. The first capacitor electrode 6510 may include the same material as the first layer 110a of the second substrate 110, and may be formed in the same process as the first layer 110a. The first capacitor electrode 6510 may have a thickness substantially equal to that of the first layer 110a of the second substrate 110. The first capacitor electrode 6510 may not be connected to the first layer 110a of the second substrate 110. That is, the first capacitor electrode 6510 may be separated from the first layer 110a of the second substrate 110. Different voltages may be applied to the first capacitor electrode 6510 and the first layer 110a of the second substrate 110.

[0191] The semiconductor device may further include a first voltage line 6551. The first voltage line 6551 may be disposed on the same layer as the first wiring portion (e.g., the floating electrode 230a). The first voltage line 6551 may include the same material as the floating electrode 230a and may be formed in the same process as the floating electrode 230a. The first capacitor electrode 6510 may be connected to the first voltage line 6551. The first capacitor electrode 6510 may receive a first voltage through the first voltage line 6551.

[0192] The insulating layer 6560 may be disposed between the first capacitor electrode 6510 and the first voltage line 6551. The insulating layer 6560 disposed between the first capacitor electrode 6510 and the first voltage line 6551 may be disposed on the same layer as the insulating layer 240 disposed between the second substrate 110 and the floating electrode 230a. The insulating layer 6560 may be a single layer or multiple layers. For example, the insulating layer 6560 may include a lower insulating layer 6562 and an upper insulating layer 6564. An opening is formed in the insulating layer 6560, and the first capacitor electrode 6510 may be connected to the first voltage line 6551 through the opening.

[0193] The second capacitor electrode 6520 may be disposed on the same layer as the second layer 110b of the second substrate 110. The second capacitor electrode 6520 may include the same material as the second layer 110b of the second substrate 110 and may be formed in the same process as the second layer 110b. The second capacitor electrode 6520 may have a thickness substantially equal to that of the second layer 110b of the second substrate 110. The second capacitor electrode 6520 may not be connected to the second layer 110b of the second substrate 110. That is, the second capacitor electrode 6520 may be separated from the second layer 110b of the second substrate 110. Different voltages may be applied to the second capacitor electrode 6520 and the second layer 110b of the second substrate 110. The thickness of the second capacitor electrode 6520 may be substantially equal to the thickness of the first capacitor electrode 6510. However, not limited thereto, the thickness of the second capacitor electrode 6520 may be different from the thickness of the first capacitor electrode 6510. The sum of the thickness of the first capacitor electrode 6510 and the thickness of the second capacitor electrode 6520 may correspond to the thickness of the second substrate 110.

[0194] The semiconductor device may further include a second voltage line 6553. The second voltage line 6553 may be disposed on the same layer as the first wiring portion (e.g., the floating electrode 230a). The second voltage line 6553 may include the same material as the floating electrode 230a and may be formed in the same process as the floating electrode 230a. The second voltage line 6553 may be disposed on the same layer as the first voltage line 6551. The second voltage line 6553 may include the same material as the first voltage line 6551 and may be formed in the same process as the first voltage line 6551. The second capacitor electrode 6520 may be connected to the second voltage line 6553. The second capacitor electrode 6520 may receive a second voltage through the second voltage line 6553.

[0195] The insulating layer 6560 and the first capacitor electrode 6510 may be disposed between the second capacitor electrode 6520 and the second voltage line 6553. An opening may be formed in the insulating layer 6560 and the first capacitor electrode 6510. Sidewalls of the openings of the insulating layer 6560 and the first capacitor electrode 6510 may be covered by the first dielectric layer 6542. An opening overlapping the second voltage line 6553 may be formed in the first dielectric layer 6542, and the second capacitor electrode 6520 may be connected to the second voltage line 6553 through the opening.

[0196] The respective electrodes of the capacitor disposed in the capacitor region of the semiconductor device, the dielectric layer disposed between the electrodes, and the voltage lines connected to the electrodes can be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming a capacitor in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process can be simplified and the integration can be improved.

[0197] Now refer to Figures 15 to 19 A method of manufacturing a semiconductor device according to example embodiments is described.

[0198] Figures 15 to 19 Process cross-sectional views of parts of a method of manufacturing a semiconductor device according to example embodiments are sequentially shown. Figures 15 to 19 Shows the manufacturing method Fig.14 A process for a semiconductor device according to an example embodiment is shown.

[0199] like Fig.15 As shown, the floating electrode 230a, the first voltage line 6551 and the second voltage line 6553 are formed by using a conductive material. For example, a conductive material may be deposited, and then the conductive material may be patterned to form the floating electrode 230a, the first voltage line 6551 and the second voltage line 6553. The floating electrode 230a, the first voltage line 6551 and the second voltage line 6553 may be spaced apart from each other. Although not shown, various constituent elements included in the first wiring portion and the floating electrode 230a may be formed together.

[0200] The lower insulating layers 242 and 6562 and the upper insulating layers 244 and 6564 are formed on the floating electrode 230a, the first voltage line 6551 and the second voltage line 6553 by using an insulating material. In this case, the lower insulating layers 242 and 6562 may include silicon nitride, and the upper insulating layers 244 and 6564 may include silicon oxide. However, the materials of the lower insulating layers 242 and 6562 and the upper insulating layers 244 and 6564 are not limited thereto, and they may be changed with many other substances.

[0201] The insulating layers 240 and 6560 are patterned to form an opening for exposing at least a portion of an upper surface of the floating electrode 230 a , and to form an opening for exposing at least a portion of an upper surface of the first voltage line 6551 .

[0202] The first layer 110a of the second substrate 110 and the first capacitor electrode 6510 are formed on the insulating layers 240 and 6560 by using a conductive material. The first layer 110a of the second substrate 110 may be connected to the floating electrode 230a through an opening formed in the insulating layer 240. The first capacitor electrode 6510 may be connected to the first voltage line 6551 through an opening formed in the insulating layer 6560.

[0203] like Fig.16 As shown, an opening 6561 for exposing at least a portion of an upper surface of the second voltage line 6553 is formed by patterning the first capacitor electrode 6510 and the insulating layer 6560 .

[0204] like Fig.17 As shown, a first dielectric layer 6542 is formed on the first capacitor electrode 6510 by using an insulating material. For example, the first dielectric layer 6542 may be formed by depositing silicon oxide. The first dielectric layer 6542 may be formed in the opening 6561. The first dielectric layer 6542 may be disposed on the second voltage line 6553 in the opening 6561. The sidewall of the opening 6561 may be covered by the first dielectric layer 6542. The first dielectric layer 6542 may have a conformal shape in the opening 6561.

[0205] The first dielectric layer 6542 may be formed on the first layer 110a of the second substrate 110. Fig.18 As shown, the first dielectric layer 6542 is patterned to remove the portion of the first dielectric layer 6542 disposed on the first layer 110a of the second substrate 110, and to form an opening overlapping the second voltage line 6553. Therefore, the upper surface of the first layer 110a of the second substrate 110 can be exposed to the outside. At least a portion of the upper surface of the second voltage line 6553 can be exposed to the outside. The side of the insulating layer 6560 and the first capacitor electrode 6510 can be covered by the first dielectric layer 6542.

[0206] like Fig.19As shown, the second layer 110b of the second substrate 110 and the second capacitor electrode 6520 are formed on the first layer 110a of the second substrate 110 and the first dielectric layer 6542 by using a conductive material. The second layer 110b of the second substrate 110 can be formed on the first layer 110a and can contact the first layer 110a. The second capacitor electrode 6520 can be formed on the first dielectric layer 6542 and can overlap with the first capacitor electrode 6510. The first capacitor electrode 6510 and the second capacitor electrode 6520 can overlap each other with the first dielectric layer 6542 therebetween to form a capacitor. In addition, the second capacitor electrode 6520 can be connected to the second voltage line 6553 through the opening 6561 of the insulating layer 6560 and the opening of the first dielectric layer 6542.

[0207] Now we will refer to Fig. 20 A semiconductor device according to example embodiments is described.

[0208] Fig. 20 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0209] according to Fig. 20 The semiconductor device of the exemplary embodiment shown corresponds largely to the Fig.14 The semiconductor device of the example embodiment shown in the figure is not limited to the semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. The present example embodiment is partially different from the previous example embodiment in that the barrier layer is provided under the first capacitor electrode and the second capacitor electrode, which will be described below.

[0210] like Fig. 20 As shown, the semiconductor device includes a first capacitor electrode 6510, a second capacitor electrode 6520, and a first dielectric layer 6542 disposed therebetween. A first barrier layer 6510s may be further disposed below the first capacitor electrode 6510. A second barrier layer 6520s may be further disposed below the second capacitor electrode 6520. The first barrier layer 6510s and the second barrier layer 6520s may include a conductive material, for example, they may include metal nitrides. For example, the first barrier layer 6510s and the second barrier layer 6520s may include titanium nitride.

[0211] In the previous example embodiment, the first capacitor electrode 6510 may contact the first voltage line 6551, and the second capacitor electrode 6520 may contact the second voltage line 6553. In the present example embodiment, the first barrier layer 6510s may be disposed between the first capacitor electrode 6510 and the first voltage line 6551. The first barrier layer 6510s may be disposed between the first capacitor electrode 6510 and the insulating layer 6560. The second barrier layer 6520s may be disposed between the second capacitor electrode 6520 and the second voltage line 6553. The second barrier layer 6520s may be disposed between the second capacitor electrode 6520 and the first dielectric layer 6542.

[0212] The first dummy barrier layer 110s1 may be further disposed below the first layer 110a of the second substrate 110. The first dummy barrier layer 110s1 may be disposed on the same layer as the first barrier layer 6510s. The first dummy barrier layer 110s1 may include the same material as the first barrier layer 6510s and may be formed in the same process as the first barrier layer 6510s. The first dummy barrier layer 110s1 may be disposed between the first layer 110a of the second substrate 110 and the floating electrode 230a. In addition, the first dummy barrier layer 110s1 may be disposed between the second substrate 110 and the insulating layer 240. Depending on circumstances, the first dummy barrier layer 110s1 may be omitted.

[0213] The second dummy barrier layer 110s2 may be further disposed below the second layer 110b of the second substrate 110. The second dummy barrier layer 110s2 may be disposed on the same layer as the second barrier layer 6520s. The second dummy barrier layer 110s2 may include the same material as the second barrier layer 6520s and may be formed in the same process as the second barrier layer 6520s. The second dummy barrier layer 110s2 may be disposed between the first layer 110a and the second layer 110b of the second substrate 110. Depending on circumstances, the second dummy barrier layer 110s2 may be omitted.

[0214] Now refer to Fig.21 A semiconductor device according to example embodiments is described.

[0215] Fig.21 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0216] according to Fig.21 The semiconductor device of the exemplary embodiment shown corresponds largely to the Fig.14The semiconductor device of the example embodiment shown in the figure is not limited to the semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar components as the components of the previous example embodiment. This example embodiment is partially different from the previous example embodiment in that it further includes a third capacitor electrode and a fourth capacitor electrode, which will be described below.

[0217] like Fig.21 As shown, the semiconductor device includes a first capacitor electrode 6510, a second capacitor electrode 6520, and a first dielectric layer 6542 disposed therebetween. The semiconductor device may further include a third capacitor electrode 6530, a fourth capacitor electrode 6540, a second dielectric layer 6544, and a third dielectric layer 6546. The second capacitor electrode 6520 and the third capacitor electrode 6530 may overlap each other with the second dielectric layer 6544 therebetween to configure a capacitor. The third capacitor electrode 6530 and the fourth capacitor electrode 6540 may overlap each other with the third dielectric layer 6546 therebetween to configure a capacitor.

[0218] The semiconductor device includes a second substrate 110, and the second substrate 110 includes a first layer 110a, a second layer 110b, a third layer 110c, and a fourth layer 110d stacked in sequence. The second layer 110b may be disposed on the first layer 110a, the third layer 110c may be disposed on the second layer 110b, and the fourth layer 110d may be disposed on the third layer 110c. That is, the bottom surface of the third layer 110c may contact the upper surface of the second layer 110b, and the bottom surface of the fourth layer 110d may contact the upper surface of the third layer 110c. The first layer 110a, the second layer 110b, the third layer 110c, and the fourth layer 110d may include conductive materials, respectively. The first layer 110a, the second layer 110b, the third layer 110c, and the fourth layer 110d may include the same material, or may include at least a portion of different materials.

[0219] The third capacitor electrode 6530 may be disposed on the same layer as the third layer 110c of the second substrate 110. The third capacitor electrode 6530 may include the same material as the third layer 110c of the second substrate 110 and may be formed in the same process as the third layer 110c. The third capacitor electrode 6530 may have a thickness substantially equal to that of the third layer 110c of the second substrate 110.

[0220] The semiconductor device may further include a third voltage line 6555. The third voltage line 6555 may be disposed on the same layer as the first wiring portion (e.g., the floating electrode 230a). The third voltage line 6555 may be disposed on the same layer as the first voltage line 6551 and the second voltage line 6553. The third capacitor electrode 6530 may be connected to the third voltage line 6555. The third capacitor electrode 6530 may receive a third voltage through the third voltage line 6555. The third voltage may be a constant voltage.

[0221] The fourth capacitor electrode 6540 may be disposed on the same layer as the fourth layer 110d of the second substrate 110. The fourth capacitor electrode 6540 may include the same material as the fourth layer 110d of the second substrate 110 and may be formed in the same process as the fourth layer 110d. The fourth capacitor electrode 6540 may have a thickness substantially equal to that of the fourth layer 110d of the second substrate 110.

[0222] The semiconductor device may further include a fourth voltage line 6557. The fourth voltage line 6557 may be disposed on the same layer as the first wiring portion (e.g., the floating electrode 230a). The fourth voltage line 6557 may be disposed on the same layer as the first voltage line 6551, the second voltage line 6553, and the third voltage line 6555. The fourth capacitor electrode 6540 may be connected to the fourth voltage line 6557. The fourth capacitor electrode 6540 may receive a fourth voltage through the fourth voltage line 6557. The fourth voltage may be a constant voltage.

[0223] By forming capacitor electrodes disposed on many layers, the semiconductor device can obtain sufficient capacitor capacity. In this case, by forming the first to fourth capacitor electrodes in the same process as the second substrate including multiple layers, the process can be simplified and integration can be improved.

[0224] Now refer to Fig. 22 A semiconductor device according to example embodiments is described.

[0225] Fig. 22 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0226] according to Fig. 22 The semiconductor device of the exemplary embodiment shown corresponds largely to the Fig.21 The semiconductor device of the example embodiment shown in the figure is not limited to the semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. The present example embodiment is partially different from the previous example embodiment in that a barrier layer is provided under the first to fourth capacitor electrodes, which will be described below.

[0227] like Fig. 22 As shown, the semiconductor device includes a first capacitor electrode 6510, a second capacitor electrode 6520, a third capacitor electrode 6530, and a fourth capacitor electrode 6540. The first barrier layer 6510s may be further disposed under the first capacitor electrode 6510, and the second barrier layer 6520s may be further disposed under the second capacitor electrode 6520. The third barrier layer 6530s may be further disposed under the third capacitor electrode 6530, and the fourth barrier layer 6540s may be further disposed under the fourth capacitor electrode 6540. The first barrier layer 6510s, the second barrier layer 6520s, the third barrier layer 6530s, and the fourth barrier layer 6540s may include a conductive material, for example, they may include metal nitride. For example, the first barrier layer 6510s, the second barrier layer 6520s, the third barrier layer 6530s, and the fourth barrier layer 6540s may include titanium nitride.

[0228] In the previous example embodiment, the first capacitor electrode 6510 may contact the first voltage line 6551, the second capacitor electrode 6520 may contact the second voltage line 6553, the third capacitor electrode 6530 may contact the third voltage line 6555, and the fourth capacitor electrode 6540 may contact the fourth voltage line 6557. In the present example embodiment, the first barrier layer 6510s may be disposed between the first capacitor electrode 6510 and the first voltage line 6551. The first barrier layer 6510s may be disposed between the first capacitor electrode 6510 and the insulating layer 6560. The second barrier layer 6520s may be disposed between the second capacitor electrode 6520 and the second voltage line 6553. The second barrier layer 6520s may be disposed between the second capacitor electrode 6520 and the first dielectric layer 6542. The third barrier layer 6530s may be disposed between the third capacitor electrode 6530 and the third voltage line 6555. The third barrier layer 6530s may be disposed between the third capacitor electrode 6530 and the second dielectric layer 6544. The fourth barrier layer 6540s may be disposed between the fourth capacitor electrode 6540 and the fourth voltage line 6557. The fourth barrier layer 6540s may be disposed between the fourth capacitor electrode 6540 and the third dielectric layer 6546.

[0229] The first dummy barrier layer 110s1 may be further disposed below the first layer 110a of the second substrate 110. The first dummy barrier layer 110s1 may be disposed on the same layer as the first barrier layer 6510s. The first dummy barrier layer 110s1 may include the same material as the first barrier layer 6510s and may be formed in the same process as the first barrier layer 6510s. The first dummy barrier layer 110s1 may be disposed between the first layer 110a of the second substrate 110 and the floating electrode 230a. The first dummy barrier layer 110s1 may be disposed between the second substrate 110 and the insulating layer 240.

[0230] The second dummy barrier layer 110s2 may be further disposed under the second layer 110b of the second substrate 110. The second dummy barrier layer 110s2 may be disposed on the same layer as the second barrier layer 6520s. The second dummy barrier layer 110s2 may include the same material as the second barrier layer 6520s and may be formed in the same process as the second barrier layer 6520s. The second dummy barrier layer 110s2 may be disposed between the first layer 110a and the second layer 110b of the second substrate 110.

[0231] The third dummy barrier layer 110s3 may be further disposed under the third layer 110c of the second substrate 110. The third dummy barrier layer 110s3 may be disposed on the same layer as the third barrier layer 6530s. The third dummy barrier layer 110s3 may include the same material as the third barrier layer 6530s and may be formed in the same process as the third barrier layer 6530s. The third dummy barrier layer 110s3 may be disposed between the second layer 110b and the third layer 110c of the second substrate 110.

[0232] The fourth dummy barrier layer 110s4 may be further disposed under the fourth layer 110d of the second substrate 110. The fourth dummy barrier layer 110s4 may be disposed on the same layer as the fourth barrier layer 6540s. The fourth dummy barrier layer 110s4 may include the same material as the fourth barrier layer 6540s and may be formed in the same process as the fourth barrier layer 6540s. The fourth dummy barrier layer 110s4 may be disposed between the third layer 110c and the fourth layer 110d of the second substrate 110.

[0233] Now refer to Fig.23 and Fig.24 A semiconductor device according to example embodiments is described.

[0234] Fig.23 A cross-sectional view showing a region of a semiconductor device according to an example embodiment, Fig.24 A top view of some constituent elements of a semiconductor device according to example embodiments is shown. Fig.24The planar shape of the first capacitor electrode is shown.

[0235] according to Fig.23 and Fig.24 The semiconductor device of the exemplary embodiment shown corresponds largely to the Fig.14 The semiconductor device of the example embodiment shown in the figure is not shown, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar components as the components of the previous example embodiment. This example embodiment is partially different from the previous example embodiment in that the thickness of the first capacitor electrode is relatively large, which will be described below.

[0236] like Fig.23 As shown, the semiconductor device includes a first capacitor electrode 6510, a second capacitor electrode 6520, and a first dielectric layer 6542 disposed therebetween. The first capacitor electrode 6510 and the second capacitor electrode 6520 may overlap each other with the first dielectric layer 6542 therebetween to configure a capacitor.

[0237] In the previous example embodiment, the thickness of the first capacitor electrode 6510 may be substantially equal to the thickness of the second capacitor electrode 6520. In the present example embodiment, the thickness of the first capacitor electrode 6510 may be different from the thickness of the second capacitor electrode 6520. The first capacitor electrode 6510 may be thicker than the second capacitor electrode 6520. In this case, the thickness means, in a portion where the first capacitor electrode 6510 and the second capacitor electrode 6520 overlap each other in the Z-axis direction, the thickness of the first capacitor electrode 6510 in the Z-axis direction and the thickness of the second capacitor electrode 6520 in the Z-axis direction. In a portion where the first capacitor electrode 6510 and the second capacitor electrode 6520 do not overlap each other in the Z-axis direction, the thickness of the second capacitor electrode 6520 in the Z-axis direction may be greater than the thickness of the first capacitor electrode 6510 in the Z-axis direction.

[0238] The semiconductor device includes a second substrate 110, and the second substrate 110 includes a first layer 110a and a second layer 110b. The first layer 110a may be thicker than the second layer 110b. The thickness of the first layer 110a may be substantially equal to the thickness of the first capacitor electrode 6510, and the thickness of the second layer 110b may be substantially equal to the thickness of the second capacitor electrode 6520.

[0239] The semiconductor device may include a plurality of first voltage lines 6551, and the first capacitor electrode 6510 may be connected to the plurality of first voltage lines 6551. The same first voltage may be applied to the plurality of first voltage lines 6551. The semiconductor device may include a plurality of second voltage lines 6553, and the second capacitor electrode 6520 may be connected to the plurality of second voltage lines 6553. The same second voltage may be applied to the plurality of second voltage lines 6553.

[0240] Regarding the first capacitor electrode 6510, Fig.24 In the plan view, openings 6511 arranged at regular intervals may be formed in the first capacitor electrode 6510. The openings 6511 may be arranged at the vertices of the hexagon. However, the arrangement of the openings 6511 is not limited thereto and may be modified in various ways. For example, the openings 6511 may be arranged at regular intervals in the X-axis direction and the Y-axis direction. In addition, the openings 6511 may be circular in the plan view. However, the planar shape of the openings 6511 is not limited thereto and may be modified in various ways. For example, the planar shape of the openings 6511 may have a polygonal shape such as a quadrilateral.

[0241] The openings 6511 of the first capacitor electrode 6510 may overlap the second voltage line 6553, respectively. The sidewalls of the openings 6511 may be covered by the first dielectric layer 6542. The openings overlapping the second voltage line 6553 may be formed in the first dielectric layer 6542, and the second capacitor electrode 6520 may be connected to the second voltage line 6553 through the openings 6511 of the first capacitor electrode 6510 and the openings of the first dielectric layer 6542.

[0242] In the previous example embodiments, the capacitor can generally be formed in a portion where the first capacitor electrode 6510 and the second capacitor electrode 6520 overlap in the vertical direction (Z-axis direction in the drawings). In the present example embodiment, by forming the first capacitor electrode 6510 to be relatively thick, the capacitor can be formed in a portion where the first capacitor electrode 6510 and the second capacitor electrode 6520 overlap in the horizontal direction (X-axis direction or Y-axis direction in the drawings). In addition, by forming the opening 6511 in the first capacitor electrode 6510 and disposing the second capacitor electrode 6520 in the opening 6511, sufficient capacitor capacity can be obtained.

[0243] Now refer to Fig.25 A semiconductor device according to example embodiments is described.

[0244] Fig.25 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown. Fig.251 shows a capacitor region of a semiconductor device according to an example embodiment, a circuit region and a cell region are substantially equivalent to those according to reference Figure 1 The circuit region and the unit region are described in accordance with an exemplary embodiment of the present invention, which will be referred to in the following description.

[0245] according to Fig.25 The semiconductor device of the exemplary embodiment shown corresponds largely to the Figures 1 to 3 The semiconductor device of the example embodiment shown in the figure is not limited to the semiconductor device of the example embodiment shown in the figure, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. The present example embodiment is partially different from the previous example embodiment in that the second capacitor electrode can be provided on the same layer as the gate electrode, which will be described below.

[0246] like Fig.25 As shown, the semiconductor device includes a first capacitor electrode 7510, a second capacitor electrode 7520, and a first dielectric layer 7542 disposed therebetween. The first capacitor electrode 7510 and the second capacitor electrode 7520 overlap each other with the first dielectric layer 7542 therebetween to configure a capacitor.

[0247] At least a portion of the first capacitor electrode 7510 may be disposed at Figure 1 Another portion of the first capacitor electrode 7510 may be disposed on the same layer as the second substrate 110. Figure 1 The first capacitor electrode 7510 may include a first layer 7510a and a second layer 7510b. The first layer 7510a of the first capacitor electrode 7510 may be disposed on the same layer as the second horizontal conductive layer 114. Figure 1 The first layer 7510a of the first capacitor electrode 7510 may include Figure 1 The second substrate 110 is made of the same material as Figure 1 The second layer 7510b of the first capacitor electrode 7510 may be disposed on the same substrate 110 as the second substrate 110. Figure 1 The second layer 7510b of the first capacitor electrode 7510 may include Figure 1 The second horizontal conductive layer 114 is made of the same material and can be Figure 1 The second horizontal conductive layer 114 is formed in the same process. The second layer 7510b of the first capacitor electrode 7510 may be disposed on the first layer 7510a. The second layer 7510b of the first capacitor electrode 7510 may be connected to the first layer 7510a.

[0248] The insulating layer 7540 may be disposed between the first layer 7510a and the second layer 7510b of the first capacitor electrode 7510. The second layer 7510b of the first capacitor electrode 7510 may be connected to the first layer 7510a through an opening formed in the insulating layer 7540. The insulating layer 7540 may include a lower layer 7540a, an intermediate layer 7540b, and an upper layer 7540c. In this case, the intermediate layer 7540b may be disposed on the lower layer 7540a, and the upper layer 7540c may be disposed on the intermediate layer 7540b. That is, the intermediate layer 7540b may be disposed between the lower layer 7540a and the upper layer 7540c. The insulating layer 7540 may include various types of insulating materials. For example, the lower layer 7540a and the upper layer 7540c may include silicon oxide, and the intermediate layer 7540b may include silicon nitride.

[0249] The insulating layer 7540 may be disposed on the same layer as the horizontal insulating layer 116. The insulating layer 7540 may include the same material as the horizontal insulating layer 116 and may be formed in the same process as the horizontal insulating layer 116. The lower layer 7540a of the insulating layer 7540 may be disposed on the same layer as the lower layer 116a of the horizontal insulating layer 116. The middle layer 7540b of the insulating layer 7540 may be disposed on the same layer as the middle layer 116b of the horizontal insulating layer 116. The upper layer 7540c of the insulating layer 7540 may be disposed on the same layer as the upper layer 116c of the horizontal insulating layer 116.

[0250] The semiconductor device may further include a first voltage line 7551. The first voltage line 7551 may be provided at a position corresponding to Figure 1 The first voltage line 7551 may include the same layer as the first wiring portion 230. Figure 1 The first wiring portion 230 is made of the same material and can be Figure 1 The first wiring portion 230 is formed in the same process. The first voltage line 7551 may receive a first voltage. The first capacitor electrode 7510 may be connected to the first voltage line 7551. The first capacitor electrode 7510 may receive a first voltage through the first voltage line 7551.

[0251] The insulating layer 7560 may be disposed between the first capacitor electrode 7510 and the first voltage line 7551. The first capacitor electrode 7510 may be connected to the first voltage line 7551 through an opening formed in the insulating layer 7560. In this case, the first layer 7510a of the first capacitor electrode 7510 may be directly connected to the first voltage line 7551. The second layer 7510b of the first capacitor electrode 7510 may be connected to the first voltage line 7551 through the first layer 7510a. The insulating layer 7560 disposed between the first capacitor electrode 7510 and the first voltage line 7551 may be disposed at a position corresponding to the position of the insulating layer 7560 disposed between the first capacitor electrode 7510 and the first voltage line 7551. Figure 1 The second substrate 110 and Figure 1 The first wiring portion 230 between Figure 1 The insulating layer 7560 may be formed on the same layer as the insulating layer 240. The insulating layer 7560 may be a single layer or multiple layers. For example, the insulating layer 7560 may include a lower insulating layer 7562 and an upper insulating layer 7564 disposed on the lower insulating layer 7562. The insulating layer 7560 may include various types of insulating materials. For example, the lower insulating layer 7562 may include silicon nitride, and the upper insulating layer 7564 may include silicon oxide.

[0252] The second capacitor electrode 7520 may be disposed at Figure 1 The second capacitor electrode 7520 may include Figure 1 The gate electrode 130 is made of the same material and can be Figure 1 The first dielectric layer 7542 may be disposed on the same substrate as the gate electrode 130. Figure 1 The first dielectric layer 7542 may include the same layer as the cell insulating layer 132. Figure 1 The cell insulating layer 132 is made of the same material and can be Figure 1 The cell insulating layer 132 is formed in the same process. Figure 1 The cell insulating layer 132 and Figure 1 The gate electrodes 130 are alternately stacked in the cell region, and thus the first dielectric layers 7542 and the second capacitor electrodes 7520 are alternately stacked in the capacitor region. In this case, the stacking number of the first dielectric layers 7542 and the second capacitor electrodes 7520 may be equal to / different from Figure 1 The cell insulating layer 132 and Figure 1 The number of stacked gate electrodes 130 is .

[0253] The semiconductor device may further include a second voltage line 7553. The second voltage line 7553 may be disposed on the same layer as the first voltage line 7551. The second voltage line 7553 may include the same material as the first voltage line 7551 and may be formed in the same process as the first voltage line 7551. The second voltage line 7553 may be disposed on the same layer as the first voltage line 7551. Figure 1 The second capacitor electrode 7520 may be connected to the second voltage line 7553. The second capacitor electrode 7520 may receive the second voltage through the second voltage line 7553.

[0254] The semiconductor device may further include a connection structure 7555 for connecting the second capacitor electrode 7520 and the second voltage line 7553. The connection structure 7555 may be connected to the Figure 1The second capacitor electrode 7520 may be connected to the second voltage line 7553 through the connection structure 7555 .

[0255] The insulating layers 7540 and 7560 and the first capacitor electrode 7510 may be disposed between the second capacitor electrode 7520 and the second voltage line 7553. An opening may be formed in the first capacitor electrode 7510, and the first dielectric layer 7542 may fill the opening. The connection structure 7555 may pass through the first dielectric layer 7542, and may connect the second capacitor electrode 7520 and the second voltage line 7553.

[0256] The semiconductor device may further include a dummy partition structure 7546 passing through the stack structure of the first dielectric layer 7542 and the second capacitor electrode 7520. The dummy partition structure 7546 may be disposed at a position corresponding to the first dielectric layer 7542 and the second capacitor electrode 7520. Figure 1 The dummy partition structure 7546 may include Figure 1 The partition structure 146 is made of the same material and can be used with Figure 1 The separation structure 146 is formed in the same process.

[0257] The respective electrodes of the capacitor disposed in the capacitor region of the semiconductor device, the dielectric layer disposed between the electrodes, and the voltage lines connected to the electrodes can be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming a capacitor in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process can be simplified and the integration can be improved.

[0258] Now refer to Figures 26 to 30 A method of manufacturing a semiconductor device according to example embodiments is described.

[0259] Figures 26 to 30 Process cross-sectional views of parts of a method of manufacturing a semiconductor device according to example embodiments are sequentially shown. Figures 26 to 30 Shows the manufacturing method Fig.25 A process for a semiconductor device according to an example embodiment is shown.

[0260] like Fig.26 As shown, the first voltage line 7551 and the second voltage line 7553 are formed by using a conductive material. For example, the first voltage line 7551 and the second voltage line 7553 can be formed by depositing a conductive material and patterning the conductive material. In this case, Figure 1 The first wiring portion 230 may be formed together.

[0261] An insulating layer 7560 is formed on the first voltage line 7551 and the second voltage line 7553 by sequentially stacking a lower insulating layer 7562 and an upper insulating layer 7564 using an insulating material. In this case, the lower insulating layer 7562 may include silicon nitride, and the upper insulating layer 7564 may include silicon oxide. However, the materials of the lower insulating layer 7562 and the upper insulating layer 7564 are not limited thereto and may be modified in various ways.

[0262] An opening for exposing at least a portion of the first voltage line 7551 is formed by patterning the insulating layer 7560. A first layer 7510a of the first capacitor electrode 7510 is formed on the insulating layer 7560 by using a conductive material. The first layer 7510a of the first capacitor electrode 7510 may be connected to the first voltage line 7551 through the opening formed in the insulating layer 7560.

[0263] A lower layer 7540a, an intermediate layer 7540b, and an upper layer 7540c are stacked on the first layer 7510a of the first capacitor electrode 7510 to form an insulating layer 7540. In this case, the lower layer 7540a and the upper layer 7540c may include silicon oxide, and the intermediate layer 7540b may include silicon nitride. However, the materials of the lower layer 7540a, the intermediate layer 7540b, and the upper layer 7540c are not limited thereto and may be modified in various ways.

[0264] An opening for exposing at least a portion of the first layer 7510a of the first capacitor electrode 7510 is formed by patterning the insulating layer 7540. A second layer 7510b of the first capacitor electrode 7510 is formed on the insulating layer 7540 by using a conductive material. The second layer 7510b of the first capacitor electrode 7510 may be connected to the first layer 7510a of the first capacitor electrode 7510 through the opening formed in the insulating layer 7540.

[0265] The first dielectric layer 7542 and the sacrificial layer 7520s are alternately stacked on the first capacitor electrode 7510. An opening overlapping with the second voltage line 7553 may be formed in the first capacitor electrode 7510, and the opening of the first capacitor electrode 7510 may be filled with the first dielectric layer 7542.

[0266] The portion of the second layer 7510b of the first capacitor electrode 7510 on which the first layer 7510a is contacted may be disposed in the opening of the insulating layer 7540, and thus the portion of the second layer 7510b contacting the first layer 7510a may have a height difference from other portions. Therefore, the upper surface of the first dielectric layer 7542 disposed on the first capacitor electrode 7510 may not be flat. In order to flatten the upper surface of the first dielectric layer 7542, a chemical mechanical polishing (CMP) process may be performed.

[0267] like Fig. 27 As shown, an opening is formed through the stacked structure of the first dielectric layer 7542 and the sacrificial layer 7520s, and a sacrificial structure 7555s filling the opening is formed. In this case, the opening can pass through the first dielectric layer 7542 that fills the opening of the first capacitor electrode 7510, and can pass through the insulating layers 7540 and 7560. The opening can overlap with the second voltage line 7553. Therefore, at least a portion of the second voltage line 7553, such as a portion of the upper surface, can be exposed through the opening. The sacrificial structure 7555s can contact the upper surface of the second voltage line 7553. The sacrificial structure 7555s may include polysilicon. However, not limited to this, the material of the sacrificial structure 7555s can be modified in a variety of ways.

[0268] like Fig.28 As shown, an opening 7520h is formed through the stacked structure of the first dielectric layer 7542 and the sacrificial layer 7520s. At least a portion of the sacrificial layer 7520s may be exposed through the opening 7520h. For example, the side of the sacrificial layer 7520s may be exposed to the outside. The opening 7520h may overlap with the first capacitor electrode 7510. When the first dielectric layer 7542 and the sacrificial layer 7520s are etched to form the opening 7520h, at least a portion of the first capacitor electrode 7510 may be etched together. That is, a groove may be formed in the upper surface of the first capacitor electrode 7510.

[0269] like Fig.29 As shown, the exposed sacrificial layer 7520s is removed through the opening 7520h. In this case, in the etching process for removing the sacrificial layer 7520s, the first dielectric layer 7542 may not be removed, but may be retained due to the difference in etching ratios of the sacrificial layer 7520s and the first dielectric layer 7542. Therefore, a space may be generated between the first dielectric layer 7542 having many layers. In order to fill the space, a conductive material is deposited and the second capacitor electrode 7520 is formed. Therefore, a stacked structure of the first dielectric layer 7542 and the second capacitor electrode 7520 may be formed. In this case, Figure 1 The gate electrode 130 may be formed together.

[0270] A dummy partition structure 7546 is formed to fill the opening 7520h. The dummy partition structure 7546 may include an insulating material. For example, the dummy partition structure 7546 may include silicon oxide. In this case, Figure 1 The separation structure 146 can be formed together.

[0271] like Fig.30As shown, the sacrificial structure 7555s is removed. For example, the sacrificial structure 7555s can be removed by performing an etching process using an etching solution for selectively removing the sacrificial structure 7555s. A space can be created in the portion in which the sacrificial structure 7555s is set. A connecting structure 7555 is formed to fill the space. The connecting structure 7555 can be connected to the second capacitor electrode 7520. For example, the connecting structure 7555 can be connected to the side of the second capacitor electrode 7520. The connecting structure 7555 can be connected to the second voltage line 7553. For example, the connecting structure 7555 can be connected to the upper surface of the second voltage line 7553. The second capacitor electrode 7520 can be connected to the second voltage line 7553 through the connecting structure 7555. The connecting structure 7555 can be insulated from the first capacitor electrode 7510 by the first dielectric layer 7542.

[0272] Now refer to Fig.31 A semiconductor device according to example embodiments is described.

[0273] Fig.31 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0274] Fig.31 The example embodiments shown correspond largely to Fig.25 The example embodiment shown in FIG. 1 is a block diagram of a capacitor electrode, and its description will be omitted, and the differences will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as those of the previous example embodiment. The difference between this example embodiment and the previous example embodiment is that the third layer is further disposed between the first layer and the second layer of the first capacitor electrode, which will now be described.

[0275] like Fig.31 As shown, the semiconductor device includes a first capacitor electrode 7510, a second capacitor electrode 7520, and a first dielectric layer 7542 disposed therebetween. The first capacitor electrode 7510 and the second capacitor electrode 7520 may overlap each other with the first dielectric layer 7542 to configure a capacitor.

[0276] In the previous example embodiment, the first capacitor electrode 7510 includes a first layer 7510a and a second layer 7510b, Fig.25The insulating layer 7540 may be disposed between the first layer 7510a and the second layer 7510b. In the present example embodiment, the first capacitor electrode 7510 includes the first layer 7510a, the second layer 7510b, and the third layer 7510c. Instead of the insulating layer, the third layer 7510c may be disposed between the first layer 7510a and the second layer 7510b of the first capacitor electrode 7510. The third layer 7510c may be disposed on the first layer 7510a of the first capacitor electrode 7510, and the second layer 7510b may be disposed on the third layer 7510c. The third layer 7510c may be disposed on the same layer as the first horizontal conductive layer. The first layer 7510a, the second layer 7510b, and the third layer 7510c of the first capacitor electrode 7510 may include a conductive material. For example, the first layer 7510a, the second layer 7510b, and the third layer 7510c of the first capacitor electrode 7510 may include polysilicon doped with impurities. However, without limitation thereto, the materials of the first layer 7510a, the second layer 7510b, and the third layer 7510c of the first capacitor electrode 7510 may be changed in various ways. The first layer 7510a, the second layer 7510b, and the third layer 7510c of the first capacitor electrode 7510 may include the same material, or at least some of them may include different materials.

[0277] Now refer to Fig.32 A semiconductor device according to example embodiments is described.

[0278] Fig.32 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0279] according to Fig.32 The semiconductor device of the exemplary embodiment shown corresponds largely to the Fig.31 The semiconductor device of the example embodiment shown in the figure is not provided, and therefore its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous example embodiment. The present example embodiment is partially different from the previous example embodiment in that the second voltage line is not provided on the same layer as the first voltage line, which will be described below.

[0280] like Fig.32 As shown, the semiconductor device includes a first capacitor electrode 7510, a second capacitor electrode 7520, and a first dielectric layer 7542 disposed therebetween. The first capacitor electrode 7510 and the second capacitor electrode 7520 may overlap each other with the first dielectric layer 7542 to configure a capacitor.

[0281] In the previous example implementation, Fig.31The first voltage line 7551 and the second voltage line 7553 may be arranged on the same layer. In this example embodiment, the first voltage line 7551 and the second voltage line may be arranged on different layers. Although not shown, the second voltage line may be arranged on the same layer as the first voltage line 7551 and the second voltage line 7553. Figure 1 The second wiring portion 180 is on the same layer.

[0282] In addition, the end of the multilayer second capacitor electrode 7520 may be formed in a stepped shape. The semiconductor device may include a connection structure 7555 connected to the end of the second capacitor electrode 7520 of each layer. Although not shown, the connection structure 7555 may be connected to the second voltage line. That is, the second capacitor electrode 7520 may be connected to the second voltage line through the connection structure 7555 and may receive the second voltage.

[0283] Now refer to Fig.33 A semiconductor device according to example embodiments is described.

[0284] Fig.33 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown. Fig.33 Portions of a cell region and a capacitor region of a semiconductor device according to example embodiments are shown.

[0285] Fig.33 The example embodiments shown correspond largely to Fig.25 The example embodiment shown in the figure is not shown, so its description will be omitted, and the differences will be mainly described. In addition, the same or similar reference numerals are used for the same or similar components as the components of the previous example embodiment. This example embodiment is partially different from the previous example embodiment in that the unit area is inverted.

[0286] Although not shown, the semiconductor device may have a chip-to-chip structure by a wafer bonding method. The circuit region of the semiconductor device according to the example embodiment is not shown, and the second substrate 110, the gate stack structure 120, and the channel structure CH may be disposed in the cell region. The first capacitor electrode 8510, the second capacitor electrode 8520, and the first dielectric layer 8542 disposed therebetween may be disposed in the capacitor region. The first capacitor electrode 8510 and the second capacitor electrode 8520 may overlap each other with the first dielectric layer 8542 therebetween to configure the first capacitor.

[0287] The gate stack structure 120 includes alternately stacked unit insulating layers 132 and gate electrodes 130. The channel structure CH may pass through the gate stack structure 120. The channel structure CH may include a channel layer 140, a gate dielectric layer 150, and a core insulating layer 142. The channel layer 140 may be disposed between the gate dielectric layer 150 and the core insulating layer 142. The gate dielectric layer 150 may include a tunneling layer 152, a charge storage layer 154, and a blocking layer 156 sequentially stacked on the channel layer 140. At least a portion of the channel structure CH may be disposed in a groove formed in the second substrate 110. Compared to the gate dielectric layer 150, the channel layer 140 may protrude upward, and the protruding portion of the channel layer 140 may be surrounded by the second substrate 110. An end of the channel layer 140 may contact the second substrate 110.

[0288] The semiconductor device may further include a separation structure 146 . The separation structure 146 may pass through the gate stack structure 120 , and an end of the separation structure 146 may be disposed in a groove formed in the second substrate 110 .

[0289] The first capacitor electrode 8510 may be disposed on the same layer as the second substrate 110. The first capacitor electrode 8510 may include the same material as the second substrate 110 and may be formed in the same process as the second substrate 110. The first capacitor electrode 8510 may be separated from the second substrate 110.

[0290] The semiconductor device may further include a first connection electrode 8559a. The first connection electrode 8559a is connected to the first capacitor electrode 8510. Although not shown, the semiconductor device may further include a first voltage line, and the first voltage line may be connected to the first connection electrode 8559a. Therefore, the first capacitor electrode 8510 may be connected to the first voltage line through the first connection electrode 8559a and may receive a first voltage.

[0291] The second capacitor electrode 8520 may be disposed on the same layer as the gate electrode 130. The second capacitor electrode 8520 may include the same material as the gate electrode 130 and may be formed in the same process as the gate electrode 130. The second capacitor electrode 8520 may be separated from the gate electrode 130.

[0292] The semiconductor device may further include a connection structure 8555 and a second connection electrode 8559b. The connection structure 8555 is connected to the second capacitor electrode 8520. The connection structure 8555 may extend in the same direction as the channel structure CH (Z-axis direction in the drawing). The connection structure 8555 may be connected to the second connection electrode 8559b. The second capacitor electrode 8520 may be connected to the second connection electrode 8559b through the connection structure 8555. Although not shown, the semiconductor device may further include a second voltage line, which may be connected to the second connection electrode 8559b. Therefore, the second capacitor electrode 8520 may be connected to the second voltage line through the connection structure 8555 and the second connection electrode 8559b, and may receive a second voltage.

[0293] The first dielectric layer 8542 may be disposed between the first capacitor electrode 8510 and the second capacitor electrode 8520. The first dielectric layer 8542 may be disposed on the same layer as the cell insulating layer 132. The first dielectric layer 8542 may include the same material as the cell insulating layer 132 and may be formed in the same process as the cell insulating layer 132.

[0294] The respective electrodes of the capacitor disposed in the capacitor region of the semiconductor device, the dielectric layer disposed between the electrodes, and the voltage lines connected to the electrodes can be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming a capacitor in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process can be simplified and the integration can be improved.

[0295] Now refer to Figure 34 to Figure 39 A method of manufacturing a semiconductor device according to example embodiments is described.

[0296] Figure 34 to Figure 39 Process cross-sectional views of parts of a method of manufacturing a semiconductor device according to example embodiments are sequentially shown. Figure 34 to Figure 39 Shows the manufacturing method Fig.33 A process for a semiconductor device according to an example embodiment is shown.

[0297] like Fig.34 As shown, a gate stack structure 120, a channel structure CH, a separation structure 146, a second capacitor electrode 8520, a first dielectric layer 8542, and a connection structure 8555 are formed on a substrate material layer 111. For example, insulating materials and sacrificial materials may be alternately stacked on the substrate material layer 111, openings may be formed through them, the channel structure CH may be formed, the sacrificial material may be removed, and a conductive material replacing the sacrificial material may be deposited to form a gate electrode 130 and a second capacitor electrode 8520. Then, the separation structure 146 and the connection structure 8555 may be formed.

[0298] The substrate material layer 111 may be a semiconductor substrate made of a semiconductor material. For example, the substrate material layer 111 may be configured of silicon, epitaxial silicon, germanium, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0299] The substrate material layer 111 is turned over so that its bottom surface may face upward, and the cell region and the circuit region are arranged to face each other, thereby performing a bonding process.

[0300] like Fig.35 As shown, the substrate material layer 111 is removed. For example, the substrate material layer 111 may be removed by using one or more of a grinding process, an etching process, and a chemical mechanical polishing process. As the substrate material layer 111 is removed, ends such as the channel structure CH, the separation structure 146, and the connection structure 8555 may be exposed to the outside. In this case, the gate dielectric layer 150 of the channel structure CH is exposed to the outside, and the channel layer 140 is surrounded by the gate dielectric layer 150, so it may not be exposed to the outside.

[0301] like Fig.36 As shown, the portion of the gate dielectric layer 150 exposed to the outside is removed. For example, the blocking layer 156, the charge storage layer 154, and the tunneling layer 152 of the gate dielectric layer 150 may be removed in sequence by using an etching process. As the exposed portion of the gate dielectric layer 150 is removed, one side of the gate dielectric layer 150 and the cell insulating layer 132 may be planarized. In addition, the end of the channel layer 140 may be exposed to the outside. That is, the channel layer 140 may protrude from the gate dielectric layer 150, and the protruding portion of the channel layer 140 may be exposed to the outside.

[0302] A conductive material layer 111 a is formed on the gate stack structure 120 , the channel structure CH, the separation structure 146 , the first dielectric layer 8542 , and the connection structure 8555 .

[0303] The conductive material layer 111a may include a conductive material. For example, the conductive material layer 111a may include polysilicon doped with impurities. In this case, the upper surface of the conductive material layer 111a may not be planarized. The height of the portion of the conductive material layer 111a used to cover the channel structure CH, the separation structure 146, and the connection structure 8555 may be greater than the height of the portion of the conductive material layer 111a used to cover the gate stack structure 120 and the first dielectric layer 8542.

[0304] The first insulating layer 8572 is formed on the conductive material layer 111a by using an insulating material. The first insulating layer 8572 may include various types of insulating materials. For example, the first insulating layer 8572 may include silicon oxide.

[0305] like Fig.37 As shown, a first opening 8573a and a second opening 8573b are formed by patterning the first insulating layer 8572 and the conductive material layer 111a. The first insulating layer 8572 may be etched, and then the conductive material layer 111a may be etched. The conductive material layer 111a may be divided into the second substrate 110 and the first capacitor electrode 8510 by the first opening 8573a. The end of the connection structure 8555 may be exposed to the outside through the second opening 8573b. As the conductive material layer 111a covering the connection structure 8555 is removed, the connection between the connection structure 8555 and the conductive material layer 111a may be disconnected.

[0306] like Fig.38 As shown, a second insulating layer 8574 is formed on the first insulating layer 8572 using an insulating material. The second insulating layer 8574 may include various types of insulating materials. For example, the second insulating layer 8574 may include silicon oxide. The second insulating layer 8574 may fill the first opening 8573a and the second opening 8573b. Therefore, the second insulating layer 8574 may be disposed between the second substrate 110 and the first capacitor electrode 8510. In addition, the second insulating layer 8574 may surround the end of the connection structure 8555.

[0307] like Fig.39 As shown, a third opening 8575a and a fourth opening 8575b are formed by patterning the first insulating layer 8572 and the second insulating layer 8574. At least a portion of the upper surface of the first capacitor electrode 8510 may be exposed to the outside through the third opening 8575a. The upper surface of the connection structure 8555 may be exposed to the outside through the fourth opening 8575b.

[0308] A first connection electrode 8559a may be formed in the third opening 8575a by using a conductive material, and a second connection electrode 8559b may be formed in the fourth opening 8575b. For example, a conductive material may be deposited on the second insulating layer 8574, and a planarization process may be performed to retain the conductive material disposed in the third opening 8575a and the fourth opening 8575b, and to remove the conductive material disposed on the upper surface of the second insulating layer 8574. The first connection electrode 8559a may be connected to the first capacitor electrode 8510. A first voltage line connected to the first connection electrode 8559a may be formed in a subsequent process. The first capacitor electrode 8510 may receive a first voltage from the first voltage line through the first connection electrode 8559a. The second connection electrode 8559b may be connected to the connection structure 8555. A second voltage line connected to the second connection electrode 8559b may be formed in a subsequent process. The second capacitor electrode 8520 may receive a second voltage from the second voltage line through the second connection electrode 8559b and the connection structure 8555.

[0309] Now refer to Fig.40 A semiconductor device according to example embodiments is described.

[0310] Fig.40 A cross-sectional view of a region of a semiconductor device according to example embodiments is shown.

[0311] Fig.40 The example embodiments shown correspond largely to Fig.33 The exemplary embodiment shown in the figure is not shown, so its description will be omitted, and the difference will be mainly described. In addition, the same or similar reference numerals are used for the same or similar constituent elements as the constituent elements of the previous exemplary embodiment. This exemplary embodiment is partially different from the previous exemplary embodiment in that the upper surface of the second substrate and the first capacitor electrode is flat, which will now be described.

[0312] like Fig.40 As shown, the semiconductor device may include a first capacitor electrode 8510, a second capacitor electrode 8520, and a first dielectric layer 8542 disposed therebetween. The first capacitor electrode 8510 and the second capacitor electrode 8520 may overlap each other with the first dielectric layer 8542 therebetween to configure a first capacitor.

[0313] In the previous example embodiment, the upper surfaces of the second substrate 110 and the first capacitor electrode 8510 may be uneven. For example, a portion of the second substrate 110 covering the channel structure CH and the separation structure 146 may be disposed higher than another portion of the second substrate 110 and the first capacitor electrode 8510 .

[0314] In the present example embodiment, the upper surfaces of the second substrate 110 and the first capacitor electrode 8510 may be flat. The height of the upper surface of the second substrate 110 may be substantially similar to the height of the upper surface of the first capacitor electrode 8510. This difference may be generated according to various process conditions. For example, in the previous example embodiment, the second substrate 110 and the first capacitor electrode 8510 may be formed by using polysilicon, while in the present example embodiment, the second substrate 110 and the first capacitor electrode 8510 may be formed by using a metal material.

[0315] Now refer to Fig.41 An electronic system including a semiconductor device according to example embodiments is described.

[0316] Fig.41 An electronic system including a semiconductor device according to example embodiments is illustrated.

[0317] like Fig.41As shown, the electronic system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0318] The semiconductor device 1100 may be a nonvolatile memory device, for example, referring to Figures 1 to 3 The NAND flash memory device described herein. However, not limited thereto, the semiconductor device 1100 may be a NAND flash memory device according to other modifiable example embodiments. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S disposed on the first structure 1100F. In an example embodiment, the first structure 1100F may be disposed close to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0319] Regarding the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 disposed near a common source line CSL, upper transistors UT1 and UT2 disposed near a bit line BL, and memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to example embodiments, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified in various ways.

[0320] In example embodiments, the lower transistors LT1 and LT2 may include ground selection transistors, and the upper transistors UT1 and UT2 may include string selection transistors. The first and second lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2.

[0321] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word line WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S.

[0322] Regarding the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may control at least one of the memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0323] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to example embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and the controller 1200 may control the plurality of semiconductor devices 1100.

[0324] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may be operable according to a predetermined firmware, and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 for processing communication with the semiconductor device 1100. Control instructions for controlling the semiconductor device 1100, data to be written into the memory cell transistors MCT of the semiconductor device 1100, and data to be read from the memory cell transistors MCT of the semiconductor device 1100 may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control instruction is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control instruction.

[0325] Fig.42 A perspective view of an electronic system including a semiconductor device according to example embodiments is shown.

[0326] like Fig.42As shown, the electronic system 2000 may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 formed on the main substrate 2001.

[0327] The main substrate 2001 may include a connector 2006, which includes pins for combining with an external host. According to the communication interface between the electronic system 2000 and the external host, the number and arrangement of the pins of the connector 2006 are variable. In an example embodiment, the electronic system 2000 may communicate with the external host according to one of the interfaces including a universal serial bus (USB), a peripheral component interconnect high speed (PCI-Express), a serial advanced technology attachment (SATA), and a universal flash memory (UFS) M-Phy. In an example embodiment, the electronic system 2000 may operate with a power supply voltage supplied by an external host via the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) for providing the power supply voltage supplied by the external host to the controller 2002 and the semiconductor package 2003.

[0328] The controller 2002 may write data to the semiconductor package 2003 , may read data from the semiconductor package 2003 , and may increase the operation rate of the electronic system 2000 .

[0329] The DRAM 2004 may be a buffer memory for reducing a rate difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a high-speed cache memory and may provide a space for temporarily storing data when controlling the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0330] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may include semiconductor chips 2200, respectively. The first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 disposed on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each semiconductor chip 2200, a connection structure 2400 for electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a mold layer 2500 on the package substrate 2100 for covering the semiconductor chip 2200 and the connection structure 2400.

[0331] The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.41 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include a reference Figures 1 to 3 However, not limited thereto, the semiconductor chip 2200 may include a semiconductor device according to another modified example embodiment.

[0332] In example embodiments, the connection structure 2400 may be a bonding wire for electrically connecting the input / output pad 2210 and the package upper pad 2130. Therefore, with respect to the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a wire bonding method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to example embodiments, with respect to the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other not by the connection structure 2400 according to the wire bonding method but by a connection structure including a through silicon via TSV.

[0333] In example embodiments, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the main substrate 2001, and the controller 2002 may be connected to the semiconductor chip 2200 through leads formed on the interposer substrate.

[0334] Fig.43 and Fig.44 A cross-sectional view of a semiconductor package according to example embodiments is shown. Fig.43 and Fig.44 They are shown respectively Fig.42An example implementation of a semiconductor package 2003 is shown conceptually Fig.42 A cutting area of ​​the semiconductor package 2003 along a cutting line II'.

[0335] Reference Fig.43 Regarding the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate main body 2120, a package upper pad 2130 disposed on the upper surface of the package substrate main body 2120, a lower pad 2125 disposed on the lower surface of the package substrate main body 2120 or exposed through the lower surface, and an internal wiring 2135 in the package substrate main body 2120 for electrically connecting the package upper pad 2130 and the lower pad 2125. The package upper pad 2130 may be electrically connected to the connection structure 2400. Fig.42 As shown, the lower pad 2125 may be connected to the wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 through a conductive connector 2800 .

[0336] The semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 disposed on the common source line 3205, a channel structure 3220 and a separation structure 3230 passing through the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line (e.g., Fig.41 The gate connection wiring of the word line WL).

[0337] With regard to the semiconductor chip 2200 or the semiconductor device according to the example embodiment, each electrode of the capacitor disposed in the capacitor region, a dielectric layer disposed between the electrodes, and a voltage line connected to each electrode may be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming a capacitor in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process may be simplified and the integration may be improved.

[0338] Each semiconductor chip 2200 may include a penetration wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The penetration wiring 3245 may pass through the gate stack structure 3210, and may be further disposed outside the gate stack structure 3210. Each semiconductor chip 2200 may further include an input / output connection wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connection wiring 3265.

[0339] In example embodiments, the semiconductor chips 2200 may be electrically connected to each other through connection structures 2400 in the form of bonding wires in the semiconductor package 2003. For another example, the semiconductor chips 2200 or portions configuring the semiconductor chips 2200 may be electrically connected to each other through connection structures including through silicon vias (TSVs).

[0340] Reference Fig.44 , regarding the semiconductor package 2003A, each semiconductor chip 2200 may include a semiconductor substrate 4010 , a first structure 4100 disposed on the semiconductor substrate 4010 , and a second structure 4200 bonded to the first structure 4100 on the first structure 4100 by a wafer bonding method.

[0341] The first structure 4100 may include a peripheral circuit region including a peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 disposed between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 passing through the gate stack structure 4210, and a word line (e.g., Fig.41 The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 may be in contact with each other and may be bonded to each other. The bonding portions of the first bonding structure 4150 and the second bonding structure 4250 may be made of, for example, copper (Cu).

[0342] With regard to the semiconductor chip 2200 or the semiconductor device according to the example embodiment, each electrode of the capacitor disposed in the capacitor region, a dielectric layer disposed between the electrodes, and a voltage line connected to each electrode may be disposed on the same layer as the constituent elements disposed in the circuit region and the cell region. That is, by forming a capacitor in the capacitor region by using the constituent elements disposed in the circuit region and the cell region, the process may be simplified and the integration may be improved.

[0343] Each semiconductor chip 2200 may further include an input / output pad 2210 and an input / output connection wiring 4265 disposed at a lower portion of the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0344] In example embodiments, the semiconductor chips 2200 may be electrically connected to each other through a connection structure 2400 in a bonding wire shape in the semiconductor package 2003. For another example, the semiconductor chips 2200 or portions configuring the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through silicon via.

[0345] Throughout the specification and claims, when a part is “connected” to another part, it includes not only the case where the parts are “directly connected” but also the case where the parts are “indirectly connected” with another part therebetween.

[0346] Any functional blocks shown in the figures and described above may be implemented in a processing circuit (such as hardware including logic circuits, a hardware / software combination such as a processor running software, or a combination thereof). For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0347] While the present disclosure has been described in connection with what are presently considered to be feasible example embodiments, it is to be understood that the present disclosure is not limited to the disclosed example embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0348] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0082972 filed in the Korean Intellectual Property Office on June 27, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: a first substrate; a wiring layer, on the first substrate; a second substrate on the wiring layer and comprising a conductive material; A first horizontal conductive layer and a second horizontal conductive layer are sequentially stacked on the second substrate and connected to the second substrate; A gate stack structure, comprising an interlayer insulating layer and a gate electrode alternately stacked on the second horizontal conductive layer; a channel structure passing through the gate stack structure and connected to the second substrate; a first capacitor electrode on the same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; as well as a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on the same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer, and the gate electrode.

2. The semiconductor device according to claim 1, wherein the second capacitor electrode is on the same layer as a portion of the first horizontal conductive layer, and The first dielectric layer is on the same layer as another portion of the first horizontal conductive layer.

3. The semiconductor device according to claim 2, further comprising: a third capacitor electrode overlapping the second capacitor electrode; as well as a second dielectric layer between the second capacitor electrode and the third capacitor electrode, Wherein, the third capacitor electrode is on the same layer as the second horizontal conductive layer.

4. The semiconductor device according to claim 3, further comprising: a first voltage line connected to the first capacitor electrode; a second voltage line connected to the second capacitor electrode; as well as A first connection structure connects the second capacitor electrode and the second voltage line and extends in the same direction as the channel structure.

5. The semiconductor device according to claim 4, wherein The first voltage line is on the same layer as the wiring layer, and The first capacitor electrode is connected to the third capacitor electrode.

6. The semiconductor device according to claim 4, further comprising: a third voltage line connected to the third capacitor electrode, Wherein, the third voltage line is on the same layer as the wiring layer.

7. The semiconductor device according to claim 4, further comprising: a second connection structure connected to the first capacitor electrode and extending parallel to the channel structure; as well as A third connection structure is connected to the third capacitor electrode and extends parallel to the channel structure.

8. The semiconductor device according to claim 1, wherein The second capacitor electrode is on the same layer as the wiring layer, and The first dielectric layer is on the same layer as an insulating layer between the wiring layer and the second substrate.

9. The semiconductor device according to claim 8, further comprising: a first voltage line connected to the first capacitor electrode, Wherein, the first voltage line is on the same layer as the wiring layer.

10. The semiconductor device according to claim 1, wherein The second capacitor electrode is on the same layer as the second substrate, and A sum of a thickness of the first capacitor electrode and a thickness of the second capacitor electrode corresponds to a thickness of the second substrate.

11. The semiconductor device according to claim 10, further comprising: a first voltage line connected to the first capacitor electrode; as well as a second voltage line connected to the second capacitor electrode, The first voltage line and the second voltage line are on the same layer as the wiring layer.

12. The semiconductor device according to claim 11, further comprising: a first barrier layer between the first capacitor electrode and the first voltage line; as well as A second barrier layer is between the second capacitor electrode and the second voltage line.

13. The semiconductor device according to claim 12, further comprising: a floating electrode connected to the second substrate; a first dummy barrier layer on the same layer as the first barrier layer; as well as a second dummy barrier layer, on the same layer as the second barrier layer, wherein the floating electrode is on the same layer as the wiring layer, The first dummy barrier layer is between the floating electrode and the second substrate, The second substrate includes a first layer and a second layer on the first layer, and The second dummy barrier layer is between the first layer and the second layer.

14. The semiconductor device according to claim 1, wherein the second capacitor electrode being on the same layer as the gate electrode, The first dielectric layer is on the same layer as the interlayer insulating layer, and A portion of the first capacitor electrode is on the same layer as the first horizontal conductive layer.

15. The semiconductor device according to claim 14, further comprising: a first voltage line connected to the first capacitor electrode; a second voltage line connected to the second capacitor electrode; as well as a connecting structure connecting the second capacitor electrode and the second voltage line and extending in the same direction as the channel structure, The first voltage line and the second voltage line are on the same layer as the wiring layer.

16. A semiconductor device comprising: a first substrate; a second substrate facing the first substrate and comprising a conductive material; a wiring layer between the first substrate and the second substrate; A gate stack structure, comprising an interlayer insulating layer and a gate electrode alternately stacked between the wiring layer and the second substrate; a channel structure passing through the gate stack structure and connected to the second substrate; a first capacitor electrode on the same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; as well as a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on the same layer as at least one of the wiring layer, the second substrate, and the gate electrode.

17. The semiconductor device according to claim 16, wherein The first capacitor electrode is separated from the second substrate.

18. The semiconductor device according to claim 16, further comprising: A first connecting electrode is connected to the first capacitor electrode.

19. An electronic system comprising: main substrate; a semiconductor device, on the main substrate; as well as a controller electrically connected to the semiconductor device on the main substrate, Wherein, the semiconductor device comprises: a first substrate; a wiring layer, on the first substrate; a second substrate on the wiring layer and comprising a conductive material; A gate stack structure, comprising an interlayer insulating layer and a gate electrode alternately stacked on the second substrate; a channel structure passing through the gate stack structure and connected to the second substrate; a first capacitor electrode on the same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; and a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on the same layer as at least one of the wiring layer, the second substrate, and the gate electrode.

20. The electronic system of claim 19, wherein The second capacitor electrode is on the same layer as the wiring layer, and The first dielectric layer is on the same layer as an insulating layer between the wiring layer and the second substrate.

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