Semiconductor device, preparation method and electronic equipment
By simultaneously setting the metal interconnection structure and storage structure in the first dielectric layer of the semiconductor device and using the isolation layer to isolate the electrodes, the complex problem of traditional preparation of variable resistance memory processes is solved, the process is simplified, and the cost and time are reduced , improves the electrical properties and storage capabilities of the device.
Patent Information
- Application Number
- CN202411349034.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2024-12-27
AI Technical Summary
The traditional process of preparing variable resistive memory is complicated, resulting in high costs and long cycles, which is not conducive to large-scale mass production.
By simultaneously setting a metal interconnection structure and a storage structure in the first dielectric layer of the semiconductor device, the first electrode and the second electrode are completely isolated by an isolation layer, and a pulse voltage is applied to form a large resistance difference to store data, simplifying production process to reduce preparation costs and time.
It realizes the addition of device memory storage on the basis of CMOS ultra-dense logic, simplifies the production process, reduces the production cost and time, and improves the electrical properties of semiconductor devices.
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Figure CN119212400A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device. Background Art
[0002] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory. It applies pulse voltage to the metal oxide film in the RRAM to generate a large resistance difference to store digital signals "0" and digital signals "1" to store data. RRAM has the advantages of low power consumption, high rewrite speed and simple structure.
[0003] However, the conventional process for preparing variable resistance memory is extremely complicated, resulting in high preparation cost and long cycle, which is not conducive to large-scale mass production. Summary of the invention
[0004] The purpose of this application is to provide a semiconductor device, a preparation method and an electronic device, which solves the problem that the traditional process of preparing variable resistance memory is extremely complicated, resulting in high preparation cost and long cycle, and improves the electrical properties of semiconductor devices. To achieve the purpose of this application, this application provides the following technical solutions:
[0005] In a first aspect, the present application provides a semiconductor device, comprising:
[0006] substrate;
[0007] A first dielectric layer, located above the substrate;
[0008] A metal interconnect structure, comprising a metal interconnect layer and an interconnect barrier layer wrapping the bottom and side surfaces of the metal interconnect layer;
[0009] A storage structure, comprising a first electrode, a resistive switching layer, a second electrode and an isolation layer, wherein the first electrode surrounds part of the side surface and bottom surface of the second electrode, the resistive switching layer is located between the first electrode and the second electrode, the isolation layer is located on the side surface of the second electrode, and the isolation layer covers the top surface of the first electrode and the resistive switching layer;
[0010] The metal interconnection structure is flush with the top surface and the bottom surface of the storage structure, and the first dielectric layer circumferentially surrounds the metal interconnection structure and the storage structure.
[0011] The semiconductor device of the present application includes a substrate, a first dielectric layer, a metal interconnection structure and a storage structure, wherein the metal interconnection structure includes a metal interconnection layer and an interconnection barrier layer wrapping the bottom and side surfaces of the metal interconnection layer, and the storage structure includes a first electrode, a resistive switching layer, a second electrode and an isolation layer, wherein the first electrode surrounds part of the side and bottom surfaces of the second electrode, the resistive switching layer is located between the first electrode and the second electrode, the isolation layer is located on the side surfaces of the second electrode, and the isolation layer covers the top surfaces of the first electrode and the resistive switching layer, wherein the metal interconnection structure is flush with the top and bottom surfaces of the storage structure, and the first dielectric layer circumferentially surrounds the metal interconnection structure and the storage structure. By simultaneously arranging the metal interconnection structure and the storage structure in the first dielectric layer, the storage structure can be formed while the metal interconnection structure is formed, and the first electrode surrounds part of the side surface and bottom surface of the second electrode, the resistive layer is arranged between the first electrode and the second electrode, and then the first electrode and the second electrode are completely isolated by the isolation layer. On this basis, a pulse voltage is applied to the resistive layer to generate a large resistance difference to store data, thereby realizing the stacking of the variable resistive memory on the logic gate of the complementary metal oxide semiconductor, increasing the memory storage of the device on the basis of the CMOS ultra-dense logic, and simplifying the manufacturing process. There is no need to manufacture the CMOS part after separately manufacturing the variable resistive memory, thereby reducing the manufacturing cost and time, and improving the electrical properties of the semiconductor device.
[0012] In one of the embodiments, it also includes a plurality of metal connection structures, which are respectively located on the top and bottom surfaces of the metal interconnection structure and the top and bottom surfaces of the storage structure. The metal connection structure includes a metal connection layer and a connection barrier layer wrapping the bottom and side surfaces of the metal connection layer.
[0013] In one embodiment, the material of the metal connection layer is different from the material of the metal interconnection layer.
[0014] In one embodiment, it also includes:
[0015] A second dielectric layer is located on the top surface of the substrate, and the metal connection structure on the bottom surface of the metal interconnection structure and the metal connection structure on the bottom surface of the storage structure are both located in the second dielectric layer;
[0016] The third dielectric layer is located between the top surface of the second dielectric layer and the bottom surface of the first dielectric layer, the metal interconnection structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the metal interconnection structure, and the storage structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the storage structure.
[0017] In a second aspect, the present application further provides an electronic device, including:
[0018] A semiconductor device as described in any of the above.
[0019] The electronic device of the present application includes any of the semiconductor devices described above. By simultaneously arranging the metal interconnection structure and the storage structure in the first dielectric layer, the storage structure can be formed while the metal interconnection structure is formed, and the first electrode surrounds part of the side surface and bottom surface of the second electrode, the resistive layer is arranged between the first electrode and the second electrode, and the first electrode and the second electrode are completely isolated by the isolation layer. On this basis, a pulse voltage is applied to the resistive layer to generate a large resistance difference to store data, thereby realizing the stacking of the variable resistive memory on the logic gate of the complementary metal oxide semiconductor, increasing the memory storage of the device on the basis of the CMOS ultra-dense logic, and simplifying the manufacturing process. There is no need to manufacture the CMOS part after separately manufacturing the variable resistive memory, thereby reducing the manufacturing cost and time, and improving the electrical properties of the semiconductor device.
[0020] In a third aspect, the present application further provides a method for preparing a semiconductor device, comprising:
[0021] providing a substrate;
[0022] forming a first dielectric layer above the substrate;
[0023] A metal interconnect structure and a storage structure are formed in the first dielectric layer, wherein the metal interconnect structure includes a metal interconnect layer and an interconnect barrier layer wrapping the bottom and side surfaces of the metal interconnect layer, and the storage structure includes a first electrode, a resistive switching layer, a second electrode and an isolation layer, wherein the first electrode surrounds part of the side and bottom surfaces of the second electrode, the resistive switching layer is located between the first electrode and the second electrode, the isolation layer is located on the side walls of the second electrode, and the isolation layer covers the top surfaces of the first electrode and the resistive switching layer, wherein the metal interconnect structure is flush with the top and bottom surfaces of the storage structure, and the first dielectric layer circumferentially surrounds the metal interconnect structure and the storage structure.
[0024] The preparation method of the semiconductor device of the present application includes providing a substrate; forming a first dielectric layer on the substrate; and finally forming a metal interconnection structure and a storage structure in the first dielectric layer, wherein the metal interconnection structure includes a metal interconnection layer and an interconnection barrier layer wrapping the bottom and side surfaces of the metal interconnection layer, and the storage structure includes a first electrode, a resistive switching layer, a second electrode and an isolation layer, wherein the first electrode surrounds part of the side and bottom surfaces of the second electrode, the resistive switching layer is located between the first electrode and the second electrode, the isolation layer is located on the side wall of the second electrode, and the isolation layer covers the top surface of the first electrode and the resistive switching layer, wherein the metal interconnection structure is flush with the top and bottom surfaces of the storage structure, and the first dielectric layer circumferentially surrounds the metal interconnection structure and the storage structure. By simultaneously arranging the metal interconnection structure and the storage structure in the first dielectric layer, the storage structure can be formed while the metal interconnection structure is formed, and the first electrode surrounds part of the side surface and bottom surface of the second electrode, the resistive layer is arranged between the first electrode and the second electrode, and then the first electrode and the second electrode are completely isolated by the isolation layer. On this basis, a pulse voltage is applied to the resistive layer to generate a large resistance difference to store data, thereby realizing the stacking of the variable resistive memory on the logic gate of the complementary metal oxide semiconductor, increasing the memory storage of the device on the basis of the CMOS ultra-dense logic, and simplifying the manufacturing process. There is no need to manufacture the CMOS part after separately manufacturing the variable resistive memory, thereby reducing the manufacturing cost and time, and improving the electrical properties of the semiconductor device.
[0025] In one embodiment, forming a metal interconnect structure and a storage structure in the first dielectric layer includes:
[0026] Forming a first groove and a second groove spaced apart from each other along a first direction in the first dielectric layer;
[0027] forming an interconnection barrier layer and a metal interconnection layer in the first trench and the second trench to form a metal interconnection structure;
[0028] removing the interconnection barrier layer and the metal interconnection layer in the second trench;
[0029] A first electrode material layer, an initial resistive layer, and a second electrode material layer are sequentially stacked along a second direction in the second trench, wherein the first electrode material layer surrounds the sidewall and the bottom of the second electrode material layer, and the initial resistive layer is located between the first electrode material layer and the second electrode material layer;
[0030] Carving back the top surface of the first electrode material layer and the top surface of the initial resistive layer to form a first groove and a second groove;
[0031] An isolation layer is formed in the first groove and the second groove to form a storage structure.
[0032] In one embodiment, before forming the first dielectric layer, and after forming the metal interconnect structure and the storage structure in the first dielectric layer, the method includes:
[0033] A plurality of metal connection structures are formed, wherein the metal connection structures include a metal connection layer and a connection barrier layer wrapping the bottom and side surfaces of the metal connection layer, wherein the plurality of metal connection structures are respectively located on the top and bottom surfaces of the metal interconnection structure and the top and bottom surfaces of the storage structure.
[0034] In one embodiment, the material of the metal connection layer is different from the material of the metal interconnection layer.
[0035] In one embodiment, after providing the substrate and before forming the first dielectric layer, the method further includes:
[0036] forming a second dielectric layer on the top surface of the substrate, wherein the metal connection structure on the bottom surface of the metal interconnection structure and the metal connection structure on the bottom surface of the storage structure are both located in the second dielectric layer;
[0037] A third dielectric layer is formed on the top surface of the second dielectric layer, the metal interconnection structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the metal interconnection structure, and the storage structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the storage structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0039] FIG1 is a schematic cross-sectional view of a semiconductor device provided in an embodiment;
[0040] FIG2 is a flow chart of a method for preparing a semiconductor device provided in another embodiment;
[0041] FIG3 is a flow chart of steps S151 to S156 in a method for preparing a semiconductor device provided in another embodiment;
[0042] 4 is a schematic cross-sectional view of a structure obtained in step S151 in a method for preparing a semiconductor device provided in another embodiment;
[0043] 5 is a schematic cross-sectional view of a structure obtained in step S152 of a method for preparing a semiconductor device provided in another embodiment;
[0044] 6 is a schematic cross-sectional view of a structure obtained in step S153 in a method for preparing a semiconductor device provided in another embodiment;
[0045] 7 and 8 are schematic cross-sectional views of a structure obtained in step S154 of a method for preparing a semiconductor device provided in another embodiment;
[0046] 9 is a schematic cross-sectional view of a structure obtained in step S155 in a method for preparing a semiconductor device provided in another embodiment;
[0047] FIG. 10 is a schematic cross-sectional view of a structure obtained in step S156 in a method for preparing a semiconductor device provided in another embodiment.
[0048] Description of Reference Numerals
[0049] 10. substrate; 20. first dielectric layer; 30. metal interconnection structure; 301. metal interconnection layer; 302. interconnection barrier layer; 40. storage structure; 401. first electrode; 4011. first electrode material layer; 402. resistive layer; 4021. initial resistive layer; 403. second electrode; 4031. second electrode material layer; 404. isolation layer; 4041. isolation material layer; 50. metal connection structure; 501. metal connection layer; 502. connection barrier layer; 60. second dielectric layer; 70. third dielectric layer; 80. first groove; 90. second groove; 100. first recess; 110. second recess. DETAILED DESCRIPTION
[0050] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0052] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0053] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0054] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0055] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.
[0056] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory. It applies pulse voltage to the metal oxide film in the RRAM to generate a large resistance difference to store digital signals "0" and digital signals "1" to store data. RRAM has the advantages of low power consumption, high rewrite speed and simple structure.
[0057] However, the conventional process for preparing variable resistance memory is extremely complicated, resulting in high preparation cost and long cycle, which is not conducive to large-scale mass production.
[0058] An embodiment of the present application provides a semiconductor device. Please refer to FIG. 1 . The semiconductor device may include: a substrate 10 , a first dielectric layer 20 , a metal interconnect structure 30 and a storage structure 40 .
[0059] The first dielectric layer 20 is located above the substrate 10; the metal interconnection structure 30 includes a metal interconnection layer 301 and an interconnection barrier layer 302 that wraps the bottom and side surfaces of the metal interconnection layer 301; the storage structure 40 includes a first electrode 401, a resistive layer 402, a second electrode 403 and an isolation layer 404, wherein the first electrode 401 surrounds part of the side and bottom surfaces of the second electrode 403, the resistive layer 402 is located between the first electrode 401 and the second electrode 403, the isolation layer 404 is located on the side of the second electrode 403, and the isolation layer 404 covers the top surfaces of the first electrode 401 and the resistive layer 402; wherein the metal interconnection structure 30 is flush with the top and bottom surfaces of the storage structure 40, and the first dielectric layer 20 circumferentially surrounds the metal interconnection structure 30 and the storage structure 40.
[0060] Exemplarily, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer.
[0061] For example, the first dielectric layer 20 may include, but is not limited to, at least one of hafnium oxide (HfOx), aluminum oxide (AlOx), hafnium aluminum oxide (HfAlO), and tantalum oxide (TaOx).
[0062] By way of example, the metal interconnection layer 301 may include but is not limited to a metal layer, such as a cobalt metal layer, a molybdenum metal layer or a rubidium metal layer.
[0063] By way of example, the interconnection barrier layer 302 may include, but is not limited to, a titanium nitride layer or a tantalum nitride layer.
[0064] Exemplarily, the first electrode 401 may include but is not limited to a tantalum nitride electrode or a titanium nitride electrode.
[0065] For example, the resistive layer 402 may include but is not limited to a metal oxide layer. For example, the resistive layer 402 may be a hafnium oxide (HfOx) layer, an aluminum oxide (AlOx) layer, a tantalum oxide (TaOx) layer, or a combination of the above layers.
[0066] Exemplarily, the second electrode 403 may include but is not limited to a tantalum nitride electrode or a titanium nitride electrode.
[0067] By way of example, the isolation layer 404 may include, but is not limited to, a silicon dioxide layer, a silicon nitride layer, a silicon carbide layer, or the like.
[0068] The semiconductor device of the present application includes a substrate 10, a first dielectric layer 20, a metal interconnection structure 30 and a storage structure 40, wherein the metal interconnection structure 30 includes a metal interconnection layer 301 and an interconnection barrier layer 302 wrapping the bottom and side surfaces of the metal interconnection layer 301, and the storage structure 40 includes a first electrode 401, a resistive layer 402, a second electrode 403 and an isolation layer 404, wherein the first electrode 401 surrounds part of the side and bottom surfaces of the second electrode 403, the resistive layer 402 is located between the first electrode 401 and the second electrode 403, the isolation layer 404 is located on the side of the second electrode 403, and the isolation layer 404 covers the top surfaces of the first electrode 401 and the resistive layer 402, wherein the metal interconnection structure 30 is flush with the top and bottom surfaces of the storage structure 40, and the first dielectric layer 20 circumferentially surrounds the metal interconnection structure 30 and the storage structure 40. By simultaneously arranging the metal interconnect structure 30 and the storage structure 40 in the first dielectric layer 20, the storage structure 40 can be formed at the same time as the metal interconnect structure 30 is formed, and the first electrode 401 surrounds part of the side surface and bottom surface of the second electrode 403, the resistive layer 402 is arranged between the first electrode 401 and the second electrode 403, and then the first electrode 401 and the second electrode 403 are completely isolated by the isolation layer 404. On this basis, a pulse voltage is applied to the resistive layer 402 to generate a large resistance difference to store data, thereby realizing the stacking of the variable resistive memory on the logic gate of the complementary metal oxide semiconductor, increasing the memory storage of the device on the basis of the CMOS ultra-dense logic, and simplifying the manufacturing process. It is no longer necessary to manufacture the CMOS part after separately manufacturing the variable resistive memory, thereby reducing the manufacturing cost and time, and improving the electrical properties of the semiconductor device.
[0069] In some embodiments, please continue to refer to Figure 1, the semiconductor device also includes a plurality of metal connection structures 50, and the plurality of metal connection structures 50 are respectively located on the top surface and bottom surface of the metal interconnection structure 30 and the top surface and bottom surface of the storage structure 40, and the metal connection structure 50 includes a metal connection layer 501 and a connection barrier layer 502 wrapping the bottom surface and side surface of the metal connection layer 501.
[0070] As an example, the metal connection layer 501 may include but is not limited to a copper metal layer. The connection barrier layer 502 may include but is not limited to a titanium nitride layer or a tantalum nitride layer.
[0071] In the embodiment of the present application, by providing a connection barrier layer 502 to wrap the bottom and side surfaces of the metal connection layer 501, the copper metal connection layer 501 can be prevented from diffusing into the resistive layer outside the metal connection structure, and the connection barrier layer 502 has an adhesive effect, which can make the metal connection layer 501 more easily adhere to the surface of the connection barrier layer 502, thereby being more conducive to the formation of the metal connection layer 501.
[0072] In some embodiments, please continue to refer to FIG. 1 , the material of the metal connection layer is different from the material of the metal interconnection layer.
[0073] As an example, the different materials of the metal connection layer 501 and the metal interconnection layer 301 can be more conducive to removing the metal connection layer 501 to prepare for the subsequent preparation of the storage structure 40 .
[0074] In some embodiments, please continue to refer to Figure 1, the semiconductor device also includes: a second dielectric layer 60, located on the top surface of the substrate 10, and the metal connection structure 50 on the bottom surface of the metal interconnection structure 30 and the metal connection structure 50 on the bottom surface of the storage structure 40 are both located in the second dielectric layer 60; a third dielectric layer 70, located between the top surface of the second dielectric layer 60 and the bottom surface of the first dielectric layer 20, the metal interconnection structure 30 penetrates the third dielectric layer 70 and contacts the metal connection structure 50 on the bottom surface of the metal interconnection structure 30, and the storage structure 40 penetrates the third dielectric layer 70 and contacts the metal connection structure 50 on the bottom surface of the storage structure 40.
[0075] As an example, the second dielectric layer 60 may include but is not limited to a low-K dielectric material, for example, the second dielectric layer 60 may be silicon oxide doped with carbon, phosphorus or boron, and a composite material thereof. The third dielectric layer 70 may include but is not limited to an insulating layer, for example, the second dielectric layer 60 may be a silicon nitride layer, a silicon carbonitride layer, a silicon carbide layer, or a fluorosilicate glass layer, etc.; the second dielectric layer 60 may also be a stacked structure of the above layers.
[0076] An embodiment of the present application provides an electronic device, comprising the semiconductor device in any one of the above embodiments.
[0077] The electronic device of the present application includes the semiconductor device in any of the above embodiments. By simultaneously arranging the metal interconnection structure and the storage structure in the first dielectric layer, the storage structure can be formed at the same time as the metal interconnection structure is formed, and the first electrode surrounds part of the side surface and bottom surface of the second electrode, the resistive layer is arranged between the first electrode and the second electrode, and the first electrode and the second electrode are completely isolated by the isolation layer. On this basis, a pulse voltage is applied to the resistive layer to generate a large resistance difference to store data, thereby realizing the stacking of the variable resistive memory on the logic gate of the complementary metal oxide semiconductor, increasing the memory storage of the device on the basis of the CMOS ultra-dense logic, and simplifying the manufacturing process. There is no need to manufacture the CMOS part after separately manufacturing the variable resistive memory, thereby reducing the manufacturing cost and time, and improving the electrical properties of the semiconductor device.
[0078] The present application embodiment provides a method for preparing a semiconductor device. Please refer to FIG. 2 . The method for preparing a semiconductor device may include:
[0079] S11: providing a substrate.
[0080] As an example, please continue to refer to Figure 1, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer.
[0081] S14: forming a first dielectric layer above the substrate.
[0082] As an example, please continue to refer to Figure 1. The first dielectric layer 20 can be formed on the substrate 10 by using but not limited to a molecular beam epitaxy process (MBE), a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or an atomic layer deposition process (ALD).
[0083] S15: forming a metal interconnect structure and a storage structure in the first dielectric layer, wherein the metal interconnect structure comprises a metal interconnect layer and an interconnect barrier layer wrapping the bottom and side surfaces of the metal interconnect layer, and the storage structure comprises a first electrode, a resistive switching layer, a second electrode and an isolation layer, wherein the first electrode surrounds part of the side and bottom surfaces of the second electrode, the resistive switching layer is located between the first electrode and the second electrode, the isolation layer is located on the side walls of the second electrode, and the isolation layer covers the top surfaces of the first electrode and the resistive switching layer, wherein the metal interconnect structure is flush with the top and bottom surfaces of the storage structure, and the first dielectric layer circumferentially surrounds the metal interconnect structure and the storage structure.
[0084] The preparation method of the semiconductor device of the present application includes providing a substrate; forming a first dielectric layer on the substrate; and finally forming a metal interconnection structure and a storage structure in the first dielectric layer, wherein the metal interconnection structure includes a metal interconnection layer and an interconnection barrier layer wrapping the bottom and side surfaces of the metal interconnection layer, and the storage structure includes a first electrode, a resistive switching layer, a second electrode and an isolation layer, wherein the first electrode surrounds part of the side and bottom surfaces of the second electrode, the resistive switching layer is located between the first electrode and the second electrode, the isolation layer is located on the side wall of the second electrode, and the isolation layer covers the top surface of the first electrode and the resistive switching layer, wherein the metal interconnection structure is flush with the top and bottom surfaces of the storage structure, and the first dielectric layer circumferentially surrounds the metal interconnection structure and the storage structure. By simultaneously arranging the metal interconnection structure and the storage structure in the first dielectric layer, the storage structure can be formed while the metal interconnection structure is formed, and the first electrode surrounds part of the side surface and bottom surface of the second electrode, the resistive layer is arranged between the first electrode and the second electrode, and then the first electrode and the second electrode are completely isolated by the isolation layer. On this basis, a pulse voltage is applied to the resistive layer to generate a large resistance difference to store data, thereby realizing the stacking of the variable resistive memory on the logic gate of the complementary metal oxide semiconductor, increasing the memory storage of the device on the basis of the CMOS ultra-dense logic, and simplifying the manufacturing process. There is no need to manufacture the CMOS part after separately manufacturing the variable resistive memory, thereby reducing the manufacturing cost and time, and improving the electrical properties of the semiconductor device.
[0085] In some embodiments, referring to FIG. 3 , forming a metal interconnect structure and a storage structure in the first dielectric layer may include the following steps: step S151 to step S156 .
[0086] S151: forming a first trench and a second trench spaced apart and distributed along a first direction in a first dielectric layer.
[0087] As an example, referring to FIG. 4 , a wet etching process or a dry etching process may be used but is not limited to form first trenches 80 and second trenches 90 spaced apart along the first direction ox in the first dielectric layer 20 .
[0088] S152: forming an interconnection barrier layer and a metal interconnection layer in the first trench and the second trench to form a metal interconnection structure.
[0089] As an example, referring to FIG. 5 , a molecular beam epitaxy (MBE), a physical vapor deposition (PVD), a chemical vapor deposition (CVD), or an atomic layer deposition (ALD) process may be used but is not limited to form an interconnection barrier layer 302 and a metal interconnection layer 301 in the first trench 80 and the second trench 90 to form a metal interconnection structure 30.
[0090] S153: removing the interconnection barrier layer and the metal interconnection layer in the second trench.
[0091] As an example, please continue to refer to FIG. 6 , the interconnection barrier layer 302 and the metal interconnection layer 301 in the second trench 90 may be removed by, but not limited to, a wet etching process or a dry etching process.
[0092] S154: forming a first electrode material layer, an initial resistive layer, and a second electrode material layer sequentially stacked along a second direction in the second groove, wherein the first electrode material layer surrounds the side wall and the bottom of the second electrode material layer, and the initial resistive layer is located between the first electrode material layer and the second electrode material layer.
[0093] As an example, chemical vapor deposition, atomic layer deposition process or organic vapor phase reaction can be used but not limited to form a first electrode material layer 4011, an initial resistive layer 4021 and a second electrode material layer 4031 stacked in sequence along the second direction oy in the second trench 90 and on the top surface of the first dielectric layer 20 and the top surface of the metal interconnect structure 30, as shown in FIG7. It should be noted that chemical mechanical polishing is also included to remove the first electrode material layer 4011, the initial resistive layer 4021 and the second electrode material layer 4031 on the top surface of the first dielectric layer 20 and the top surface of the metal interconnect structure 30, as shown in FIG8.
[0094] S155: etching back the top surface of the first electrode material layer and the top surface of the initial resistive layer to form a first groove and a second groove.
[0095] As an example, referring to FIG. 9 , a wet etching process or a dry etching process may be used but is not limited to etch back the top surface of the first electrode material layer 4011 and the top surface of the initial resistive layer 4021 to form the first groove 100 and the second groove 110 .
[0096] S156: forming an isolation layer in the first groove and the second groove to form a storage structure.
[0097] As an example, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process may be used, but not limited to, to form an isolation material layer 4041 in the first groove 100, in the second groove 110, on the top surface of the first dielectric layer 20, and on the top surface of the metal interconnect structure 30, as shown in FIG10. It should be noted that a chemical mechanical polishing process may also be used to remove the isolation material layer 4041 on the top surface of the first dielectric layer 20 and the top surface of the metal interconnect structure 30 to form an isolation layer 404, thereby forming a storage structure 40, as shown in FIG1.
[0098] In the embodiment of the present application, a storage structure can be formed while a metal interconnection structure is formed, which can simplify the preparation process of embedding a variable resistive memory into a CMOS, saving preparation cost and preparation time. The first electrode surrounds part of the side and bottom surface of the second electrode, and the resistive layer is disposed between the first electrode and the second electrode. The first electrode and the second electrode are then isolated by an isolation layer, so that the first electrode and the second electrode can be completely isolated. On this basis, a pulse voltage is applied to the resistive layer to generate a large resistance difference to store data, thereby realizing the stacking of the variable resistive memory on the logic gate of the complementary metal oxide semiconductor. On the basis of the CMOS ultra-dense logic, the memory storage of the device is increased, and the manufacturing process is simplified. There is no need to manufacture the CMOS part after separately manufacturing the variable resistive memory, thereby reducing the manufacturing cost and manufacturing time, and improving the electrical properties of the semiconductor device.
[0099] In some embodiments, before forming the first dielectric layer, and after forming the metal interconnection structure and the storage structure in the first dielectric layer, the steps include: forming a plurality of metal connection structures, the metal connection structure including a metal connection layer and a connection barrier layer wrapping the bottom and side surfaces of the metal connection layer, wherein the plurality of metal connection structures are respectively located on the top and bottom surfaces of the metal interconnection structure and the top and bottom surfaces of the storage structure.
[0100] As an example, please continue to refer to FIG. 1 , the plurality of metal connection structures 50 may be formed by, but not limited to, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.
[0101] In some embodiments, after providing the substrate and before forming the first dielectric layer, the following steps may also be included:
[0102] S12: forming a second dielectric layer on the top surface of the substrate, wherein the metal connection structure on the bottom surface of the metal interconnect structure and the metal connection structure on the bottom surface of the storage structure are both located in the second dielectric layer.
[0103] As an example, please continue to refer to FIG. 1 , the second dielectric layer 60 may be formed on the top surface of the substrate 10 by using, but not limited to, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.
[0104] S13: forming a third dielectric layer on the top surface of the second dielectric layer, the metal interconnection structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the metal interconnection structure, and the storage structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the storage structure.
[0105] As an example, please continue to refer to FIG. 1 , the third dielectric layer 70 may be formed on the top surface of the second dielectric layer 60 by using, but not limited to, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.
[0106] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0107] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A semiconductor device, characterized in that: include: substrate; A first dielectric layer, located above the substrate; A metal interconnect structure, comprising a metal interconnect layer and an interconnect barrier layer wrapping the bottom and side surfaces of the metal interconnect layer; A storage structure, comprising a first electrode, a resistive switching layer, a second electrode and an isolation layer, wherein the first electrode surrounds part of the side surface and bottom surface of the second electrode, the resistive switching layer is located between the first electrode and the second electrode, the isolation layer is located on the side surface of the second electrode, and the isolation layer covers the top surface of the first electrode and the resistive switching layer; The metal interconnection structure is flush with the top surface and the bottom surface of the storage structure, and the first dielectric layer circumferentially surrounds the metal interconnection structure and the storage structure.
2. The semiconductor device according to claim 1, wherein: It also includes multiple metal connection structures, which are respectively located on the top and bottom surfaces of the metal interconnection structure and the top and bottom surfaces of the storage structure. The metal connection structure includes a metal connection layer and a connection barrier layer that wraps the bottom and side surfaces of the metal connection layer.
3. The semiconductor device according to claim 2, characterized in that The material of the metal connection layer is different from the material of the metal interconnection layer.
4. The semiconductor device according to claim 2, characterized in that Also includes: A second dielectric layer is located on the top surface of the substrate, and the metal connection structure on the bottom surface of the metal interconnection structure and the metal connection structure on the bottom surface of the storage structure are both located in the second dielectric layer; The third dielectric layer is located between the top surface of the second dielectric layer and the bottom surface of the first dielectric layer, the metal interconnection structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the metal interconnection structure, and the storage structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the storage structure.
5. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 4.
6. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a first dielectric layer above the substrate; A metal interconnect structure and a storage structure are formed in the first dielectric layer, wherein the metal interconnect structure includes a metal interconnect layer and an interconnect barrier layer wrapping the bottom and side surfaces of the metal interconnect layer, and the storage structure includes a first electrode, a resistive switching layer, a second electrode and an isolation layer, wherein the first electrode surrounds part of the side and bottom surfaces of the second electrode, the resistive switching layer is located between the first electrode and the second electrode, the isolation layer is located on the side walls of the second electrode, and the isolation layer covers the top surfaces of the first electrode and the resistive switching layer, wherein the metal interconnect structure is flush with the top and bottom surfaces of the storage structure, and the first dielectric layer circumferentially surrounds the metal interconnect structure and the storage structure.
7. The method for preparing a semiconductor device according to claim 6, characterized in that: The forming of the metal interconnect structure and the storage structure in the first dielectric layer comprises: forming a first groove and a second groove spaced apart from each other along a first direction in the first dielectric layer; forming an interconnection barrier layer and a metal interconnection layer in the first trench and the second trench to form a metal interconnection structure; removing the interconnection barrier layer and the metal interconnection layer in the second trench; A first electrode material layer, an initial resistive layer, and a second electrode material layer are sequentially stacked along a second direction in the second trench, wherein the first electrode material layer surrounds the sidewall and the bottom of the second electrode material layer, and the initial resistive layer is located between the first electrode material layer and the second electrode material layer; Carving back the top surface of the first electrode material layer and the top surface of the initial resistive layer to form a first groove and a second groove; An isolation layer is formed in the first groove and the second groove to form a storage structure.
8. The method for preparing a semiconductor device according to claim 6, characterized in that: Before forming the first dielectric layer, and after forming the metal interconnect structure and the storage structure in the first dielectric layer, the method includes: A plurality of metal connection structures are formed, wherein the metal connection structures include a metal connection layer and a connection barrier layer wrapping the bottom and side surfaces of the metal connection layer, wherein the plurality of metal connection structures are respectively located on the top and bottom surfaces of the metal interconnection structure and the top and bottom surfaces of the storage structure.
9. The method for preparing a semiconductor device according to claim 8, characterized in that: The material of the metal connection layer is different from the material of the metal interconnection layer.
10. The method for preparing a semiconductor device according to claim 8, characterized in that: After providing the substrate and before forming the first dielectric layer, the method further includes: forming a second dielectric layer on the top surface of the substrate, wherein the metal connection structure on the bottom surface of the metal interconnection structure and the metal connection structure on the bottom surface of the storage structure are both located in the second dielectric layer; A third dielectric layer is formed on the top surface of the second dielectric layer, the metal interconnection structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the metal interconnection structure, and the storage structure penetrates the third dielectric layer and contacts the metal connection structure on the bottom surface of the storage structure.