Optical encoder

Abstract

A controller of an optical encoder is provided, the controller configured to: receive an electronic signal, where a value of the electronic signal is based on a complex element; receiving a feedback signal based on a phase drift associated with a photonic device of the optical encoder; modifying the received electronic signal based on the received feedback signal to generate a modified electronic signal; and providing the modified electronic signal to modulate the photonic device.

Description

Technical Field

[0001] The present disclosure relates to methods and apparatus for controlling an optical encoder. The optical encoder encodes and decodes complex numbers to and from optical signals and performs arithmetic using optical circuits. Background Art

[0002] Optical computing methods are expected to perform similar operations at much higher speeds while consuming much less energy than using digital electronics to perform mathematical operations. However, optical computing systems are typically designed to be compatible only with integers and are limited by digital interfaces with existing hardware. It would be beneficial to provide optical computing systems that can perform more complex operations. Summary of the invention

[0003] This Summary introduces concepts that are described in greater detail in the Detailed Description. It should not be used to identify essential features of the claimed subject matter, nor should it be used to limit the scope of the claimed subject matter.

[0004] The methods disclosed herein generally relate to a system and method for providing an improved optical computing system capable of performing operations that are much more complex than those performed by existing optical computing systems. As optical computing systems become more complex, various factors and requirements need to be addressed and compensated for so that the improved optical computing system can operate reliably and efficiently. Further, it is desirable that controllers and control circuits are compatible with multiple types of photonic devices so that each type of photonic device does not require its own custom control circuitry. The present disclosure provides mechanisms for addressing these objectives.

[0005] In more detail, the inventors have recognized that as optical computing systems become more complex, e.g., to be compatible with calculations involving complex numbers, optical computing systems become sensitive to phase changes and phase effects operating within / on components of the optical computing systems. These phase effects must be compensated for to ensure the accuracy of the calculations performed. The present disclosure provides methods and apparatus directed to a controller of an optical encoder, e.g., that may be used as part of an optical computing system, that is capable of accounting for such phase effects.

[0006] The inventors have also recognized that an array of photonic device types may be needed for use in an optical computing system. It is desirable that the controller and control circuitry can be easily adjusted to accommodate different types of photonic devices. This avoids the need to provide a different controller type to match each possible photonic device type.

[0007] According to a first aspect of the present disclosure, a controller of an optical encoder is provided, the controller being configured to: receive an electronic signal, wherein the value of the electronic signal is based on a complex element; receive a feedback signal based on a phase drift associated with a photonic device of the optical encoder; modify the received electronic signal based on the received feedback signal to generate a modified electronic signal; and provide the modified electronic signal to modulate the photonic device. Obviously, there may be more than one controller and more than one photonic device. The controller and the photonic device may operate together in a manner described as a one-to-one relationship, a one-to-many relationship, or a many-to-one relationship. Therefore, a reference to "the controller / controller" may be interpreted as a reference to "one or more controllers", and a reference to "the photonic device / photonic device" may be interpreted as a reference to "one or more photonic devices".

[0008] A "complex element" in this context may be understood to mean a complex number or a component of a complex number. A component of a complex number may be the real or imaginary part of a complex number, or may be based on the real or imaginary part of a complex number (e.g., a component may be the modulus of the real or imaginary part of a complex number, or a positive or negative value of the real or imaginary part of a complex number).

[0009] In the manner just described, the controller is able to compensate for phase drift of the photonic device of the optical encoder. As described above, such phase drift effects may otherwise impair the ability of the photonic device (and by extension, the optical computing system as a whole) to perform accurate and reliable calculations and operations. By receiving a feedback signal related to the phase drift and using the feedback signal to modify the input signal to the photonic device, a feedback loop can be established, which in some arrangements can continuously or periodically update the electronic signal as needed. Thus, any phase drift of the photonic device can be continuously or periodically compensated, thereby ensuring reliable and accurate calculations.

[0010] The feedback signal may be received as a bias voltage provided via feedback logic. In this way, information about the phase drift of the photonic device may be received and processed by the feedback logic, and the feedback logic may then be configured to provide an appropriate correction to the electronic signal in the form of a bias voltage provided to the controller. In this way, the feedback logic may be adjusted as needed based on the type of photonic device used and taking into account any other requirements that may affect the desired correction to the electronic signal.

[0011] The controller may be configured to split the received electronic signal into a first signal component and a second signal component. This may advantageously enable the first signal component and the second signal component to be processed differently and, optionally, to encode different information, as will be described in more detail below.

[0012] The second signal component may be an inverted version of the first signal component. This is done to increase the dynamic operating range of the photonic devices and reduce quantization noise from these devices; this in turn improves the bit precision / accuracy / addressability limits of the photonic devices.

[0013] The controller may invert the second signal component of the divided signal in the digital domain or the analog domain. For example, in one arrangement, the controller may include a push-pull amplifier configured to invert the second signal component in the analog domain. In another arrangement, the controller may include an inverter configured to invert the second signal component in the digital domain. If the second signal component is inverted in the digital domain, the circuit may be advantageously simplified. This is because inversion in the analog domain may require additional circuit components, such as a push-pull amplifier. Such a push-pull amplifier may remove AC coupling or add DC artifacts to the second signal component, which may require the use of additional circuits to correct. Inverting the second signal component in the digital domain avoids the need for such corrections and associated components. However, inverting the digital signal requires two digital-to-analog converters, which may increase power consumption. A compromise between designs is achieved by considering the total electrical power budget of the electronic circuit.

[0014] The controller may be configured to receive an adjustment signal to correct a DC offset on the second signal component, and to modify the second signal component based on the received adjustment signal to generate a modified second signal component. Correcting the DC offset or correcting any DC artifacts advantageously ensures that the second signal component maintains AC coupling. AC coupling results in the DC component or DC offset of the signal being removed, so the resolution of the signal can be increased. Such AC coupling may be particularly advantageous when processing high frequency signals or when there is a large DC offset.

[0015] The controller can be configured to modify the received electronic signal by adjusting the first signal component and the second signal component to offset the phase drift associated with the photonic device. This is a mechanism by which the controller can compensate for the phase drift of the photonic device. Compensating at the level of the split signal components provides a finer level of control, precision, and flexibility. For example, the first signal component can be used to carry a data signal to one or more photonic devices, while the second signal component can be used to account for and correct the phase drift effects of the photonic device. In such an example, the second signal component can then be used to modify the first signal component as needed to compensate for the phase drift.

[0016] The controller can be configured to modify the received electronic signal by adjusting the first signal component and the second signal component so that their swing voltages span the dynamic operating range of the photonic device. This adjustment advantageously enables the voltage to swing close to its maximum value or rail-to-rail without the waveform being clipped. This enables signal distortion to be reduced and the amplitude of the output signal to be increased.

[0017] The controller may be configured to receive an indication of a dynamic operating range of the photonic device and to modify the received electronic signal based on the received indication of the dynamic operating range. This further enables the signal provided to the photonic device to take into account the operating parameters and limitations of the photonic device, thereby ultimately enabling improved control and, therefore, more accurate and reliable calculations and operations. Adjusting the signal based on the dynamic operating range of the photonic device also again enables the voltage to swing close to its maximum value or rail-to-rail while the waveform is not clipped, again enabling reduced signal distortion and increased amplitude of the output signal.

[0018] The controller may be configured to amplify the received electronic signal. Signal amplification in this manner advantageously allows the output signal to have a higher amplitude without changing the shape of the input signal. Amplification also helps to minimize the effects of signal noise or interference.

[0019] The received electronic signal may be a digital electronic signal. The controller may be configured to convert the received (digital) electronic signal into an analog electronic signal using a Digital to Analogue Converter (DAC).

[0020] The controller may be configured to AC couple the analog electronic signal to adjust the DC offset of the analog electronic signal. Correcting the DC offset or correcting any DC artifacts advantageously ensures that the signal maintains AC coupling. AC coupling results in the DC component or DC offset of the signal being removed, so the resolution of the signal may be increased. Such AC coupling may be particularly advantageous when processing high frequency signals or when there is a large DC offset.

[0021] The controller can be configured to modify the received electronic signal to compensate for the phase offset caused by the push-pull amplifier of the optical encoder. This enables the system to compensate for the undesired phase effects caused by the push-pull amplifier to be corrected. Otherwise, such phase effects may impair the ability of the optical computing system to perform accurate and reliable calculations and operations.

[0022] The controller may be configured to provide the modified electronic signal by: providing a first portion of the modified electronic signal, wherein the first portion moves quickly; and providing a second portion of the modified electronic signal, wherein the second portion moves slowly. In this context, a "fast moving" signal describes an AC data signal. In this context, a "slow moving" signal describes a slowly moving DC signal. The slowly moving component of the circuit may typically include a DC component.

[0023] In one arrangement, the fast moving signal may include the data signal, while the slow moving signal may include the correction signal. In this way, the fast moving signal may carry data to the photonic device quickly, while the slow moving signal may encode the correction facilitated by the received feedback signal. The slow moving signal may then be used to modify the fast moving signal as needed. This is beneficial because phase drifts of the photonic device occur slowly, and therefore the slow moving signal is sufficient to capture and correct these phase effects. Phase drifts can only be corrected when they occur, so the fast moving signal will be less suitable for correcting phase drifts. At the same time, the fast moving signal may continue to transmit data to the photonic device at a fast rate.

[0024] Modifying the received electronic signal may generate a second portion of the modified electronic signal. The received electronic signal may be a multi-bit signal. The received electronic signal may be received via an interface and at least one buffer. The interface may include a digital input and output board.

[0025] According to a second aspect of the present disclosure, there is provided an electronic to optical encoder, comprising: a controller as described herein and a photonic device as described herein. The photonic device comprises a modulator, the modulator being configured to apply a first modulation element to an optical input signal based on a modified electronic signal, and the first modulation element being operable to encode a complex element onto the optical input signal to generate an encoded optical signal.

[0026] According to a third aspect of the present disclosure, a method for being executed by a controller of an optical encoder is provided, the method comprising: receiving an electronic signal, wherein a value of the electronic signal is based on a complex element; receiving a feedback signal based on a phase drift associated with a photonic device of the optical encoder; modifying the received electronic signal based on the received feedback signal to generate a modified electronic signal; and providing the modified electronic signal to modulate the photonic device.

[0027] The present disclosure generally relates to improved optical computing systems capable of performing operations of increasing complexity. More specifically, the present disclosure provides methods and apparatus that allow optical computing systems to compensate for phase effects that affect components of the system. These phase effects do not adversely affect more primitive optical computing systems, however, the inventors have recognized that as the complexity of optical computing systems increases, these phase effects must be taken into account. Compensating for these effects ensures the reliability and accuracy of calculations performed by the optical computing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Specific embodiments are described below by way of example only and with reference to the accompanying drawings, in which:

[0029] Figure 1a to Figure 1c is an Argentograph including complex curves;

[0030] Figure 2 Photonic circuit components (modulators), their photonic functions and their mathematical operators applied to complex elements in the optical domain are shown;

[0031] Figure 3a A method of encoding a complete complex number onto an optical input signal according to an embodiment is shown;

[0032] Figure 3b An optical encoder according to an embodiment is shown;

[0033] Figure 4a An optical encoder including a controller according to an embodiment is shown;

[0034] Figure 4b to Figure 4g Shows Figure 3b and Figure 4a A specific example of an optical encoder;

[0035] Figure 5a An optical encoder according to an embodiment is shown;

[0036] Figure 5b to Figure 5f Shows Figure 5a A specific example of an optical encoder;

[0037] Figure 6a An optical encoder according to an embodiment is shown;

[0038] Figure 6b and Figure 6c Shows Figure 6a A specific example of an optical encoder;

[0039] Figure 6d and Figure 6e The following are respectively shown as a function of the phase shift applied by each phase shifter according to Figures 6a to 6c A graph of the magnitude and phase of the encoder output;

[0040] Figure 7a and Figure 7b An optical circuit including an encoder is shown, wherein the optical circuit is configured to perform an arithmetic operation on an encoded optical signal;

[0041] Figure 8a and Figure 8b An optical decoder according to an embodiment is shown;

[0042] Figure 9a is a schematic diagram of the optical Fourier transform stage;

[0043] Figure 9b is a schematic diagram of a free-space optical Fourier transform stage having a 2D input array and a 2D output array;

[0044] Figure 9dis a schematic diagram of an integrated optical Fourier transform stage having a 1D input array and a 1D output array;

[0045] Fig.9c It is shown Figure 9b 2D input / output arrays and Figure 9d Close-up diagram of the 1D input / output array of

[0046] Fig.10a is a schematic diagram of an optical device according to an embodiment;

[0047] Fig.10b It shows that you can use Fig.10a Schematic diagram of the mathematical operations performed by the optical device;

[0048] Fig.11 is a schematic diagram of an optical device according to an embodiment;

[0049] Fig.12 It shows that you can use Fig.11 Schematic diagram of the mathematical operations performed by the optical device;

[0050] Fig.13 is a schematic diagram illustrating mathematical operations that may be performed using an optical Fourier transform stage according to an embodiment;

[0051] Fig.14 An example of a system for correcting phase effects in an encoder is shown;

[0052] Fig.15 and Fig.16 A first exemplary embodiment and a second exemplary embodiment are illustrated, respectively, showing the signal flow through components of the controller 1402 of the optical encoder;

[0053] Fig.17 It is used to realize Fig.15 Example circuit of a controller;

[0054] Fig.18 A flow chart illustrating a method that may be implemented by a controller to provide an input signal to a photonic device;

[0055] Fig.19 and Fig. 20 A circuit for processing an optical signal received by a decoder according to an embodiment is shown; and

[0056] Fig.21 and Fig. 22 Shows Fig.19 and Fig. 20 A detailed example of the operation of the differential ADC and binary output decoder is shown in FIG.

[0057] In the drawings, like reference numerals denote like parts. DETAILED DESCRIPTION

[0058] Refer to Figures 1 to Figure 8b , the present disclosure begins by describing an encoder arranged to encode a complex element onto an optical signal, an optical circuit for performing mathematical operations on the complex element, and a decoder arranged to decode the complex element from the optical signal. The term "complex element" when used in the present disclosure may be understood to mean a complex number or a component of a complex number. A component of a complex number may be a real part or an imaginary part of a complex number, or may be based on the real part or imaginary part of a complex number (e.g., a component may be a modulus of the real part or imaginary part of a complex number, or a positive or negative value of the real part or imaginary part of a complex number).

[0059] Then, Figures 9a to 13 Optical devices (e.g., photonic integrated circuits) are described that are capable of performing complex operations including arithmetic, optical Fourier transforms (OFTs), and convolutions, wherein each of these operations is performed using complex elements, and wherein the complete complex number is decoded from any output signal. Such operations provide the basis for numerous computationally intensive applications such as cryptography, artificial intelligence, and scientific simulations. The photonic architecture provided as part of an optical computing system naturally operates on multi-bit information and is suitable not only for silicon photonics (SiPh) platforms, but also for III-V semiconductor material systems or any integration of the two.

[0060] Then, refer to Figures 14 to 22 The following description describes these optical computing systems, methods and devices. This includes electronic circuits that control encoders and help decode complex numbers from signals received at decoders. The elements of these electronic circuits compensate for phase effects that affect optical computing systems of increased complexity, such as the optical computing systems of the present disclosure.

[0061] I-Encoders, Decoders and Optical Circuits

[0062] Using photonics to encode complex numbers

[0063] Complex numbers can be encoded onto light signals emitted from coherent light sources. By using its actual weight and imaginary component Define a complex number using Cartesian coordinates (Equation 1a) or by using its magnitude and phase (hereafter referred to as "argument") Definition Complex numbers are encoded using polar coordinates (Equation 1b).

[0064]

[0065] like Figure 1aAs shown, the Argentum diagram 100 may be defined by a first axis 101 and a second axis 102, the second axis being orthogonal to the first axis 101 such that the angular relationship between the positive arm of the second axis 102 and the positive arm of the first axis 101 is π / 2 radians. The intersection of the first axis 101 and the second axis 102 defines an origin 103 of the Argentum diagram 100. The first axis 101 represents the real dimension and the second axis 102 represents the imaginary dimension. Complex numbers 104 are defined as points on the Argentum diagram.

[0066] It is helpful to define the complex number 104 and its location on the Argentogram 100 using a vector 105 that starts at the origin 103 and ends at the point representing the complex number 104. This vector can be defined by the vector sum of its projections onto the first axis 101 and the second axis 102. The projections define the real components in Cartesian coordinates and imaginary component Alternatively, vector 105 may be defined as having a magnitude (or modulus or absolute value) measured as the length of vector 105 and the argument measured as the angle swept from the first axis 101 to the vector 105

[0067] Real weight and imaginary component Each of these can be simplified to its absolute value Multiply by its polarity (or sign) As shown in equations 2a and 2b respectively:

[0068]

[0069] Figure 1b and Figure 1c Examples are given for Figure 1a The Argent diagrams 100 of the same characteristics are shown in Figure 100, each diagram representing an array of complex numbers 104a, 104b for a system capable of encoding complex numbers 104a, 104b at fixed intervals at a quantization level N for each component. Figure 1b and Figure 1c As shown in the comparison of ( Figure 1b ) provides a complex plane (complex number domain) with an equidistant rectangular grid, while complex numbers are represented in polar coordinates. ( Figure 1c ) provides a less uniform resolution in the complex domain, because as the complex Size As the number of pixels increases, the resolution of the system becomes denser near the origin and sparser in the argument domain. Although not discussed in detail here, another prominent space on which coordinates can be projected is the two-dimensional surface of the Riemann sphere. However, this can also have problems with uniform resolution when fixed spacing is used in the quantization levels. Therefore, although encoding in each of these spaces is possible, in a quantized (or digital) coding system with fixed spacing in the quantization levels N of the components, encoding in Cartesian coordinates has advantages.

[0070] Despite Figure 1a to Figure 1c The complex number domain is shown as a Cartesian coordinate with orthogonal axes, but it is also possible to represent the complex number domain using axes that are arranged at oblique angles so that the angle between them is greater than zero and less than 90 degrees. That is, the phase difference (or argument difference) between the real and imaginary parts is no longer π / 2 radians, but a number greater than 0 radians and less than π radians. A transformation matrix can be used to map complex numbers from one set of axes to another set of axes.

[0071] The inventors have recognized that by manipulating one or a combination of photonic devices based on quantized (or digital) electronic signals, it is possible to encode optical signals modulated by photonic devices using complex numbers (or at least components of complex numbers). The complex numbers (or their components) originate from the digital electronic domain, but are encoded in the optical domain for processing there. For example, by encoding the constituent terms on the right-hand side of equations 1a to 2b onto optical signals, these terms can be represented in the optical domain. A digital electronic signal having a value based on the terms is converted into an analog signal to drive one or a combination of photonic devices so as to modulate an optical input signal to produce an optical signal encoded with the terms. Using a received digital electronic signal encoded with a complex number and then converting the data to an optical signal output by a photonic device (which is usually operated in an analog manner) creates an improved interface between the digital signal domain used in electronic computing and the optical domain used in optical computing. In particular, dividing the digital word defining the complex element into segments and then using these segments alone to control a separate modulator to encode the entire complex element onto an optical stream is a more efficient and controllable means of encoding an optical signal with a complex element. This allows optical computer processors to be more easily, efficiently and effectively integrated with electronic computer processors.

[0072] Photonic circuit components (also referred to herein as photonic devices or modulators) are used to modulate the phase or amplitude of an optical signal to encode complex elements (e.g., complex numbers or components thereof) onto the optical signal, and / or to combine or otherwise process the optical signal to perform mathematical operations, such as addition, multiplication, Fourier transform, and convolution, on the complex numbers or components thereof.

[0073] Figure 2 Various photonic circuit components, their photonic functions, and the mathematical operations encoded (or imparted) onto the optical signals are shown.

[0074] like Figure 2 For example, the addition of complex numbers (or their components) in the optical domain is performed using a Y-branch 211 or a 2×1 multimode interferometer (MMI) 212 or a combination of either or both in parallel.

[0075] The phase shift of π / 2 generated by the π / 2 phase shifter 220 (eg, the real term of the phase shift of π / 2 in different branches of the optical circuit) and imaginary terms Orthogonality is introduced between them) and the optical signal can be encoded onto the optical signal using a current / voltage driven phase shifter 221 utilizing thermal effects, plasma dispersion effects, Franz-Caldesci effects or electro-absorption effects; or encoded onto the optical signal through a delay line 222, or through a combination of the two.

[0076] By simply cascading the photonic elements representing the numbers in series in the branches 231 of the optical circuit, multiplication of complex numbers or their components which have been encoded onto the optical signal can be performed in the optical domain.

[0077] The polarity or sign of the complex number (or its components) can be encoded onto the optical signal by imparting a fixed π phase shift by a phase shifter 240, for example using any one or more of a thermal phase shifter 241, a carrier depletion phase shifter 242, or an electro-absorption phase shifter 243. The phase shifter can also be a phase switch.

[0078] The absolute value or modulus of a complex number (or its components) can be encoded onto an optical signal via an intensity modulator 250, such as a Micro-Ring Resonator (MRR) 251, a Mach-Zehnder Interferometer (MZI) 252 operating in push-pull mode, an Electro-Absorption Modulator (EAM), or a Direct Intensity Modulated Laser (DIML) 253.

[0079] The above listed and Figure 2 The devices shown in can be implemented using silicon photonics or III-V photonics or a combination of both. By using a combination of these devices, some or all of the terms in equations 1a to 2b can be encoded onto optical signals using photonic integrated circuits (also referred to herein as PIC architectures, encoders, or electrical to optical encoders).

[0080] Furthermore, the PIC architecture is made modular in the following ways:

[0081] Using photonics to encode complete complex numbers

[0082] Photonically encode the signed real and imaginary components of a complex number and add them together

[0083] Photonically encode the unsigned real and imaginary components of a complex number and add them together

[0084] Using photonics to encode complex numbers in Cartesian coordinates

[0085] Complex numbers expressed in Cartesian coordinates are encoded in the optical domain by encoding the signed real term and the signed imaginary term of the complex number separately and adding the two together.

[0086] In all figures showing encoding circuits, the optical signal propagation is from left to right.

[0087] Figure 3a is a diagram showing encoding of complex numbers in the optical domain by modulating and combining input optical signals to form an optical output signal A schematic diagram of the process 30 is shown.

[0088] A first optical input signal 331 is received in a first series branch 311 of an optical circuit, and a second optical input signal 332 is simultaneously received in a second series branch 312 of the optical circuit. In a first step S301, a complex The first component The absolute value of The first input signal 331 is encoded to generate a first amplitude modulated signal 361. In the second step S302, the first amplitude modulated signal 361 is encoded using polarity (or sign) to generate a first intermediate signal 362. In the third step S303, the complex The second component The absolute value of The second input signal 332 is encoded to generate a second amplitude modulated signal 363. In a fourth step S304, the second amplitude modulated signal is encoded with polarity or sign to generate a second intermediate signal 364. In a fifth step S305, the second intermediate signal 364 is encoded with a phase offset to generate a phase offset signal 365, which is orthogonal to the first intermediate signal 362. In a sixth step S306, the first intermediate signal 362 and the phase offset signal 365 are added together to form the output signal 333.

[0089] The output signal 333 is a complex number of the form shown in equation 1a The first amplitude modulated signal 361 represents a complex number The real part of The unsigned real component of the complex modulus of The first intermediate signal 362 represents a complex The real part (or component) of [Signed (+ or -)] real number or The second amplitude modulation signal 363 represents a complex The imaginary part The unsigned imaginary component of the modulus The second intermediate signal 364 represents the complex The imaginary part [Signed (+ or -)] real number or The phase shift signal 365 represents the imaginary part Multiply by the uncertain j, where (i.e. j is a complex number whose square is -1).

[0090] In mathematical terms, the absolute values ​​of the real and imaginary terms are multiplied by the polarity of the real and imaginary terms, respectively. The relative arguments of the real and imaginary terms (2n-1)π / 2 are offset by (2n-1)π / 2, where n is an integer. The real and imaginary terms are then added together to form a complex number.

[0091] The first input signal 331 and the second input signal 332 are coherent. This ensures that the output signal 333 can be represented by a complex Code accurately.

[0092] although Figure 3a The first step S301 and the third step S303 are shown to occur before the second step S302 and the fourth step S304 respectively, but the order of these steps can be reversed so that the sign is encoded before the absolute value in one or both of the first series branch 311 and the second series branch 312.

[0093] The third step S303 and the fourth step S304 are optional because the plural The real part of and the imaginary part can be positive. That is, in the real part of the code and the imaginary part of the code When the value is positive, the first amplitude modulation signal 361 and the second amplitude modulation signal 363 do not need to be further modulated in the second step S302 and the fourth step S304, so these steps become redundant. Figure 3b As described, one suitable way of achieving such an optional modulation of the sign of the signal is by using a phase switch.

[0094] Although the fifth step S305 is shown as occurring in the second series branch 312, the step may alternatively occur in the first series branch 311, or may additionally occur partly in the first series branch 311 and partly in the second series branch 312. The purpose of the fifth step S305 is to provide orthogonality between the signals emerging from the first series branch 311 and the second series branch 312 (e.g. Figure 1a in the complex domain in ). That is, the fifth step S305 involves imparting a phase difference of (2n-1)π / 2 between the signals in the first series branch 311 and the second series branch 312 before they are added together. This may occur in the second series branch 312 by adding a phase offset of, for example, (2n-1)π / 2 to the second intermediate signal, or may occur in the first series branch 311 by adding a phase offset of, for example, -(2n-1)π / 2 to the first intermediate signal. Alternatively, the fifth step S305 may occur by adding a phase offset of, for example, -(2n-1)π / 4 to the first intermediate signal and a phase offset of, for example, (2n-1)π / 4 to the second intermediate signal, such that the total phase offset between the first series branch 311 and the second series branch 312 is (2n-1)π / 2.

[0095] Furthermore, although the fifth step S305 is shown as occurring between the fourth step S304 and the sixth step S306, the fifth step S305 may be performed at any stage prior to the sixth step S306, for example, the fifth step S305 may be performed in the first series branch 311 prior to the first step S301, or in the second series branch 312 between the second step S302 and the fourth step S304. As the reader will appreciate, the terms first, second, etc., when used with respect to steps, are convenient labeling conventions, but do not necessarily limit when the steps may be performed relative to each other.

[0096] Furthermore, although orthogonality (provided by a phase shift of (2n-1)π / 2) radians is provided for encoding complex numbers A convenient convention or mathematical construction of , but it is possible to encode complex numbers without a phase shift of (2n-1)π / 2 radians The condition is that there is an angle between the axes of the complex field that is greater than zero and less than π (as explained earlier with reference to the skewed version of the Argentum diagram, where the angle between the real and imaginary axes is greater than zero but less than π radians). Detecting complex numbers encoded in this way This is more difficult than when there is an orthogonal relationship between the real and imaginary axes. This is because a compensation, usually involving the application of a scaling factor between the two axes, must be employed to account for the new angular relationship between the axes in the chosen (non-regular) complex plane.

[0097] Figure 3aThe method can be used Figure 3b The encoder is implemented by the exemplary encoder 300 shown in FIG. The encoder includes a first series branch 321 and a second series branch 322. The first series branch 321 includes a first intensity modulator 351 and a first phase switch 341. The second series branch 322 includes a second intensity modulator 352 and a second phase switch 342. The encoder also includes a combiner 310, which is arranged to combine the first output from the first series branch 321. and the second output from the second series branch 322 To produce plural The second series branch 322 may further include a phase shifter 320, which is arranged to encode the second output with a phase shift to generate a phase shift signal The first output and the second output are made orthogonal.

[0098] exist Figure 3b In the encoder 300, the first step S301 and the third step S303 (from Figure 3a ) are respectively performed by the first intensity modulator 351 and the second intensity modulator 352. The second step S302 and the fourth step S304 are respectively performed by the first phase switch 341 and the second phase switch 342. The fifth step S305 is performed by the phase shifter 320, and the sixth step S306 is performed by the combiner 310. The processed and generated signals are as shown in FIG. Figure 3a As will be understood by a skilled reader, the first intensity modulator 351 and the second intensity modulator 352, the first phase switch 341 and the second phase switch 342, and the phase shifter 320 are arranged in various positions in the first series branch 311 and the second series branch 312 to achieve the purpose of the present invention. Figure 3a The various methods described, Figure 3a All described variations of the method are possible. For example, the order of the first intensity modulator 351 and the first phase switch 341 or the second intensity modulator 352 and the second phase switch 342 can be reversed, and / or the phase shifter 320 can be incorporated into any of the first series branch 321 and the second series branch 322 as a separate component or as a component integrated into any one or more of the first intensity modulator 351, the second intensity modulator 352, the first phase switch 341 or the second phase switch 342. Like any of the photonic components for encoding optical signals described herein, the first intensity modulator 351, the second intensity modulator 352, the first phase switch 341 or the second phase switch 342 can be more generally described as a modulator.

[0099] Figure 3bThe encoder 300 may be passive in the sense that the first intensity modulator and the second intensity modulator do not receive any control signal but are set to apply a fixed intensity modulation to the first input signal 331 and the second input signal 332, respectively. Likewise, the first phase switch 341 and the second phase switch 342 may be passive in that they do not receive any control signal and apply a fixed phase offset (or no phase offset) to the first input signal 331 and the second input signal 332. Similarly, the π / 2 phase shifter 320 is passive and neither receives any control signal nor applies any phase offset to the first input signal 331 and / or the second input signal 332.

[0100] The same complex number must always be encoded by the encoder 300 In this case, a passive encoder can be useful. However, as will be referenced Figure 4a As described, it is useful to provide an active encoder that can encode any given complex element onto an optical signal based on a received digital electronic signal that carries information based on the value of the complex element. The active encoder allows the first intensity modulator 351 and / or the second intensity modulator 352 and the first phase switch 341 and the second phase switch 342 to be addressable to provide different amplitude and phase modulations so as to encode different absolute values ​​and signs onto the first input signal 331 and the second input signal 332, thereby encoding the complex element. The real weight and imaginary component Encoded to have different values.

[0101] Figure 4a As part of a system 400 including a controller 460, Figure 3b The controller 460 is arranged to receive the digital electronic signal and control the components 351, 341, 352, 342 of the encoder based on the value of the digital electronic signal 461, 462, 463, 464, thereby controlling the complex number encoded on the optical signal output 430 from the encoder. The value of .

[0102] The digital word contains the sign and magnitude of the real or imaginary component of the complex number, or contains the sign and magnitude of both the real and imaginary components, thereby forming a complete complex number. The digital signal received in all encoders described herein is a segment of the digital word. The controller generates PAMx, NRZ, DC, or any combination of these signals to control the components 351, 341, 352, 342 of the encoder. The controller can do this by creating a PAMx, NRZ, or DC analog electronic signal based on the received digital data (i.e., the segment of the digital word) and providing the analog electronic signal to the modulator. PAMx, NRZ, and DC signals can be described as quantized analog signals.

[0103] Thus, the controller 460 is configured to: provide a first electronic signal 461 to the first intensity modulator 351 via at least one first line 401 based on the value of the first digital electronic signal; provide a second electronic signal 462 to the first phase switch 341 via at least one second line 402 based on the value of the second digital electronic signal; provide a third electronic signal 463 to the second intensity modulator 352 via at least one third line 403 based on the value of the third digital electronic signal; and provide a fourth electronic signal 464 to the second phase switch 342 via at least one fourth line 404 based on the value of the fourth digital electronic signal. Optionally, the controller 460 may provide a DC electronic signal 465 to the phase shifter 320 via at least one fifth line 405. Alternatively, instead of providing a signal to the phase shifter 320, passive components (e.g., a (phase) delay line 222) are used.

[0104] The first electronic signal 461 and the third electronic signal 463 are PAMx (Pulse Amplitude Modulation) signals, where x is greater than 2 (i.e., 4-level PAM (PAM4) or above). That is, the first electronic signal 461 and the third electronic signal 463 are multi-bit signals. The PAMx signal is a unipolar signal. The higher the value of x, the greater the resolution of the first intensity modulator 351 and the second intensity modulator 352, and the complex The first component and the second component The higher the accuracy of the encoding of the absolute value.

[0105] The second electronic signal 462 and the fourth electronic signal 464 are NRZ (Non-Return-to-Zero) signals (PAMx signals, where x is equal to 2). That is, the second electronic signal 462 and the fourth electronic signal 464 are single or binary signals. This is because the first phase switch 341 and the second phase switch 342 only need to switch between two possible states. Each of the first phase switch 341 and the second phase switch 342 is configured to: add a phase of 2nπ when the sign of the corresponding encoded component is positive; and add a phase of (2n-1)π when the sign of the corresponding encoded component is negative; where n is an integer. That is, each of the first phase switch 341 and the second phase switch 342 adds a phase of zero or an even number of π when encoding a positive value, and adds a phase of an odd number of π when encoding a positive value. Although not ideal, as long as the difference between the phase used to encode a positive value and the phase used to encode a negative value is π, other added phase values ​​can be used to encode positive and negative signals. Such a system will shift the total output in phase. If this phase shift is undesirable, a phase compensator can be added elsewhere in the circuit to ensure that the signal encoded with positive values ​​is in phase with the input signal.

[0106] The format of the signals that control photonic devices can be summarized as follows:

[0107] o Based on a multi-bit signal derived from the received digital data (e.g., an analog PAMx signal quantized to have x levels, where x=2 N , and N is the bit precision of the system) to modulate the absolute value (both real and imaginary terms).

[0108] o The polarity (both real and imaginary terms) is modulated based on a binary signal derived from the received digital data (eg, an analog NRZ signal quantized to have only two levels).

[0109] o The quadrature angle bias between the real and imaginary terms is controlled using a variable DC current / voltage line that does not necessarily (although in some cases can) depend on the received digital data.

[0110] Figure 3a The method can be used Figure 4b to Figure 4g Any one of the encoders 411, 412, 413, 414, 415, 416 shown is performed, which encoders are Figure 3b A more specific example of an encoder 300 is shown. Figure 4b to Figure 4g Each of the encoders 411, 412, 413, 414, 415, 416 is configured to perform reference Figure 3a Method 30 described. Figure 4b to Figure 4gEach of the encoders 411, 412, 413, 414, 415, 416 can be connected to the controller 460 so as to be consistent with the reference Figure 4a In the same manner as described, electronic signals are provided to the optical (photonic) components 320 , 341 , 342 , 351 , 352 based on the received digital electronic signals 461 , 462 , 463 , 464 , 465 .

[0111] Figure 4b The encoder 411 shows the use of a microring resonator (MRR) 251 as an intensity modulator 451, 452 to encode the real component of a complex number. and imaginary component The absolute value or modulus of the two. The carrier depletion type phase shifter 242 is used as phase switches 441, 442 to encode the real component and imaginary component The phase separation between the first series branch 311 and the second series branch 312 is provided by the phase shifter 221, which uses the thermal effect and acts as a phase switch 420 to shift the phase of the imaginary component by π / 2; while the Y branch 211 or the 2×1 MMI 212 (not shown) acts as a combiner 410 to combine the real component and imaginary component Add.

[0112] Similarly, Figure 4c The encoder 412 shows the use of MRR 251 as intensity modulators 451, 452 to encode the real component of the complex number. and imaginary component The absolute value or modulus of the two. The thermal phase shifter 241 is used as a phase switch 443, 444 to encode the real component and imaginary component In this case, one of the phase switches 444 also performs the function of shifting the phase of the imaginary component by π / 2, so the controller 460 sends a DC signal covered with an NRZ signal to control the phase switch. The Y branch 211 or the 2×1 MMI 212 acts as a combiner 410 to shift the real component and imaginary component Add.

[0113] Figure 4d The encoder 413 shows the use of the MZI 252 as an intensity modulator 453, 454 to encode the real component and imaginary component The absolute value or modulus of the two. The carrier depletion type phase shifter 242 is used as phase switches 441, 442 to encode the real component and imaginary component The phase separation between the first series branch 311 and the second series branch 312 is provided by the phase shifter 221, which uses the thermal effect and acts as a phase switch 420 to shift the phase of the imaginary component by π / 2; while the Y branch 211 or the 2×1 MMI 212 (not shown) acts as a combiner 410 to combine the real component and imaginary component Add.

[0114] Similarly, Figure 4e The encoder 414 shows the use of the MZI 252 as an intensity modulator 453, 454 to encode the real component and imaginary component The absolute value or modulus of the two. The thermal phase shifter 241 is used as a phase switch 443, 444 to encode the real component and imaginary component One of the phase switches 444 is also used to shift the phase of the imaginary component by π / 2 by applying a DC+NRZ signal, as shown in FIG. Figure 4c The Y branch 211 or the 2×1 MMI 212 (not shown) acts as a combiner 410 to combine the real component and imaginary component Add.

[0115] Figure 4f The encoder 415 shows the use of DIML 253 as intensity modulators 455, 456 to encode the real component of a complex number. and imaginary component The absolute value or modulus of both. The electro-absorption phase shifter 243 is used as phase switches 445, 446 to encode the real component and imaginary component The delay line 222 acts as a phase shifter 421 to shift the phase of the imaginary component by π / 2. The Y branch 211 or the 2×1 MMI 212 (not shown) acts as a combiner 410 to combine the real component and imaginary component Add.

[0116] Similarly, Figure 4g The encoder 416 shows the use of DIML 253 as intensity modulators 455, 456 to encode the real component of a complex number. and imaginary component The absolute value or modulus of both. The electro-absorption phase shifter 243 is used as phase switches 445, 447 to encode the real component and imaginary component One of the phase shifters 447 is also used to shift the phase of the imaginary component by π / 2 by applying a DC+NRZ signal, as shown in FIG. Figure 4cThe Y branch 211 or the 2×1 MMI 212 (not shown) acts as a combiner 410 to combine the real component and imaginary component Add.

[0117] for Figure 4f and Figure 4g Both, DIMLs are phase locked to another master laser (not shown) to lock the phase of the DIML to the phase of the master laser. In this way, the phase of the light in the two arms encoding the real and imaginary terms is the same.

[0118] Encoding signed real or imaginary components of complex numbers using photonics

[0119] It is useful to encode only a portion (i.e., a component) of a complex number. For example, the real and imaginary components of a complex number can be encoded independently. This can be useful for performing mathematical operations on complex numbers, since the operations can be performed independently on the components of the complex number.

[0120] Figure 5a An encoder 500 is shown, which is similar in structure, function and operation to Figure 4a The first series branches 311 of the systems shown are identical. Figure 5a The encoder 500 is configured to convert the complex The real weight or imaginary component The absolute value and sign of are encoded onto the first input signal 331 . Figure 5a The encoder 500 shown includes the Figure 4a The first intensity modulator 351 and the first phase switch 341 are arranged in series. The encoder 500 also includes a controller 460, which is arranged to receive the first digital electronic signal and the second digital electronic signal, and apply the first electronic signal 461 and the second electronic signal 462 to the first intensity modulator 351 and the first phase switch 341, respectively, as shown in FIG. Figure 4a described.

[0121] Figure 5b to Figure 5f The encoders 511, 512, 513, 514, 515 shown are Figure 5a An example of an encoder 500 . Figure 5b to Figure 5f Each of the encoders 511, 512, 513, 514, 515 is configured to perform as described in reference Figure 3a The first step S301 and the second step S302. Figure 5b to Figure 5f Each of the encoders 511, 512, 513, 514, 515 can be connected to the controller 460 so as to be consistent with the reference Figure 4a and Figure 5a The same approach described provides electronic signals to optical (photonic) components.

[0122] Figure 5b The encoder 511 is shown, including an intensity modulator 451, specifically an MRR 251, which is configured to modulate the real component of the complex number or imaginary component The absolute value or modulus is encoded; the MRR 251 is connected in series with the carrier depletion type phase shifter 242 used as the phase switch 441 to encode the real component or imaginary component The polarity (or sign) of

[0123] Figure 5c The encoder 512 is shown, including an intensity modulator 451, specifically an MRR 251, which is configured to modulate the real component of the complex number or imaginary component The absolute value or modulus is encoded; the MRR 251 is connected in series with the thermal phase shifter 241 used as the phase switch 443 to encode the real component or imaginary component The polarity (or sign) of

[0124] Figure 5d The encoder 513 is shown, including an intensity modulator 453, specifically an MZI 252, which is configured to modulate the real component of the complex number or imaginary component The absolute value or modulus is encoded; the MZI 252 is connected in series with the carrier depletion type phase shifter 242 used as the phase switch 441 to encode the real component or imaginary component The polarity (or sign) of

[0125] Figure 5e The encoder 514 is shown, including an intensity modulator 453, specifically an MZI 252, which is configured to modulate the real component of the complex number or imaginary component The absolute value or modulus is encoded; the MZI 252 is connected in series with the thermal phase shifter 241 used as the phase switch 443 to encode the real component or imaginary component The polarity (or sign) of

[0126] Figure 5f The encoder 515 is shown, including an intensity modulator 455, specifically a DIML 253, to modulate the real component of the complex number. or imaginary component DIML 253 is connected in series with electro-absorption phase shifter 243 used as phase switch 445 to encode the real component or imaginary component The polarity (or sign) of

[0127] Encoding the unsigned real or imaginary components of complex numbers using photonics

[0128] although Figure 5a to Figure 5f shows the real components of complex numbers arranged to include their polarity or sign or imaginary component The encoder for encoding can also be used to encode the unsigned real component by using only the absolute value of the encoded component using the intensity modulator 250 (without the phase shifter and / or phase switch 220, 240). or imaginary component The intensity modulator 250 is suitable for encoding. Figure 5b to Figure 5f , and includes an MRR 251, an MZI 252 operating in a push-pull mode, and a DIML 253 including a surface emitting DIML, such as a vertical cavity surface emitting laser, a microdisk laser, a distributed feedback laser, or a laser with a multi-segment sampled grating distributed Bragg reflector.

[0129] Using photonics to encode complex numbers in polar coordinates

[0130] By modulating the magnitude and phase of the input signal while exploiting the physical properties of the encoding circuit, complex numbers represented in polar coordinates can be encoded in the optical domain. Figure 6a is shown to be configured to encode complex numbers in this way Schematic diagram of encoder 600. Encoder 600 includes a controller 660, which is arranged to provide electronic signals 661, 662 to the optical (photonic) components of encoder 600 to convert complex numbers in polar coordinate form Encoded onto the optical input signal. The electronic signal is based on the carrier representing the complex number A digital signal of component data.

[0131] The optical part of the encoder 600 is in the form of an MZI, wherein a first phase shifter 641 is included in its first branch 611 and a second phase shifter 642 is included in its second branch 612. The input channel 630 is operably connected to a splitter 605, which in turn is operably connected to the inputs of the first branch 631 and the second branch 632 of the MZI 252. The outputs of the first branch 633 and the second branch 634 are operably connected to a combiner 610, and the combiner 610 is operably connected to an output line 635. The controller 660 is connected to the first phase shifter 641 via at least one first line 601 and to the second phase shifter 642 via at least one second line 602.

[0132] In operation, an optical input signal is provided through an input channel 630, which is split by a splitter 605 into a first branch 631 and a second branch 632 of the MZI 252. A controller 660 provides at least one first electronic signal 661 to a first phase shifter 641 via at least one first line 601; and provides at least one second electronic signal 662 to a second phase shifter 642 via at least one second line 602. The at least one first electronic signal and the second electronic signal are based on at least one value of a first digital electronic signal and a second digital electronic signal, respectively, received by the controller. The digital data received by the controller is calibrated (or obtained from a digital lookup table) against a digital lookup table. The digital lookup table contains the data words required to accurately encode a complex number, more specifically, phase and magnitude encoding in polar coordinates. In this way, the controller accurately provides the necessary first and second electronic signals to the phase shifters to accurately represent a given complex number. The first phase shifter 641 and the second phase shifter 642 introduce independent phase shifts into the first branch 611 and the second branch 612 of the MZI 252, for example by utilizing plasma dispersion effects, Franz-Caldisi effects, electro-absorption effects, or thermal effects, respectively. The outputs from the first branch 633 and the second branch 634 are then combined by the combiner 610 (Y branch 211 or 2×1 MMI 212) to provide a complex number represented in polar coordinate form (i.e., in the form of Equation 1b) Coded optical signal.

[0133] In more detail, by controlling the phase shift at the first phase shifter 641 and the second phase shifter 642 relative to the phase at the splitter 605, To control the amplitude and phase of the photon signal at the combiner 610. Figure 6d and Figure 6e The independent relative phase shifts at the first phase shifter 641 and the second phase shifter 642 are shown as Graphs of normalized intensity (magnitude) variation and phase at the combiner 610 relative to the input optical signal as a function of . The information represented by these graphs may alternatively take the form of a lookup table. The electronic signals 661 and 662 that drive the first phase shifter 641 and the second phase shifter 642 are provided so that the phases in the various branches of the MZI are modulated so that the intensity and phase of the photon signal at the combiner 610 form an accurate photon representation of the corresponding mathematical equivalent of the complex number encoded onto the digital electronic signal received at the controller (and the resulting electronic signal provided to the phase shifter). The lookup table converts the phase offset at the first phase shifter 641 and the second phase shifter 642 as a function of the voltage or current of the photonic device This is taken into account, and the controller provides an electronic signal sufficient to provide the desired phase shift at the first phase shifter 641 and the second phase shifter 642.

[0134] More specifically, the first lookup table (or function or graph) contains master data of phase and magnitude (of the output signal at combiner 610) as a function of the phase disturbance in the two arms of the MZI. Figure 6d and Figure 6e The raw digital data (complex numbers - magnitude and argument) are checked against equivalent phase and magnitude graphs of the optical input signal to determine the required phase perturbations in MZI arms 1 and 2, respectively. The exact digital data used by the controller for analog conversion is then retrieved using a second lookup table (or function or graph) containing the voltage and / or current data necessary to drive the phase shifters to apply the necessary phase shift, and then electronic signals are sent to the phase shifters to encode the complex numbers onto the optical input signal.

[0135] exist Figure 6a In the encoder 600, the first electronic signal 661 and the second electronic signal 662 are both PAMx signals, where x is greater than 2 (in other words, the first electronic signal 661 and the second electronic signal 662 are multi-bit signals).

[0136] Figure 6b and Figure 6c Shown is a reference Figure 6a The example of encoder 600 described above, wherein both splitter 605 and combiner 610 are Y branches 211. Figure 6b In the embodiment, the phase shifters 643 and 644 are both carrier depletion type phase shifters 242, and in Figure 6c In FIG. 2 , phase shifters 645 and 646 are both thermal phase shifters 241 .

[0137] In reference Figure 6a In the alternative arrangement described, complex numbers represented in polar coordinates can be encoded in the optical domain by separately modulating the magnitude and phase of the input optical signal in a single series branch. This effectively multiplies the magnitude and phase values. This approach can be used Figure 5a to Figure 5f The system is implemented as described above, but a phase shifter is used instead of a phase switch, wherein the second electronic signal 462 is (or is based on) a PAMx signal (i.e., a multi-bit signal) with x greater than 2, so that a range of amplitude values ​​can be encoded onto the optical input signal. That is, the photonic device is based on a multi-bit signal (e.g., PAMx, where x=2 N , and N is the bit accuracy of the system) to modulate.

[0138] refer to Figure 4a to Figure 4g , Figure 5a to Figure 5f and Figures 6a to 6cThe controller described may include a plurality of sub-controllers such that each modulator receives a signal from a separate sub-controller. Each sub-controller is arranged to receive a digital electronic signal and control a modulator based on a value of the digital electronic signal such that the modulator applies a corresponding modulation element operable to encode a complex element onto an optical signal. Fig.15 , Fig.16 and Fig.17 An example of such a sub-controller is described.

[0139] Encoding in these ways allows for improved (e.g., more efficient, more streamlined) digital data input and fast / efficient encoding of input streams / optical signals using complex elements. Photonic integrated circuits employing encoders as described above are more suitable for interfacing with external electronic components (e.g., computer processors or memory).

[0140] Perform mathematical operations on complex numbers encoded onto optical signals

[0141] A method of performing mathematical operations (eg, arithmetic) on complex numbers using photonics is provided.

[0142] Multiplication of complex numbers

[0143] The multiplication of complex elements (complex numbers or components of complex numbers) can be performed by serially cascading encoders, which represent the various multiplicands successively. For example, Figure 7a A first encoder 711 and a second encoder 712 are shown connected in series, such that the optical output signal from the first encoder 711 forms the input to the second encoder 712. The first encoder 711 and the second encoder 712 may be any encoder described in the present disclosure. Figure 7a In the example, the first encoder 711 and the second encoder 712 respectively take reference Figure 4b The form of the encoder described. Figure 7a In the example, the first encoder 711 is configured to convert the first complex number The second encoder 712 is configured to encode the second complex number The output of the first encoder 711 is connected to the input of the second encoder 712 via the connecting branch 730, so that the optical signal input to the second encoder 712 is encoded with the first complex number. Then, using the third complex number The optical output signal 731 from the second encoder 712 is encoded. Is the first plural and the second plural Multiples of . Use Figure 7aBased on the principle of , it is also possible to multiply a first complex element by a second complex element by feeding an optical signal that has been encoded with the first complex element (by any means, such as via the output of an OFT stage) into the input of an encoder configured to encode a second complex number.

[0144] Addition of complex numbers

[0145] Complex element addition can be performed by placing encoders representing the various multiplicands in parallel. For example, Figure 7b A first encoder 713 and a second encoder 714 connected in parallel are shown. An optical input signal is input to a Y branch that acts as a splitter 710 to provide an optical input to the first encoder 713 and to provide the same optical input to the second encoder 714. The first encoder 713 and the second encoder 714 may be any encoder described in the present disclosure. Figure 7b In the example, the first encoder 713 and the second encoder 714 respectively take reference Figure 4b The form of the encoder described. Figure 7b In the example, the first encoder 713 is configured to convert the first complex number The second encoder 714 is configured to encode the second complex number The Y branch 211 acts as a combiner 715, which combines the output of the first encoder 713 with the output of the second encoder 714 so that the third complex Encode the optical output signal 732 output from the combiner 715, the third complex Is the first plural and the second plural Use Figure 7b Based on the principle of FIG. 1 , the first complex element and the second complex element can also be added by feeding an optical signal that has been encoded with the first complex element (by any means) and an optical signal that has been encoded with the second complex element (by any means) into a combiner.

[0146] Using photonics to detect complex numbers

[0147] A method of detecting a complex number or a component of a complex number from a characteristic of an optical signal, the optical signal having previously been encoded with a complex number (or a component of a complex number) by any of the methods and apparatus described herein, is provided. This may include detecting a second complex number or a component thereof from a characteristic of an optical signal, the optical signal having previously been encoded with a first complex number (or a component thereof) and modified to perform a mathematical (e.g., arithmetic, OFT, or convolution) operation on the first complex number to produce a second complex number.

[0148] Decodes the absolute value or modulus of a complex number encoded onto an optical signal

[0149] An intensity detector such as a photodiode can be used to naturally detect the absolute value or modulus of a complex number encoded onto the optical signal by detecting the amplitude of the optical signal.

[0150] Decode the real or imaginary component of a complex number

[0151] Homodyne detection using a balanced detector can be used to naturally decode real or imaginary numbers (ie, the real or imaginary component of a complex number, including its modulus and sign) that have been encoded onto an optical signal. Figure 8a A schematic diagram of a balanced detector 800 configured to decode in this manner is shown in . The balanced detector 800 comprises: a first input branch comprising a reference line 801 having a reference input; and a second input branch comprising a signal line 802 having a signal input coupled to an input of an interferometer 810, the interferometer 810 being specifically a 2×2 MMI. The interferometer has two output branches 803, each of which has a photodetector 804 included therein, specifically, two balanced photodetectors are connected to receive the output 803 from the interferometer 810. The output 805 from the balanced photodetector 804 is the difference in photocurrents from the individual constituent photodetectors forming the balanced photodetector. The reference line comprises a (e.g. variable) phase shifter 806. The reference line is arranged to receive a signal based on an input optical signal to the encoder as a source.

[0152] The full complex number can be decoded from the optical signal by performing two detections (or measurements) using balanced detectors - one detector decoding the real part of the complex number and the other detector decoding the imaginary part; by appropriately adjusting the phase shifter 806 (e.g., a heater or delay line). The real part of the complex number is decoded from the optical signal by selecting the reference input to the balanced detector to be in phase with the light used to encode the real part. The imaginary part of the complex number is decoded if the phase of the reference input to the balanced detector is selected to be in phase with the light used to encode the imaginary part. The full complex number in Cartesian coordinates (Cartesian form) is recovered by adding the decoded real and imaginary parts.

[0153] For polar coordinates, the magnitude and argument are calculated numerically from the real and imaginary terms using Equation 3a and Equation 3b, respectively.

[0154]

[0155] Decoding complex numbers encoded onto optical signals

[0156] Two balanced detectors and a π / 2 (90 degree) optical hybrid can be used to naturally detect complex numbers encoded onto the optical signal. Figure 8b This arrangement is shown in Figure 8bIn the decoder circuit 850, a first balanced detector 851 configured to decode the real part of a complex number and a second balanced detector 852 configured to decode the imaginary part of a complex number are included. The first balanced detector 851 and the second balanced detector 852 are respectively similar in structure, function and operation to the reference Figure 8a The balanced detector 800 described is substantially the same.

[0157] Figure 8b A reference branch 860 is shown split into a first input branch 861 and a second input branch 862, and a signal branch 865 is split into a third input branch 863 and a fourth input branch 864. The first input branch 861 and the third input branch 863 serve as a reference input 871 and a signal input 872, respectively, to the first balanced detector 851. The second branch 862 and the fourth branch 864 serve as a reference input 873 and a signal input 874, respectively, to the second balanced detector 852. The first input branch 861 includes a first phase shifter 891, and the second input branch 862 includes a second phase shifter 892.

[0158] In operation, a coded optical signal (coded with a complete complex number) is input to the signal branch 865, while a reference input signal is simultaneously input to the reference branch 860. When the complex number is encoded onto the optical signal, the reference input signals 861 and 862 are selected to be in phase with the light used to encode the real and imaginary parts of the complex number, respectively. The first phase shifter 891 and the second phase shifter 892 allow the phase of the reference input signals 861 and 862 to be adjusted in the first input branch 861 and the second input branch 862, respectively. The first phase shifter 891 is configured to make the signal in the first input branch 861 in phase with the light encoded with the real part of the complex number. For example, if the reference Figure 4a The encoder 300 described is used to encode a complex number, then Figure 8b The first reference in the first input branch 861 of the decoder circuit 850 will be selected to be Figure 4a The signal in the first series branch 311 of the encoder 300 is the same, and the second phase shifter 892 will be configured to make the reference in the second input branch 862 and the signal in the second series branch 312 in phase after providing a phase shift for orthogonality (ie step S305).

[0159] In other words, the 90 degree optical hybrid splits the reference input signal into two. The imaginary part of the encoded complex number is recovered from the encoded optical signal using the second balanced detector 852, wherein the phase of the reference input signal is shifted by π / 2 to be in phase with the light used to encode the imaginary part. The real part of the encoded complex number is recovered from the encoded optical signal using the first balanced detector 851, wherein the phase of the reference input signal remains unchanged.

[0160] refer to Fig.19 , Fig. 20 , Fig.21 and Fig. 22 Description Connect to Figure 8a and Figure 8b Detail of the electronic decoder circuit of the balanced detector shown. This electronic decoder circuit converts the optical signal received at the photodetector into a digital electronic signal carrying the complex element encoded onto the optical signal.

[0161] Once the real and imaginary parts of the complex number have been decoded, the full complex number is recovered by adding the decoded real and imaginary parts.

[0162] More generally, a decoder is provided, which is arranged to generate a first difference signal based on an output stream of an optical Fourier transform stage and a first reference stream, and to generate a second difference signal based on the output stream and the second reference stream. The output stream is encoded with a complete complex number (e.g. the second complex element mentioned above). The decoder is also arranged to detect at least one first characteristic of the first difference signal, detect at least one second characteristic of the second difference signal, output a first digital electronic signal encoded with a first component of the second complex element based on the at least one first characteristic, and output a second digital electronic signal encoded with a second component of the complete complex number based on the at least one second characteristic. The at least one characteristic may be phase and / or amplitude.

[0163] The decoder includes at least one balanced detector, such as a first balanced detector and a second balanced detector. The first balanced detector is configured to receive an output stream and a first reference stream, and the second balanced detector is configured to receive an output stream and a second reference stream. The phase difference between the first reference stream and the second reference stream is nπ / 2, where n is an odd number.

[0164] The first digital signal is a first segment of a digital word, the first segment represents a real part of a complete complex number, and the second digital signal is a second segment of a digital word, the second segment represents an imaginary part of the complete complex number, wherein the digital word represents the complete complex number.

[0165] Decoding in this manner provides improved digital data output and fast / efficient decoding of the output stream. Photonic integrated circuits incorporating such decoders are better suited for interfacing with external electronic components such as computer processors or memory.

[0166] II-Optical Devices (Photonic Integrated Circuits)

[0167] Basic optical Fourier transform stage

[0168] Figures 9a to 9d Characteristics of the optical Fourier transform stage are shown.

[0169] Figure 9aA schematic diagram of a 2f stage 900 is shown. The 2f stage includes a transparent free-space optical block (hereinafter "optical block") 901 housing a Fourier lens 902. The Fourier lens is positioned at a focal length f from each of an input end 903 and an output end 904 of the optical block 901. Light entering the input end 903 undergoes an optical Fourier transform when passing through the Fourier lens 902. Therefore, the light at the output end 904 of the optical block is the Fourier transform of the light entering the input end 903.

[0170] Figure 9b Shows Figure 9a Schematic diagram of a 2f stage 900 of FIG. 1 , which includes an input waveguide array through which a light stream (i.e., an optical signal) travels and enters an optical block 901 upon exiting the input waveguide. The light is coupled into the optical block by optical fiber; by using a grating coupler; or any other method of coupling light out of the waveguide. The output waveguide collects the light output of the 2f stage at the output plane of the Fourier lens. In this case, the optical block 901 has prismatic ends at the input and output ends, so that light initially enters the transparent block orthogonal to the optical axis of the Fourier lens, and the light path is bent 90 degrees by internal reflection from the surface of the prismatic end to travel through the Fourier lens 902. The output end of the optical block is formed in the same manner so that the light passing through the Fourier lens 902 is bent at 90 degrees toward the entrance aperture of the output waveguide. The output light stream is coupled into the output waveguide.

[0171] like Fig.9c As shown, the input port 905 and the output port 906 (i.e., the exit aperture of the input waveguide and the entrance aperture of the output waveguide, respectively) can be arranged as a 2D array or a 1D array. The term "input port" refers to the terminal of the waveguide, which is arranged at the beginning of the 2f level so that the input light flow leaving the waveguide enters the 2f level. The term "output port" refers to the terminal of the waveguide, which is arranged at the end of the 2f level so that the light leaving the 2f level enters the waveguide as the output light flow.

[0172] for Figure 9d For an integrated OFT device, beam quality is irrelevant since it is a guided mode device. Figure 9b At the 2f level, the optical block may have corrective optics such as a microlens array for each input or output port to ensure the beam quality so that it can be efficiently coupled back into the receiving waveguide.

[0173] An example of a 2f-level arrangement using a 1-dimensional waveguide array is provided in C. Dragone, 'Efficient N*N star couplers using Fourier optics', J. Light. Technol., Vol. 7, No. 3, pp. 479–489, March 1989, doi: 10.1109 / 50.16884. Figure 9d An OFTC type 2f stage with a 1D array of input ports and a 1D array of output ports is shown. In this device, the input port 905 and the output port 906 are located along the circumference of two confocal circles, the radius of which depends on the number of input and output waveguides.

[0174] Optical Fourier transform stage including encoder and decoder

[0175] In general, an optical device according to an embodiment comprises: a plurality of encoders, each encoder being arranged to encode a first complex element onto an input optical stream; and a plurality of input ports, the plurality of input ports being arranged into a first array. Each input port is arranged to be provided with a corresponding one of the input streams, thereby forming an input function that can be defined based on the value of the first complex element and the position of the corresponding input port in the first array. The input port is arranged to provide an optical input to an optical Fourier transform stage, which is arranged to perform at least one optical Fourier transform or convolution of the input function. The optical device also comprises: a plurality of output ports, the plurality of output ports being arranged into a second array, each output port being arranged to receive a portion of the output of the optical Fourier transform stage, thereby forming an output stream. The optical device also comprises a plurality of decoders, each decoder being arranged to decode a second complex element from each of the output streams based on at least one characteristic of the corresponding output stream.

[0176] Fig.10a is a schematic diagram of a more specific example of such an optical device. Fig.10a The optical device 1000 is built around an optical Fourier transform stage 1000, which includes a 2-focal length (2f stage) or a four-focal length (4f stage) Fourier optical device arrangement, the 4f stage arrangement including a first 2f stage and a second 2f stage. Each 2f stage can take Figure 9b (2D array of input ports and output ports) or Figure 9d (OFTC with a 1D array of input and output ports). The optical device may be described as a photonic circuit (or photonic integrated circuit PIC) and may be included as part of a hybrid computer chip comprising both electronic and optical components.

[0177] In general, the optical device includes a light source arranged to provide coherent light and a splitter arranged to split the coherent light into a plurality of input streams. In an embodiment, the light source is a laser source, such as a solid-state semiconductor laser. However, embodiments are not limited to laser sources, and other coherent light sources are also contemplated. The optical device is wavelength independent, but the use of monochromatic light for each Fourier transform ensures the fidelity of the optical Fourier transform. If a filtering approach is employed for each Fourier transform, a broadband source may be used.

[0178] exist Fig.10a In an optical device (or PIC) of the present invention, a solid-state semiconductor laser source 1010 provides coherent light. The laser can be housed off-chip, in which case the light is coupled into the PIC (i.e., the rest of the optical device) using an optical fiber 1011 and coupling the optical fiber via a grating coupler 1012, or an edge coupler using a metal ferrule 1013, or a V-groove. Alternatively, the light (e.g., laser) source 1010 can be packaged in the same carrier substrate as the PIC, and the light is coupled into the PIC via an edge coupler and a photonic wire bond. Alternatively, the light (e.g., laser) source 1010 can be integrated with the PIC, and the light is coupled into the PIC via an edge coupler and a tapered portion with or without a photonic wire bond.

[0179] exist Fig.10a In the optical device of , the input coherent light from the light source 1010 is amplified using an optical amplifier 1015 before being split into a plurality of input waveguides 1025. This is achieved by splitting the coherent light from the off-chip laser and coupling the laser into a fiber bundle using a fiber splitter 1021, or initially coupling the laser into a single fiber and splitting the light using a cascaded MMI or Y-branch 1022. The input waveguide 1025 is a channel for the input stream and may include, for example, an optical fiber or any other optical conduit. If a cascaded MMI or Y-branch 1022 is used, the input stream originates from the output of the last stacked or cascaded 1×2 splitter. The input waveguide 1025 carries the input optical stream split from the source to the input ports 1005 arranged in a first array.

[0180] Fig.10a A plurality of optical encoders 1030 (also referred to herein as photonic devices) are shown, each optical encoder 1030 being arranged in the path of a corresponding one of the input streams. The optical encoder 1030 is arranged to encode the first complex element onto the corresponding input stream. Fig.10a As an example, Figure 4b The optical encoder 1030 of the type shown is used so that the complete complex number in Cartesian form is encoded onto each input stream. However, the optical encoder 1030 may include a reference Figure 3a , Figure 3b , Figure 4a to Figure 4g , Figure 5a to Figure 5f or Figures 6a to 6c The optical encoder 1030 encodes complex elements (e.g., complex numbers or components of complex numbers) onto an input optical stream before the input stream enters the optical Fourier transform stage 1001. Alternatively, the input stream may pass through an optical circuit, each optical circuit comprising at least the optical encoder 1030 and optionally further optical encoders. The optical circuit acts on each input optical stream before entering the optical Fourier transform stage. Applications of such optical circuits are described herein.

[0181] The input streams described herein (as well as the subsequent output streams and intermediate streams) may be described as optical streams or optical signals. In an embodiment, the streams are carried by waveguides. The term "waveguide" as used herein refers to an optical (i.e., photonic) waveguide, such as an optical fiber. The light in the streams is monochromatic and coherent within and between the individual input streams.

[0182] The value of the first complex element encoded onto each input stream may differ between the input streams such that the value of the input function varies with the position of the input port in the first array due to a variation of the input function in the x-direction and / or the y-direction.

[0183] Two variables can be used to define or approximate each input and output function: (i) the relative position of the port within the array (e.g., xy position); and (ii) the value of the complex number encoded into the optical flow passing through (e.g., entering or leaving) the port. It can therefore be understood that the input and output functions are sampled versions of continuous functions, respectively, where the sampling resolution is determined by the aperture size of the port and / or the port spacing or pitch.

[0184] Time variations in the input streams may also be applied by varying the value of the first complex element encoded onto each input stream over time. The input stream may be continuous (always on, or on for multiple cycles of a clock signal). Alternatively, the input stream may also be pulsed (intermittently turned on and off, optionally synchronized with a clock signal). The value of the first complex element encoded onto the input stream may vary with each clock cycle, so that multiple optical Fourier transforms may be performed consecutively, frame by frame.

[0185] Depending on the type of encoder used to encode the first complex elements and the type of optical circuitry used to perform arithmetic operations on the first complex elements as will be described in more detail herein, the waveguides carrying the separate input streams may be split and recombined in various ways.

[0186] Out-coupling from the waveguide to the optical Fourier transform stage (i.e. OFTC or free space optics, depending on the type of OFT stage) and vice versa can be performed using grating coupler devices or alternatively using fiber bundles coupled to the OFT stage using edge couplers.

[0187] The first array of input ports is now described in more detail, however, the description is also applicable to the second array of output ports and the third array of intermediate output ports and the fourth array of intermediate input ports described herein. The terms "array" and "port" are temporarily used as general substitutes for the aforementioned features.

[0188] The port can be described as a pixel, and the waveguide carrying the corresponding flow can be referred to as a "channel". In an embodiment, the port array described herein is a 1D or 2D array. Depending on the type of optical Fourier transform stage used, the array can be arranged on a straight line (1D), a plane (2D), a curve (1D) or other types of splines (1D), or a curved surface (2D) or other types of surfaces (2D). For example, usually, although not always, when an integrated OFTC device is used to perform an optical Fourier transform, the array is a 1D array arranged on a curve. In contrast, if a free-space optical Fourier transform stage with a Fourier transform lens is used, the array can be arranged on a plane facing the Fourier transform lens. The array can take the form of a 1D or 2D pattern, such as a regular rectangular array or a staggered array including regular port rows and orthogonal port columns, in which adjacent port columns are offset from each other in the direction of the column so that the port row is formed in a direction inclined to the direction of the column.

[0189] The array faces the Fourier transform lens so that the input port is arranged to illuminate the Fourier transform lens and the output port is arranged to collect light that has passed through the Fourier transform lens. The input port is arranged one focal length after the Fourier transform lens and the output port is arranged one focal length before the Fourier transform lens. It will be understood that the input port is arranged to provide a light input to the optical Fourier transform stage and the output port is arranged to sample the light output of the optical Fourier transform stage. The optical Fourier transform stage performs an optical Fourier transform on the light input to provide a light output.

[0190] return Fig.10a , the optical device comprises an array of output ports 1008, each of which is connected via an output waveguide 1065 to an optical amplifier 1080 and then to a detector (or decoder) 1090. Each optical amplifier 1080 is arranged to amplify a corresponding output stream. Fig.10a In the embodiment, the optical amplifier 1080 is a semiconductor optical amplifier (SOA). However, the embodiment is not limited thereto, and other types of optical amplifiers may be used. Alternatively, no optical amplifier is used.

[0191] The detector (or decoder) 1090 is arranged to detect (or decode) the second complex elements encoded onto the respective output streams collected by the output port 1008. Fig.10a As an example, Figure 8b The decoder 1090 is shown in FIG. 1 , where the decoder uses two balanced detectors with 90 degree optical hybrids to detect complete complex numbers from the output stream. However, each decoder 1090 may include reference Figure 8a or Figure 8b Any decoder described herein or other type of decoder arranged to decode complex elements from an optical signal. The decoder may include reference Fig.19 , Fig. 20 , Fig.21 and Fig. 22 One or more of the circuits described.

[0192] Decoder 1090 is arranged to decode the second complex element from each output stream based on at least one characteristic of the corresponding output stream. The decoder detects the value of at least one characteristic, and the value is converted into a form representing the second complex element. In an embodiment, at least one characteristic is the phase and / or amplitude of the output stream, and the value of the phase and / or amplitude is equal to or related to the value of the second complex element. The phase can be a phase relative to the phase of the input stream.

[0193] In another example, the optical Fourier transform stage includes a single 2f stage (two focal length OFT) that is used to compute the OFT of an input function to obtain the Fourier transform of the input function as an output function. The complex mathematical function g is encoded onto the input stream. The OFT of the input function is performed using the optical Fourier transform stage. The OFT light is recoupled back to the output port and the output stream is waveguided for decoding. As with all 2f stages described herein, the OFT stage may include Figure 9a and Figure 9b The free space optical module shown or Figure 9d OFTC shown.

[0194] Fig.10b Shows Fig.10a Application of optical devices. Fig.10b In , the first complex element is encoded onto the input stream to create the input function g shown in the first array at the input of the OFT stage 1001, which is a 2f stage. An optical Fourier transform is performed using the optical Fourier transform stage 1001 to produce an output function G=F(g) in the Fourier plane (where the output port is located). The output function G=F(g) is the Fourier transform of the input function g. If the input function itself is the product of two Fourier transforms g=F(x)*F(y), then the output of the Fourier transform is the convolution of the input functions x and y.

[0195] Mathematical operations and optical Fourier transforms

[0196] Before the input stream leaves the input port, the first complex element encoded onto the input stream may be the subject of a mathematical operation. For example, the first complex element may be multiplied by or added to an additional complex element so that a third complex element is encoded onto the input stream, the third complex element being the result of the mathematical operation. The mathematical operation may be performed by encoding the complex elements onto the input stream using one or more encoders. It may be said that the one or more encoders form an optical circuit.

[0197] In general, the optical device further comprises a plurality of first optical circuits, each of the first optical circuits being arranged to act on a corresponding one of the input streams to perform an arithmetic operation on the corresponding encoded first complex element, thereby encoding the input stream using a third complex element. The input function may be defined based on the value of the third complex element instead of the value of the first complex element, and the position of the corresponding input port in the first array.

[0198] In general, each first optical circuit is a multiplier circuit arranged to act on the input stream to multiply the first complex element with the additional complex element so as to encode the input stream with a third complex element. In other embodiments, each first optical circuit is an addition circuit arranged to act on the input stream to add the additional complex element to the first complex element so as to encode the input stream with a third complex element.

[0199] In an embodiment, the optical circuit is referenced Figure 7a and Figure 7b For example, a multiplier circuit can be a reference Figure 7a The type described, wherein the first encoder 711 is arranged to encode a first complex element, the second encoder 712 is arranged to encode an additional complex element, and the output stream from the multiplier circuit is encoded with a third complex element, wherein the third complex element is the product of the first complex element and the additional complex element. The adding circuit may be a reference Figure 7b The type described, wherein the first encoder 713 is arranged to encode a first complex element, the second encoder 714 is arranged to encode an additional complex element, and the output stream from the adding circuit is encoded with a third complex element, wherein the third complex element is the sum of the first complex element and the additional complex element.

[0200] Generally speaking, in a first mode of operation, the values ​​of the appended complex elements are such that the third complex element is equal to the first complex element. In a second mode of operation, the values ​​of the appended complex elements are such that the third complex element is not equal to the first complex element.

[0201] The first operation mode described above is achieved by setting the value of the additional complex element to 1 (ie, one) in the multiplier circuit or to zero in the adder circuit.

[0202] 2fOFT stage for performing convolution

[0203] A single 2f optical Fourier transform stage (hereinafter "2f stage") can be made to perform the same function as a 4f optical Fourier transform stage (ie, convolution) by performing two consecutive OFT operations as follows.

[0204] In a first operation, the 2f stage is set to the first operation mode described above. Additional complex elements are set for the first operation mode as described above so that an input function of the 2f stage is defined by the value of the first complex element in the first array. The 2f stage then performs an optical Fourier transform of the input function and outputs a first output function at a second array of output ports. A second complex element is decoded from the output stream as described herein. An intermediate step of determining the output function from the output stream and the position of the corresponding output port may then be performed.

[0205] In the second operation, the value of each additional complex element applied in the optical circuit is set equal to the value of the second complex element decoded from the output stream generated in the first operating mode. In other words, the output function is sampled in the first operating mode and then in the second operating mode, the resulting output function is then fed back into the optical circuit in the form of an additional complex element. This can be achieved by configuring an encoder to encode the additional complex element and applying the encoder in the optical path together with the encoder arranged to encode the first complex element for each input stream. The result is that the optical circuit effectively multiplies the first complex element by the additional complex element, so that the input stream is encoded with a third complex element.

[0206] Continuing in the second mode of operation, the 2f stage performs another optical Fourier transform of the input function, this time defined by the value of the third complex element and the corresponding position of the input port in the array. The output function is then sampled in the second mode of operation by decoding the complex element from the output stream.

[0207] This method involving two consecutive measurements using the same 2f stage effectively provides the same result as one measurement using a 4f stage in which an additional complex element is applied in the optical circuit located between the two 2f stages constituting the 4f stage. Such a 4f stage is now described below.

[0208] 4fOFT stages for performing convolution

[0209] Generally speaking, the optical Fourier transform stage described above is a 4f stage comprising a first 2f stage and a second 2f stage. The input port is arranged to provide an optical input as an input to the first 2f stage, and each output port is arranged to receive a portion of the output of the second 2f stage as a previously described portion of the output of the optical Fourier transform stage.

[0210] Thus, the input port of the previously described optical Fourier transform stage is part of the first 2f stage and the output port of the previously described optical Fourier transform stage is part of the second 2f stage.

[0211] Continuing in general terms, the 4f stage also includes: a plurality of intermediate output ports arranged as a third array. Each intermediate output port is arranged to receive a portion of the output of the first 2f stage, thereby forming a first intermediate stream encoded with a fourth complex element. The 4f stage includes a plurality of second optical circuits, each second optical circuit being arranged to act on the intermediate stream to perform an arithmetic operation on the fourth complex element, thereby encoding the intermediate stream using a fifth complex element. The 4f stage also includes a plurality of intermediate input ports arranged as a fourth array, each intermediate input port being arranged to be provided with a corresponding one of the intermediate streams, thereby forming an intermediate function that can be defined based on the value of the fifth complex element and the position of the corresponding intermediate input port in the fourth array. The intermediate input port is arranged to provide an optical input to the second 2f stage.

[0212] The intermediate output port is arranged at the output plane of the first 2f stage so that the intermediate output function which is the Fourier transform of the aforementioned input function is sampled by the intermediate output port. The intermediate output function can be defined based on the value of the fourth complex element encoded on the intermediate stream and the position of the corresponding intermediate output port in the third array.

[0213] The intermediate input port is arranged at the input plane of the second 2f stage such that the intermediate input function is input to the second 2f stage. The intermediate input function may be defined based on the value of the fifth complex element encoded onto the intermediate stream and the position of the corresponding intermediate input port in the fourth array.

[0214] Fig.11 A specific example of a 4f circuit that implements the above-mentioned 4f stage principle is shown. The 4f stage includes a first 2f stage 1001a and a second 2f stage 1001b. The input to the first 2f stage 1001a and the output from the second 2f stage 1001b are respectively as described for reference in structure. Fig.10a The input and output of the optical Fourier transform stage are described above, and therefore, detailed descriptions of the same components will be omitted here, except for noting that Fig.10a Encoder reference for the reference Fig.11 And is labeled as "first encoder" 1030a.

[0215] Fig.11A plurality of intermediate output ports 1006 arranged in a third array are shown. Each intermediate output port is arranged to receive a portion of the output of the first 2f stage, thereby forming a first intermediate stream in an intermediate waveguide 1045, wherein the intermediate stream is encoded with a fourth complex element. The 4f stage comprises a plurality of second encoders 1030b, each second encoder 1030b being arranged to act on the intermediate stream to perform an arithmetic operation on the fourth complex element, thereby encoding the intermediate stream with a fifth complex element.

[0216] Each second encoder 1030b is arranged to encode an additional complex element onto the optical stream. If the arithmetic operation is a multiplication, each second encoder 1030b is simply arranged "in line" (or in series) in the optical waveguide carrying the intermediate stream. Therefore, the aforementioned optical circuit in the general description of the 4f level only includes the second encoder and no other encoders (in other words, each optical circuit is replaced by the second encoder).

[0217] Fig.12 The 4f stage also includes a plurality of intermediate input ports 1007 arranged in a fourth array, each intermediate input port 1007 being arranged to be provided with a corresponding one of the intermediate streams (or other streams encoded with the fifth complex element, e.g., intermediate streams combined with separate streams in the case of addition), thereby forming an intermediate function definable based on the value of the fifth complex element and the position in the fourth array of the corresponding intermediate input port 1007. The intermediate input port 1007 is arranged to provide an optical input to the second 2f stage 1001b.

[0218] In some embodiments, the respective second encoder is arranged to act on the intermediate stream to multiply the fourth complex element with the additional complex element in order to encode the intermediate stream with the fifth complex element.

[0219] Fig.12 is shown in the reference Fig.11 Schematic diagram of the complex mathematical function represented in the 4f level of the first 2f level 1001a and the second 2f level 1001b. Fig.12 , the convolution is performed using 4f stages, where initially, the OFT of function g is calculated optically, the OFT being an intermediate output function G=F(g). The OFT result (G) is then optically multiplied by another function H=F(h), which has been pre-calculated (and optionally retrieved from memory). This produces an intermediate input function G·H. After the OFT of the product of the multiplications G·H, the convolution g*h is calculated. Using this approach, the signal processing remains within the optical / photonic domain; although a pre-processed OFT multiplier function H (also referred to herein as an additional function) is required.

[0220] For more details, refer to Fig.11 and Fig.12, the input function g to the first 2f stage can be defined based on the value of the first complex element encoded on the input stream and the corresponding position of the input port 1005 in the first array. The first 2f stage 1001a performs an optical Fourier transform of the input function to form an intermediate output function G=F(g). The intermediate output function G=F(g) can be defined based on the value of the fourth complex element encoded on the intermediate stream and the corresponding position of the intermediate output port 1006 in the third array. The intermediate output function is then multiplied by an additional function H=F(h) applied to the intermediate stream. This can be accomplished by encoding the additional complex element onto the intermediate stream using the second encoder 1030b, which itself has been encoded using the fourth complex element. As described above, this results in the fifth complex element being encoded onto the intermediate stream when arriving at the intermediate input port 1007 that provides input to the second 2f stage. The additional function H=F(h) can be defined based on the value of the additional complex element and the position of the intermediate output port 1007 corresponding to the intermediate stream onto which the additional complex element is encoded. The result of multiplying the intermediate output function G = F (g) and the additive function H = F (h) is the intermediate input function G H. The intermediate input function G H can be defined based on the value of the fifth complex element and the position of the corresponding intermediate input port 1007 in the fourth array. The second 2f stage then performs an optical Fourier transform of the intermediate input function G H to provide an output function g * h (the convolution of g and h). The output function can be defined based on the value of the second complex element encoded on the output stream and the corresponding position of the output port 1008 in the second array.

[0221] Fig.13 An alternative method for optically computing the convolution of two functions g*h is shown in . Fig.13 A convolution method using a modular rearrangement of a first 2f stage 1301a, a second 2f stage 1301c, and a third 2f stage 1301b is shown. Each of the first, second, and third stages may be a reference Fig.10a described form. The first 2f stage and the second 2f stage are used to optically calculate the OFT of a first input function g and a second input function h to provide a first intermediate output function G=F(g) and a second intermediate output function H=F(h), respectively. The results are then multiplied electronically (for example using a feedforward circuit) to obtain an intermediate function i=G·H. The electronic result of the multiplication is then encoded back into the optical domain and subsequently inverse Fourier transformed using a third 2f stage to calculate the convolution I=F(i)=g*h. Using this approach, despite having electronic multiplication stages, the OFT of both functions can be calculated during run time. That is, functions g and h can be received and processed simultaneously, as compared to the reference Fig.12 This can speed up operation compared to the process described above and does not require storing / retrieving a previously calculated value of H.

[0222] All functions described herein are mathematical functions defined by complex elements. The output function may be defined by complete complex numbers (and thus may be referred to as a complex output function). If the encoded complex elements are complete complex numbers, the input function may be a complex function. If the encoded complex elements are components of a complex number, the input function may be a real function.

[0223] III-Controller

[0224] Compensation for phase effects and photonic device properties

[0225] More complex forms of optical computing systems capable of performing complex number operations have been described. As discussed above, the inventors have recognized that optical computing systems of increased complexity, such as the optical computing systems of the present disclosure, are subject to phase effects that do not adversely affect less complex optical computing devices. In more detail, the photonic devices of the disclosed optical computing systems are susceptible to experiencing so-called "phase drift," for example as a result of environmental factors such as temperature. Such phase drift affects the behavior of light used by the photonic devices to perform operations and arithmetic. More specifically, because the presently disclosed systems utilize the phase of light to encode complex numbers, phase drift of the photonic device(s) will affect this process and affect the associated calculations. Accordingly, the inventors have devised mechanisms for compensating for such phase effects to enable reliable and accurate calculations to be performed. Reference will now be made to the Figures 14 to 22 Describe these mechanisms in detail.

[0226] First turn Fig.14 , schematically illustrating an example of a system for correcting phase effects (e.g., phase drift) of a photonic device of an optical computing system. An example chiplet is shown that includes at least four schematic building blocks 1401, 1402, 1403, 1404. The digital backend 1401 of the chiplet includes a set of driver electronics, digital backend logic, and digital interconnects, and allows data exchange to and from the chiplet. In practice, data will typically be received from a data bus of a digital computing element. Connected to the digital backend 1401 of the chiplet is a controller 1402 of an optical encoder of the chiplet. The controller 1402 may alternatively be referred to as an optical driver or encoder driver. The controller 1402 enables data to flow through the chiplet and feeds signals to photonic devices in a photonic integrated circuit (PIC) 1403 of the chiplet. The PIC 1403 is connected to the controller 1402 of the optical encoder and includes at least one photonic device that enables optical arithmetic operations, optical Fourier transforms (OFTs), and convolutions to be performed on complex mathematical elements or complex numbers.

[0227] It should be understood that the controller 1402 may be included as a reference Figures 3a to 6d Similarly, PIC 1403 may be a reference to any of the encoders described in any of the arrangements described in (continuous and inclusive). Figures 9a to 13 Any of the PIC or optical devices described (continuous and inclusive). The controller 1402 may take reference Fig.15 , Fig.16 or Fig.17 Describes the form of any controller.

[0228] Feedback 1404 from the PIC 1403 is fed back to the optical encoder's controller 1402. In this example, the feedback 1404 provides an offset voltage set by feedback logic to the controller 1402. The feedback signal 1404 can be used to modify the signal provided by the controller 1402 to the PIC 1403 in a manner that will be described in further detail below. Where this occurs periodically or continuously, Fig.14 The arrangement can thereby form a continuous or periodic feedback loop. In this example, the operation of the PIC 1403 is controlled by a dedicated state machine that controls, monitors and optimizes the electronic control of the photonic devices in the PIC 1403 to maximize efficiency, reduce data latency and increase throughput. To this end, the PIC 1403 is hybrid or co-integrated with the digital back end 1401 via the controller 1402. The feedback signal provided by the feedback 1404 from the PIC enables the system to maximize the performance of the multi-bit operation of the photonic devices.

[0229] With this general overview in mind, a more complete example embodiment of a controller 1402 for an optical encoder will now be described.

[0230] Fig.15 and Fig.16 A first example embodiment and a second example embodiment are provided that illustrate the signal flow through components of the controller 1402 of the optical encoder. Fig.15 and Fig.16 The diagrams are shown in a linked manner to facilitate understanding and to show which common components (e.g., power management and feedback logic modules) feed signals to which components in each respective embodiment. However, it should be understood that the linking of the two arrangements is merely schematic and that, in practice, one or the other arrangement may be provided separately.

[0231] exist Fig.15 and Fig.16 In both arrangements, the individual photonic devices are fed with signals via optical encoders. Fig.15 and Fig.16For simplicity, only a single optical encoder will be described, however, there may be more than one optical encoder. The optical encoder may include an encoder driver that receives an electronic input signal from an interface, wherein the value of the electronic signal is based on a complex element. In this example, the optical encoder includes at least one buffer, or more specifically, at least one First-In-First-Out (FIFO) that formats and organizes data. The interface may include a digital input and output (DIDO) board or module. The received electronic signal may be a multi-bit signal or a bit stream of data from the interface or more specifically from the data backend logic of the digital backend 1401.

[0232] In an optical encoder, Fig.15 and Fig.16 In an embodiment of the invention, the received electronic signal is split into two components: a first signal component and a second signal component. The second signal component is an inverted version of the first signal component, thereby providing a push-pull signal. Thus, the received electronic signal may be modified or inverted in some manner before being output at or provided to the photonic device. Fig.15 and Fig.16 Two example embodiments are provided of how to split and invert received electronic signals for provision to photonic devices. Fig.15 An embodiment using a push-pull amplifier configured to invert the second signal component in the analog domain is shown, while Fig.16 An embodiment using an inverter configured to invert the second signal component in the digital domain is shown. If the second signal component is inverted in the digital domain, i.e., if using Fig.16 arrangement, the circuit can be advantageously simplified because the additional circuit components required when inverting the signal in the analog domain are not required. In this example, one signal component is provided to each of the two contacts of the photonic device, respectively. For example, a first signal component may be provided to a first photonic device contact, and a second signal component may be provided to a second photonic device contact (the first photonic device contact and the second photonic device contact are contacts of the same photonic device). In other examples, this may vary. For example, in other embodiments, a first signal may be provided to a first photonic device contact, and the second photonic device contact may be connected to a ground or reference voltage line.

[0233] Now turn to the Fig.15In this example arrangement, the electronic signal received from the FIFO is a digital electronic signal and is stored in a digital buffer. The received electronic signal is then output from the digital buffer to a digital-to-analogue converter (DAC) to convert the received electronic signal into an analog electronic signal. The output of the DAC is AC coupled to adjust the DC bias of the analog electronic signal. In other words, the received digital electronic signal is ultimately converted into an AC coupled analog electronic signal. The DAC may be accompanied by a sample and hold circuit to capture and hold the analog signal until the subsequent circuit or more specifically the VGA is ready to process it. The sample and hold circuit holds the value and changes the output value only when new data is retrieved from the FIFO.

[0234] In this example, the controller 1402 is configured to amplify the received electronic signal using a variable gain amplifier (VGA). However, it is understood that the VGA may or may not be included depending on the voltage range supported by the DAC. The received electronic signal is then output from the VGA and divided into a first signal component and a second signal component. Splitting the electronic signal in this way forms a push-pull signal. A push-pull amplifier is used to invert the second signal component, resulting in the second signal component being an inverted version of the first signal component. In this example, the push-pull amplifier is configured to invert the second signal component in the analog domain because the push-pull amplifier can drive two output levels. This means that the signal can be inverted. However, the push-pull amplifier may result in the removal of AC coupling or the increase of DC artifacts. Therefore, if AC coupling of the second signal component is necessary, the second signal component (or balance adjustment) can be adjusted for balance.

[0235] Including voltage V BAL The adjustment signal may be provided to the controller 1402 to provide such a balance adjustment, in other words, to adjust the DC offset, DC artifacts and / or lack of AC coupling of the second signal component. Fig.15 is designated as "balance adjustment", and V BAL The adjustment signal is provided at Fig.17 In this way, based on the received adjustment signal V BAL The second signal component is modified to generate a modified second signal component. The adjustment signal may include an average voltage of a desired peak-to-peak swing voltage.

[0236] In this example arrangement, the V BAL The adjustment depends on the voltage swing required by the controller 1402 and can be set by firmware, for example by Fig.15Advantageously, the firmware can be configured to take into account the type of photonic device to which the controller 1402 is connected. This in turn can affect the V BAL In other words, adjust the signal V BAL It may depend on the type of photonic device used in the optical encoder and may therefore allow the controller to adapt to the type of photonic device.

[0237] The controller 1402 may also be configured to modify the received electronic signal to compensate for the phase shift caused by the push-pull amplifier of the optical encoder. Fig.15 , and designated as "center adjustment". In this embodiment, the first signal component and the second signal component of the electronic signal are adjusted to correct for a phase offset imposed on the AC coupled analog electronic signal by active components in the circuit (e.g., a push-pull amplifier). An analog delay line can be used to match the phase of the signal.

[0238] In order to enable such adjustments, the dynamic operating range V of the photonic device CENTRE The instruction is received by the controller 1402, such as Fig.17 Based on the received dynamic operating range V CENTRE The received electronic signal is modified according to the instructions. This process can be referred to as the signal being "center adjusted". BAL Under the same conditions, the dynamic operating range V CENTRE The indication of V may be set by firmware, which may be configured to take into account the type of photonic device to which the controller 1402 is connected, as described above. In other words, the adjustment signal V CENTRE It may depend on the type of photonic device used in the optical encoder. Further, when the received electronic signal is split into two components, the center adjustment correction performed in this embodiment includes adjusting the first signal component and the second signal component so that their swing voltages span the dynamic operating range of the photonic device and ensure compliance with the signal-to-noise ratio and bit precision / accuracy specifications outlined for the photonic device.

[0239] As mentioned above, the adjustment signal V BAL and the dynamic operating range V CENTRE The indication of V may be provided by firmware, which may take into account the type of photonic device used by the optical encoder. For example, different photonic devices may require different dynamic voltage ranges to function properly. BAL and the dynamic operating range V CENTREThe indication of V allows such changes to be made to the dynamic voltage range when providing an input signal to the photonic device. Therefore, the same controller 1402 can be used for a variety of different photonic devices. If a new photonic device is to be used, the controller 1402 firmware can simply be updated to modify V accordingly. BAL and V CENTRE This avoids the need to use different types of controllers 1402 for each type of photonic device, or the need to design multiple controller circuits for different specific photonic devices. BAL and the dynamic operating range V CENTRE The indication may be set by a power management block operating the aforementioned firmware, wherein the power management block controls voltage lines in one or more circuits of the controller 1402. Fig.17 It is schematically shown in FIG.

[0240] Back to Fig.15 , showing the final adjustment, which is designated as a "bias adjustment". The adjustment involves the controller 1402 receiving a feedback signal based on a phase drift associated with the photonic device of the optical encoder. In response to the feedback signal, the controller 1402 modifies the received electronic signal based on the received feedback signal to generate a modified electronic signal (which may be referred to as a bias adjustment), and provides the modified electronic signal to modulate the photonic device. The feedback signal is provided as a bias voltage V provided via feedback logic or set by feedback logic OFFSET Receive, such as Fig.17 In the present example where the electronic signal comprises two already split components, the received electronic signal is modified by adjusting the first signal component and the second signal component to cancel the phase drift associated with the photonic device.

[0241] The above adjustment process (designated as balance adjustment, center adjustment and bias adjustment) can be implemented as a feedback loop. In particular, a signal can be output from the controller 1402 to the photonic device, such as Fig.14 As shown. The effect of the signal on the photonic device can then be evaluated by monitoring the photonic device. Based on this monitoring, the system can determine (e.g., via firmware operational feedback and / or power management logic) that an adjustment is needed. This adjustment can then be implemented via the balance adjustment, center adjustment, and bias adjustment described above to generate a modified signal. This cyclic feedback loop can then be repeated so that each feedback signal received by the controller 1402 is based on the effect of the modified electronic signal previously provided to the photonic device by the controller 1402. This provides Fig.14 It should be understood that, in practice, the balance adjustment signal, the center adjustment signal, and the bias adjustment signal may be provided to the circuit of the controller 1402 in the form of corresponding input voltages, such as Fig.17 shown.

[0242] Now turn to Fig.16 , shows how an alternative arrangement of a controller 1402 for an optical encoder may be implemented. Fig.16 The process is similar in many ways to Fig.15 The process is similar, but with some significant differences.

[0243] exist Fig.16 In the embodiment, the electronic signal received from the FIFO is a digital electronic signal and is again divided into a first signal component and a second signal component. The signal is divided to form a push-pull signal. Fig.15 In the same arrangement as in FIG. 1 , the second signal component is inverted, in this case using an inverter, resulting in the second signal component being an inverted version of the first signal component. However, unlike Fig.15 The layout is different. Fig.16 In this example, both the division and inversion of the signal occur in the digital domain. The inverter in this example is a digital inverter. As a result of performing the inversion in the digital domain, Fig.15 Compared with the arrangement of BAL , because the received electronic signal is still a digital electronic signal. Fig.15 This simplifies the circuitry of controller 1402 compared to the push-pull amplifier embodiment.

[0244] After inversion, Fig.16 The arrangement then involves the first signal component and the second signal component being propagated to two digital buffers. Each digital buffer outputs either the first signal component or the second signal component to one of two DACs to convert the first signal component and the second signal component of the received electronic signal into analog electronic signals. Each DAC may be accompanied by a sample and hold circuit to capture and hold the analog signal until subsequent circuitry, or more specifically the VGA, is ready to process it. The sample and hold circuit holds the value and only changes the output value when new data is retrieved from the FIFO. With Fig.15 As in the case of FIG. 14A , in this example, the controller 1402 is then configured to amplify the received electronic signal using a variable gain amplifier (VGA).

[0245] Likewise with Fig.15 The arrangement is the same as that of the analog electronic signal, and then the received electronic signal is output and undergoes a center adjustment process so that they are AC coupled to adjust the DC bias of the analog electronic signal. In other words, as described above with respect to Fig.15 The first signal component and the second signal component of the digital electronic signal are converted into AC-coupled analog electronic signals.

[0246] As mentioned above, the dynamic operating range V of the receiving photonic device CENTREBased on the received dynamic operating range V CENTRE The dynamic operating range V CENTRE The indication is set by firmware depending on the connected photonic device. Further, when the received electronic signal is split, the received electronic signal is modified by adjusting the first signal component and the second signal component so that their swing voltages span the dynamic operating range of the photonic device. Dynamic operating range V CENTRE The indication can be set by the power management block and allows the circuit to be reused for a variety of different photonic devices, rather than using different circuits for each photonic device, as shown in the reference Fig.15 described.

[0247] Likewise with Fig.15 As in the case of , the signal then undergoes bias adjustment, whereby the controller 1402 receives a feedback signal based on a phase drift associated with the photonic device of the optical encoder, modifies (or bias adjusts) the received electronic signal based on the received feedback signal to generate a modified electronic signal, and provides the modified electronic signal to modulate the photonic device. Fig.15 The feedback signal is provided as a bias voltage V via feedback logic or set by feedback logic. OFFSET Receive, such as Fig.17 shown.

[0248] In the present example where the signal includes two already split components, the received electronic signal is modified by adjusting the first signal component and the second signal component to cancel out a phase drift associated with the photonic device.

[0249] As about Fig.15 As stated, Fig.16 The process may occur as part of a feedback loop, wherein a previously modified signal provided by the controller 1402 to the photonic device informs the next "loop" of the modifications provided via the center adjustment and the bias adjustment.

[0250] Unlike the driver circuits used in traditional data communication applications, the Figure 15 to Figure 16 The example controller flow shown in the push-pull and data inversion optical encoder circuit takes into account the use of the adjustment signal V BAL and the dynamic operating range V CENTREThe drive signal is dynamically adjusted based on at least one of the indications of the photonic device. The swing voltage of the photonic device spans its dynamic operating range, or in other words, the voltage swing of the photonic device is centered around its dynamic operating range. This increases the data level separation in the optical signal generated using the photonic device. Further, phase drift is compensated by modifying the received electronic signal based on a received feedback signal, wherein the feedback signal is received as a bias voltage provided via feedback logic. The feedback logic also sets the amplification of the VGA.

[0251] Now turn to Fig.17 , shows an example circuit for implementing controller 1402. Such a circuit can be used to control and execute Fig.15 The signal flow is schematically shown in FIG. Various modules are provided in the circuit to implement the above reference Fig.15 The resistor is represented by R sub , where the subscript "sub" indicates which functional block the resistor forms part of. Similarly, a capacitor is denoted as C sub , where the subscript “sub” indicates which functional block the capacitor forms part of. The supply voltage is denoted as V dd and V SS , where V dd Represents the positive supply voltage, V SS Indicates a negative supply voltage or a connection to ground. The use of “d” and “s” indicates the drain and source respectively. This means that the circuit provided is made using Field Effect Transistor (FET).

[0252] It can be seen that, from Fig.15 The DAC described receives an input signal. The signal is then amplified by the VGA 1702. Then, a split signal including a first signal component and a second signal component flows from the VGA 1702 into two branches of the circuit.

[0253] As about Fig.15 As described above, the two components can be adjusted by the offset adjustment 1712 block and the center adjustment 1710 block, wherein the adjustment is provided by the V OFFSET and V CENTRE Terminal signal control.

[0254] Provided to V OFFSET The signal can be set using feedback logic 1708, which sets the bias based on the feedback signal indicating the phase drift experienced by the photonic device of the optical encoder. This allows the bias adjustment 1712 to modify the signal provided to the photonic device so that the modified input signal causes the photonic device to operate in a manner that compensates for or corrects the phase drift. This ensures proper function of the photonic device and ultimately allows accurate and reliable calculations.

[0255] V CENTRE The adjustment may be set by the power management logic 1706, which sets the center adjustment based on the type of photonic device connected to the optical encoder to which the output signal will be provided. This allows the center adjustment 1710 to adjust the signal provided to the photonic device to account for the specific requirements, characteristics, and / or behavior of the photonic device. If a new type of photonic device is connected to the controller 1402, V may be adjusted accordingly. CENTRE This avoids the need to provide separate, specific controllers for each type of photonic device or for controllers to be extensively modified when new photonic device types are connected.

[0256] Likewise, as Fig.15 As described above, one of the split signal components may further undergo push-pull and balance adjustment modifications. Fig.17 This is achieved by push-pull driver 1704 and balance adjustment 1714. Fig.15 The balance is adjusted via terminal V BAL As with the case of center adjustment 1710, balance adjustment 1714 allows the control circuit to adjust the signal provided to the photonic device to take into account the specific requirements, characteristics and behavior of the photonic device.

[0257] After the above modifications, the two components of the processed signal are finally provided to the terminals V OUT1 and V OUT2 It will be appreciated that where more than one photonic device is provided, Fig.17 There are multiple copies of the circuit, each copy providing a terminal of a corresponding photonic device.

[0258] In realization Fig.16 The process flow instead of Fig.15 In the case of process flow, you can Fig.17 For example, the push-pull driver 1704 and the balance adjustment 1714 may be omitted because Fig.16 The circuit can be further modified by using two DACs with sample and hold and two VGAs 1702 instead of one. The output of the VGA will be fed to the rest of the control circuit, including the center adjustment 1710 and the balance adjustment 1714, and the two components of the processed signal will then be provided to the terminals V OUT1 and V OUT2 .

[0259] The optical encoder of this example is a mixed signal circuit that is composed of different logic families - for example, CMOS (Complementary Metal-Oxide Semiconductor) logic associated with digital data and TTL (Transistor-Transistor Logic) associated with analog circuits. Therefore, appropriate signal integrity blocks (pull-up / pull-down resistor networks) are used to ensure that signal integrity is maintained in the circuit.

[0260] Next turn Fig.18 , schematically illustrating the method of the present disclosure. The method may be implemented by the controller 1402 to provide an input signal to the photonic device of the PIC 1403.

[0261] Fig.18 The method of begins by receiving an electronic signal at box 1801, where the value of the electronic signal is based on a complex element. As described above, "complex element" in this context can be understood to mean a complex number or a component of a complex number. The component of a complex number can be the real part or imaginary part of the complex number, or can be based on the real part or imaginary part of the complex number (for example, the component can be the modulus of the real part or imaginary part of the complex number, or a positive or negative value of the real part or imaginary part of the complex number). In this way, method E provides a mechanism whereby the controller 1402 can provide an input signal to the photonic device, which enables the photonic device to encode and perform operations using complex numbers or their components.

[0262] The method then continues at block 1802 with receiving a feedback signal based on a phase drift associated with the photonic device of the optical encoder. As described above, the photonic device (e.g., the photonic device of the PIC 1403) experiences phase drift due to environmental factors such as temperature. If such phase drift is not addressed, such phase drift may impair the ability of the photonic device to perform accurate and reliable calculations. The feedback signal received at block 1802 is configured such that it allows the controller 1402 to modify the processed electronic signal to compensate for any phase drift experienced by the photonic device. The feedback signal may be set / provided via feedback logic that monitors the photonic device and quantifies or evaluates any phase drift experienced by the photonic device.

[0263] The method also includes modifying the received electronic signal based on the received feedback signal to generate a modified electronic signal at block 1803. This may include modifying a parameter of the received electronic signal so that when the modified electronic signal is provided to the photonic device, a phase drift of the photonic device as indicated in the received feedback signal is compensated. In practice, the modification provided at block 1803 may be performed as described above with respect to Figures 15 to 17 The method described in V OFFSETProvide an appropriate bias signal to provide.

[0264] Next, the method continues at block 1804 by providing a modified electronic signal to modulate the photonic device in a manner to compensate for or correct the identified phase drift of the photonic device. This ensures that any such phase drift does not impair the ability of the photonic device to perform accurate and reliable computations.

[0265] Fig.18 The method can be implemented as a loop, as already described Fig.14 In other words, the feedback signal can be continuously or periodically provided to the controller 1402, for example, via feedback logic. The controller 1402 can thereby continuously or periodically update the signal it provides to the photonic device in order to continuously or periodically compensate for the phase drift experienced by the photonic device. This ensures the continuous reliability of the calculation.

[0266] It should be understood that Fig.18 The method may include additional blocks, particularly to compensate for or adjust for other factors, such as the type of photonic device used in the optical encoder.

[0267] The method may include splitting the received electronic signal into a first signal component and a second signal component. The second signal component may be an inverted version of the first signal component. The method may include inverting the second signal component of the split signal in the digital domain or the analog domain in the manner described above.

[0268] The method may include receiving an adjustment signal to correct a DC offset on the second signal component, and modifying the second signal component based on the received adjustment signal to generate a modified second signal component.

[0269] The method may include modifying the received electronic signal by adjusting the first signal component and the second signal component to offset a phase drift associated with the photonic device. The method may include modifying the received electronic signal by adjusting the first signal component and the second signal component so that their swing voltages span a dynamic operating range of the photonic device.

[0270] The method may include receiving an indication of a dynamic operating range of the photonic device, and modifying the received electronic signal based on the received indication of the dynamic operating range.

[0271] The method may include amplifying the received electronic signal. The received electronic signal may be a digital electronic signal. The method may include converting the received (digital) electronic signal into an analog electronic signal using a digital-to-analog converter (DAC).

[0272] The method may include AC coupling the analog electronic signal to adjust a DC bias of the analog electronic signal.

[0273] The method may include modifying the received electronic signal to compensate for a phase offset caused by a push-pull amplifier of the optical encoder.

[0274] Providing 1804 a modified electronic signal may include providing a first portion of the modified electronic signal, wherein the first portion is fast moving. Providing 1804 a modified electronic signal may include providing a second portion of the modified electronic signal, wherein the second portion is slowly moving. In this context, a "fast moving" signal describes an AC data signal. In this context, a "slow moving" signal describes a slowly moving DC signal. Slow moving components of a circuit may generally include a DC component.

[0275] Modifying 1803 the received electronic signal may generate a second portion of the modified electronic signal. The received electronic signal may be a multi-bit signal. The received electronic signal may be received via an interface and at least one buffer. The interface may include a digital input and output board.

[0276] Fig.19 and Fig. 20 A first exemplary embodiment and a second exemplary embodiment are provided, which illustrate the signal flow through the components of the controller of the optical decoder. The optical decoder referred to herein may include any of the previously described optical decoders 850 and referenced Figure 8a or Figure 8b Detector (or decoder) 1090 is described. Photodetectors referred to herein may include any of the photodetectors 804 previously described.

[0277] exist Fig.19 and Fig. 20 In both arrangements, the optical decoder receives an optical signal from an optical device. For example, the optical signal may be an output stream received at an output port of any previously described OFT optical device. The two example embodiments are arranged to decode complex elements, such as the sign and absolute value of components of a complex number, from respective output streams based on at least one characteristic of the respective output streams. In the example, the differential photocurrent from the balanced photodiodes is converted into an electronic signal, or more specifically, a digital electronic signal or digital data including one bit (or sign bit) for the sign (or polarity) of the real and / or imaginary part and a multi-bit signal (or multi-bit word) for the magnitude (or modulus or absolute value) of the real and / or imaginary part. The digital electronic signal may also be referred to as a binary number. In a binary number, the leftmost bit is referred to as the most significant bit and the rightmost bit is referred to as the least significant bit. The sign bit is typically the most significant bit of the binary number.

[0278] The circuit is implemented using either a single-ended ADC or a differential ADC. Fig.19An embodiment is shown in which the analog electronic signal is split into a third component and a fourth component. The single-ended ADC is configured to convert the fourth component into the modulus of the digital electronic signal, and the remaining circuit is configured to convert the third component into the sign bit of the digital signal. On the other hand, Fig. 20 An embodiment using a differential ADC configured to convert an analog electronic signal into a sign bit of a digital electronic signal and a modulus of the digital electronic signal is shown. The sign bit and modulus of the digital electronic signal represent a complex element encoded onto an optical signal received at a photodetector.

[0279] In both embodiments, the received electronic signal fed from the balanced photodetector into the optical decoder is the difference in the photocurrents from the individual constituent photodetectors that form the balanced photodetector. This current is amplified and converted to a voltage signal using a transimpedance amplifier (TIA). If additional gain of the voltage signal is required, a VGA amplifies the voltage signal. High gain improves the accuracy of the voltage signal and can be beneficial when the noise in the system is considerable. After amplification by the TIA and VGA, the voltage signal is converted to a voltage signal. Fig.19 and Fig. 20 In various embodiments, different methods are then used to convert the voltage signal (or analog electronic signal) into a digital electronic signal.

[0280] Turn to more details Fig.19 , after the voltage signal has been amplified if necessary, the voltage signal is split into two analog components: a third component and a fourth component. The sign of the complex element is determined from the third component, and the modulus of the complex element is determined from the fourth component, thereby determining the complex element encoded onto the light signal received by the photodetector.

[0281] In order to determine the sign of the complex element, a comparator is connected to a reference line and a VGA to compare a reference voltage with the voltage of the third component. The reference voltage is provided to the comparator via the reference line and is set by the power management component. The comparator then outputs a modified third component, which indicates which of the two voltages input to the comparator is greater. The comparator uses TTL logic, so its output is a binary signal, or more specifically, a TTL signal. If the voltage of the third component is lower than the reference voltage, the voltage signal of the modified third component is negative. For example, if the reference line is provided with a reference voltage equal to 0, the output of the comparator will indicate that when the voltage of the third component is less than 0, the voltage signal of the modified third component is negative. The output of the comparator is then converted from TTL logic to CMOS logic. The TTL CMOS pull-up receives the modified third component and converts it to a voltage level understood by CMOS logic. The TTL CMOS pull-up is essentially a resistor circuit that changes the voltage level of the received signal by connecting the unused input pin of a digital logic gate (e.g., a digital inverter) to a DC supply voltage to keep the input voltage of the resistor circuit high. Because the values ​​of high and low voltages (or currents) are different with respect to TTL logic and CMOS logic, the voltage levels need to be changed. The use of CMOS logic allows for very low power consumption. The comparator could also use another logic family, for which appropriate matching networks are placed to convert the comparator output to CMOS logic, but for this embodiment, the comparator uses TTL logic.

[0282] In this embodiment, the digital logic gate is a digital inverter (or NOT gate), and implements the logical NOT for CMOS conversion. Therefore, the modified third component is inverted by the digital inverter to output the bit (or sign bit) representing the sign of the complex element. This is used because the TTL CMOS pull-up circuit has an error tolerance, so the output (sign bit) may not be correct. Therefore, the digital inverter ensures that the sign is correct. If the logic level 1 is used to represent a negative number, the output of the digital inverter is the sign bit. On the other hand, if the logic level 0 is used to represent a negative number, the output of the digital inverter is inverted again to determine the sign and output the sign bit.

[0283] When determining the modulus of the received signal, the fourth component is rectified using a rectifier circuit in the analog domain to reverse the polarity of the negative portion of the fourth component. In this way, the magnitude of the fourth component can be tracked because the rectifier circuit limits the signal to ensure that there is no negative portion, leaving only the magnitude (or modulus or absolute value). In this embodiment, the fourth component undergoes full-wave rectification, which results in the inversion of the negative portion to ensure unipolarity. Therefore, this extracts the modulus of the signal. The modified fourth component is then fed to a single-ended ADC to convert the modified fourth component into a multi-bit word (a segment of a longer word that defines a complete complex number). The single-ended ADC is a unipolar device, so its range is from 0 to a positive value. The output from the single-ended ADC represents the modulus of the signal. Two instances of this circuit are used, one for real terms and the other for imaginary terms, to construct a complete complex number.

[0284] Therefore, the third component and the fourth component are modified and output the sign and modulus in the form of digital electronic signals. These signals are fed into a separate digital buffer. The digital buffer outputs the sign bit or multi-bit word to one of the two FIFOs for storage. The sign bit and multi-bit word can be input as digital signals into any previously described optical encoder.

[0285] Now turn to the Fig. 20 In this example arrangement, in the Fig.19 After the voltage signal is amplified by the TIA and VGA components, the voltage signal is fed into the differential ADC. The differential ADC specifies a voltage range with a maximum value (+) and a minimum value (-). If the voltage signal fed into the differential ADC is within the specified voltage range, the output of the differential ADC is a digital electronic signal (or a binary signal or a digital or binary signal or a code). In an optical computing system designed to be compatible only with integers, this is a case where the circuit stops because the sign and modulus of the integer do not need to be implemented. The system currently described is capable of performing more complex operations because the output of the differential ADC can be decoded by separating the sign bit and modulus of the number using a signed output decoder logic. In this embodiment, a signed output decoder logic is provided in the binary output decoder, which divides the signal into a (single) bit signal (sign bit) and a multi-bit signal (multi-bit word, which is a segment of a word defining a complete complex number). The values ​​of the bit signal and the multi-bit signal represent the sign and absolute value (modulus) of the complex element encoded on the optical signal received at the photodiode, respectively.

[0286] Fig.21 and Fig. 22 A detailed example of the operation of a differential ADC and a binary output decoder is shown. Fig.21 The differential ADC output is a signed embodiment, and Fig. 22An embodiment is shown where the differential ADC output is unsigned. In both embodiments, the differential ADC is provided with a reference signal and a voltage signal from a previous component in the decoder. The reference signal specifies the above voltage range of the differential ADC. As described above, the differential ADC output is a digital number. The number can be signed or unsigned.

[0287] Fig.21 Shows Fig. 20 The operation of the binary output decoder, wherein the number is signed. If the signed number is negative, the binary output decoder sets the sign bit to negative, and if the signed number is not negative, the binary output decoder sets the sign bit to positive. The sign bit of a signed number is the most significant bit. In this way, if the sign bit of the signed number is 0, the sign bit is negative, and if the sign bit of the signed number is 1, the sign bit is positive. The modulus of a signed number is implemented as the absolute value (or absolute word or abs word) of the remaining bits from the signed number, which is set as the modulus of the signed number.

[0288] Fig. 22 Shows Fig. 20 The operation of the binary output decoder, wherein the number is unsigned. If the unsigned number is less than the differential ADC code of 0, the binary output decoder sets the sign bit to negative, and if the unsigned number is greater than the differential ADC code of 0, the binary output decoder sets the sign bit to positive. In the binary output decoder, the input line can be a logic level 0 or 1. In addition, one output line is high at logic 1, while the remaining output lines remain low at logic 0. The combination of these input lines determines which output lines remain low at logic 0 and which outputs remain high at logic 1. The differential ADC code of 0 identifies that the input line is set at logic 0, so the unsigned number determines which output line is high at logic 1. Therefore, the binary output that is high when the unsigned number is input identifies the sign bit. In this embodiment, the first input of the binary output decoder (differential ADC) is 0, and the second input is set by the unsigned number. If the unsigned number is negative (i.e., logic level 0), the output line that identifies the second input as logic 0 is high at logic 1, and the sign bit is set to negative. On the other hand, if the unsigned number is positive (i.e., logic level 1), the output line identifying the second input as a logic 1 is high at a logic 1, and the sign bit is set to positive. The code of the differential ADC of 0 is then subtracted from the unsigned number, and the modulus of the signed number is implemented as the absolute value (or absolute word or abs word) of the bits from the unsigned number, the bits of the unsigned number being set to the modulus of the unsigned number. In alternative embodiments, the logic may be reversed, i.e., 0 is 1 (and high is low) and vice versa, in which case commensurate adjustments need to be implemented as will be appreciated by the skilled person.

[0289] The binary output decoder splits the signal into a fifth component (carrying the sign) and a sixth component (carrying the modulus). The fifth and sixth components can be considered to be related to the reference Fig.19 The third and fourth components described are similar in that they include a sign bit and a multi-bit word, respectively. These fifth and sixth components are fed into separate digital buffers, respectively. The digital buffers output the sign bit or the multi-bit word to one of the two FIFOs for storage, respectively. The values ​​of the sign bit and the multi-bit word represent the sign and absolute value (modulus) of the complex element encoded into the optical signal received at the photodiode, respectively.

[0290] The described embodiments are provided for the purpose of illustration and are not intended to be limiting. As will be appreciated by the skilled person, various modifications may be made to the embodiments. The present invention is defined by the scope of the appended claims.

Claims

1. A controller for an optical encoder, the controller being configured to: receiving an electronic signal, wherein The value of the electronic signal is based on a complex element; receiving a feedback signal based on a phase drift associated with a photonic device of the optical encoder; modifying the received electronic signal based on the received feedback signal to generate a modified electronic signal; as well as The modified electronic signal is provided to modulate the photonic device.

2. The controller according to claim 1, wherein: The feedback signal is received as a bias voltage provided via feedback logic.

3. A controller according to claim 1 or 2, the controller being configured to split the received electronic signal into a first signal component and a second signal component.

4. The controller according to claim 3, wherein: The second signal component is an inverted version of the first signal component.

5. The controller according to claim 4, wherein the controller is configured to: receiving an adjustment signal to adjust a DC offset on the second signal component; and Based on the received adjustment signal, the second signal component is modified to generate a modified second signal component. 6 . The controller according to claim 4 , further comprising a push-pull amplifier configured to invert the second signal component in the analog domain.

7. The controller according to any one of claims 4 or 5, further comprising an inverter configured to invert the second signal component in the digital domain.

8. A controller according to any one of claims 3 to 7, the controller being configured to modify the received electronic signal by adjusting the first signal component and the second signal component to counteract the phase drift associated with the photonic device.

9. The controller according to any one of claims 1 to 8, wherein the controller is configured to: receiving an indication of a dynamic operating range of the photonic device; and The received electronic signal is modified based on the received indication of the dynamic operating range.

10. A controller according to claim 9 when dependent on any one of claims 3 to 8, the controller being configured to modify the received electronic signal by adjusting the first signal component and the second signal component so that their swing voltages span the dynamic operating range of the photonic device.

11. A controller according to any preceding claim, configured to amplify the received electronic signal.

12. A controller according to any one of the preceding claims, wherein: The received electronic signal is a digital electronic signal, and the controller is configured to: A digital-to-analog converter (DAC) is used to convert the received electronic signal into an analog electronic signal. 13 . The controller of claim 12 , the controller being configured to AC couple the analog electronic signal to adjust a DC bias of the analog electronic signal.

14. A controller according to any preceding claim, configured to modify the received electronic signal to compensate for a phase offset caused by a push-pull amplifier of the optical encoder.

15. A controller according to any preceding claim, configured to provide the modified electronic signal by: providing a first portion of the modified electronic signal, wherein The first portion moves rapidly; and A second portion of the modified electronic signal is provided, wherein the second portion moves slowly.

16. A controller according to any one of the preceding claims, wherein: The received feedback signal is also based on a modified electronic signal previously provided to the photonic device by the controller.

17. A controller according to any one of the preceding claims, wherein: The received electronic signal is a multi-bit signal.

18. A controller according to any one of the preceding claims, wherein: The received electronic signal is received via the following components: Interfaces; and At least one buffer, Wherein, the interface comprises a digital input and output board.

19. An electronic to optical encoder comprising: A controller according to any one of the preceding claims; as well as The photonic device as claimed in any one of the preceding claims, wherein the photonic device is a modulator configured to apply a first modulation element to an optical input signal based on the modified electronic signal; and The first modulation element is operable to encode the complex element onto the optical input signal to produce an encoded optical signal.

20. An optical computer or optical computer chip comprising an electronic to optical encoder or controller according to any preceding claim.

21. A method for execution by a controller of an optical encoder, the method comprising: receiving an electronic signal, wherein a value of the electronic signal is based on a complex element; receiving a feedback signal based on a phase drift associated with a photonic device of the optical encoder; modifying the received electronic signal based on the received feedback signal to generate a modified electronic signal; and The modified electronic signal is provided to modulate the photonic device.

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