Data writing method, storage control chip and flash memory device thereof

Abstract

The embodiment of the invention relates to the field of storage device application, and discloses a data writing method, a storage control chip and a flash memory device thereof.The data writing method comprises the steps that a writing command is obtained, a first programming instruction is sent to a flash memory medium based on the writing command, and data transmission operation is conducted; after each time of data transmission operation is completed, detecting whether a cutoff mark exists or not; and when the cutoff mark is detected, resending the first programming instruction to the flash memory medium and performing data transmission operation again, and when the cutoff mark is not detected after any data transmission operation is completed, sending a second programming instruction to the flash memory medium so as to write the data into the flash memory medium. According to the method and the device, the data cutoff can be processed in the writing process, so that the data can be correctly and completely written into the flash memory medium, data writing errors caused by the data cutoff are reduced, the integrity and the accuracy of data writing are improved, and the reliability and the stability of flash memory equipment are further improved.

Description

Technical Field

[0001] The present application relates to the application field of storage devices, and in particular to a data writing method, a storage control chip and a flash memory device thereof. Background Art

[0002] Flash memory devices, such as solid state drives (SSDs), are storage devices that use semiconductor flash memory (NAND Flash) as the medium. When writing data to a flash memory device, the storage control chip of the flash memory device needs to transfer the data to the flash memory medium. However, during high-speed data transmission, the storage control chip is prone to processing bottlenecks, resulting in data interruption.

[0003] Data interruption means that when the processing speed of the storage control chip of the flash memory device is lower than the data transmission speed, data transmission is temporarily interrupted until the storage control chip completes the processing of the current data and then continues to transmit data from the interrupted point. This will cause errors in the data writing process, affecting the integrity and accuracy of the data.

[0004] Currently, after a data interruption causes a data write error, the erroneous data is usually recovered. For example, for a flash memory device that uses Redundant Arrays of Inexpensive Disks (RAID) technology, when a data interruption occurs in a data logical unit (die), part of the erroneous data is recovered based on the redundancy characteristics of the RAID.

[0005] In the process of implementing this application, the inventors found that the prior art has at least the following problems: the prior solution does not provide a sufficient processing mechanism for data interruption during the writing process. Once data interruption occurs, the written data is prone to errors. In addition, for flash memory devices using RAID technology, when data interruption occurs in multiple dies, it exceeds the recovery capability of RAID technology, which can easily lead to permanent data loss. Summary of the invention

[0006] The embodiments of the present application provide a data writing method, a storage control chip and a flash memory device thereof, so as to reduce data writing errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of the flash memory device.

[0007] The embodiments of the present application provide the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a data writing method, the data writing method is applied to a flash memory device, the flash memory device includes a flash memory medium, and the data writing method includes:

[0009] Obtaining a write command, sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation;

[0010] After each data transmission operation is completed, detecting whether there is a flow interruption mark, wherein the flow interruption mark is used to indicate that a data flow interruption occurs during the data transmission operation;

[0011] When a disconnection mark is detected, the first programming instruction is resent to the flash memory medium and the data transmission operation is performed again, until the disconnection mark is not detected after any data transmission operation is completed, and the second programming instruction is sent to the flash memory medium to write the data into the flash memory medium;

[0012] The first programming instruction includes address information of the data, and the second programming instruction is used to instruct the flash memory medium to write the data.

[0013] In a second aspect, an embodiment of the present application provides a storage control chip, including:

[0014] at least one processor; and,

[0015] a memory communicatively connected to at least one processor; wherein,

[0016] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the data writing method according to the first aspect.

[0017] In a third aspect, an embodiment of the present application provides a flash memory device, including:

[0018] The storage control chip of the second aspect;

[0019] At least one flash memory medium is communicatively connected to the storage control chip.

[0020] In a fourth aspect, an embodiment of the present application further provides a non-volatile computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable a flash memory device to execute the data writing method of the first aspect.

[0021] The beneficial effect of the embodiments of the present application is as follows: different from the prior art, the embodiments of the present application provide a data writing method, which is applied to a flash memory device, and the flash memory device includes a flash memory medium. The data writing method includes: obtaining a write command, sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether there is a disconnection mark, wherein the disconnection mark is used to indicate that a data disconnection occurs during the data transmission operation; when the disconnection mark is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation, until the disconnection mark is not detected after any data transmission operation is completed, sending a second programming instruction to the flash memory medium to write data to the flash memory medium; wherein the first programming instruction includes address information of the data, and the second programming instruction is used to instruct the flash memory medium to write the data.

[0022] By resending the first programming instruction to the flash memory medium and re-performing the data transmission operation when a disconnection mark is detected, and sending the second programming instruction to the flash memory medium when the disconnection mark is not detected after any data transmission operation is completed to write data to the flash memory medium, the present application can handle data disconnection during the writing process so that the data can be correctly and completely written to the flash memory medium, thereby reducing data writing errors caused by data disconnection, improving the integrity and accuracy of data writing, and thereby improving the reliability and stability of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0024] Figure 1 It is a structural schematic diagram of a main control system of a flash memory device provided in an embodiment of the present application;

[0025] Figure 2 It is a flowchart of a data writing method provided in an embodiment of the present application;

[0026] Figure 3 is a schematic diagram of a data writing process provided by an embodiment of the present application;

[0027] Figure 4 yes Figure 3 A detailed flow chart of step S202 in FIG.

[0028] Figure 5 It is a detailed flowchart of the first data writing method provided in the embodiment of the present application;

[0029] Figure 6 is a detailed flowchart of a second data writing method provided in an embodiment of the present application;

[0030] Figure 7 This is a schematic diagram of a data writing process based on RAID technology provided in an embodiment of the present application;

[0031] Figure 8 is a detailed flowchart of a third data writing method provided in an embodiment of the present application;

[0032] Fig. 9 is a schematic diagram of a super block provided in an embodiment of the present application;

[0033] Fig.10 is a schematic diagram of the structure of a storage control chip provided in an embodiment of the present application;

[0034] Fig.11 It is a structural schematic diagram of a flash memory device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0036] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional module division is performed in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a sequence different from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in this application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0037] The technical solution of this application is described in detail below with reference to the accompanying drawings:

[0038] In an embodiment of the present application, the flash memory device includes a solid state drive or other storage device using flash memory as storage medium, and the storage control chip includes a controller of the solid state drive or other storage device using flash memory as storage medium.

[0039] See also Figure 1 , Figure 1 It is a structural schematic diagram of a main control system of a flash memory device provided in an embodiment of the present application;

[0040] It is understandable that the storage control chip of the flash memory device includes a main control system, and the main control system is used to connect the host and the flash memory array to realize data input and output (Input / Output, IO) processing.

[0041] like Figure 1 As shown, the main control system 100 includes:

[0042] The front end module 101 (FE) is used to obtain host commands to generate IO operations. The front end module 101 is also responsible for the communication protocol with the host 200, the parsing of host commands and solid state drive commands, and other operations.

[0043] The flash algorithm module 102, namely the flash translation layer (FTL), is used to map the IO operation to determine the flash array to be sent.

[0044] The flash algorithm module 102 sends an IO operation to a back-end module 103 (BE) of the storage control chip, so that the back-end module 103 receives the IO operation sent by the flash algorithm module 102 .

[0045] The back-end module 103 (Back End, BE) is connected to the flash algorithm module 102 and is used to receive the IO operation sent by the flash algorithm module 102 to control the hardware module 104 to perform read / write / erase operations on the flash array.

[0046] The hardware module 104 (HW Op Nand Mode) refers to a module for operating the Flash memory, which is connected to the back-end module 103 and controlled by the back-end module 103. It is used to operate the Flash memory, for example: according to the IO operation, the operation is performed on the corresponding flash memory array or flash memory medium, that is, the operation processing of data to the Flash memory is completed, and the operation includes a read operation, a write operation or an erase operation.

[0047] Among them, after the front-end module 101 obtains the host command, it processes it to generate IO operations, and sequentially passes through the flash algorithm module 102, the back-end module 103 and the hardware module 104 to operate the flash array. For example: when the host needs to read or write data, the host (Host) sends a host command to the flash device (Device), and the front-end module 101 (FE) of the flash device receives the host command, processes it and distributes it to the flash algorithm module 102 (FTL). After receiving it, the flash algorithm module 102 converts it from logic to physical, and then sends the NAND read or write operation request to the back-end module 103 (BE). After receiving it, the back-end module 103 sends the hardware instruction to the hardware module 104 to operate the NAND processing in parallel.

[0048] When writing data to a flash memory device, the storage control chip of the flash memory device needs to transfer data to the flash memory medium. With the development of flash memory technology, the transmission rate of the storage control chip is getting faster and faster, and the signal quality requirements are getting higher and higher. However, in the process of high-speed data transmission, the storage control chip is prone to processing bottlenecks, resulting in data interruption. Among them, high-speed transmission refers to data transmission rates greater than 1600 Mega Transfers per second (MT / s).

[0049] Specifically, data interruption means that when the processing speed of the storage control chip of the flash memory device is lower than the data transmission speed, data transmission is temporarily interrupted until the storage control chip completes the processing of the current data and then continues to transmit data from the interrupted point. This will cause errors in the data writing or reading process, affecting the integrity and accuracy of the data.

[0050] Existing solutions do not provide adequate processing mechanisms for data interruption. When data interruption occurs during a read operation, the read data will be identified as containing uncorrectable errors (UNC), and a reread operation is usually performed to obtain correct data in the next read.

[0051] However, there is often no excessive processing for data interruption during the writing process, which usually causes the written data to be wrong. The wrong data can only be recovered after the data interruption causes the data writing error. For example: for a flash memory device that uses Redundant Arrays of Inexpensive Disks (RAID) technology, when the data interruption occurs in a data logical unit (die), part of the wrong data is recovered based on the redundancy characteristics of RAID.

[0052] Specifically, RAID technology is a data storage virtualization technology that combines multiple disk drives into a logical unit, and provides data redundancy and improves performance by allocating data between disks. For flash memory devices that use RAID technology, the data logical unit is divided into a normal data logical unit and a check data logical unit (ParityDie), and the flash memory medium includes at least two normal data logical units and one check data logical unit. The normal data logical unit is used to store normal data, and the check data logical unit is used to store check data. When writing data, the flash memory device divides the data to be written into multiple normal data, and performs XOR processing on the multiple normal data to obtain check data, so that the flash memory device writes each normal data into the corresponding normal data logical unit, and writes the check data into the corresponding check data logical unit.

[0053] If a data interruption occurs in a certain common data logic unit during the writing process, resulting in a data writing error, the erroneous data can only be recovered after the writing operation is completed. Specifically, after the writing operation is completed, if an uncorrectable error occurs when reading the data in the common data logic unit, and no error occurs when reading the data in other common data logic units and the verification data logic unit, the data in the common data logic unit can be recovered by performing XOR processing on the data in the other common data logic units and the verification data logic unit.

[0054] For example, the verification data D is obtained by performing XOR processing on data A, data B, and data C. When an error occurs in the process of writing data A into the flash memory medium, data A can be obtained by performing XOR processing on verification data D, data B, and data C.

[0055] However, this method only allows data interruption to occur in one Die. When data interruption occurs in multiple Dies, it will exceed the recovery capability of RAID technology and easily lead to permanent data loss.

[0056] Based on this, an embodiment of the present application proposes a data writing method that can handle data interruption during the writing process, rather than recovering data after a write error caused by data interruption. The present application can reduce data writing errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of flash memory devices.

[0057] See also Figure 2 , Figure 2 It is a flowchart of a data writing method provided in an embodiment of the present application;

[0058] The data writing method is applied to a flash memory device, for example, to a storage control chip of a flash memory device, wherein the flash memory device includes a flash memory medium.

[0059] like Figure 2 As shown, the data writing method includes:

[0060] Step S201: obtaining a write command, sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation;

[0061] Wherein, the write command includes the data to be written and the corresponding data information, and the data information includes the logical address (Logical Block Address, LBA) of the data. The first programming instruction includes the first command and the address information of the data, and the first command is used to indicate that the flash memory medium is ready to write data, and the address information of the data includes the physical address (Physical Block Address, PBA) of the data, and the physical address is the physical location where the data is written in the flash memory medium. The data transfer operation is used to transfer data to the flash memory medium. In the embodiment of the present application, the first command is the 80h command, and the 80h command is used to indicate that the flash memory medium is ready to write data.

[0062] Specifically, the storage control chip receives a write command sent by the host, performs address conversion on the logical address of the data contained in the write command, determines the physical address corresponding to the data, and thereby sends a first programming instruction to the flash memory medium, and then performs a data transmission operation to transfer the data to the flash memory medium.

[0063] In an embodiment of the present application, the first programming instruction includes an 80h command and a physical address corresponding to the data. The storage control chip first sends an 80h command to the flash memory medium to indicate that the flash memory medium is ready to write data. The 80h command is followed by the physical address corresponding to the data to indicate that the flash memory medium writes the data to the physical address. Then, the storage control chip sends the data to the flash memory medium. At this time, the data is only loaded into the page buffer of the flash memory medium and is not written to the storage unit (Cell). Only after the subsequent second programming instruction is sent, the flash memory medium will perform the actual programming action and write the data in the page buffer to the specified physical location. Among them, the second programming instruction is used to instruct the flash memory medium to write data.

[0064] See also Figure 3 , Figure 3 is a schematic diagram of a data writing process provided by an embodiment of the present application;

[0065] like Figure 3As shown, the storage control chip first sends a first programming instruction to the flash memory medium, then performs a data transmission operation, and finally sends a second programming instruction to the flash memory medium, thereby triggering the flash memory medium to perform a programming action to complete the write operation. After the flash memory medium receives the second programming instruction, the storage unit in the flash memory medium will perform a charging process, change the charge state of the floating gate, and thus store data.

[0066] In the embodiment of the present application, the flash memory device further includes a front-end module, a flash memory algorithm module, a back-end module, and a hardware module. The connection method of the front-end module, the flash memory algorithm module, the back-end module, and the hardware module can be found in Figure 1 .

[0067] In step S201, the front-end module receives the write command sent by the host, distributes it to the flash algorithm module after processing; the flash algorithm module converts the logical address of the data contained in the write command, determines the physical address corresponding to the data, and then sends the write operation request to the back-end module; after receiving the write operation request, the back-end module executes the write operation and sends the first programming instruction to the flash memory medium; then the hardware module performs a data transmission operation to transfer the data to the flash memory medium.

[0068] Step S202: After each data transmission operation is completed, detecting whether there is a flow interruption mark;

[0069] The interruption mark is used to indicate that data interruption occurs during the data transmission operation. After each data transmission operation is completed, the storage control chip detects whether there is an interruption mark. Specifically, the back-end module in the storage control chip detects whether there is an interruption mark after each data transmission operation is completed.

[0070] See also Figure 4 , Figure 4 yes Figure 2 A detailed flow chart of step S202 in FIG.

[0071] In an embodiment of the present application, the flash memory device further includes a register. The register is used to record whether a data interruption occurs during a data transmission operation. When a data interruption occurs, the value of the register is set to a first value. When a data interruption does not occur, the value of the register is a second value. The register includes but is not limited to a hardware status register (HSR). The first value and the second value can be set by a person skilled in the art according to actual conditions, and are not limited in the embodiment of the present application. For example, the first value is 1 and the second value is 0.

[0072] like Figure 4As shown, step S202: after each data transmission operation is completed, detecting whether there is a flow interruption mark includes:

[0073] Step S221: performing data transmission operation;

[0074] Specifically, before each data transmission operation, the storage control chip initializes the register and sets the register value to a second value, for example, setting the register value to 0. Then, after each data transmission operation is completed, steps S222 to S227 are executed to detect whether there is a disconnection mark.

[0075] Step S222: determining whether data interruption occurs during the data transmission operation based on the hardware module;

[0076] Specifically, the hardware module determines whether data interruption occurs during the data transmission operation.

[0077] In some embodiments, the hardware module determines whether a data interruption occurs during a data transmission operation by timeout detection. For example, during a data transmission operation, if the hardware module does not receive data within a preset time or does not detect any data transmission activity, the hardware module determines that a data interruption occurs during the data transmission operation. Otherwise, the hardware module determines that no data interruption occurs during the data transmission operation. The preset time can be set by those skilled in the art according to actual conditions and is not limited in the embodiments of the present application.

[0078] In some embodiments, the hardware module determines whether data interruption occurs during the data transmission operation through error checking. For example, during the data transmission process, a cyclic redundancy check (CRC) is used to calculate the check result. If the check result calculated by the hardware module for the received data is inconsistent with the expectation, the hardware module determines that data interruption occurs during the data transmission operation. Otherwise, the hardware module determines that data interruption does not occur during the data transmission operation.

[0079] The cyclic redundancy check calculates the check result of the data by using a specific polynomial, and then appends the check result to the end of the data. When the data is transmitted, the receiver can use the same polynomial to recalculate the check result of the received data and compare it with the check result provided by the sender.

[0080] Furthermore, if data interruption occurs during the data transmission operation, the process proceeds to step S223; if data interruption does not occur during the data transmission operation, the process proceeds to step S224.

[0081] It is understandable that if no data interruption occurs during the data transmission operation, the value of the register remains the second value.

[0082] Step S223: setting the value of the register to the first value;

[0083] Specifically, if data interruption occurs during the data transmission operation, the hardware module sets the value of the register to a first value, for example, to 1.

[0084] Step S224: querying the value of the register based on the backend module;

[0085] Specifically, the back-end module determines whether there is a cut-off mark by querying the value of the register.

[0086] Step S225: determining whether the value is the first value;

[0087] Specifically, the backend module determines whether the value of the queried register is the first value. If the value of the register is the first value, the process proceeds to step S226; if the value of the register is not the first value, that is, the value of the register is the second value, the process proceeds to step S227.

[0088] Step S226: Determine whether a flow interruption mark is detected;

[0089] Specifically, when the value queried by the backend module is the first value, the backend module determines that the flow interruption mark is detected, for example, when the value of the register queried by the backend module is 1, it is determined that the flow interruption mark is detected. It can be understood that when the flow interruption mark is detected, it can be determined that data flow interruption has occurred during the data transmission operation.

[0090] Step S227: Determine whether the flow interruption mark is not detected.

[0091] Specifically, when the value queried by the back-end module is the second value, the back-end module determines that the disconnection mark is not detected. For example, when the value of the register queried by the back-end module is 0, it is determined that the disconnection mark is not detected. It can be understood that when the disconnection mark is not detected, it can be determined that no data disconnection occurs during the data transmission operation.

[0092] Step S203: When a disconnection mark is detected, the first programming instruction is resent to the flash memory medium and the data transmission operation is performed again, until the disconnection mark is not detected after any data transmission operation is completed, and then the second programming instruction is sent to the flash memory medium to write data to the flash memory medium.

[0093] The second programming instruction is used to instruct the flash memory medium to write data, that is, to instruct the storage unit in the flash memory medium to perform a charging process, change the charge state of the floating gate, and thus store data. In the embodiment of the present application, the second programming instruction is a 10h command, and the 10h command is used to instruct the flash memory medium to perform an actual programming action, that is, to trigger the storage unit of the flash memory medium to start the charging process, and to achieve data storage by changing the charge state of the floating gate in the storage unit, thereby ensuring that the data is successfully written into the storage unit and completing the write operation.

[0094] Specifically, after each data transmission operation, if the storage control chip detects a disconnection mark, the first programming instruction is resent to the flash memory medium and the data transmission operation is performed again, until the disconnection mark is not detected after any data transmission operation is completed, and then the second programming instruction is sent to the flash memory medium to write the data to the flash memory medium. After each data transmission operation, if the storage control chip does not detect the disconnection mark, the storage control chip sends the second programming instruction to the flash memory medium to write the data to the flash memory medium.

[0095] In some embodiments, for a flash memory device that does not have a RAID data protection function, that is, a flash memory device that does not use RAID technology, step S203 includes: after each data transmission operation is completed, if a disconnection mark is detected and the number of disconnections is less than or equal to a first threshold, the value of the number of disconnections is increased by one, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again.

[0096] The number of interruptions is the number of interruptions that occur during a single write operation. After the storage control chip sends the first programming instruction to the flash memory medium, if a data interruption occurs during the data transmission operation, the number of interruptions is incremented by one.

[0097] In some embodiments, for a flash memory device that does not have a RAID data protection function, the data writing method also includes: after each data transmission operation is completed, if a disconnection mark is detected and the number of disconnections is greater than a first threshold, it is determined that a disconnection error has occurred and the disconnection error is processed.

[0098] The first threshold is the maximum number of data interruptions allowed by the flash memory device, and the interruption error is a data write error caused by data interruption during the data transmission operation. The first threshold can be set by those skilled in the art according to actual conditions, and is not limited in the embodiment of the present application. Exemplarily, the first threshold is 3.

[0099] In some embodiments, for a flash memory device with RAID data protection function, that is, a flash memory device using RAID technology, step S203 includes: after each data transmission operation is completed, if a flow interruption mark is detected and the flow interruption number is less than or equal to a first threshold, the value of the flow interruption number is increased by one, the value of the non-flow interruption mark is set to a second value, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again. The non-flow interruption mark indicates that no data interruption occurs during the data transmission operation.

[0100] In some embodiments, for a flash memory device with RAID data protection function, step S203 further includes: after each data transmission operation is completed, the value of the number of transmissions is increased by one; after each data transmission operation is completed, if a flow interruption mark is detected, and the flow interruption number is greater than the first threshold, and the number of transmissions is an even number, the value of the flow interruption number is increased by one, the value of the non-flow interruption mark is set to a second value, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again. The number of transmissions is the number of completed data transmission operations during a single write operation.

[0101] In some embodiments, for a flash memory device with RAID data protection function, step S203 also includes: after each data transmission operation is completed, if no interruption mark is detected and the number of transmissions is an odd number, a second programming instruction is sent to the flash memory medium to write data to the flash memory medium.

[0102] In some embodiments, for a flash memory device with a RAID data protection function, the data writing method also includes: after each data transmission operation is completed, if the disconnection mark is not detected, the value of the non-disconnection mark is set to a first value; after each data transmission operation is completed, if the disconnection mark is not detected and the number of transmissions is an even number, the value of the number of disconnections is increased by one, the value of the non-disconnection mark is set to a second value, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again.

[0103] In some embodiments, for a flash memory device with RAID data protection function, the data writing method also includes: after each data transmission operation is completed, if a disconnection mark is detected, and the number of disconnections is greater than a first threshold, and the number of transmissions is an odd number, it is determined that a disconnection error has occurred, and the disconnection error is processed.

[0104] For details, please refer to Figure 5 , Figure 5 It is a detailed flowchart of the first data writing method provided in the embodiment of the present application;

[0105] In the embodiment of the present application, the first data writing method is applied to a flash memory device without RAID data protection function, that is, applied to a flash memory device that does not adopt RAID technology. The flash memory device also includes a first counter, which is used to record the number of interruptions.

[0106] like Figure 5 As shown, the detailed process of the first data writing method includes:

[0107] Step S501: Obtain a write command, send a first programming instruction to the flash memory medium based on the write command, and perform a data transmission operation;

[0108] Specifically, the front-end module receives the write command sent by the host, processes it and distributes it to the flash algorithm module; the flash algorithm module performs address conversion on the logical address of the data contained in the write command, determines the physical address corresponding to the data, and then sends the write operation request to the back-end module; after receiving the write operation request, the back-end module executes the write operation and sends a first programming instruction to the flash memory medium, the first programming instruction includes an 80h command and the physical address corresponding to the data; then the hardware module performs a data transmission operation to transfer the data to the flash memory medium.

[0109] Wherein, before performing the data transmission operation, the storage control chip initializes the first counter and the register, and clears the first counter and the register.

[0110] Step S502: Determine that a data transmission operation is completed;

[0111] Step S503: Detect whether there is a cut-off mark;

[0112] Specifically, after each data transmission operation is completed, the backend module detects whether there is a flow interruption mark. This step is the same as step S202 and will not be described in detail here.

[0113] Furthermore, if the flow cut-off mark is detected, the process proceeds to step S504; if the flow cut-off mark is not detected, the process proceeds to step S507.

[0114] Step S504: determining whether the number of interruptions is greater than a first threshold;

[0115] Specifically, the backend module determines whether the number of interruptions is greater than a first threshold, for example, whether the number of interruptions is greater than 3. The number of interruptions is the number of interruptions in a data transmission operation during a single write operation, that is, the number of interruptions in a data transmission operation in step S501 and step S506.

[0116] Furthermore, if the number of disconnections is greater than the first threshold, the process proceeds to step S505; if the number of disconnections is less than or equal to the first threshold, the process proceeds to step S506.

[0117] In an embodiment of the present application, by determining whether the number of interruptions is greater than a first threshold after detecting the interruption mark, the present application can take into account the situation where data interruptions occur during each data transmission operation. In this case, the present application will not perform data transmission in an infinite loop, but will subsequently report the interruption error to the flash algorithm module, which will process the interruption error, thereby improving the stability and reliability of data transmission, while reducing resource waste and performance degradation caused by frequent interruptions.

[0118] Step S505: determining that a flow interruption error occurs;

[0119] Specifically, after each data transmission operation is completed, if a disconnection mark is detected and the number of disconnections is greater than the first threshold, the back-end module determines that a disconnection error has occurred and reports the disconnection error to the flash algorithm module, which then handles the disconnection error.

[0120] In some embodiments, the backend module reports the interruption error to the flash algorithm module by reporting an error code.

[0121] In some embodiments, the flash algorithm module processes the interruption error by selecting a physical block from the remaining Dies and re-executing steps S501 to S507 to write data into the newly selected physical block.

[0122] In some embodiments, the flash algorithm module may process the interruption error in other ways, which is not limited in the embodiments of the present application.

[0123] Step S506: adding one to the value of the number of interruptions, resending the first programming instruction to the flash memory medium, and re-performing the data transmission operation;

[0124] Specifically, after each data transmission operation is completed, if the back-end module detects a disconnection mark and the number of disconnections is less than or equal to the first threshold, the back-end module increases the number of disconnections by one, resends the first programming instruction to the flash memory medium and re-performs the data transmission operation.

[0125] Further, after the backend module executes step S506, it returns to step S502 and repeatedly executes steps S503 to S506 until the backend module does not detect the interruption mark or the number of interruptions is greater than the first threshold.

[0126] Step S507: Send a second programming instruction to the flash memory medium to write data into the flash memory medium.

[0127] Specifically, after each data transmission operation is completed, if the back-end module does not detect the interruption mark, a second programming instruction is sent to the flash memory medium to write the data into the flash memory medium. After the flash memory medium receives the second programming instruction, the storage unit in the flash memory medium will perform a charging process to change the charge state of the floating gate to store data. At this time, the data is completely written into the flash memory medium, and this write operation is completed.

[0128] In an embodiment of the present application, after each data transmission operation is completed, if a disconnection mark is detected and the number of disconnections is less than or equal to a first threshold, the value of the number of disconnections is increased by one, the first programming instruction is resent to the flash memory medium and the data transmission operation is performed again, until the disconnection mark is not detected after any data transmission operation is completed, and the second programming instruction is sent to the flash memory medium to write data to the flash memory medium. Compared with the existing scheme that can only recover erroneous data after data disconnection causes a data writing error, the present application can process the data disconnection during the writing process, so that the data can be correctly and completely written to the flash memory medium, thereby reducing data writing errors caused by data disconnection, improving the integrity and accuracy of data writing, and thereby improving the reliability and stability of the flash memory device.

[0129] See also Figure 6 , Figure 6 is a detailed flowchart of a second data writing method provided in an embodiment of the present application;

[0130] In the embodiment of the present application, the second data writing method is applied to a flash memory device with a RAID data protection function, that is, applied to a flash memory device using RAID technology. The flash memory device also includes a second counter, which is used to record the number of transmissions, which is the number of completed data transmission operations during a single write operation.

[0131] For a flash memory device using RAID technology, the flash memory device also includes a cache space and a redundant buffer. The cache space includes at least two data buffers, and the flash memory medium includes at least two common data logic units and one check data logic unit, wherein each common data logic unit corresponds to a data buffer one by one, and the check data logic unit corresponds to the redundant buffer.

[0132] The data buffer is used to store the data to be written, and the redundant buffer is used to store the data after XOR processing in several data buffers, and the data after XOR processing includes verification data. The ordinary data logic unit is used to store the data written by the corresponding data buffer in the cache space (i.e., the data to be written), and the verification data logic unit is used to store the verification data written by the redundant data buffer.

[0133] The cache space includes but is not limited to memories such as Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), etc. The redundant buffer includes but is not limited to disk arrays such as Redundant Array of Independent Disks (RAID), etc.

[0134] like Figure 6 As shown, the detailed process of the second data writing method includes:

[0135] Step S601: Obtain a write command, send a first programming instruction to the flash memory medium based on the write command, and perform a data transmission operation;

[0136] Specifically, the front-end module receives a write command sent by the host, divides the data contained in the write command, obtains at least two data to be written, and stores each data to be written in the corresponding data buffer; the flash algorithm module determines the physical address corresponding to each data to be written, and then sends a write operation request to the back-end module; after receiving the write operation request, the back-end module executes the write operation and sends a first programming instruction to the flash memory medium, the first programming instruction includes an 80h command and the physical address of a normal data logic unit corresponding to each data to be written; then the hardware module performs a data transmission operation to transfer each data to be written from the corresponding data buffer to the flash memory medium.

[0137] Before performing the data transmission operation, the data writing method further includes: initializing the register; and setting the values ​​of the interruption times, the transmission times, and the non-interruption mark to a second value.

[0138] Specifically, the storage control chip initializes the first counter, the second counter, the register, and the non-disconnection flag, clears the first counter, the second counter, and the register to 0, and sets the value of the non-disconnection flag to a second value, for example, to 0. It can be understood that when the first counter and the second counter are cleared to 0, it means that the values ​​of the number of disconnections and the number of transmissions are set to 0.

[0139] The non-interruption mark indicates that no data interruption occurs during the data transmission operation. After a data transmission operation is completed, if the storage control chip does not detect the interruption mark, the value of the non-interruption mark is set to the first value, for example, to 1. At this time, the non-interruption mark indicates that no data interruption occurs during the data transmission operation. If a data interruption occurs during the data transmission operation, the value of the non-interruption mark is still the second value, that is, still 0.

[0140] See also Figure 7, Figure 7 This is a schematic diagram of a data writing process based on RAID technology provided in an embodiment of the present application;

[0141] like Figure 7 As shown, the cache space includes at least two data buffers, Figure 7 Taking the first data buffer, the second data buffer, and the third data buffer as examples, each data buffer is used to store data to be written. The flash memory medium includes at least two normal data logic units and one check data logic unit. Figure 7 Taking the first common data logic unit and the second common data logic unit as examples, each common data logic unit is used to store the data to be written in the corresponding data buffer in the cache space, and the check data logic unit is used to store the check data written in the redundant data buffer.

[0142] by Figure 7 For example, the hardware module performs XOR processing on the data to be written in the three data buffers to obtain verification data, and then saves the verification data to the redundant buffer. The hardware module writes the data to be written in the three data buffers into the corresponding ordinary data logic unit, and after obtaining the verification data, the hardware writes the verification data in the redundant buffer into the verification data logic unit in the flash medium.

[0143] In the embodiment of the present application, step S601: obtaining a write command, sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation, including steps S611-S614:

[0144] Step S611: Split the data contained in the write command to obtain at least two pieces of data to be written;

[0145] Specifically, the front-end module divides the data contained in the write command to obtain at least two data to be written.

[0146] Step S612: storing each piece of data to be written into the corresponding data buffer;

[0147] Specifically, the front-end module stores each piece of data to be written into the corresponding data buffer one by one.

[0148] Step S613: Sending a first programming instruction to the flash memory medium;

[0149] Specifically, the flash algorithm module determines the physical address corresponding to each data to be written, and then sends a write operation request to the back-end module. After receiving the write operation request sent by the flash algorithm module, the back-end module executes the write operation and sends a first programming instruction to the flash memory medium. The first programming instruction includes an 80h command and the physical address of each ordinary data logical unit corresponding to each data to be written. Each data to be written corresponds to a different ordinary data logical unit.

[0150] Step S614: performing a data transmission operation to transmit each to-be-written data from the corresponding data buffer to the flash memory medium.

[0151] Specifically, the hardware module performs a data transmission operation to transmit each piece of data to be written from a corresponding data buffer to the flash memory medium.

[0152] When performing the data transmission operation, the method further includes:

[0153] When a data transmission operation is performed on the data to be written in the first data buffer, the data to be written is XOR-processed to obtain a first XOR result, and the first XOR result is stored in a redundant buffer; when a data transmission operation is performed on the data to be written in the remaining data buffers, the currently transmitted data to be written and the first XOR result currently stored in the redundant buffer are XOR-processed to obtain a second XOR result, and the second XOR result is used to update the first XOR result stored in the redundant buffer.

[0154] Specifically, the first data buffer is the first data buffer for data transmission. Before transmitting the to-be-written data in the first data buffer to the flash memory medium, the flash memory device controls the redundant buffer to be cleared.

[0155] In an embodiment of the present application, the hardware module performs XOR processing on the data to be written in each data buffer in series. When the data to be written in the first data buffer is subjected to data transmission operation, the hardware module performs XOR processing on the data to be written, obtains a first XOR result, and stores the first XOR result in the redundant buffer. When the data to be written in the remaining data buffers is subjected to data transmission operation, the hardware module performs XOR processing on the data to be written currently transmitted and the first XOR result currently stored in the redundant buffer, obtains a second XOR result, and updates the first XOR result stored in the redundant buffer with the second XOR result, that is, assigns the second XOR result to the first XOR result, thereby realizing the update of the original first XOR result in the redundant buffer. Until the data to be written in the last data buffer for data transmission is subjected to XOR processing with the first XOR result currently stored in the redundant buffer, obtains the second XOR result, and updates the first XOR result stored in the redundant buffer with the second XOR result, stops performing XOR processing, at this time, the first XOR result stored in the redundant buffer is the verification data.

[0156] Among them, the remaining data buffers refer to data buffers other than the first data buffer, the first XOR result is the XOR result stored in the redundant buffer, the first XOR result will be updated by the second XOR result, and the second XOR result is the XOR result obtained by XORing the currently transmitted data to be written with the first XOR result currently stored in the redundant buffer.

[0157] Among them, the XOR processing includes XOR operation or modulo-2 addition. XOR operation is a binary operation, and its result is 1 only when the two input bits are different, otherwise it is 0. Modulo-2 addition is a binary operation, which is equivalent to the "XOR" operation. Its operation rule is to add two sequences bit by bit modulo-2, that is, add the corresponding bits in the two sequences, without carry, the same is 0, and different is 1. That is, 1 plus 1 equals 0, 0 plus 0 equals 0, 1 plus 0 equals 1, and 0 plus 1 equals 1. Since the speed of XOR processing is very fast, the hardware module can ensure that the XOR processing of the data to be written in all data buffers is completed before reading the check data in the redundant buffer.

[0158] Step S602: Determine that a data transmission operation is completed;

[0159] Specifically, after each data transmission operation is completed, the backend module increases the value of the number of transmissions by one to indicate that one data transmission is completed.

[0160] Step S603: Detect whether there is a cut-off mark;

[0161] Specifically, after each data transmission operation is completed, the backend module detects whether there is a flow interruption mark. This step is the same as step S202 and will not be described in detail here.

[0162] Furthermore, if the flow cut-off mark is not detected, the process proceeds to step S604; if the flow cut-off mark is detected, the process proceeds to step S605.

[0163] Step S604: setting the value of the uninterrupted flow flag to a first value;

[0164] Specifically, if the interruption mark is not detected, the backend module sets the value of the non-interruption mark to a first value, for example, to 1.

[0165] Step S605: determining whether the number of interruptions is greater than a first threshold;

[0166] Specifically, the backend module determines whether the number of interruptions is greater than a first threshold, for example, determining whether the number of interruptions in data flow during data transmission operations in step S601 and step S607 is greater than 3.

[0167] Further, if the number of disconnections is greater than the first threshold, the process proceeds to step S606; if the number of disconnections is less than or equal to the first threshold, the process proceeds to step S607.

[0168] In an embodiment of the present application, by determining whether the number of data interruptions is greater than a first threshold after detecting a data interruption mark, the present application can take into account extreme situations where data interruptions occur frequently, for example, data interruptions occur during each data transmission operation. In this case, the present application will not perform data transmission in an infinite loop, but will subsequently report the interruption error to the flash algorithm module, which will process the interruption error, thereby improving the stability and reliability of data transmission and reducing resource waste and performance degradation caused by frequent interruptions.

[0169] Step S606: Determine whether the number of transmissions is an odd number;

[0170] Specifically, if a flow interruption mark is detected and the number of flow interruptions is greater than a first threshold, the back-end module determines whether the number of transmissions is an odd number.

[0171] Alternatively, if the interruption mark is not detected, after setting the value of the non-interruption mark to the first value, the back-end module determines whether the number of transmissions is an odd number.

[0172] In an embodiment of the present application, after each data transmission operation is completed, the value of the number of transmissions is increased by one, and before each data transmission operation in step S601 and step S607, each data to be written is XOR-processed, so that when the number of transmissions is an odd number, it means that the transmitted data to be written has been subjected to a RAID XOR operation, that is, the XOR result obtained by the XOR processing has not been offset. At this time, the data to be written can be written to the ordinary data logic unit of the flash memory medium, and when the number of transmissions is an even number, it means that the XOR result obtained by the XOR processing is offset. At this time, it is necessary to re-XOR-process each data to be written, and then re-perform the data transmission operation.

[0173] Further, if the number of transmissions is an odd number, the process proceeds to step S608; if the number of transmissions is not an odd number, that is, the number of transmissions is an even number, the process proceeds to step S607.

[0174] Step S607: increasing the value of the interruption times by one, setting the value of the non-interruption flag to a second value, resending the first programming instruction to the flash memory medium, and re-performing the data transmission operation;

[0175] Specifically, if a disconnection mark is detected and the number of disconnections is less than or equal to the first threshold, the back-end module increases the number of disconnections by one, sets the value of the non-disconnection mark to the second value, resends the first programming instruction to the flash memory medium, and re-performs the data transmission operation.

[0176] For example: If a disconnection mark is detected and the number of disconnections is less than or equal to 3, the back-end module will increase the value of the number of disconnections by one, set the value of the non-disconnection mark to 0, resend the first programming instruction to the flash memory medium, and retransmit each data to be written from the corresponding data buffer to the flash memory medium.

[0177] Alternatively, if the number of transmissions is an even number, the backend module increases the value of the number of interruptions by one, sets the value of the non-interruption mark to a second value, resends the first programming instruction to the flash memory medium, and performs the data transmission operation again.

[0178] For example: if the number of transmissions is an even number, the back-end module will increase the value of the number of interruptions by one, set the value of the non-interruption mark to 0, resend the first programming instruction to the flash memory medium and retransmit each data to be written from the corresponding data buffer to the flash memory medium.

[0179] The first programming instruction includes an 80h command and a physical address of a common data logic unit corresponding to each data to be written. Each time the data transmission operation is repeated, the data writing method further includes: performing an XOR process on the currently transmitted data to be written and the first XOR result currently stored in the redundant buffer to obtain a second XOR result, and using the second XOR result to update the first XOR result stored in the redundant buffer.

[0180] Step S608: Determine whether the value of the uninterrupted flow flag is a first value;

[0181] Specifically, the backend module determines whether the value of the flow not interrupted flag is a first value, for example, determines whether the value of the flow not interrupted flag is 1.

[0182] Further, if the value of the uninterrupted flow mark is the first value, the process proceeds to step S609; if the value of the uninterrupted flow mark is not the first value, that is, the value of the uninterrupted flow mark is the second value, the process proceeds to step S610.

[0183] Step S609: Send a second programming instruction to the flash memory medium to write data into the flash memory medium.

[0184] Specifically, if the number of transmissions is an odd number, and the value of the unbroken flow mark is the first value, the back-end module sends a second programming instruction to the flash memory medium to write each data to be written into the corresponding normal data logic unit. The second programming instruction is a 10h command, and after receiving the second programming instruction, the flash memory medium writes each data to be written into the corresponding normal data logic unit.

[0185] In an embodiment of the present application, the data writing method further includes: after the data to be written is written into the corresponding normal data logic unit, writing the first XOR result stored in the redundant buffer into the verification data logic unit.

[0186] Specifically, after the data to be written is written into the corresponding ordinary data logic unit, the back-end module sends a third programming instruction to the flash memory medium, and the third programming instruction includes an 80h command and a physical address of the verification data logic unit; then the hardware module performs a data transmission operation, and transmits the first XOR result from the redundant buffer to the flash memory medium; then the back-end module sends a second programming instruction to the flash memory medium, and the second programming instruction is a 10h command; after receiving the second programming instruction, the flash memory medium writes the first XOR result into the verification data logic unit, and at this point, the write operation is completed.

[0187] It is understandable that in step S601 and step S607, the data transmission operation only transmits each data to be written, and does not transmit the first XOR result stored in the redundant buffer. When the back-end module sends the second programming instruction to the flash memory medium, the first XOR result stored in the redundant buffer is the verification data that needs to be written to the flash memory medium.

[0188] Step S610: Determine whether a flow interruption error occurs.

[0189] Specifically, if the number of transmissions is an odd number and the value of the non-interrupted flow mark is the second value, the backend module determines that an interrupted flow error has occurred and reports the interrupted flow error to the flash algorithm module, so that the flash algorithm module performs a rollback operation or a garbage collection operation.

[0190] In some embodiments, the backend module reports the interruption error to the flash algorithm module by reporting an error code.

[0191] In some embodiments, the flash algorithm module performs a rollback operation, including: the flash algorithm module sends a rollback command to the backend module, and after receiving the rollback command, the backend module instructs the hardware module to perform XOR processing on each data to be written and the first XOR result currently stored in the redundant buffer to obtain a second XOR result, and uses the second XOR result to update the first XOR result stored in the redundant buffer, thereby offsetting the result of the XOR processing. The rollback command is used to instruct the backend module to perform XOR processing again.

[0192] In some embodiments, the flash algorithm module performs garbage collection operations, including: performing garbage collection on the stripe where the data to be written is located, and moving each piece of data to be written to other free physical blocks.

[0193] Among them, stripe is a data organization method. When data is divided into small blocks, these small blocks are written to different physical locations of the flash media to form a stripe. The stripe where the data to be written is located includes each data to be written. Garbage Collection (GC) refers to moving data to new physical blocks to free up the original storage space.

[0194] In some embodiments, the flash algorithm module selects the remaining Dies to re-execute step S601 to step S610. The flash algorithm module may use other methods to process the interruption error, which is not limited in the embodiments of the present application.

[0195] In an embodiment of the present application, after each data transmission operation is completed, when a flow interruption mark is detected, when the flow interruption number is less than or equal to the first threshold, or when the flow interruption number is greater than the first threshold and the number of transmissions is an even number, the first programming instruction is resent to the flash memory medium, and the data transmission operation is re-performed, until the flow interruption mark is not detected after any data transmission operation is completed, and the number of transmissions is an odd number, a second programming instruction is sent to the flash memory medium to write data to the flash memory medium. On the one hand, compared with the existing solution that can only recover data after a write error caused by data flow interruption, the present application can handle data flow interruption during the writing process through a reasonable flow interruption detection and retry mechanism, instead of recovering data after a write error caused by data flow interruption, which can improve the integrity and reliability of data during the writing process;

[0196] On the other hand, compared with the existing solutions for flash memory devices using RAID technology, when data interruption occurs in multiple Dies, it exceeds the recovery capability of the RAID technology, which can easily lead to permanent data loss. For flash memory devices using RAID technology, when data interruption occurs in one or more Dies, the present application can handle the data interruption by re-performing the data transmission operation during the writing process, which can reduce data writing errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of the flash memory device.

[0197] In some embodiments, a flash memory device using RAID technology still has a verification function and can recover data damaged due to interruption of data flow. For example, when reading data in a normal data logical unit, if an uncorrectable error occurs, the erroneous data in the normal data logical unit can be recovered by performing XOR processing on the data in other normal data logical units and the verification data in the verification data logical unit.

[0198] See also Figure 8 , Figure 8 is a detailed flowchart of a third data writing method provided in an embodiment of the present application;

[0199] In the embodiment of the present application, the third data writing method is applied to any flash memory device, that is, the third data writing method can be applied to a flash memory device without a RAID data protection function, and can also be applied to a flash memory device with a RAID data protection function.

[0200] like Figure 8 As shown, the detailed process of the third data writing method includes:

[0201] Step S801: Obtain a write command, send a first programming instruction to the flash memory medium based on the write command, and perform a data transmission operation;

[0202] Specifically, for a flash memory device without RAID data protection function, this step is the same as step S501 and will not be repeated here; for a flash memory device with RAID data protection function, this step is the same as step S601 and will not be repeated here.

[0203] Step S802: Determine that the data transmission operation is completed;

[0204] Step S803: sending a second programming instruction to the flash memory medium to write data into the flash memory medium;

[0205] Specifically, after the back-end module sends the first programming instruction to the flash memory medium, the hardware module performs a data transmission operation, and then the back-end module sends the second programming instruction to the flash memory medium to write the data into the flash memory medium. The first programming instruction includes an 80h command and a physical address corresponding to the data, and the second programming instruction is a 10h command.

[0206] Step S804: reading the data;

[0207] Specifically, after the above-mentioned write operation is completed, the back-end module sends a read command to the flash memory medium to read the data just written into the flash memory medium.

[0208] Furthermore, after reading the data, the back-end module performs error checking based on the error checking code to obtain the number of error bits. Among them, the error correction code (Error-Correcting Code, ECC) is a technology used to detect and correct errors in data transmission or storage, and the number of error bits is the number of error bits in the data read after a data reading operation is completed. Exemplarily, the number of error bits is the number of error bits in the data read after a 4KB data reading operation is completed.

[0209] When data is written to the flash memory, the ECC algorithm generates a check code and stores this check code in the Out-Of-Band (OOB) area or a specific ECC storage area. The read operation not only reads the data, but also reads the corresponding error check code. After reading the data, the error check code is recalculated for the read data using the same ECC algorithm to obtain a new error check code. By analyzing the bits of the error check code, the number of error bits can be determined. For example: When the error correction code is a Hamming code, the Hamming weight can be determined by calculating the difference between the received error check code and the recalculated error check code. The Hamming weight refers to the number of error bits.

[0210] Step S805: Determine whether an uncorrectable error occurs or the number of error bits is greater than a second threshold;

[0211] Specifically, the back-end module determines whether an uncorrectable error occurs based on the error checking code: the newly calculated error checking code is compared with the received error checking code. If the two error checking codes are the same, it means that the data is not damaged and it is determined that no uncorrectable error occurs; if the two error checking codes are different, according to the rules of the ECC algorithm, it can be determined whether the nature of the error is a correctable error or an uncorrectable error.

[0212] A correctable error is an error pattern that can be corrected by the ECC algorithm, such as a single bit error. An uncorrectable error is an error pattern that exceeds the ECC algorithm's ability to correct, such as multiple bit errors.

[0213] The second threshold value may be set by a person skilled in the art according to the decoder actually used, and is not limited in the embodiments of the present application. For example, when the amount of data read by a read operation is 4KB, the second threshold value is 200 bits.

[0214] Furthermore, if an uncorrectable error occurs during the reading process, or the number of error bits is greater than the second threshold, the process proceeds to step S806; if no uncorrectable error occurs during the reading process, and the number of error bits is less than or equal to the second threshold, the process proceeds to step S807.

[0215] Step S806: Determine that the current write operation fails;

[0216] Specifically, if an uncorrectable error occurs during the reading process, or the number of error bits is greater than the second threshold, the backend module determines that the write operation has failed. The backend module reports the failure of the write operation to the flash algorithm module, which then processes the write operation.

[0217] In some embodiments, when the flash memory device is a flash memory device with a RAID data protection function, the flash memory device also includes a cache space and a redundant buffer, the cache space includes at least two data buffers, the flash memory medium includes at least two normal data logical units and one verification data logical unit, each normal data logical unit corresponds to a data buffer one by one, and the verification data logical unit corresponds to the redundant buffer.

[0218] In step S801, the front-end module divides the data contained in the write command to obtain at least two data to be written, and stores each data to be written into the corresponding data buffer; the flash memory algorithm module sends a first programming instruction to the flash memory medium; the hardware module performs a data transmission operation to transfer each data to be written from the corresponding data buffer to the flash memory medium.

[0219] When performing data transmission operations on the data to be written in the first data buffer, the hardware module performs XOR processing on the data to be written, and stores the first XOR result obtained by the processing in the redundant buffer; when performing data transmission operations on the data to be written in the remaining data buffers, the hardware module performs XOR processing on the currently transmitted data to be written and the first XOR result currently stored in the redundant buffer, and updates the first XOR result stored in the redundant buffer with the second XOR result obtained by the processing; until the XOR processing is completed on the data to be written in the last data buffer for data transmission, and the first XOR result currently stored in the redundant buffer is completed, and the first XOR result stored in the redundant buffer is updated.

[0220] The data writing method further includes: after determining that the write operation has failed, performing XOR processing on the data and the first XOR result stored in the redundant buffer to obtain a third XOR result, and using the third XOR result to update the first XOR result stored in the redundant buffer. The data includes first data to be written, and the first data to be written is the data to be written in the data buffer corresponding to a certain common data logic unit that has an error during the read operation.

[0221] Specifically, the flash algorithm module sends a rollback processing command to the back-end module. After receiving the rollback processing command, the back-end module instructs the hardware module to perform an XOR process on the first XOR result stored in the redundant buffer and the first data to be written, obtain a third XOR result, and assign the third XOR result to the first XOR result to update the first XOR result stored in the redundant buffer. The rollback processing command is used to instruct the back-end module to perform an XOR process on the first XOR result and the first data to be written, and the third XOR result is the XOR result obtained by performing an XOR process on the first XOR result stored in the redundant buffer and the first data to be written in the third data writing method.

[0222] By performing XOR processing on the first XOR result stored in the redundant buffer and the first data to be written, the XOR operation (or modulo-2 addition) performed on the first data to be written in the redundant buffer can be offset, so that the redundant buffer can check errors in other ordinary data logical units in the stripe. In this way, the stripe where the first data to be written is located still has a verification function.

[0223] In some embodiments, the data writing method further includes: re-performing a write operation to write the data into the flash memory medium, wherein the storage locations of the data in the flash memory medium are different in the two write operations.

[0224] For example, the flash memory device writes the first data to be written into other idle normal data logical units or other idle physical blocks in the same normal data logical unit.

[0225] Step S807: Determine that the write operation is completed;

[0226] If no uncorrectable error occurs during the reading process and the number of error bits is less than or equal to the second threshold, the back-end module determines that the write operation is completed.

[0227] In an embodiment of the present application, after sending a first programming instruction to the flash memory medium and performing a data transmission operation, a second programming instruction is sent to the flash memory medium to write data to the flash memory medium, and then the data is read from the flash memory medium. When no uncorrectable error occurs during the reading process and the number of error bits is less than or equal to the second threshold, it is determined that the write operation is completed. When an uncorrectable error occurs during the reading process, or the number of error bits is greater than the second threshold, it is determined that the write operation has failed. The present application can immediately determine whether a data write error caused by data interruption occurs after completing the write operation, so as to immediately handle the write operation when it fails.

[0228] In the embodiments of the present application, the above three data writing methods can be applied to flash memory devices without the concept of super block management, such as flash disks or flash memory cards (T cards), and can also be applied to flash memory devices with the concept of super block management.

[0229] See also Fig. 9 , Fig. 9 is a schematic diagram of a super block provided in an embodiment of the present application;

[0230] like Fig. 9 As shown, a super block is composed of multiple physical blocks, each of which is in a different data logical unit (Die). Each physical block is composed of multiple physical pages, for example: physical block A is composed of physical page 0, physical page 1, ..., physical page P, ..., physical page M.

[0231] When performing a write operation, data can be written to these data logical units at the same time, and when performing a read operation, data can be read from different data logical units at the same time, thereby accelerating the read and write performance.

[0232] In the embodiment of the present application, the physical blocks contained in each super block must be in different data logical units, and the physical block numbers can be different. For example, physical block 2 in data logical unit 0, physical block 3 in data logical unit 1, and physical block 4 in data logical unit 2 can all belong to the same super block.

[0233] For flash memory devices using RAID technology, Fig. 9 The data logic unit n in may be a verification data logic unit, and only one data logic unit is allowed to have an uncorrectable error during a read operation.

[0234] For a flash memory device with a super block management concept, when the back-end module determines in step S806 that the write operation fails, the flash memory device can write the first data to be written into other free super blocks or other free super pages in the same super block.

[0235] In an embodiment of the present application, a data writing method is provided, which is applied to a flash memory device, and the flash memory device includes a flash memory medium. The data writing method includes: obtaining a write command, sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether there is a disconnection mark, wherein the disconnection mark is used to indicate that a data disconnection occurs during the data transmission operation; when the disconnection mark is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation, until the disconnection mark is not detected after any data transmission operation is completed, sending a second programming instruction to the flash memory medium to write data to the flash memory medium; wherein the first programming instruction includes address information of the data, and the second programming instruction is used to instruct the flash memory medium to write the data.

[0236] By resending the first programming instruction to the flash memory medium and re-performing the data transmission operation when a disconnection mark is detected, and sending the second programming instruction to the flash memory medium when the disconnection mark is not detected after any data transmission operation is completed to write data to the flash memory medium, the present application can reduce data writing errors caused by data disconnection, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of the flash memory device.

[0237] See also Fig.10 , Fig.10 is a schematic diagram of the structure of a storage control chip provided in an embodiment of the present application;

[0238] like Fig.10 As shown, the storage control chip 1000 includes one or more processors 1001 and a memory 1002. Fig.10 A processor 1001 is taken as an example.

[0239] The processor 1001 and the memory 1002 may be connected via a bus or other means. Fig.10 The example of connecting through bus is taken in the following.

[0240] The processor 1001 is used to provide computing and control capabilities to control the flash memory device 1100 to perform corresponding tasks, for example, to control the flash memory device 1100 to perform a data writing method in any of the above method embodiments, the data writing method is applied to a flash memory device, the flash memory device includes a flash memory medium, and the data writing method includes: obtaining a write command, sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether there is a disconnection mark, wherein the disconnection mark is used to indicate that a data disconnection occurs during the data transmission operation; when the disconnection mark is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation, until the disconnection mark is not detected after any data transmission operation is completed, sending a second programming instruction to the flash memory medium to write data to the flash memory medium; wherein the first programming instruction includes address information of the data, and the second programming instruction is used to instruct the flash memory medium to write data.

[0241] By resending the first programming instruction to the flash memory medium and re-performing the data transmission operation when a disconnection mark is detected, and sending the second programming instruction to the flash memory medium when the disconnection mark is not detected after any data transmission operation is completed to write data to the flash memory medium, the present application can reduce data writing errors caused by data disconnection, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of the flash memory device.

[0242] The processor 1001 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0243] The memory 1002, as a non-transient computer-readable storage medium, can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the data writing method in the embodiment of the present application. The processor 1001 can implement the data writing method in any of the above method embodiments by running the non-transient software programs, instructions and modules stored in the memory 1002. Specifically, the memory 1002 may include a volatile memory (Volatile Memory, VM), such as a random access memory (Random Access Memory, RAM); the memory 1002 may also include a non-volatile memory (Non-Volatile Memory, NVM), such as a read-only memory (Read-Only Memory, ROM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, HDD) or a solid-state drive (Solid-State Drive, SSD) or other non-transient solid-state storage devices; the memory 1002 may also include a combination of the above-mentioned types of memories.

[0244] The memory 1002 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 1002 may optionally include a memory remotely arranged relative to the processor 1001, and these remote memories may be connected to the processor 1001 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0245] One or more modules are stored in the memory 1002, and when executed by one or more processors 1001, the data writing method in any of the above method embodiments is executed, for example, the data writing method described above is executed. Figure 2 The steps shown.

[0246] See also Fig.11 , Fig.11 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0247] like Fig.11 As shown, the flash memory device 1100 includes a storage control chip 1000 and at least one flash memory medium 1101 . Fig.11 Taking a flash memory medium 1101 as an example, the storage control chip 1000 and the flash memory medium 1101 are communicatively connected.

[0248] The storage control chip 1000 is used to execute the data writing method in any of the above embodiments, and the data writing method includes: obtaining a write command, sending a first programming instruction to a flash memory medium based on the write command and performing a data transmission operation; after each data transmission operation is completed, detecting whether there is a disconnection mark, wherein the disconnection mark is used to indicate that a data disconnection occurs during the data transmission operation; when the disconnection mark is detected, resending the first programming instruction to the flash memory medium and re-performing the data transmission operation, until the disconnection mark is not detected after any data transmission operation is completed, sending a second programming instruction to the flash memory medium to write data to the flash memory medium; wherein the first programming instruction includes address information of the data, and the second programming instruction is used to instruct the flash memory medium to write data.

[0249] At least one flash memory medium 1101 is communicatively connected to the storage control chip 1000 and is used to store data.

[0250] The flash memory device includes a storage control chip and at least one flash memory medium, the storage control chip is used to execute the data writing method in any of the above embodiments, and the flash memory medium is used to store data. The present application can reduce data writing errors caused by data interruption, improve the integrity and accuracy of data writing, and thus improve the reliability and stability of the flash memory device.

[0251] An embodiment of the present application also provides a non-volatile computer storage medium, which stores computer executable instructions, and the computer executable instructions are executed by one or more processors. For example, the one or more processors can execute the data writing method in any of the above method embodiments, for example, execute the data writing method in any of the above method embodiments, for example, execute the various steps described above.

[0252] The above-described device or equipment embodiments are merely illustrative, wherein the unit modules described as separate components may or may not be physically separated, and the components displayed as module units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0253] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution can be essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute various embodiments or certain parts of the embodiments.

[0254] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data writing method, characterized in that: Applied to a flash memory device, the flash memory device includes a flash memory medium, and the method includes: Obtaining a write command, sending a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation; After each data transmission operation is completed, detecting whether there is a flow interruption mark, wherein the flow interruption mark is used to indicate that a data flow interruption occurs during the data transmission operation; When the disconnection mark is detected, the first programming instruction is resent to the flash memory medium and the data transmission operation is performed again, until the disconnection mark is not detected after any data transmission operation is completed, and the second programming instruction is sent to the flash memory medium to write data to the flash memory medium; The first programming instruction includes address information of the data, and the second programming instruction is used to instruct the flash memory medium to write the data.

2. The method according to claim 1, characterized in that The data transmission operation is used to transfer the data to the flash memory medium, and the flash memory device also includes a backend module, a hardware module and a register; The detecting whether there is a flow interruption mark comprises: Based on the hardware module, determining whether data interruption occurs during the data transmission operation; If data interruption occurs during the data transmission operation, setting the value of the register to a first value; Based on the backend module, query the value of the register; When the value queried by the backend module is the first value, determining that the interruption mark is detected; When the value queried by the backend module is the second value, it is determined that the interruption mark is not detected.

3. The method according to claim 1, characterized in that The method further comprises: After each data transmission operation is completed, if the interruption mark is detected and the number of interruptions is less than or equal to the first threshold, the value of the number of interruptions is increased by one, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again; After each data transmission operation is completed, if the interruption mark is detected and the number of interruptions is greater than a first threshold, it is determined that an interruption error occurs, and the interruption error is processed; After each data transmission operation is completed, if the interruption mark is not detected, a second programming instruction is sent to the flash memory medium to write data into the flash memory medium.

4. The method according to claim 1, characterized in that: The flash memory device also includes a cache space and a redundant buffer, wherein the cache space includes at least two data buffers; The sending of a first programming instruction to the flash memory medium based on the write command and performing a data transmission operation includes: Splitting the data contained in the write command to obtain at least two pieces of data to be written; Store each piece of data to be written into the corresponding data buffer one by one; Sending a first programming instruction to the flash memory medium; Performing a data transmission operation to transmit each to-be-written data from a corresponding data buffer to the flash memory medium; The method further comprises: When performing a data transmission operation on the data to be written in the first data buffer, performing an XOR process on the data to be written to obtain a first XOR result, and storing the first XOR result in the redundant buffer, wherein the first data buffer is the first data buffer for performing data transmission; When performing data transmission operations on the data to be written in the remaining data buffers, the currently transmitted data to be written and the first XOR result currently stored in the redundant buffer are XORed to obtain a second XOR result, and the second XOR result is used to update the first XOR result stored in the redundant buffer.

5. The method according to claim 4, characterized in that The method further comprises: The values ​​of the number of interruptions, the number of transmissions, and the non-interruption mark are set to the second value; After each data transmission operation is completed, the value of the number of transmissions is increased by one, and a check is performed to see if there is a flow interruption mark; If the interruption mark is detected and the number of interruptions is less than or equal to the first threshold, the value of the number of interruptions is increased by one, the value of the non-interruption mark is set to a second value, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again; If the interruption mark is detected and the number of interruptions is greater than a first threshold, determining whether the number of transmissions is an odd number; If the interruption mark is not detected, the value of the non-interruption mark is set to a first value, and it is determined whether the number of transmissions is an odd number.

6. The method according to claim 5, characterized in that The method further comprises: If the number of transmissions is an odd number, and the value of the non-interrupted flow mark is a second value, it is determined that an interrupted flow error occurs, and a rollback operation or a garbage collection operation is performed; If the number of transmissions is an even number, the value of the interruption number is increased by one, the value of the non-interruption flag is set to a second value, the first programming instruction is resent to the flash memory medium, and the data transmission operation is performed again; Each time a data transmission operation is repeated, an XOR process is performed on the currently transmitted data to be written and the first XOR result currently stored in the redundant buffer to obtain a second XOR result, and the second XOR result is used to update the first XOR result stored in the redundant buffer.

7. The method according to claim 5, characterized in that The flash memory medium comprises at least two common data logic units and one check data logic unit, wherein each of the common data logic units corresponds to one of the data buffers, and the check data logic unit corresponds to the redundant buffer; The method further comprises: If the number of transmissions is an odd number, and the value of the uninterrupted flow mark is a first value, sending a second programming instruction to the flash memory medium to write each data to be written into a corresponding common data logic unit; After the data to be written is written into the corresponding normal data logic unit, the first XOR result stored in the redundant buffer is written into the verification data logic unit.

8. The method according to claim 1 or 4, characterized in that: The method further comprises: After sending a first programming instruction to the flash memory medium and performing a data transmission operation, sending a second programming instruction to the flash memory medium to write data into the flash memory medium; Reading the data from the flash memory medium, and performing error checking based on an error checking code to obtain the number of error bits; If no uncorrectable error occurs during the reading process, and the number of error bits is less than or equal to the second threshold, determining that the write operation is completed; If an uncorrectable error occurs during the reading process, or the number of error bits is greater than the second threshold, it is determined that the write operation has failed.

9. The method according to claim 8, characterized in that The flash memory device also includes a redundant buffer; The method further comprises: after determining that the write operation fails, performing XOR processing on the data and the first XOR result stored in the redundant buffer to obtain a third XOR result, and updating the first XOR result stored in the redundant buffer with the third XOR result; The write operation is re-executed to write the data into the flash memory medium, wherein the storage locations of the data in the flash memory medium are different in the two write operations.

10. A storage control chip, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the data writing method according to any one of claims 1 to 9.

11. A flash memory device, characterized in that: include: The storage control chip as claimed in claim 10; At least one flash memory medium is communicatively connected to the storage control chip.

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