A CPU-based DSP computing simulation system and method

Abstract

The present invention discloses a DSP operation simulation system and method based on CPU, which belongs to the field of multi-process control technology, and specifically includes: dividing a shared memory space in a memory; setting a monitoring cycle, and obtaining the operation cycle of any operation process of all DSP core modules within the monitoring cycle, calculating the mean of the length of the operation cycle, and selecting a reference cycle according to the cycle mean; obtaining the consumption within the reference cycle and generating reference data points to obtain a reference curve; fitting the reference curve of the operation process to obtain a task operation cycle curve, and determining a target DSP core module according to the operation cycle curve, wherein the target DSP core module is used for a DSP core module that performs operation tasks simultaneously. The present invention can avoid the performance degradation caused by resource competition among various DSP modules during multi-process operation, and improve the operation efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-process control, and in particular to a CPU-based DSP operation simulation system and method. Background Art

[0002] Digital signal processing (DSP for short) is an emerging discipline that involves many disciplines and is widely used in many fields. Since the 1960s, with the rapid development of computer and information technology, digital signal processing technology has emerged and developed rapidly. In the past two decades, digital signal processing has been widely used in fields such as communications. Digital signal processing is the use of computers or special processing equipment to collect, transform, filter, evaluate, enhance, compress, identify and process signals in digital form to obtain a signal form that meets people's needs.

[0003] When a DSP (digital signal processor) runs a DSP algorithm, the number of algorithms it can run is limited by the size of the algorithm itself and the size of the DSP's internal storage. If you want to add a new algorithm beyond the DSP's resource limit, you must restart the DSP and reload the new algorithm firmware. This method requires constantly restarting the DSP and reloading the DSP firmware during operation, which greatly affects the performance of the DSP.

[0004] In the current solution, an operating system instance is run on each processor core, and a hybrid mechanism of shared memory and distributed memory is used to implement task allocation, result synchronization, task release and execution in the task pool. Although the parallel processing of tasks is completed, although each task processing process theoretically does not interfere with each other, they may compete for the same type of resources (such as storage devices, network bandwidth), and system resources (such as CPU, memory, bandwidth) are limited. If the system resources are not allocated reasonably, performance degradation or resource exhaustion may occur due to resource competition among multiple processes. Summary of the invention

[0005] The object of the present invention is to provide a CPU-based DSP operation simulation system and method to solve the following technical problems:

[0006] In the current solution, an operating system instance is run on each processor core, and a hybrid mechanism of shared memory and distributed memory is used to implement task allocation, result synchronization, task release and execution in the task pool. Although the parallel processing of tasks is completed, although each task processing process theoretically does not interfere with each other, they may compete for the same type of resources (such as storage devices, network bandwidth), and system resources (such as CPU, memory, bandwidth) are limited. If the system resources are not allocated reasonably, performance degradation or resource exhaustion may occur due to resource competition among multiple processes.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] A CPU-based DSP operation simulation method, wherein a DSP control module is connected to multiple DSP core modules and the multiple DSP core modules are connected in parallel, comprises the following steps:

[0009] S1, dividing the shared memory space of the DSP control module and multiple DSP core modules in the memory; the DSP control module divides the application into a control part and a computing part, performs process control on the control part of the application, performs computing task analysis on the computing part of the application, and publishes the parsed computing tasks to the shared memory space; the multiple DSP core modules monitor the computing tasks published in the shared memory space, and perform computing according to the computing tasks using corresponding algorithm programs;

[0010] S2, set the monitoring period, and obtain the operation period of any operation process of all DSP core modules within the monitoring period, [Tami, Temi] represents the time range of the mth operation process, i∈[1, n], n represents the total number of times the operation process is in the monitoring period, Tami represents the time point when the operation process m starts the i-th operation, and Temi represents the time point when the operation process m ends the i-th operation;

[0011] S3, according to the calculation formula Calculate the average operation cycle Tv of the operation process m corresponding to any DSP core module, calculate the reference value ΔTm=|Tm-Tv| and select the operation cycle corresponding to the minimum difference MINΔTm as the reference cycle;

[0012] S4, periodically obtain the computing consumption D'=α*D within the reference period, where D represents the total CPU resources of the system, α is the consumption coefficient, and D' represents the CPU usage of the computing process m, and generates reference data points (ti / H, D ti '), H is the length of the reference period, D ti' is the mean value of the computing consumption on ti / H, the reference data points are fitted, the fitting formula is f(tm), and the reference curve of process m is obtained; the reference curves of all computing processes of the DSP module are obtained and fitted to obtain the task computing cycle curve Q;

[0013] S5, determining a target DSP core module group according to the operation cycle curve, wherein the target DSP core module group is used for DSP core modules that perform operation tasks simultaneously.

[0014] As a further solution of the present invention: the DSP core module includes a plurality of operation units, and the operation units are in a serial architecture, and each operation unit corresponds to a operation process.

[0015] As a further solution of the present invention: S3 further includes a screening step, which specifically includes:

[0016] When Temi-Tami≥T 标 When removing the i-th operation cycle, T 标 Indicates the preset duration threshold.

[0017] As a further solution of the present invention: in S3, if there are two or more reference values ​​that are the same and are minimum values, let the length of the reference period H=Tv.

[0018] As a further solution of the present invention: in S4, the specific calculation process of the task operation cycle curve Q is:

[0019] The series connection sequence and the corresponding reference curve of each operation unit are obtained, and the reference curve of each operation unit is fitted according to the series connection sequence to obtain the task operation cycle curve Q.

[0020] As a further solution of the present invention: In S5, the specific process of determining the target core module is:

[0021] S11: Draw the task operation cycle curve Q corresponding to all DSP core modules in the same coordinate system and set Z time nodes at a preset time interval Δt, where Z is the preset number of nodes, and obtain the consumption corresponding to the same time node on the task operation cycle curve as the resource consumption;

[0022] S12: Calculate resource consumption starting from the first time node , where f A (Δt) represents the resource consumption corresponding to the Ath DSP core module, and S represents the total number of DSP core modules;

[0023] When the resource consumption G≥Dt-ΔG, the task operation cycle curve corresponding to maxf(Δt) is removed, Dt represents the total CPU resources of the current system, and ΔG represents the preset CPU resource threshold;

[0024] S13: recalculate the resource consumption G, and repeat S12 until the resource consumption at the first time node satisfies G<Dt-ΔG;

[0025] Calculate the resource consumption at the second time node, and repeat the above steps until the resource consumption G of all unremoved task operation cycle curves at each time node is less than Gt-ΔG, and take the DSP core modules corresponding to all unremoved task operation cycle curves as a target core group module;

[0026] S14: Obtain the task operation cycle curve that does not belong to the target core module, repeat S12 to S13, and determine all the target core group modules.

[0027] As a further solution of the present invention: it also includes obtaining all task operation cycle curves in any target core group module and calculating the corresponding length mean T' of the task operation cycle curve, sorting the target DSP core group modules according to the size of the corresponding length mean of the task operation cycle curve, the larger the corresponding length mean of the task operation cycle curve, the lower the ranking, generating an operation ranking, and performing synchronous operation on all operation processes in the target DSP core group module according to the operation ranking.

[0028] The present application also provides a CPU-based DSP computing simulation system, comprising:

[0029] A preprocessing module is used to divide the shared memory space of the DSP control module and multiple DSP core modules in the memory; the DSP control module divides the application into a control part and a computing part, performs process control on the control part of the application, performs computing task analysis on the computing part of the application, and publishes the parsed computing tasks to the shared memory space; the multiple DSP core modules monitor the computing tasks published in the shared memory space, and perform computing using corresponding algorithm programs according to the computing tasks;

[0030] The data acquisition module is used to set the monitoring period and obtain the operation period of any operation process of all DSP core modules within the monitoring period, [Tami, Temi] represents the time range of the mth operation process, i∈[1, n], n represents the total number of times the operation process is in the monitoring period, Tami represents the time point when the operation process m starts the i-th operation, and Temi represents the time point when the operation process m ends the i-th operation;

[0031] Data analysis module, used to calculate the formula Calculate the average operation cycle Tv of the operation process m corresponding to any DSP core module, calculate the reference value ΔTm=|Tm-Tv| and select the operation cycle corresponding to the minimum difference MINΔTm as the reference cycle;

[0032] The computing consumption D'=α*D is periodically obtained during the reference period, where D represents the total CPU resources of the system, α is the consumption coefficient, and D' represents the CPU usage of the computing process m. The reference data point (ti / H, D ti '), H is the length of the reference period, D ti ' is the mean value of the computing consumption on ti / H, the reference data points are fitted, the fitting formula is f(tm), and the reference curve of process m is obtained; the reference curves of all computing processes of the DSP module are obtained and fitted to obtain the task computing cycle curve Q;

[0033] The result generation module is used to determine the target DSP core module according to the operation cycle curve, and the target DSP core module is used as the DSP core module for performing the operation tasks at the same time.

[0034] Beneficial effects of the present invention:

[0035] By dividing the shared memory between the DSP control module and multiple DSP core modules, efficient data transmission and task allocation can be achieved. This method reduces communication delay and ensures that the DSP core module can obtain the required computing tasks in a timely manner. By monitoring the computing process and CPU usage of each DSP core module, the resource usage can be evaluated in real time, and task allocation can be adjusted dynamically to avoid the situation where some core modules are overloaded while other modules are idle. The application is divided into a control part and a computing part and processed separately. The control part is responsible for task scheduling, while the computing part focuses on efficient computing. By setting the monitoring cycle and analyzing the execution time of each computing process, real-time computing performance data can be obtained, providing feedback to optimize the scheduling and execution strategy of subsequent tasks. By calculating the average computing cycle and reference value of each DSP core module, the computing cycle corresponding to the minimum difference is selected as the reference cycle. This mechanism can be dynamically adjusted according to the actual computing situation to improve the adaptability and responsiveness of computing tasks. By fitting the reference data points, a reference curve for computing tasks can be formed, so that the scheduling system can better predict the performance of each DSP core module under different loads. As the number of DSP core modules increases or the complexity of tasks changes, the system can still maintain efficient operation and adapt to new computing needs by appropriately adjusting the monitoring cycle and correction strategy. Through efficient task allocation and monitoring, multiple DSP core modules can process tasks in parallel, thereby significantly improving the computing performance and throughput of the overall system. Real-time monitoring and dynamic adjustment can reduce the response time of task execution and improve computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention will be further described below in conjunction with the accompanying drawings.

[0037] Figure 1 It is a flow chart of a CPU-based DSP operation simulation method of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] See also Figure 1 As shown, the present invention is a CPU-based DSP operation simulation method, a DSP control module is connected to multiple DSP core modules and the multiple DSP core modules are connected in parallel, comprising the following steps:

[0040] S1, dividing the shared memory space of the DSP control module and multiple DSP core modules in the memory; the DSP control module divides the application into a control part and a computing part, performs process control on the control part of the application, performs computing task analysis on the computing part of the application, and publishes the parsed computing tasks to the shared memory space; the multiple DSP core modules monitor the computing tasks published in the shared memory space, and perform computing according to the computing tasks using corresponding algorithm programs;

[0041] S2, set the monitoring period, and obtain the operation period of any operation process of all DSP core modules within the monitoring period, [Tami, Temi] represents the time range of the mth operation process, i∈[1, n], n represents the total number of times the operation process is in the monitoring period, Tami represents the time point when the operation process m starts the i-th operation, and Temi represents the time point when the operation process m ends the i-th operation;

[0042] S3, according to the calculation formula Calculate the average operation cycle Tv of the operation process m corresponding to any DSP core module, calculate the reference value ΔTm=|Tm-Tv| and select the operation cycle corresponding to the minimum difference MINΔTm as the reference cycle;

[0043] S4, periodically obtain the computing consumption D'=α*D within the reference period, where D represents the total CPU resources of the system, α is the consumption coefficient, and D' represents the CPU usage of the computing process m, and generates reference data points (ti / H, D ti'), H is the length of the reference period, D ti ' is the mean value of the computing consumption on ti / H, the reference data points are fitted, the fitting formula is f(tm), and the reference curve of process m is obtained; the reference curves of all computing processes of the DSP module are obtained and fitted to obtain the task computing cycle curve Q;

[0044] S5, determining a target DSP core module group according to the operation cycle curve, wherein the target DSP core module group is used for DSP core modules that perform operation tasks simultaneously.

[0045] By dividing the shared memory between the DSP control module and multiple DSP core modules, efficient data transmission and task allocation can be achieved. This method reduces communication delay and ensures that the DSP core module can obtain the required computing tasks in a timely manner. By monitoring the computing process and CPU usage of each DSP core module, the resource usage can be evaluated in real time, and task allocation can be adjusted dynamically to avoid the situation where some core modules are overloaded while other modules are idle. The application is divided into a control part and a computing part and processed separately. The control part is responsible for task scheduling, while the computing part focuses on efficient computing. By setting the monitoring cycle and analyzing the execution time of each computing process, real-time computing performance data can be obtained, providing feedback to optimize the scheduling and execution strategy of subsequent tasks. By calculating the average computing cycle and reference value of each DSP core module, the computing cycle corresponding to the minimum difference is selected as the reference cycle. This mechanism can be dynamically adjusted according to the actual computing situation to improve the adaptability and responsiveness of computing tasks. By fitting the reference data points, a reference curve for computing tasks can be formed, so that the scheduling system can better predict the performance of each DSP core module under different loads. As the number of DSP core modules increases or the complexity of tasks changes, the system can still maintain efficient operation and adapt to new computing needs by appropriately adjusting the monitoring cycle and correction strategy. Through efficient task allocation and monitoring, multiple DSP core modules can process tasks in parallel, thereby significantly improving the computing performance and throughput of the overall system. Real-time monitoring and dynamic adjustment can reduce the response time of task execution and improve computing efficiency.

[0046] It is worth noting that DSP is used for filtering, equalization, noise reduction and other operations of audio signals in audio processing. In actual systems, it is necessary to continuously perform the same processing operations such as sampling, noise reduction, encoding and decoding on the input multi-channel audio data streams. However, since they may compete for the same type of resources, and system resources (such as CPU, memory, bandwidth) are limited, if the system resources are not reasonably allocated, performance degradation or resource exhaustion may occur due to resource competition among multiple processes. Therefore, the present invention first obtains the consumption of any operating DSP core module corresponding to each channel of audio stream data. By monitoring the operation process and CPU usage of each DSP core module, it can evaluate the resource usage in real time and dynamically adjust task allocation to avoid overloading of some core modules and idleness of other modules, so as to realize multiple core modules to process tasks in parallel at the same time, thereby significantly improving the operation performance and throughput of the overall system. Real-time monitoring and dynamic adjustment can reduce the response time of task execution and improve operation efficiency.

[0047] In a preferred embodiment of the present invention, the DSP core module includes a plurality of operation units, and the operation units are serially connected, and each operation unit corresponds to a operation process.

[0048] In another preferred embodiment of the present invention, said S3 further includes a screening step, and said screening step specifically includes:

[0049] When Temi-Tami≥T 标 When removing the i-th operation cycle, T 标 Indicates the preset duration threshold.

[0050] In another preferred embodiment of the present invention, in S3, if there are two or more reference values ​​that are the same and are minimum values, the length of the reference period H=Tv.

[0051] In another preferred embodiment of the present invention, in S4, the specific calculation process of the task operation cycle curve Q is:

[0052] The series connection sequence and the corresponding reference curve of each operation unit are obtained, and the reference curve of each operation unit is fitted according to the series connection sequence to obtain the task operation cycle curve Q.

[0053] In another preferred embodiment of the present invention, in S5, the specific process of determining the target core module is:

[0054] S11: Draw the task operation cycle curve Q corresponding to all DSP core modules in the same coordinate system and set Z time nodes at a preset time interval Δt, where Z is the preset number of nodes, and obtain the consumption corresponding to the same time node on the task operation cycle curve as the resource consumption;

[0055] S12: Calculate resource consumption starting from the first time node , where f A (Δt) represents the resource consumption corresponding to the Ath DSP core module, and S represents the total number of DSP core modules;

[0056] When the resource consumption G≥Dt-ΔG, the task operation cycle curve corresponding to maxf(Δt) is removed, Dt represents the total CPU resources of the current system, and ΔG represents the preset CPU resource threshold;

[0057] S13: recalculate the resource consumption G, and repeat S12 until the resource consumption at the first time node satisfies G<Dt-ΔG;

[0058] Calculate the resource consumption at the second time node, and repeat the above steps until the resource consumption G of all unremoved task operation cycle curves at each time node is less than Gt-ΔG, and take the DSP core modules corresponding to all unremoved task operation cycle curves as a target core group module;

[0059] S14: Obtain the task operation cycle curve that does not belong to the target core module, repeat S12 to S13, and determine all the target core group modules.

[0060] In another preferred embodiment of the present invention, it also includes obtaining all task operation cycle curves in any target core group module and calculating the corresponding length mean T' of the task operation cycle curve, sorting the target DSP core group modules according to the size of the corresponding length mean of the task operation cycle curve, the larger the corresponding length mean of the task operation cycle curve, the lower the ranking, generating an operation ranking, and performing synchronous operation on all operation processes in the target DSP core group module according to the operation ranking.

[0061] The present application also provides a CPU-based DSP computing simulation system, comprising:

[0062] A preprocessing module is used to divide the shared memory space of the DSP control module and multiple DSP core modules in the memory; the DSP control module divides the application into a control part and a computing part, performs process control on the control part of the application, performs computing task analysis on the computing part of the application, and publishes the parsed computing tasks to the shared memory space; the multiple DSP core modules monitor the computing tasks published in the shared memory space, and perform computing using corresponding algorithm programs according to the computing tasks;

[0063] The data acquisition module is used to set the monitoring period and obtain the operation period of any operation process of all DSP core modules within the monitoring period, [Tami, Temi] represents the time range of the mth operation process, i∈[1, n], n represents the total number of times the operation process is in the monitoring period, Tami represents the time point when the operation process m starts the i-th operation, and Temi represents the time point when the operation process m ends the i-th operation;

[0064] Data analysis module, used to calculate the formula Calculate the average operation cycle Tv of the operation process m corresponding to any DSP core module, calculate the reference value ΔTm=|Tm-Tv| and select the operation cycle corresponding to the minimum difference MINΔTm as the reference cycle;

[0065] The computing consumption D'=α*D is periodically obtained during the reference period, where D represents the total CPU resources of the system, α is the consumption coefficient, and D' represents the CPU usage of the computing process m. The reference data point (ti / H, D ti '), H is the length of the reference period, D ti ' is the mean value of the computing consumption on ti / H, the reference data points are fitted, the fitting formula is f(tm), and the reference curve of process m is obtained; the reference curves of all computing processes of the DSP module are obtained and fitted to obtain the task computing cycle curve Q;

[0066] The result generation module is used to determine the target DSP core module according to the operation cycle curve, and the target DSP core module is used as the DSP core module for performing the operation tasks at the same time.

[0067] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A CPU-based DSP operation simulation method, characterized in that: A DSP control module is connected to a plurality of DSP core modules and the plurality of DSP core modules are connected in parallel, comprising the following steps: S1, dividing the shared memory space of the DSP control module and multiple DSP core modules in the memory; the DSP control module divides the application into a control part and a computing part, performs process control on the control part of the application, performs computing task analysis on the computing part of the application, and publishes the parsed computing tasks to the shared memory space; the multiple DSP core modules monitor the computing tasks published in the shared memory space, and perform computing according to the computing tasks using corresponding algorithm programs; S2, set the monitoring period, and obtain the operation period of any operation process of all DSP core modules within the monitoring period, [Tami, Temi] represents the time range of the mth operation process, i∈[1, n], n represents the total number of times the operation process is in the monitoring period, Tami represents the time point when the operation process m starts the i-th operation, and Temi represents the time point when the operation process m ends the i-th operation; S3, according to the calculation formula Calculate the average operation cycle Tv of the operation process m corresponding to any DSP core module, calculate the length difference ΔTm=|Tm-Tv|, generate the difference set ΔT=(ΔT1, ΔT2, …, ΔTn), and select the operation cycle corresponding to the minimum difference MINΔT as the correction cycle; S4, periodically obtain the consumption C'=α*C within the correction period, where C represents the total CPU resources of the system, α is the consumption coefficient, and C' represents the CPU usage of the operation process m, and generate data points (ti, C ti ), C ti Indicates the consumption when the interval from the start point of the correction period is ti, and generates a correction data point (ti / H, C ti ), H represents the length of the correction period; calculate the average consumption C on ti / H ti ', and generate standard data points (ti / H, C ti '), fitting the standard data points to obtain a standard curve for process m; obtaining the standard curves of all operation processes of the DSP core module and fitting them to obtain a task operation cycle curve Q; S5, determining a target DSP core module group according to the operation cycle curve, wherein the target DSP core module group is used for DSP core modules that perform operation tasks simultaneously.

2. The CPU-based DSP operation simulation method according to claim 1, characterized in that: The DSP core module includes a plurality of operation units, and the operation units are serially connected, and each operation unit corresponds to a operation process.

3. The CPU-based DSP operation simulation method according to claim 1, characterized in that: The step S3 further includes a screening step, which specifically includes: When Temi-Tami≥T 标 When removing the i-th operation cycle, T 标 Indicates the preset duration threshold.

4. The CPU-based DSP operation simulation method according to claim 1, characterized in that: In S3, if there are two or more length differences that are the same and are minimum values, the length of the correction period is set to H=Tv.

5. The CPU-based DSP operation simulation method according to claim 1, characterized in that: In S4, the specific calculation process of the task operation cycle curve Q is: The series connection sequence and the corresponding standard curve of each computing unit are obtained, and the standard curve of each computing unit is fitted according to the series connection sequence to obtain the task computing cycle curve Q.

6. The CPU-based DSP operation simulation method according to claim 1, characterized in that: In S5, the specific process of determining the target DSP core module group is as follows: S11: Draw the task operation cycle curve Q corresponding to all DSP core modules in the same coordinate system and set Z time nodes at a preset time interval Δt, where Z is the preset number of nodes, and obtain the consumption corresponding to the same time node on the task operation cycle curve as the evaluation consumption; S12: Calculate the total evaluation consumption starting from the first time node , where f A (Δt) represents the Ath standard curve, S represents the number of DSP core modules; When the total evaluation consumption G ≥ Ct-ΔG, remove f (Δt) max =max(f(Δt)) corresponding standard curve, f(Δt)=(f1(Δt), f2(Δt), …, fs(Δt)), Ct represents the total CPU resources of the current system, ΔG represents the preset CPU resource safety value; S13: recalculate the total evaluation consumption G, and repeat S12 until the total evaluation consumption G at the first time node is less than Ct-ΔG; Calculate the total evaluation consumption at the second time node, and repeat the above steps until the total evaluation consumption of all standard curves that have not been removed at each time node is less than Gt-ΔG, and take the DSP core modules corresponding to all standard curves that have not been removed at this time as a target DSP core module group; S14: Acquire a standard curve that does not belong to the target DSP core module group, repeat S12 to S13, and determine all target DSP core module groups.

7. The CPU-based DSP operation simulation method according to claim 1, characterized in that: Obtain the task operation cycle curve in any target DSP core module group, and obtain the corresponding length mean T' of the task operation cycle curve, and use it as the priority value, sort the target DSP core module group according to the size of the priority value, the larger the priority value, the lower the ranking, generate an operation ranking, and from the target DSP core module group that is ranked first in the operation ranking, perform operations on all the operation processes in the target DSP core module group simultaneously.

8. A CPU-based DSP computing simulation system, characterized in that: A DSP control module is connected to a plurality of DSP core modules and the plurality of DSP core modules are connected in parallel, including: A preprocessing module is used to divide the shared memory space of the DSP control module and multiple DSP core modules in the memory; the DSP control module divides the application into a control part and a computing part, performs process control on the control part of the application, performs computing task analysis on the computing part of the application, and publishes the parsed computing tasks to the shared memory space; the multiple DSP core modules monitor the computing tasks published in the shared memory space, and perform computing using corresponding algorithm programs according to the computing tasks; The data acquisition module sets a monitoring period and obtains the operation period of any operation process of all DSP core modules within the monitoring period. [Tami, Temi] represents the time range of the mth operation process, i∈[1, n], n represents the total number of times the operation process is in the monitoring period, Tami represents the time point when the operation process m starts the i-th operation, and Temi represents the time point when the operation process m ends the i-th operation. Data analysis module, according to the calculation formula Calculate the average operation cycle Tv of the operation process m corresponding to any DSP core module, calculate the length difference ΔTm=|Tm-Tv|, generate the difference set ΔT=(ΔT1, ΔT2, …, ΔTn), and select the operation cycle corresponding to the minimum difference MINΔT as the correction cycle; The consumption C'=α*C is periodically obtained during the correction period, where C represents the total CPU resources of the system, α is the consumption coefficient, and C' represents the CPU usage of the computing process m, and a data point (ti, C ti ), C ti Indicates the consumption when the interval from the start point of the correction period is ti, and generates a correction data point (ti / H, C ti ), H represents the length of the correction period; calculate the average consumption C on ti / H ti ', and generate standard data points (ti / H, C ti '), fitting the standard data points to obtain a standard curve for process m; obtaining the standard curves of all operation processes of the DSP core module and fitting them to obtain a task operation cycle curve Q; The result generation module is used to determine the target DSP core module group according to the operation cycle curve, and the target DSP core module group is used for the DSP core modules that perform operation tasks simultaneously.

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