Dual-CPU data synchronization system and method

Abstract

The invention relates to a double-CPU (Central Processing Unit) data synchronization system and method. The system comprises a CPU 1; a CPU 2; the information synchronization module is configured to adjust the pin state of the CPU1 sending pin through a first state setting unit, adjust the pin state of the CPU2 sending pin through a second state setting unit, judge whether the state of the CPU1 receiving pin is converted into the state same as the state of the CPU2 sending pin matched with the pin or not within the first preset time, and synchronize the state of the CPU1 sending pin and the state of the CPU2 sending pin. Judging whether the state of the receiving pin of the CPU 2 is converted into the same state as the sending pin of the CPU 1 matched with the receiving pin of the CPU 2; and the data transmission module is configured to send one piece of data to be synchronized to the CPU 2 through the first transmission unit, send the other piece of data to be synchronized to the CPU 1 through the second transmission unit, judge whether the CPU 1 and the CPU 2 complete sending or not, and receive the data sent by each other. According to the information processing method and device, the problems that information processing is delayed and the information processing efficiency is low are solved, the CPU 1 and the CPU 2 can process tasks at the same time, the processing speed is increased, and the working efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of computer control, and in particular to a dual CPU data synchronization system and method. Background Art

[0002] In order to improve the safety performance of the product, a single CPU can no longer meet the computing needs during the processing.

[0003] In the prior art, a CPU system and a collaborative soft reset method thereof are disclosed, wherein the dual CPU system includes two CPUs each with a communication serial port, and the two CPUs are simultaneously connected to at least one GPIO. The dual CPU system first automatically identifies the master and slave CPUs using the same GPIO state, and then implements soft reset control signaling communication through the first communication serial port on the master CPU and the second communication serial port on the slave CPU.

[0004] Currently, in the related technology, the two CPUs can only be divided into a master and a slave CPU for information processing, but the two CPUs cannot be adjusted to the same state, which may cause delays in information processing and low information processing efficiency. Summary of the invention

[0005] The embodiments of the present application provide a dual-CPU data synchronization system and method to at least solve the problems of information processing delay and low information processing efficiency in the related art.

[0006] In a first aspect, an embodiment of the present application provides a dual-CPU data synchronization system, including:

[0007] CPU1, comprising a first signal unit, a first transmission unit and a first state setting unit, wherein the first signal unit comprises a pin group, each pin group comprises a CPU1 sending pin and a CPU1 receiving pin; the first state setting unit is used to set the state of the CPU1 sending pin;

[0008] CPU2, including a second signal unit, a second transmission unit and a second state setting unit, wherein the second signal unit includes a pin group, each pin group includes a CPU2 sending pin and a CPU2 receiving pin; the second state setting unit is used to set the state of the CPU2 sending pin;

[0009] Among them, one CPU1 transmit pin matches one CPU2 receive pin, and one CPU1 receive pin matches one CPU2 transmit pin;

[0010] The information synchronization module is configured to adjust the pin state of the CPU1 sending pin through the first state setting unit, adjust the pin state of the CPU2 sending pin through the second state setting unit, and determine whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matched with the pin within a first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matched with the pin;

[0011] The data transmission module is configured to send a data to be synchronized to CPU2 through the first transmission unit, send another data to be synchronized to CPU1 through the second transmission unit, determine whether CPU1 and CPU2 have completed the transmission, and receive the data sent by the other party.

[0012] By adjusting the pin states of CPU1 and CPU2 and realizing that CPU1 and CPU2 respond accordingly to a series of adjustments, CPU1 and CPU2 can be adjusted to the same working state. Information synchronization is achieved through data transmission. CPU1 and CPU2 process tasks at the same time, which speeds up the processing speed and improves work efficiency.

[0013] In some embodiments, the information synchronization module is further configured to:

[0014] Adjust the state of the CPU1 sending pin to the first pin through the first state setting unit, adjust the state of the CPU2 sending pin to the first pin through the second state setting unit, and judge whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matched with the pin within the first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matched with the pin;

[0015] If so, adjust the state of the CPU1 sending pin to the second pin through the first state setting unit, and adjust the state of the CPU2 sending pin to the second pin through the second state setting unit, and determine whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin that matches the pin within the first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin that matches the pin.

[0016] The information synchronization module can calibrate the time of executing tasks multiple times. After multiple calibrations, the time difference of the two CPU information synchronization will become smaller and smaller. The efficiency of CPU1 and CPU2 to achieve synchronization is getting higher and higher, which is convenient for the dual CPUs to work and execute tasks.

[0017] In some embodiments, the data transmission module further includes:

[0018] The first judgment unit is configured to judge whether the sending register of CPU1 and the sending register of CPU2 are both cleared within a second preset time;

[0019] The second judgment unit is configured to judge whether the DMA receiving completion flag of CPU1 and the DMA receiving completion flag of CPU2 are both set within a second preset time.

[0020] By judging whether the sending register of CPU1 and the sending register of CPU2 are cleared and whether the DMA receiving completion flag of CPU1 and the DMA receiving completion flag of CPU2 are both set, it is determined whether CPU1 and CPU2 have completed information sending and information receiving, thereby realizing dual CPU data synchronization.

[0021] In some embodiments, the first transmission unit and the second transmission unit both include:

[0022] A data transmission pin, and a data reception pin;

[0023] The data sending pin of the first transmission unit corresponds to the data receiving pin of the second transmission unit;

[0024] The data receiving pin of the first transmission unit corresponds to the data sending pin of the second transmission unit.

[0025] The two CPUs are provided with data transmission pins and data receiving pins for data transmission, which facilitates data transmission, enables smooth transmission and reception of information, and avoids information omission.

[0026] In some embodiments, CPU1 and CPU2 each include a plurality of pin groups, and each pin group of CPU1 corresponds to a pin group of CPU2;

[0027] The information synchronization module is configured to adjust the pin states corresponding to the CPU1 pin group and the CPU2 pin group, including:

[0028] Adjust the state of a CPU1 transmit pin of a CPU1 pin group, and the state of a CPU2 transmit pin in a CPU2 pin group corresponding to the CPU1 pin group; determine whether the state of a CPU2 receive pin of the CPU2 pin group is adjusted to be the same as the state of a CPU1 transmit pin in the CPU1 pin group within a first preset time, and whether the state of a CPU1 receive pin in the CPU1 pin group is adjusted to be the same as the state of a CPU2 transmit pin of the CPU2 pin group;

[0029] If so, the state of the next corresponding CPU1 pin group and CPU2 pin group is adjusted until the state adjustment of all corresponding CPU1 pin groups and CPU2 pin groups is completed.

[0030] Both CPU1 and CPU2 include multiple pin groups. The multiple pin groups are adjusted to appropriate states to achieve CPU1 and CPU2 signal synchronization, providing basic support for subsequent data synchronization.

[0031] In some embodiments, the information synchronization module is further configured to:

[0032] Adjust the state of a CPU1 sending pin of a CPU1 pin group to a first pin state, and adjust the state of a CPU2 sending pin in a CPU2 pin group corresponding to the CPU1 pin group to a first pin state; determine whether the state of a CPU2 receiving pin of the CPU2 pin group is adjusted to be the same as the state of a CPU1 sending pin in the CPU1 pin group within a first preset time, and whether the state of a CPU1 receiving pin in the CPU1 pin group is adjusted to be the same as the state of a CPU2 sending pin of the CPU2 pin group;

[0033] If yes, then adjust the state of the next corresponding CPU1 pin group and CPU2 pin group until the states of all corresponding CPU1 pin groups and CPU2 pin groups are adjusted in the first pin state;

[0034] Further adjusting the state of a CPU1 sending pin of a CPU1 pin group to a second pin state, and the state of a CPU2 sending pin in a CPU2 pin group corresponding to the CPU1 pin group to a second pin state; determining whether the state of a CPU2 receiving pin of the CPU2 pin group is adjusted to be the same as the state of a CPU1 sending pin in the CPU1 pin group within a first preset time, and whether the state of a CPU1 receiving pin in the CPU1 pin group is adjusted to be the same as the state of a CPU2 sending pin of the CPU2 pin group;

[0035] If so, the state of the next corresponding CPU1 pin group and CPU2 pin group is adjusted until the states of all corresponding CPU1 pin groups and CPU2 pin groups are adjusted in the second pin state.

[0036] During the signal synchronization process, the states of the dual CPU pin groups are adjusted in sequence to pull the two CPUs to the same state and reduce delays. By adjusting the pin states of CPU1 and CPU2 multiple times, the time difference between the two CPUs can be reduced.

[0037] In some embodiments, the first pin state is a high level, and the second pin state is a low level.

[0038] In a second aspect, an embodiment of the present application provides a dual CPU data synchronization method, comprising:

[0039] An information synchronization step, adjusting the pin state of the CPU1 sending pin, adjusting the pin state of the CPU2 sending pin, and determining whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matched with the pin within a first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matched with the pin;

[0040] In the data transmission step, CPU1 sends a data to be synchronized to CPU2, and CPU2 sends another data to be synchronized to CPU1, and it is determined whether CPU1 and CPU2 have completed the transmission, and the data sent by the other party are received.

[0041] Through the above steps, the pin state is adjusted to achieve the state synchronization of the dual CPUs, and the data transmission is used to achieve the data synchronization of the dual CPUs. CPU1 and CPU2 are adjusted to the same working state, so that the processing speed is faster and the efficiency is higher.

[0042] In some embodiments, the information synchronization step further includes:

[0043] S11, adjusting the state of the first CPU1 sending pin to the first pin state, and the state of the first CPU2 sending pin to the first pin state; judging whether the state of the first CPU2 receiving pin matching the first CPU1 sending pin is adjusted to be the same as the state of the first CPU1 sending pin within the first preset time, and whether the state of the first CPU1 receiving pin is adjusted to be the same as the state of the first CPU2 sending pin, if so, adjusting the state of the next CPU1 sending pin and the next CPU2 sending pin to the first pin state, and judging again whether the states of the corresponding CPU2 receiving pin and CPU1 receiving pin are both adjusted to the first pin state; repeating the execution until the states of all the pins in the matching CPU1 pin group and the pins in the CPU2 pin group are in the first pin state;

[0044] S12, adjust the state of the first CPU1 sending pin to the second pin state, and the state of the first CPU2 sending pin to the second pin state; determine whether the state of the first CPU2 receiving pin matching the first CPU1 sending pin is adjusted to be the same as the state of the first CPU1 sending pin, and whether the state of the first CPU1 receiving pin is adjusted to be the same as the state of the first CPU2 sending pin within the first preset time, and if so, adjust the state of the next CPU1 sending pin and the next CPU2 sending pin to the second pin state, and determine whether the states of the corresponding CPU2 receiving pin and CPU1 receiving pin are both adjusted to the first pin state; repeat the execution until the states of all pins in the matching CPU1 pin group and the pins in the CPU2 pin group are in the second pin state.

[0045] In the above information synchronization steps, the first CPU1 sending pin and the first CPU1 receiving pin correspond to pins in a CPU1 pin group, and the first CPU2 receiving pin and the first CPU2 sending pin correspond to pins in a CPU2 pin group.

[0046] There are multiple pins in CPU1 and CPU2. To achieve signal synchronization, multiple pins need to be matched and adjusted to the same state. After multiple adjustments, CPU1 and CPU2 are synchronized, which can better handle tasks and increase the safety of operation.

[0047] In some embodiments, the data transmission step includes:

[0048] S21, CPU1 sends the first data to be synchronized, and CPU1 sends the second data to be synchronized;

[0049] S22, within the second preset time, CPU1 and CPU2 determine whether their respective SCI sending registers are cleared;

[0050] S23, within the second preset time, CPU1 and CPU2 determine whether their respective SCIDMA reception completion flags are set;

[0051] S24, CPU1 reads the second data to be synchronized, and CPU2 reads the first data to be synchronized.

[0052] By judging whether the SCI transmit register is cleared and the SCIDMA receive completion flag is set, it is determined whether CPU1 and CPU2 have sent data to each other. Further, CPU1 and CPU2 read the data to achieve data synchronization. This is conducive to the dual CPU synchronous processing of tasks and improves work efficiency.

[0053] Compared with the related art, the dual CPU data synchronization system and method provided in the embodiment of the present application adjusts the pin states of the two CPUs to adjust the two CPUs to the same working state, calibrates the time for executing tasks, improves the CPU's working efficiency, and reduces delays.

[0054] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0056] Figure 1is a structural block diagram of a dual CPU data synchronization system according to an embodiment of the present application;

[0057] Figure 2 is a flow chart of a dual CPU data synchronization method according to an embodiment of the present application;

[0058] Figure 3 is a structural block diagram of CPU1 and CPU2 in a dual CPU data synchronization system according to an embodiment of the present application;

[0059] Figure 4 is a flow chart of a signal synchronization process in a dual CPU data synchronization method according to an embodiment of the present application;

[0060] Figure 5 It is a flow chart of the data transmission process in the dual CPU data synchronization method according to an embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0062] Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. In addition, it can also be understood that although the efforts made in this development process may be complicated and lengthy, for ordinary technicians in this field related to the content disclosed in this application, some changes in design, manufacturing or production based on the technical content disclosed in this application are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

[0063] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0064] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0065] The present embodiment provides a dual CPU data synchronization system. As used below, the terms "module", "unit", "subunit", etc. can implement a combination of software and / or hardware of a predetermined function. Although the system described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and contemplated.

[0066] Figure 1 is a structural diagram of a dual CPU data synchronization system according to an embodiment of the present application, such as Figure 1 As shown, the system includes:

[0067] CPU1 includes a first signal unit, a first transmission unit and a first state setting unit, wherein the first signal unit includes a pin group, each pin group includes a CPU1 sending pin and a CPU1 receiving pin; the first state setting unit is used to set the state of the CPU1 sending pin.

[0068] CPU2 includes a second signal unit, a second transmission unit and a second state setting unit, wherein the second signal unit includes a pin group, each pin group includes a CPU2 sending pin and a CPU2 receiving pin; the second state setting unit is used to set the state of the CPU2 sending pin.

[0069] Among them, a pin group of CPU1 corresponds to a pin group of CPU2. Specifically, a CPU1 sending pin in a CPU1 pin group matches a CPU2 receiving pin in a CPU2 pin group, and a CPU1 receiving pin in a CPU1 pin group matches a CPU2 sending pin in a CPU2 pin group.

[0070] The information synchronization module is configured to adjust the pin state of the CPU1 sending pin through the first state setting unit, adjust the pin state of the CPU2 sending pin through the second state setting unit, and judge whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matching the pin within the first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matching the pin.

[0071] The data transmission module is configured to send a data to be synchronized to CPU2 through the first transmission unit, send another data to be synchronized to CPU1 through the second transmission unit, determine whether CPU1 and CPU2 have completed the transmission, and receive the data sent by the other party.

[0072] Through the above system, the pin states of CPU1 and CPU2 are adjusted, and CPU1 and CPU2 respond to a series of adjustments accordingly, so that CPU1 and CPU2 can be adjusted to the same working state. Information synchronization is achieved through data transmission. CPU1 and CPU2 process tasks at the same time, which speeds up the processing speed and improves work efficiency.

[0073] The first preset time is twice the execution time of the tasks set in CPU1 and CPU2.

[0074] In one embodiment, when two CPUs receive instructions that require data synchronization, the data synchronization task is placed in the task lists of the two CPUs. At this time, the two CPUs also need to complete the tasks already in the list. CPU1 needs to complete Task 1, and CPU2 needs to complete Task 1, Task 2, and Task 3. CPU1 completes Task 1, starts the data synchronization task, adjusts the state of its own sending pin, and waits for CPU2 to start the data synchronization task. CPU2 completes Task 1, Task 2, and Task 3, starts the data synchronization task, and adjusts the state of its own sending pin. The first preset time = (time required to complete Task 2 + time required to complete Task 3) * 2. Within the first preset time, the state of the CPU1 receiving pin is adjusted according to the state of the CPU2 sending pin that matches the pin, and the state of the CPU2 receiving pin is adjusted according to the state of the CPU1 sending pin that matches the pin, then the state adjustment is successful.

[0075] The first preset time may be understood as the time taken from when one CPU starts to execute the data synchronization task to when another CPU starts to execute the data synchronization task.

[0076] In some embodiments, the information synchronization module is further configured to:

[0077] The state of the CPU1 sending pin to the first pin is adjusted through the first state setting unit, and the state of the CPU2 sending pin to the first pin is adjusted through the second state setting unit, and it is determined whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matching the pin within the first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matching the pin.

[0078] If so, adjust the state of the CPU1 sending pin to the second pin through the first state setting unit, and adjust the state of the CPU2 sending pin to the second pin through the second state setting unit, and determine whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin that matches the pin within the first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin that matches the pin.

[0079] The information synchronization module can calibrate the time of executing tasks multiple times. After multiple calibrations, the time difference of the two CPU information synchronization will become smaller and smaller. The efficiency of CPU1 and CPU2 to achieve synchronization is getting higher and higher, which is convenient for the dual CPUs to work and execute tasks.

[0080] In some embodiments, the data transmission module further includes:

[0081] The first determination unit is configured to determine whether the sending register of CPU1 and the sending register of CPU2 are both cleared within a second preset time.

[0082] The second judgment unit is configured to judge whether the DMA receiving completion flag of CPU1 and the DMA receiving completion flag of CPU2 are both set within a second preset time.

[0083] By judging whether the sending register of CPU1 and the sending register of CPU2 are cleared and whether the DMA receiving completion flag of CPU1 and the DMA receiving completion flag of CPU2 are both set, it is determined whether CPU1 and CPU2 have completed information sending and information receiving, thereby realizing dual CPU data synchronization.

[0084] In some embodiments, the first transmission unit and the second transmission unit both include:

[0085] A data transmit pin, and a data receive pin.

[0086] The data sending pin of the first transmission unit corresponds to the data receiving pin of the second transmission unit.

[0087] The data receiving pin of the first transmission unit corresponds to the data sending pin of the second transmission unit.

[0088] The two CPUs are provided with data transmission pins and data receiving pins for data transmission, which facilitates data transmission, enables smooth transmission and reception of information, and avoids information omission.

[0089] In some embodiments, CPU1 and CPU2 each include a plurality of pin groups, and each pin group of CPU1 corresponds to a pin group of CPU2.

[0090] The information synchronization module is configured to adjust the pin states corresponding to the CPU1 pin group and the CPU2 pin group, including:

[0091] Adjust the state of the CPU1 sending pin of a CPU1 pin group, and the state of the CPU2 sending pin in the CPU2 pin group corresponding to the CPU1 pin group; determine whether the state of the CPU2 receiving pin of the CPU2 pin group is adjusted to be the same as the state of the CPU1 sending pin in the CPU1 pin group within a first preset time, and whether the state of the CPU1 receiving pin in the CPU1 pin group is adjusted to be the same as the state of the CPU2 sending pin of the CPU2 pin group.

[0092] If so, adjust the state of the next corresponding CPU1 pin group and CPU2 pin group. During the state adjustment process of each pin group, repeat the above steps of adjusting the state of the pins of the CPU1 pin group and the CPU2 pin group until the state adjustment of all corresponding CPU1 pin groups and CPU2 pin groups is completed, that is, the state of the CPU2 receiving pin is adjusted to be the same as the state of the corresponding CPU1 sending pin, and the state of the CPU1 receiving pin is adjusted to be the same as the state of the corresponding CPU2 sending pin.

[0093] Both CPU1 and CPU2 include multiple pin groups. The multiple pin groups are adjusted to appropriate states to achieve CPU1 and CPU2 signal synchronization, providing basic support for subsequent data synchronization.

[0094] In some embodiments, the information synchronization module is further configured to:

[0095] The state of a CPU1 sending pin of a CPU1 pin group is adjusted to a first pin state, and the state of a CPU2 sending pin in a CPU2 pin group corresponding to the CPU1 pin group is adjusted to a first pin state. It is determined whether the state of a CPU2 receiving pin of the CPU2 pin group is adjusted to be the same as the state of a CPU1 sending pin in the CPU1 pin group within a first preset time, and whether the state of a CPU1 receiving pin in the CPU1 pin group is adjusted to be the same as the state of a CPU2 sending pin of the CPU2 pin group.

[0096] If so, adjust the state of the next corresponding CPU1 pin group and CPU2 pin group. During the adjustment process of each pin group state, repeat the first state adjustment step of the pins of the CPU1 pin group and the CPU2 pin group above until the states of all corresponding CPU1 pin groups and CPU2 pin groups are adjusted to the first pin state, that is, the state of the CPU2 receiving pin and the corresponding state of the CPU1 sending pin are both adjusted to the first state, and the state of the CPU1 receiving pin and the corresponding state of the CPU2 sending pin are both adjusted to the first state.

[0097] After each CPU1 pin group and CPU2 pin group achieves first pin state synchronization, the two are further adjusted to second pin state synchronization.

[0098] Further adjusting the state of the CPU1 sending pin of a CPU1 pin group to a second pin state, and adjusting the state of the CPU2 sending pin in the CPU2 pin group corresponding to the CPU1 pin group to a second pin state. Determining whether the state of the CPU2 receiving pin of the CPU2 pin group is adjusted to be the same as the state of the CPU1 sending pin in the CPU1 pin group within a first preset time, and whether the state of the CPU1 receiving pin in the CPU1 pin group is adjusted to be the same as the state of the CPU2 sending pin of the CPU2 pin group.

[0099] If so, adjust the state of the next corresponding CPU1 pin group and CPU2 pin group. During the adjustment process of each pin group state, repeat the second state adjustment step of the pins of the CPU1 pin group and the CPU2 pin group until the states of all corresponding CPU1 pin groups and CPU2 pin groups are adjusted to the second pin state, that is, the state of the CPU2 receiving pin and the corresponding state of the CPU1 sending pin are both adjusted to the second state, and the state of the CPU1 receiving pin and the corresponding state of the CPU2 sending pin are both adjusted to the second state.

[0100] During the signal synchronization process, the states of the dual CPU pin groups are adjusted in sequence to pull the two CPUs to the same state and reduce delays. By adjusting the pin states of CPU1 and CPU2 multiple times, the time difference between the two CPUs can be reduced.

[0101] In some embodiments, the first pin state is a high level, and the second pin state is a low level.

[0102] The first pin state and the second pin state are related to the default level state, the first pin state is opposite to the default level state, and the second pin state is the same as the default level state. When the default level state is a low level, the first pin state is a high level, and the second pin state is a low level. When the default level state is a high level, the first pin state is a low level, and the second pin state is a high level.

[0103] It should be noted that the above modules can be functional modules or program modules, and can be implemented by software or hardware. For modules implemented by hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0104] This embodiment also provides a dual-CPU data synchronization method. Figure 2 is a flow chart of a dual CPU data synchronization method according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0105] Information synchronization step S201, adjusting the pin state of the CPU1 sending pin, adjusting the pin state of the CPU2 sending pin, judging whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matching the receiving pin within the first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matching the receiving pin. After the states are adjusted to be the same, starting the synchronous data transmission step.

[0106] In the data transmission step S202, CPU1 sends a data to be synchronized to CPU2, and CPU2 sends another data to be synchronized to CPU1, and it is determined whether CPU1 and CPU2 have completed the transmission, and the data sent by the other party are received.

[0107] Through the above steps, the pin state is adjusted to achieve the state synchronization of the dual CPUs, and the data transmission is used to achieve the data synchronization of the dual CPUs. CPU1 and CPU2 are adjusted to the same working state, so that the processing speed is faster and the efficiency is higher.

[0108] In some embodiments, the information synchronization step further includes:

[0109] S11, adjust the state of the first CPU1 sending pin to the first pin state, and the state of the first CPU2 sending pin to the first pin state; determine whether the state of the first CPU2 receiving pin matching the first CPU1 sending pin is adjusted to be the same as the state of the first CPU1 sending pin, and whether the state of the first CPU1 receiving pin is adjusted to be the same as the state of the first CPU2 sending pin within the first preset time, and if so, adjust the state of the next CPU1 sending pin and the next CPU2 sending pin to the first pin state, and determine again whether the states of the corresponding CPU2 receiving pin and CPU1 receiving pin are both adjusted to the first pin state; repeat the execution until the states of all pins in the matching CPU1 pin group and the pins in the CPU2 pin group are in the first pin state.

[0110] S12, adjust the state of the first CPU1 sending pin to the second pin state, and the state of the first CPU2 sending pin to the second pin state; determine whether the state of the first CPU2 receiving pin matching the first CPU1 sending pin is adjusted to be the same as the state of the first CPU1 sending pin, and whether the state of the first CPU1 receiving pin is adjusted to be the same as the state of the first CPU2 sending pin within the first preset time, and if so, adjust the state of the next CPU1 sending pin and the next CPU2 sending pin to the second pin state, and determine whether the states of the corresponding CPU2 receiving pin and CPU1 receiving pin are both adjusted to the first pin state; repeat the execution until the states of all pins in the matching CPU1 pin group and the pins in the CPU2 pin group are in the second pin state.

[0111] There are multiple pins in CPU1 and CPU2. To achieve signal synchronization, multiple pins need to be adjusted to the same state. After multiple adjustments, CPU1 and CPU2 are synchronized, which can better handle tasks and increase the safety of operation.

[0112] In some embodiments, the data transmission step includes:

[0113] S21, CPU1 sends first data to be synchronized, and CPU1 sends second data to be synchronized.

[0114] S22: Within the second preset time, CPU1 and CPU2 determine whether their respective SCI sending registers are cleared.

[0115] S23, within the second preset time, CPU1 and CPU2 determine whether their respective SCIDMA reception completion flags are set.

[0116] S24, CPU1 reads the second data to be synchronized, and CPU2 reads the first data to be synchronized.

[0117] By judging whether the SCI transmit register is cleared and the SCIDMA receive completion flag is set, it is determined whether CPU1 and CPU2 have sent data to each other. Further, CPU1 and CPU2 read the data to achieve data synchronization. This is conducive to the dual CPU synchronous processing of tasks and improves work efficiency.

[0118] In one embodiment, during the program initialization process, CPU1 and CPU2 set the SCI data receiving mode to DMA, and set the number of bytes to be sent N, the same serial port baud rate, and the same number of bytes C in the DMA receiving buffer, wherein the number of bytes C in the DMA receiving buffer is greater than the number of bytes N to be sent.

[0119] The second preset time is twice the time taken to send N bytes at a baud rate, that is, twice the time taken to send data in step S21.

[0120] In one embodiment, Figure 3 , the sending pins of CPU1 include: CPU1.COUPLE1.GPIOA, CPU1.COUPLE2.GPIOA; the receiving pins of CPU1 include: CPU1.COUPLE1.GPIOB, CPU1.COUPLE2.GPIOB. The sending pins of CPU2 include: CPU2.COUPLE1.GPIOA, CPU2.COUPLE2.GPIOA; the receiving pins of CPU2 include: CPU2.COUPLE1.GPIOB, CPU2.COUPLE2.GPIOB.

[0121] The state of CPU2.COUPLE1.GPIOB will be adjusted according to the state of CPU1.COUPLE1.GPIOA. The state of CPU1.COUPLE1.GPIOB will be adjusted according to the state of CPU2.COUPLE1.GPIOA. The state of CPU2.COUPLE2.GPIOB will be adjusted according to the state of CPU1.COUPLE2.GPIOA. The state of CPU1.COUPLE2.GPIOB will be adjusted according to the state of CPU2.COUPLE2.GPIOA.

[0122] To achieve dual CPU data synchronization, dual CPU signal synchronization and data transmission are required.

[0123] When the default level is low, such as Figure 4 , the signal synchronization process includes:

[0124] (1) CPU1 adjusts the CPU1.COUPLE1.GPIOA state to a high level state, and waits for the CPU1.COUPLE1.GPIOB pin state to be pulled high. CPU2 adjusts the CPU2.COUPLE1.GPIOA state to a high level state, and waits for the CPU2.COUPLE1.GPIOB pin state to be pulled high. If both CPU1.COUPLE1.GPIOB and CPU2.COUPLE1.GPIOB are pulled high within the first preset time, the next step is executed, otherwise the synchronization fails.

[0125] (2) CPU1 adjusts the CPU1.COUPLE2.GPIOA state to a high level state, and waits for the CPU1.COUPLE2.GPIOB pin state to be pulled high. CPU2 adjusts the CPU2.COUPLE2.GPIOA state to a high level state, and waits for the CPU2.COUPLE2.GPIOB pin state to be pulled high. If both CPU1.COUPLE2.GPIOB and CPU2.COUPLE2.GPIOB are pulled high within the first preset time, the next step is executed, otherwise the synchronization fails.

[0126] (3) CPU1 adjusts the state of CPU1.COUPLE1.GPIOA to a low level state, and waits for the state of CPU1.COUPLE1.GPIOB pin to be pulled low. CPU2 adjusts the state of CPU2.COUPLE1.GPIOA to a low level state, and waits for the state of CPU2.COUPLE1.GPIOB pin to be pulled low. If both CPU1.COUPLE1.GPIOB and CPU2.COUPLE1.GPIOB are pulled low within the first preset time, the next step is executed, otherwise the synchronization fails.

[0127] (4) CPU1 adjusts the CPU1.COUPLE2.GPIOA state to a low level state, and waits for the CPU1.COUPLE2.GPIOB pin state to be pulled low. CPU2 adjusts the CPU2.COUPLE2.GPIOA state to a low level state, and waits for the CPU2.COUPLE2.GPIOB pin state to be pulled low. If both CPU1.COUPLE2.GPIOB and CPU2.COUPLE2.GPIOB are pulled low within the first preset time, signal synchronization is completed.

[0128] After signal synchronization is completed, CPU1 and CPU2 are in the same state and data transmission can be performed.

[0129] like Figure 3, CPU1 sets CPU1.SCITX for data transmission and CPU1.SCIRX for data reception. CPU2 sets CPU2.SCITX for data transmission and CPU2.SCIRX for data reception.

[0130] like Figure 5 , the data transmission process includes:

[0131] (1) During program initialization, CPU1 and CPU2 set the SCI data receiving mode to DMA and set the number of bytes to be sent, N, the same serial port baud rate and the same number of bytes in the DMA receive buffer, C. The number of bytes in the DMA receive buffer, C, is greater than the number of bytes to be sent, N.

[0132] (2) CPU1 sends N bytes of data to be synchronized via CPU1.SCITX. CPU2 sends N bytes of synchronized data via CPU2.SCITX.

[0133] (3) CPU1 and CPU2 check whether their respective SCI sending registers are cleared. If they are cleared within the second preset time, it means that the data is sent successfully, otherwise the data synchronization fails.

[0134] (4) CPU1 and CPU2 check whether their respective SCIDMA reception completion flags are set. If they are set within the second preset time, it means that data DMA reception is completed, otherwise the data synchronization fails.

[0135] (5) CPU1 and CPU2 read N bytes of data from their respective DMA receive buffers.

[0136] After the data transmission is completed, dual CPU data synchronization is achieved.

[0137] In the rail transit industry, for functions with a functional safety level of SIL4, dual CPUs are required for simultaneous processing. This application uses dual CPU data synchronization to increase product safety and improve the accuracy of data processing. At the same time, this application also takes into account the possibility of homogeneous and heterogeneous CPUs, and information interaction through pins is more stable and reliable, and has a wider range of applications.

[0138] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A dual CPU data synchronization system, characterized in that: include: CPU1, comprising a first signal unit, a first transmission unit and a first state setting unit, wherein the first signal unit comprises a pin group, each pin group comprises a CPU1 sending pin and a CPU1 receiving pin; the first state setting unit is used to set the state of the CPU1 sending pin; CPU2, comprising a second signal unit, a second transmission unit and a second state setting unit, wherein the second signal unit comprises a pin group, each pin group comprises a CPU2 sending pin and a CPU2 receiving pin; the second state setting unit is used to set the state of the CPU2 sending pin; Among them, one CPU1 transmit pin matches one CPU2 receive pin, and one CPU1 receive pin matches one CPU2 transmit pin; The information synchronization module is configured to adjust the pin state of the CPU1 sending pin through the first state setting unit, adjust the pin state of the CPU2 sending pin through the second state setting unit, and determine whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matched with the pin within a first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matched with the pin; The data transmission module is configured to send a data to be synchronized to CPU2 through the first transmission unit, send another data to be synchronized to CPU1 through the second transmission unit, determine whether CPU1 and CPU2 have completed the transmission, and receive the data sent by the other party.

2. The dual CPU data synchronization system according to claim 1, characterized in that: The information synchronization module is further configured to: Adjust the state of the CPU1 sending pin to the first pin through the first state setting unit, adjust the state of the CPU2 sending pin to the first pin through the second state setting unit, and judge whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matched with the pin within the first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matched with the pin; If so, adjust the state of the CPU1 sending pin to the second pin through the first state setting unit, and adjust the state of the CPU2 sending pin to the second pin through the second state setting unit, and determine whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin that matches the pin within the first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin that matches the pin.

3. The dual CPU data synchronization system according to claim 1, characterized in that: The data transmission module also includes: The first judgment unit is configured to judge whether the sending register of CPU1 and the sending register of CPU2 are both cleared within a second preset time; The second judgment unit is configured to judge whether the DMA receiving completion flag of CPU1 and the DMA receiving completion flag of CPU2 are both set within a second preset time.

4. The dual CPU data synchronization system according to claim 1, characterized in that: The first transmission unit and the second transmission unit both include: A data transmission pin, and a data reception pin; The data sending pin of the first transmission unit corresponds to the data receiving pin of the second transmission unit; The data receiving pin of the first transmission unit corresponds to the data sending pin of the second transmission unit.

5. The dual CPU data synchronization system according to claim 1 or 2, characterized in that: Both CPU1 and CPU2 include multiple pin groups, and each pin group of CPU1 corresponds to a pin group of CPU2; The information synchronization module is configured to adjust the pin states corresponding to the CPU1 pin group and the CPU2 pin group, including: Adjust the state of a CPU1 transmit pin of a CPU1 pin group, and the state of a CPU2 transmit pin in a CPU2 pin group corresponding to the CPU1 pin group; determine whether the state of a CPU2 receive pin of the CPU2 pin group is adjusted to be the same as the state of a CPU1 transmit pin in the CPU1 pin group within a first preset time, and whether the state of a CPU1 receive pin in the CPU1 pin group is adjusted to be the same as the state of a CPU2 transmit pin of the CPU2 pin group; If so, the state of the next corresponding CPU1 pin group and CPU2 pin group is adjusted until the state adjustment of all corresponding CPU1 pin groups and CPU2 pin groups is completed.

6. The dual CPU data synchronization system according to claim 5, characterized in that: The information synchronization module is further configured to: Adjust the state of a CPU1 sending pin of a CPU1 pin group to a first pin state, and adjust the state of a CPU2 sending pin in a CPU2 pin group corresponding to the CPU1 pin group to a first pin state; determine whether the state of a CPU2 receiving pin of the CPU2 pin group is adjusted to be the same as the state of a CPU1 sending pin in the CPU1 pin group within a first preset time, and whether the state of a CPU1 receiving pin in the CPU1 pin group is adjusted to be the same as the state of a CPU2 sending pin of the CPU2 pin group; If yes, then adjust the state of the next corresponding CPU1 pin group and CPU2 pin group until the states of all corresponding CPU1 pin groups and CPU2 pin groups are adjusted in the first pin state; Further adjusting the state of a CPU1 sending pin of a CPU1 pin group to a second pin state, and the state of a CPU2 sending pin in a CPU2 pin group corresponding to the CPU1 pin group to a second pin state; determining whether the state of a CPU2 receiving pin of the CPU2 pin group is adjusted to be the same as the state of a CPU1 sending pin in the CPU1 pin group within a first preset time, and whether the state of a CPU1 receiving pin in the CPU1 pin group is adjusted to be the same as the state of a CPU2 sending pin of the CPU2 pin group; If so, the state of the next corresponding CPU1 pin group and CPU2 pin group is adjusted until the states of all corresponding CPU1 pin groups and CPU2 pin groups are adjusted in the second pin state.

7. The dual CPU data synchronization system according to claim 2 or 6, characterized in that: The first pin state is a high level, and the second pin state is a low level.

8. A dual CPU data synchronization method, characterized in that: include: An information synchronization step, adjusting the pin state of the CPU1 sending pin, adjusting the pin state of the CPU2 sending pin, and determining whether the state of the CPU1 receiving pin is converted to the same state as the CPU2 sending pin matching the receiving pin within a first preset time, and whether the state of the CPU2 receiving pin is converted to the same state as the CPU1 sending pin matching the receiving pin; In the data transmission step, CPU1 sends a data to be synchronized to CPU2, and CPU2 sends another data to be synchronized to CPU1, and it is determined whether CPU1 and CPU2 have completed the transmission, and the data sent by the other party are received.

9. The dual CPU data synchronization method according to claim 8, characterized in that: The information synchronization step further comprises: S11, adjusting the state of the first CPU1 sending pin to the first pin state, and the state of the first CPU2 sending pin to the first pin state; judging whether the state of the first CPU2 receiving pin matching the first CPU1 sending pin is adjusted to be the same as the state of the first CPU1 sending pin within the first preset time, and whether the state of the first CPU1 receiving pin is adjusted to be the same as the state of the first CPU2 sending pin, if so, adjusting the state of the next CPU1 sending pin and the next CPU2 sending pin to the first pin state, and judging again whether the states of the corresponding CPU2 receiving pin and CPU1 receiving pin are both adjusted to the first pin state; repeating the execution until the states of all the pins in the matching CPU1 pin group and the pins in the CPU2 pin group are in the first pin state; S12, adjust the state of the first CPU1 sending pin to the second pin state, and the state of the first CPU2 sending pin to the second pin state; determine whether the state of the first CPU2 receiving pin matching the first CPU1 sending pin is adjusted to be the same as the state of the first CPU1 sending pin, and whether the state of the first CPU1 receiving pin is adjusted to be the same as the state of the first CPU2 sending pin within the first preset time, and if so, adjust the state of the next CPU1 sending pin and the next CPU2 sending pin to the second pin state, and determine whether the states of the corresponding CPU2 receiving pin and CPU1 receiving pin are both adjusted to the first pin state; repeat the execution until the states of all pins in the matching CPU1 pin group and the pins in the CPU2 pin group are in the second pin state.

10. The dual CPU data synchronization method according to claim 8, characterized in that: The data transmission step comprises: S21, CPU1 sends the first data to be synchronized, and CPU1 sends the second data to be synchronized; S22, within the second preset time, CPU1 and CPU2 determine whether their respective SCI sending registers are cleared; S23, within the second preset time, CPU1 and CPU2 determine whether their respective SCIDMA reception completion flags are set; S24, CPU1 reads the second data to be synchronized, and CPU2 reads the first data to be synchronized.

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