Inspection tool generation method and device, equipment, storage medium and program product

Abstract

The invention relates to an inspection tool generation method and device, equipment, a storage medium and a program product. The method comprises the following steps: acquiring a verification information set of a target verification chip, wherein the verification information set comprises functional verification information of each verification object needing to be verified in the target verification chip; according to the function verification information of each verification object in the verification information set, generating at least one of a test end checker and a reset end checker corresponding to each verification object as a check tool of each verification object; wherein the test ending checker is used for controlling the function state of the verification object to be a preset state under the condition that verification of the verification object is finished, and the reset ending checker is used for controlling the function state of the verification object to be the preset state under the condition that verification of the verification object is reset. By adopting the method, the inspection tool required by chip verification can be efficiently obtained.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a method, device, equipment, storage medium and program product for generating an inspection tool. Background Art

[0002] During the chip verification process, a checker tool is needed in some test phases of the current verification object in the chip to ensure that the internal state of the verification object returns to the expected value.

[0003] In the related art, for each verification object, developers are required to write corresponding inspection tools to be used in the verification process. However, the process of writing inspection tools is time-consuming, resulting in low efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a method, device, equipment, storage medium and program product for efficiently generating inspection tools required for chip verification in order to solve the above technical problems.

[0005] In a first aspect, the present application provides a method for generating an inspection tool. The method comprises:

[0006] Acquire a verification information set of a target verification chip, where the verification information set includes functional verification information of each verification object to be verified in the target verification chip;

[0007] Generate at least one of a test end checker and a reset end checker corresponding to each verification object as a check tool for each verification object according to the functional verification information of each verification object in the verification information set;

[0008] Among them, the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

[0009] In one embodiment, the functional verification information includes at least one of the following:

[0010] Object identifier; the object identifier is the name of the verification object;

[0011] First signal name: the first signal name is the signal name of the function signal corresponding to the verification object;

[0012] Signal expected value; signal expected value is the expected value of the functional signal corresponding to the verification object; the expected value is used to characterize the signal value that the functional signal is expected to achieve when the target function corresponding to the functional signal is correctly realized;

[0013] The second signal name; the second signal name is the signal name of the reset signal corresponding to the function signal corresponding to the verification object; the reset signal is used to reset the signal value of the corresponding function signal.

[0014] In one embodiment, generating at least one of a test end checker and a reset end checker corresponding to each verification object according to the functional verification information of each verification object in the verification information set includes:

[0015] For each verification object, judging whether an inspection tool has been generated for the verification object according to the object identifier; wherein the generated inspection tool has been associated with the corresponding object identifier;

[0016] If a checking tool has not been generated for the verification object, a test end checker corresponding to the verification object is generated based on the first signal name and signal expected value corresponding to the verification object; and, if it is determined that a reset end checker corresponding to the verification object needs to be generated, a reset end checker corresponding to the verification object is generated based on the first signal name, signal expected value and second signal name corresponding to the verification object.

[0017] In one embodiment, the method further comprises:

[0018] Determine whether the signal name of the reset signal included in the second signal name is empty;

[0019] If it is determined that the signal name of the reset signal included in the second signal name is not empty, it is determined that a reset end checker corresponding to the verification object needs to be generated.

[0020] In one embodiment,

[0021] The test completion checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when the verification of the verification object is completed, and output a first error message if they are not equal, and the first error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when the verification of the verification object is completed;

[0022] The reset end checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when the verification object verification is reset according to the reset signal corresponding to the second signal name, and output a second error message if they are not equal. The second error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when the verification object verification is reset.

[0023] In one embodiment, the method further comprises:

[0024] Generate instantiation code;

[0025] Using the instantiation code, the checking tool is instantiated into each verification object.

[0026] In a second aspect, the present application also provides a device for generating an inspection tool. The device comprises:

[0027] An information acquisition module, used to acquire a verification information set of a target verification chip, wherein the verification information set includes functional verification information of each verification object to be verified in the target verification chip;

[0028] A tool generation module, used to generate at least one of a test end checker and a reset end checker corresponding to each verification object according to the functional verification information of each verification object in the verification information set, as a check tool for each verification object;

[0029] Among them, the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

[0030] In one embodiment, the functional verification information includes at least one of the following:

[0031] Object identifier; the object identifier is the name of the verification object;

[0032] First signal name: the first signal name is the signal name of the function signal corresponding to the verification object;

[0033] Signal expected value; signal expected value is the expected value of the functional signal corresponding to the verification object; the expected value is used to characterize the signal value that the functional signal is expected to achieve when the target function corresponding to the functional signal is correctly realized;

[0034] The second signal name; the second signal name is the signal name of the reset signal corresponding to the function signal corresponding to the verification object; the reset signal is used to reset the signal value of the corresponding function signal.

[0035] In one embodiment, the tool generation module is specifically used to:

[0036] For each verification object, judging whether an inspection tool has been generated for the verification object according to the object identifier; wherein the generated inspection tool has been associated with the corresponding object identifier;

[0037] If a checking tool has not been generated for the verification object, a test end checker corresponding to the verification object is generated based on the first signal name and signal expected value corresponding to the verification object; and, if it is determined that a reset end checker corresponding to the verification object needs to be generated, a reset end checker corresponding to the verification object is generated based on the first signal name, signal expected value and second signal name corresponding to the verification object.

[0038] In one of the embodiments, the apparatus further comprises a determining module, configured to:

[0039] Determine whether the signal name of the reset signal included in the second signal name is empty;

[0040] If it is determined that the signal name of the reset signal included in the second signal name is not empty, it is determined that a reset end checker corresponding to the verification object needs to be generated.

[0041] In one embodiment,

[0042] The test completion checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when the verification of the verification object is completed, and output a first error message if they are not equal, and the first error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when the verification of the verification object is completed;

[0043] The reset end checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when the verification object verification is reset according to the reset signal corresponding to the second signal name, and output a second error message if they are not equal. The second error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when the verification object verification is reset.

[0044] In one of the embodiments, the apparatus further comprises an instantiation module, configured to:

[0045] Generate instantiation code; use the instantiation code to instantiate the inspection tool into each verification object.

[0046] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the methods described in the first aspect when executing the computer program.

[0047] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any one of the methods described in the first aspect above.

[0048] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of any one of the methods described in the first aspect are implemented.

[0049] The above-mentioned inspection tool generation method, device, equipment, storage medium and program product obtain the verification information set of the target verification chip including the functional verification information of each verification object to be verified in the target verification chip, thereby generating at least one of the test end checker and the reset end checker corresponding to each verification object according to the functional verification information of each verification object in the verification information set as the inspection tool for each verification object; wherein the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset. In this way, the inspection tools required by each verification object in the test phase and the reset phase can be automatically generated without manual writing, thereby improving the efficiency of the generation of inspection tools. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A schematic diagram of a flow chart of a method for generating an inspection tool in one embodiment;

[0052] Figure 2 A schematic diagram of a flow chart of generating an inspection tool in one embodiment;

[0053] Figure 3 A flowchart of determining whether to generate a reset end checker in one embodiment;

[0054] Figure 4 It is a structural block diagram of an inspection tool generating device in one embodiment;

[0055] Figure 5 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0056] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It should be understood that many specific details are set forth in the following description to facilitate a full understanding of the present application, but the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0058] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0059] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0060] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0061] During the chip verification process, a checker tool is required to ensure that the internal state of the verification object returns to the expected value in some test phases of the current verification object in the chip. In the related art, for each verification object, developers need to write a corresponding checker tool to act in the verification process. However, the process of writing a checker tool is time-consuming and leads to low efficiency.

[0062] In view of this, an embodiment of the present application provides a method for generating an inspection tool, which can improve the generation efficiency of the inspection tools required for chip verification.

[0063] It should be noted that the inspection tool generation method provided in the embodiment of the present application may be executed by an inspection tool generation device, which may be implemented as part or all of an electronic device through software, hardware, or a combination of software and hardware. The electronic device may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, etc., and the embodiment of the present application does not limit the type of the electronic device. In the following method embodiments, the execution subject is described as an electronic device.

[0064] In one embodiment, Figure 1 As shown, a method for generating an inspection tool is provided, comprising the following steps:

[0065] Step 101: Acquire a verification information set of a target verification chip. The verification information set includes functional verification information of each verification object to be verified in the target verification chip.

[0066] The target verification chip refers to a chip that currently needs to be verified. For example, the target verification chip may be a SOC (system on chip), etc., which is not fully exemplified here.

[0067] All modules to be verified in the target verification chip can be used as verification objects. Exemplarily, the target verification chip includes multiple subsystems, each of which may include a single or multiple register modules, and each of which may also include a single or multiple design modules. Furthermore, the register module may also include multiple sub-register modules, all of which can be verified and tested, and therefore can all be used as verification objects.

[0068] It is understandable that, during the chip verification process, all modules in the target verification chip can be verified, and all modules can be used as verification objects. Accordingly, the verification information set includes the functional verification information of all verification objects. Alternatively, during the chip verification process, only some modules can be verified, and these modules can be used as verification objects. Accordingly, the verification information set includes the functional verification information of these verification objects.

[0069] The functional verification information includes some information related to the target function executed by the verification object to be verified, such as the name of the signal or the signal value of the signal required for the verification target object to execute a certain target function.

[0070] Optionally, the electronic device may obtain the verification information set by statistics in advance according to the design information and verification process of the target verification chip.

[0071] Step 102 , generating at least one of a test completion checker and a reset completion checker corresponding to each verification object according to the functional verification information of each verification object in the verification information set as a checking tool for each verification object.

[0072] In other words, at least one of the test end checker and the reset end checker required by each verification object can be generated respectively.

[0073] The End of Test (EOT) checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed. The End of Reset (EOR) checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

[0074] Typically, the end of chip verification marks the completion of a stage and preparation for chip production; while chip verification reset is the process of modifying and re-verifying the design when necessary to ensure that the chip can meet changing requirements and standards. Both steps are an integral part of the chip design process and are critical to ensuring the quality and performance of the chip. For example, in some cases, it may be necessary to reset a verified chip design and restart the verification process. This may be due to the discovery of new design defects or because requirements have changed and the design needs to be modified.

[0075] Here, the test end checker is used to make the internal state of the verification object return to the expected value in the verification end stage to become the preset state; the reset end checker is used to make the internal state of the verification object return to the expected value in the verification reset stage to become the preset state.

[0076] Among them, the generated test end checker and reset end checker can be implemented in the form of code, that is, a section of code is generated as the test end checker of the verification object for controlling the functional state of the verification object to a preset state when the verification of the verification object is completed; and another section of code is generated as the reset end checker of the verification object for controlling the functional state of the verification object to a preset state when the verification of the verification object is reset.

[0077] The electronic device may execute the test end checker and the reset end checker during the verification phase.

[0078] The above-mentioned inspection tool generation method obtains the verification information set of the target verification chip including the functional verification information of each verification object to be verified in the target verification chip, thereby generating at least one of the test end checker and the reset end checker corresponding to each verification object according to the functional verification information of each verification object in the verification information set, as the inspection tool for each verification object; wherein the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset. In this way, the inspection tools required for each verification object in the test phase and the reset phase can be automatically generated without manual writing, thereby improving the efficiency of the inspection tool generation. In addition, the workload of developers is simplified, a consistent code style is maintained, and inspection is convenient.

[0079] In one embodiment, the function verification information includes at least one of the following:

[0080] 1. Object ID. The object ID is the name of the verification object. For example, if the verification object is the first subsystem and the name of the first subsystem is sys1, the object ID is sys1.

[0081] 2. First signal name. The first signal name is the signal name of the function signal corresponding to the verification object. Optionally, for each verification object, it may correspond to multiple functions, each function may correspond to a single or multiple function signals, and the corresponding function is realized by each function signal.

[0082] 3. Signal expected value. The signal expected value is the expected value of the functional signal corresponding to the verification object; the expected value is used to characterize the signal value that the functional signal is expected to achieve when the target function corresponding to the functional signal is correctly implemented. For example, the signal value of the functional signal may be 0 or 1, but when the target function corresponding to the functional signal is correctly implemented, the signal value of the functional signal is required to be 1, then the signal expected value is 1. It is understandable that each functional signal can correspond to an expected value. Optionally, the expected value can also be a level value (for example, 0 for low level and 1 for high level) or a macro definition, etc.

[0083] 4. Second signal name. The second signal name is the signal name of the reset signal corresponding to the function signal corresponding to the verification object; the reset signal is used to reset the signal value of the corresponding function signal. For example, if the signal value of a function signal is 0, its corresponding reset signal needs to be used to reset the signal value of the function signal to 1.

[0084] In one embodiment, the verification information set includes the functional verification information of each verification object to be verified in the form of a table.

[0085] Taking the example that the function verification information includes the object identifier of the verification object, the first signal name, the signal expected value, and the second signal name, Table 1 exemplarily shows a table diagram of a verification information set:

[0086] Table 1

[0087]

[0088] In Table 1, "ra", "Xcore_ra_setup_raster_intf" and so on in the object identification column are all names of verification objects; "Ra_bsc_busy", "SE_RA_send" and so on in the first signal name column are all first signal names; the signal expected value column has signal expected values ​​0 and 1, as well as "'RA_DPF_FINAL_QUAD_CREDIT_NUM" and "'RA_RM_PS_WAVE_CREDIT_NUM" macro definitions. The second signal name column "bsc_ra_hard_reset" and "resetb" are the names of reset signals. For example, the ra module in the first row corresponds to a function signal named "Ra_bsc_busy", the expected value of which is 0, and the name of the reset signal that resets the function signal is "bsc_ra_hard_reset". In addition, the second, third and fourth rows are verification information of the module named “Xcore_ra_setup_raster_intf”. It can be seen that the module corresponds to function signals named “SE_RA_send”, “SE_RA_free” and “SE_RA_ciken”.

[0089] Optionally, as shown in Table 1, the verification information of the same verification object is arranged consecutively in order.

[0090] Optionally, the reset signals corresponding to different functional signals of different modules may be the same.

[0091] In the embodiment of the present application, by obtaining simple information of each verification object, such as object identification, signal expected value, first signal name and second signal name, a verification object inspection tool can be quickly generated. The process is low in complexity and high in efficiency and accuracy. In addition, the function verification information is collected based on the verification information set table, which facilitates the electronic device to identify each function verification information and ensures that the identification process is accurate and without omissions.

[0092] In one embodiment, Figure 2 A flow chart of generating an inspection tool is shown. According to the functional verification information of each verification object in the verification information set, at least one of a test end checker and a reset end checker corresponding to each verification object is generated, including:

[0093] Step 201: for each verification object, judging whether a check tool has been generated for the verification object according to the object identifier, wherein the generated check tool has been associated with the corresponding object identifier.

[0094] For example, when all functional verification information of the ra module in Table 1 is read and a test end checker and / or a reset end checker of the ra module is generated, the generated test end checker and / or reset end checker is associated with "ra".

[0095] After reading the function verification information of the Xcore_ra_setup_raster_intf module in the second row of Table 1, it is found that there is no inspection tool bound to the object identifier, so it is determined that the inspection tool of the Xcore_ra_setup_raster_intf module has not been generated.

[0096] Step 202: If a check tool is not generated for the verification object, a test completion checker corresponding to the verification object is generated according to the first signal name and signal expected value corresponding to the verification object.

[0097] That is, the object identifier is read first, and then the first signal name and the signal expected value are read to generate a test completion checker.

[0098] In one implementation, for a module containing multiple functional signals, the module corresponds to multiple first signal names. Then, after reading all functional verification information of the module (that is, reading all first signal names, signal expected values, and second signal names), an inspection tool for the module can be generated.

[0099] Taking the function verification information of the Xcore_ra_setup_raster_intf module from the second to the fourth rows in Table 1 as an example, read the object identifier "Xcore_ra_setup_raster_intf" in the second row, then read the first signal name "SE_RA_send", the signal expected value "0" and the second signal name "resetb" in the second row; then read the object identifier in the third row. If the object identifier is empty or "Xcore_ra_setup_raster_intf" (the repeated object identifiers in the third and fourth rows are omitted in Table 1), the function verification information in the third row is the same as the function verification information in the second row. Belong to the same module, that is, they all belong to the Xcore_ra_setup_raster_intf module, then continue to read the first signal name "SE_RA_free", the signal expected value "0" and the second signal name "resetb" of the third line, and similarly continue to read the first signal name "SE_RA_ciken", the signal expected value "0" and the second signal name "resetb" of the fourth line, and continue to read the object identifier of the fifth line. If it is determined that the object identifier is inconsistent with the object identifier of the second line, it is determined that the functional verification information of the Xcore_ra_setup_raster_intf module has been read, and the inspection tool of the module is generated. That is, a test end checker is generated according to each first signal name and signal expected value. And according to each first signal name, signal expected value and second signal name, a reset end checker corresponding to the verification object can be generated.

[0100] In another implementation, the function verification information of each row may be read row by row, and a checking tool for the module corresponding to the object identifier of each row may be generated according to the function verification information of each row.

[0101] Step 203, when it is determined that a reset end checker corresponding to the verification object needs to be generated, a reset end checker corresponding to the verification object is generated according to the first signal name, signal expected value and second signal name corresponding to the verification object.

[0102] Among them, whether it is necessary to generate a reset end checker corresponding to the verification object can be determined according to the first signal name.

[0103] Please refer to Figure 3 , showing a flow chart of determining whether to generate a reset end checker.

[0104] Step 301: Determine whether the signal name of the reset signal included in the second signal name is empty.

[0105] Step 302: If it is determined that the signal name of the reset signal included in the second signal name is not empty, it is determined that a reset end checker corresponding to the verification object needs to be generated.

[0106] It can be understood that the signal names of the reset signals in Table 1 are not empty.

[0107] In addition, if the signal name of the reset signal is empty, it means that there is no need to use the reset signal to reset the functional signal, so there is no reset process when the functional signal is executed, and therefore there is no need to generate a reset end checker for the functional signal.

[0108] In the case where it is determined that a reset end checker corresponding to the verification object needs to be generated, a reset end checker is generated. The second signal name can be used to indicate the timing when the reset end checker controls the functional state of the verification object to be a preset state, and the signal expected value and the first signal name are used to make the reset end checker control the functional state of the verification object to be a preset state.

[0109] For example, when the signal value of the reset signal corresponding to the second signal name changes from a reset value to a non-reset value, the reset end checker checks whether the signal value of the function signal corresponding to the first signal name is equal to the signal expected value. Here, the reset end checker can determine when it is the signal value of the reset signal and when it is the non-reset value of the reset signal according to the second signal name. Exemplarily, the reset value of the reset signal can be set to a low level value (for example, 0) by default; if "~" is added before the second signal name, it means that the high level value (for example, 1) is the reset value.

[0110] In one embodiment, a test completion checker is used to determine whether the signal value of a functional signal corresponding to a first signal name is equal to an expected signal value when verification of a verification object is completed, and to output a first error message if they are not equal. The first error message is used to indicate that the signal value of a functional signal corresponding to the first signal name is not equal to the expected signal value when verification of the verification object is completed.

[0111] That is, from the function state to the signal value of the function signal, the preset state is that the signal value of the function signal is the corresponding signal expected value. Since the test end checker is generated according to the first signal name and the signal expected value, it can call the corresponding function signal according to the first signal name at the end of the test, and determine whether the current signal value of the function signal is the signal expected value. If not, it outputs the first error message. In this way, the electronic device can determine that there is an error in the verification end stage during the chip verification process, so as to make subsequent adjustments.

[0112] In one embodiment, the reset end checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when determining that the verification object is reset based on the reset signal corresponding to the second signal name, and output a second error message if they are not equal. The second error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when the verification object is reset.

[0113] That is, since the reset end checker is generated according to the first signal name, the second signal name and the signal expected value, it can call the corresponding function signal according to the first signal name after the reset, and determine whether the current signal value of the function signal is the expected value of the signal. If not, it outputs the second error message.

[0114] In the embodiment of the present application, the electronic device uses an automatically generated inspection tool to ensure that the internal state of each verification object in the chip returns to the expected value after the test and reset are completed, thereby ensuring the efficiency and accuracy of the entire verification process.

[0115] As mentioned above, the test end checker and the reset end checker can be expressed in code. Optionally, the test end checker and / or the reset end checker can be described in Verilog syntax. The test end checker is executed when the simulation ends, and the reset end checker is executed when the simulation is reset.

[0116] In one embodiment, the method further includes: generating instantiation code; and instantiating the inspection tool into each verification object using the instantiation code.

[0117] That is, the instantiation code is used to put the test end checker and / or reset end checker into the verification object corresponding to the instantiation value.

[0118] The instantiation code is the bind statement.

[0119] Optionally, the test end checker and / or reset end checker can be instantiated into the object identifier of the verification object using instantiation code. During the verification process, the object identifier will be executed, and then the test end checker and / or reset end checker will also be executed, thereby performing the corresponding control action.

[0120] In the embodiment of the present application, by instantiating the inspection tool into the object identifier of each verification object, it is easy to implement and ensures that the inspection tool can be executed and used correctly.

[0121] For ease of understanding, a method for automatically generating an EOT and EORchecker provided in an embodiment of the present application is described below with a complete embodiment.

[0122] 1. The electronic device runs the script tool, and the script tool reads the table file generated in advance, refer to Table 1.

[0123] 2. During the reading process, for the target row, if the information in the first column is a new object identifier, a new module is generated with the suffix _eot.

[0124] 3. Read the first signal name in the second column of the target row and the signal expected value in the third column, and generate the EOT tool based on this. The EOT tool is used to check whether the signal value and expected value of the functional signal corresponding to the first signal name are equal during the verification process. The EOT tool is in Verilog syntax and will be executed when the simulation ends.

[0125] 4. Read the fourth column of the target row. If it is not empty, generate the EOR tool. If it is empty, do not generate the EOR tool.

[0126] When the EOR tool determines during the verification process that the signal value of the reset signal corresponding to the second signal name changes from a reset value to a non-reset value, it checks whether the signal value of the functional signal corresponding to the first signal name is equal to the expected value. Here, the reset value of the reset signal can be assumed to be a low level value. If "~" is added before the name of the reset signal, it means that the reset value is a high level value.

[0127] 5. Continue to read the next line. If a new object identifier is read, the generation of the current module_eot is terminated. The module_eot includes the generated EOT and EOR. In addition, a bind statement is automatically generated to instantiate and bind the generated module_eot to the corresponding verification object.

[0128] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0129] Based on the same inventive concept, the embodiment of the present application also provides an inspection tool generation device for implementing the inspection tool generation method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more inspection tool generation device embodiments provided below can refer to the limitations of the inspection tool generation method above, and will not be repeated here.

[0130] In one embodiment, Figure 4 As shown, an inspection tool generating device is provided, and the inspection tool generating device 400 includes: an information acquisition module 401 and a tool generating module 402, wherein:

[0131] The information acquisition module 401 is used to acquire a verification information set of a target verification chip, wherein the verification information set includes functional verification information of each verification object to be verified in the target verification chip;

[0132] A tool generation module 402, configured to generate at least one of a test end checker and a reset end checker corresponding to each verification object according to the functional verification information of each verification object in the verification information set, as a check tool for each verification object;

[0133] Among them, the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

[0134] In one embodiment, the functional verification information includes at least one of the following:

[0135] Object identifier; the object identifier is the name of the verification object;

[0136] First signal name: the first signal name is the signal name of the function signal corresponding to the verification object;

[0137] Signal expected value; signal expected value is the expected value of the functional signal corresponding to the verification object; the expected value is used to characterize the signal value that the functional signal is expected to achieve when the target function corresponding to the functional signal is correctly realized;

[0138] The second signal name; the second signal name is the signal name of the reset signal corresponding to the function signal corresponding to the verification object; the reset signal is used to reset the signal value of the corresponding function signal.

[0139] In one embodiment, the tool generation module 402 is specifically configured to:

[0140] For each verification object, judging whether an inspection tool has been generated for the verification object according to the object identifier; wherein the generated inspection tool has been associated with the corresponding object identifier;

[0141] If a checking tool has not been generated for the verification object, a test end checker corresponding to the verification object is generated based on the first signal name and signal expected value corresponding to the verification object; and, if it is determined that a reset end checker corresponding to the verification object needs to be generated, a reset end checker corresponding to the verification object is generated based on the first signal name, signal expected value and second signal name corresponding to the verification object.

[0142] In one of the embodiments, the apparatus further comprises a determining module, configured to:

[0143] Determine whether the signal name of the reset signal included in the second signal name is empty;

[0144] If it is determined that the signal name of the reset signal included in the second signal name is not empty, it is determined that a reset end checker corresponding to the verification object needs to be generated.

[0145] In one embodiment, the test completion checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when the verification of the verification object is completed, and output a first error message if they are not equal, and the first error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when the verification of the verification object is completed; the reset completion checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when it is determined that the verification of the verification object is reset according to the reset signal corresponding to the second signal name, and output a second error message if they are not equal, and the second error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when the verification of the verification object is reset.

[0146] In one of the embodiments, the apparatus further comprises an instantiation module, configured to:

[0147] Generate instantiation code; use the instantiation code to instantiate the inspection tool into each verification object.

[0148] Each module in the above inspection tool generation device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each module.

[0149] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 5As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store inspection tool generation data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for generating an inspection tool is implemented.

[0150] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0151] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0152] Acquire a verification information set of a target verification chip, where the verification information set includes functional verification information of each verification object to be verified in the target verification chip;

[0153] Generate at least one of a test end checker and a reset end checker corresponding to each verification object as a check tool for each verification object according to the functional verification information of each verification object in the verification information set;

[0154] Among them, the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

[0155] In one embodiment, the functional verification information includes at least one of the following: an object identifier; the object identifier is the name of the verification object; a first signal name; the first signal name is the signal name of the functional signal corresponding to the verification object; a signal expected value; the signal expected value is the expected value of the functional signal corresponding to the verification object; the expected value is used to characterize the signal value expected to be achieved by the functional signal when the target function corresponding to the functional signal is correctly implemented; a second signal name; the second signal name is the signal name of the reset signal corresponding to the functional signal corresponding to the verification object; the reset signal is used to reset the signal value of the corresponding functional signal.

[0156] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0157] For each verification object, determine whether an inspection tool has been generated for the verification object based on the object identifier; wherein the generated inspection tool has been associated with the corresponding object identifier; if the inspection tool has not been generated for the verification object, then generate a test end checker corresponding to the verification object based on the first signal name and signal expected value corresponding to the verification object; and, in the event that it is determined that a reset end checker corresponding to the verification object needs to be generated, generate a reset end checker corresponding to the verification object based on the first signal name, signal expected value and second signal name corresponding to the verification object.

[0158] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0159] Determine whether the signal name of the reset signal included in the second signal name is empty; if it is determined that the signal name of the reset signal included in the second signal name is not empty, determine that a reset end checker corresponding to the verification object needs to be generated.

[0160] In one embodiment, a test completion checker is used to determine whether the signal value of a function signal corresponding to a first signal name is equal to the expected signal value when verification of a verification object is completed, and output a first error message if they are not equal, the first error message being used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when verification of the verification object is completed; a reset completion checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when verification of the verification object is reset according to a reset signal corresponding to a second signal name, and output a second error message if they are not equal, the second error message being used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when verification of the verification object is reset.

[0161] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0162] Generate instantiation code; use the instantiation code to instantiate the inspection tool into each verification object.

[0163] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0164] Acquire a verification information set of a target verification chip, where the verification information set includes functional verification information of each verification object to be verified in the target verification chip;

[0165] Generate at least one of a test end checker and a reset end checker corresponding to each verification object as a check tool for each verification object according to the functional verification information of each verification object in the verification information set;

[0166] Among them, the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

[0167] In one embodiment, the functional verification information includes at least one of the following: an object identifier; the object identifier is the name of the verification object; a first signal name; the first signal name is the signal name of the functional signal corresponding to the verification object; a signal expected value; the signal expected value is the expected value of the functional signal corresponding to the verification object; the expected value is used to characterize the signal value expected to be achieved by the functional signal when the target function corresponding to the functional signal is correctly implemented; a second signal name; the second signal name is the signal name of the reset signal corresponding to the functional signal corresponding to the verification object; the reset signal is used to reset the signal value of the corresponding functional signal.

[0168] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0169] For each verification object, determine whether an inspection tool has been generated for the verification object based on the object identifier; wherein the generated inspection tool has been associated with the corresponding object identifier; if the inspection tool has not been generated for the verification object, then generate a test end checker corresponding to the verification object based on the first signal name and signal expected value corresponding to the verification object; and, in the event that it is determined that a reset end checker corresponding to the verification object needs to be generated, generate a reset end checker corresponding to the verification object based on the first signal name, signal expected value and second signal name corresponding to the verification object.

[0170] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0171] Determine whether the signal name of the reset signal included in the second signal name is empty; if it is determined that the signal name of the reset signal included in the second signal name is not empty, determine that a reset end checker corresponding to the verification object needs to be generated.

[0172] In one embodiment, a test completion checker is used to determine whether the signal value of a function signal corresponding to a first signal name is equal to the expected signal value when verification of a verification object is completed, and output a first error message if they are not equal, the first error message being used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when verification of the verification object is completed; a reset completion checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when verification of the verification object is reset according to a reset signal corresponding to a second signal name, and output a second error message if they are not equal, the second error message being used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when verification of the verification object is reset.

[0173] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0174] Generate instantiation code; use the instantiation code to instantiate the inspection tool into each verification object.

[0175] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0176] Acquire a verification information set of a target verification chip, where the verification information set includes functional verification information of each verification object to be verified in the target verification chip;

[0177] Generate at least one of a test end checker and a reset end checker corresponding to each verification object as a check tool for each verification object according to the functional verification information of each verification object in the verification information set;

[0178] Among them, the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

[0179] In one embodiment, the functional verification information includes at least one of the following: an object identifier; the object identifier is the name of the verification object; a first signal name; the first signal name is the signal name of the functional signal corresponding to the verification object; a signal expected value; the signal expected value is the expected value of the functional signal corresponding to the verification object; the expected value is used to characterize the signal value expected to be achieved by the functional signal when the target function corresponding to the functional signal is correctly implemented; a second signal name; the second signal name is the signal name of the reset signal corresponding to the functional signal corresponding to the verification object; the reset signal is used to reset the signal value of the corresponding functional signal.

[0180] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: for each verification object, determining whether an inspection tool has been generated for the verification object based on the object identifier; wherein the generated inspection tool has been associated with the corresponding object identifier; if the inspection tool has not been generated for the verification object, generating a test end checker corresponding to the verification object based on the first signal name and signal expected value corresponding to the verification object; and, in the event that it is determined that a reset end checker corresponding to the verification object needs to be generated, generating a reset end checker corresponding to the verification object based on the first signal name, signal expected value and second signal name corresponding to the verification object.

[0181] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: determining whether the signal name of the reset signal contained in the second signal name is empty; if it is determined that the signal name of the reset signal contained in the second signal name is not empty, determining that a reset end checker corresponding to the verification object needs to be generated.

[0182] In one embodiment, a test completion checker is used to determine whether the signal value of a function signal corresponding to a first signal name is equal to the expected signal value when verification of a verification object is completed, and output a first error message if they are not equal, the first error message being used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when verification of the verification object is completed; a reset completion checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when verification of the verification object is reset according to a reset signal corresponding to a second signal name, and output a second error message if they are not equal, the second error message being used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when verification of the verification object is reset.

[0183] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: generating instantiation code; and instantiating the inspection tool into each verification object using the instantiation code.

[0184] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0185] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0186] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for generating an inspection tool, characterized in that: The method comprises: Acquire a verification information set of a target verification chip, wherein the verification information set includes functional verification information of each verification object to be verified in the target verification chip; generating at least one of a test end checker and a reset end checker corresponding to each of the verification objects according to the functional verification information of each of the verification objects in the verification information set as a checking tool for each of the verification objects; Among them, the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

2. The method according to claim 1, characterized in that The function verification information includes at least one of the following: Object identifier; the object identifier is the name of the verification object; First signal name; the first signal name is the signal name of the function signal corresponding to the verification object; Signal expected value; the signal expected value is the expected value of the functional signal corresponding to the verification object; the expected value is used to characterize the signal value expected to be achieved by the functional signal when the target function corresponding to the functional signal is correctly implemented; The second signal name; the second signal name is the signal name of the reset signal corresponding to the function signal corresponding to the verification object; the reset signal is used to reset the signal value of the corresponding function signal.

3. The method according to claim 2, characterized in that The step of generating at least one of a test end checker and a reset end checker corresponding to each verification object according to the functional verification information of each verification object in the verification information set comprises: For each of the verification objects, judging whether an inspection tool has been generated for the verification object according to the object identifier; wherein the generated inspection tool has been associated with the corresponding object identifier; If a checking tool has not been generated for the verification object, a test end checker corresponding to the verification object is generated based on the first signal name and signal expected value corresponding to the verification object; and, in the case where it is determined that a reset end checker corresponding to the verification object needs to be generated, a reset end checker corresponding to the verification object is generated based on the first signal name, signal expected value and second signal name corresponding to the verification object.

4. The method according to claim 3, characterized in that: The method further comprises: Determine whether the signal name of the reset signal included in the second signal name is empty; If it is determined that the signal name of the reset signal included in the second signal name is not empty, it is determined that a reset end checker corresponding to the verification object needs to be generated.

5. The method according to claim 3, characterized in that: The test completion checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected signal value when the verification of the verification object is completed, and output a first error message when they are not equal, wherein the first error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected signal value when the verification of the verification object is completed; The reset end checker is used to determine whether the signal value of the function signal corresponding to the first signal name is equal to the expected value of the signal when the verification object verification reset is determined according to the reset signal corresponding to the second signal name, and output a second error message if they are not equal. The second error message is used to indicate that the signal value of the function signal corresponding to the first signal name is not equal to the expected value of the signal when the verification object verification is reset.

6. The method according to any one of claims 2 to 5, characterized in that: The method further comprises: Generate instantiation code; The checking tool is instantiated into each of the verification objects using the instantiation code.

7. An inspection tool generating device, characterized in that: The device comprises: An information acquisition module, used to acquire a verification information set of a target verification chip, wherein the verification information set includes functional verification information of each verification object to be verified in the target verification chip; A tool generation module, configured to generate at least one of a test end checker and a reset end checker corresponding to each of the verification objects according to the functional verification information of each of the verification objects in the verification information set, as a check tool for each of the verification objects; Among them, the test end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is completed, and the reset end checker is used to control the functional state of the verification object to a preset state when the verification of the verification object is reset.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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