DDR clock synchronization system and DDR memory chip with same

Abstract

The present invention provides a DDR clock synchronization system for simultaneously performing adjustment of a clock signal of DDR and clock adjustment of a plurality of control command signals, comprising: a receiver which receives the clock signal and outputs a reference clock signal to a delay-locked loop; the automatic cycle controller outputs a system signal to the delay-locked loop; a delay-locked loop which receives a reference clock signal input from the receiver and a plurality of control command signals input from the outside, and adjusts the reference clock signal on the basis of a system signal of the automatic cycle controller; a logic unit that receives an output clock signal output from the delay-locked loop; and a clock tree located to receive the plurality of output control command signals output from the delay-locked loop, the delay-locked loop having a plurality of delay chains corresponding to the reference clock signal and the plurality of control command signals, and automatically switching the plurality of delay chains based on the system signal, therefore, the reference clock signal is circularly adjusted in the plurality of delay chains in sequence.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a DDR clock synchronization system and a DDR memory chip having the DDR clock synchronization system. Background Art

[0002] DRAM (Dynamic Random Access Memory) chips are a widely used type of semiconductor memory, especially suitable for main memory and video memory. Compared with other types of RAM (such as SRAM), DRAM has higher storage density and lower cost, so it is widely used in modern computing devices.

[0003] DDR DRAM (Double Data Rate Dynamic Random Access Memory) chip is an improved DRAM technology that achieves higher bandwidth and performance than traditional DRAM by transmitting data on both the rising and falling edges of the clock signal. DDRDRAM is widely used in computer main memory and other application scenarios that require fast data processing. Due to the double data transfer rate, DDR DRAM provides higher performance at the same clock frequency, so it also requires a matching controller and system design to give full play to its advantages.

[0004] In DDR (Double Data Rate) memory, DLL (Delay-Locked Loop) is an important component, mainly used for synchronization and phase adjustment of clock signals. The task of DLL in DDR memory is to ensure that data read and write operations occur in the correct clock cycle to improve the accuracy and reliability of data transmission. In high-speed data transmission, the clock signal may deviate. DLL adjusts the clock signal from the memory controller to align the phase with the internal clock signal of the memory chip. In addition, due to the physical characteristics of PCB routing, connectors and the memory chip itself, the signal will be delayed during the propagation process. DLL eliminates these deviations by accurately controlling the delay of the signal. In addition, DLL improves the synchronization between data signal and clock signal by dynamically adjusting the clock signal, ensuring that data is read and written at the expected time, reducing signal jitter, and providing a more stable clock to support high-speed data transmission, which is the key to achieving high-performance DDR memory system. Summary of the invention

[0005] Technical Problems to be Solved by the Invention

[0006] In DDR (Double Data Rate) memory technology, DQS and DQ are two key signals that play an important role in the memory data transmission process.

[0007] DQ (Data Queue) is a pin or signal line used to transmit actual data in the DDR architecture. Each data bit has a corresponding DQ signal line, which is responsible for transferring the actual data bit between the memory module and the memory controller. In memory read and write operations, data is transmitted through these DQ signal lines.

[0008] DQS (Data Strobe) is a strobe signal used for data sampling in the DDR architecture. It plays a role as a timing reference in the data transmission process, which can help the memory controller to accurately sample data, thereby achieving efficient and reliable data reading and writing. In addition, it helps synchronize the data (DQ) signal to improve the accuracy of transmission, and provides a clock reference signal during the data reading and writing process to ensure that the data is sampled at the right time to facilitate synchronization between the DDR DRAM and the memory controller.

[0009] Each set of DQ signal lines is usually equipped with a DQS signal. DQS is a bidirectional signal. When the memory controller issues a write command, the DQS signal is driven by the controller. When reading data, the DQS signal is driven by the DRAM module. DQS supports double data rate transmission by helping to sample data at the rising and falling edges of data transmission. In DDR memory, the interaction between DQ and DQS is key. These two signals must be highly synchronized to ensure that each bit of data transmitted at double rate is sampled at the right time. The arrival time and continuity of the DQS signal are very important for system stability and data integrity. Incorrect DQS signals may cause data bit errors or system instability.

[0010] The external CPU and storage controller use the clock to accurately transmit instructions and data. During the read operation, DRAM needs to provide an output clock DQS to accurately distinguish the data transmission cycle within a clock cycle (Tck), so that the data receiver can accurately receive the data. However, when DQS reaches the device through the transmission line of the PCB, there will be a timing deviation. DQS is used as a clock to collect DQ, which cannot guarantee the correct collection of data under different conditions. Therefore, it is necessary to add a delay structure to the DQS generation path so that the circuit can work normally under any conditions and realize the synchronous alignment operation of DQS and DQ. This delay structure is the above-mentioned DLL (Delay-Locked Loop) circuit.

[0011] Existing DLL circuits are generally only used for clock signal adjustment or clock adjustment of control command (Cmd) signals, that is, only used for clock adjustment of the input reference clock signal (Refclk) and the output DQS signal (that is, making their signals coincident), or for accurately synchronizing the Cmd signal with the clock signal (making their signals coincident), but do not consider simultaneous clock adjustment of the clock signal and the control command (Cmd) signal.

[0012] In addition, most clock signals are in square wave form, with clear rising and falling edges to indicate the time scale, and unlike control command signals, they have a very high frequency. Therefore, when clock adjustment (synchronization) is performed through the DLL circuit, the high-frequency clock signal causes greater loss to the electronic components in the DLL module.

[0013] The present invention is completed in view of the above-mentioned problems, and its purpose is to provide a DDR clock synchronization system and a DDR memory chip equipped with the DDR clock synchronization system, which can simultaneously adjust the clocks of a reference clock signal and multiple control command signals, and can reduce the loss of electronic components therein, thereby extending the working life of the chip.

[0014] Technical solutions adopted to solve technical problems

[0015] The present invention provides a DDR clock synchronization system, which is used for adjusting the clock signal of DDR and the clock adjustment of multiple control command signals at the same time, and is characterized in that it comprises: a receiver, which receives the clock signal and outputs a reference clock signal to a delay locked loop located at a lower level; an automatic cycle controller, which outputs a system signal to the delay locked loop located at the lower level; a delay locked loop, which is connected to the receiver and the automatic cycle controller, receives the reference clock signal input from the receiver and multiple control command signals input from the outside, and simultaneously adjusts the reference clock signal based on the system signal input from the automatic cycle controller. signal and clock adjustment of multiple control command signals; a logic unit, which is located at the lower level of the delay locked loop and receives the output clock signal output from the delay locked loop; and a clock tree, which is located at the lower level of the delay locked loop and receives the multiple output control command signals output from the delay locked loop, the delay locked loop has a plurality of delay chains corresponding to the reference clock signal and the multiple control command signals, and the plurality of delay chains are automatically switched based on the system signal input by the automatic cycle controller, so as to cyclically adjust the reference clock signal and the clock adjustment of multiple control command signals in the plurality of delay chains in turn.

[0016] The present invention provides a DDR memory chip, characterized in that it includes: a storage cell array for storing data; a plurality of independent memory banks; a row address selector and a column address selector for selecting row and column addresses; an I / O buffer for signal conversion and temporary storage between the memory chip and an external controller; a mode register for configuring the working mode of the DDR memory during operation; a pre-fetch cache for increasing the amount of data transmitted within a clock cycle; the above-mentioned DDR clock synchronization system; an address and command control logic responsible for decoding command and address signals from the memory controller and transmitting them to appropriate internal modules; a power management module for processing and regulating the power supply of the DDR memory chip; and a command interface for receiving and interpreting command inputs from the controller and activating corresponding operations internally.

[0017] Effects of the Invention

[0018] According to the DDR clock synchronization system and the DDR memory chip equipped with the DDR clock synchronization system disclosed in the present invention, the clock adjustment of the reference clock signal and multiple control command signals can be performed simultaneously, thereby realizing the function of the delay locked loop circuit itself, and reducing the loss of electronic components therein, thereby extending the working life of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present disclosure may be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a system block diagram showing the architecture of a conventional DDR clock synchronization system.

[0021] Figure 2 is a timing diagram showing the delay between the reference clock signal and the DLL output clock signal.

[0022] Figure 3 is a schematic diagram showing the relationship between delay time and clock cycle.

[0023] Figure 4 1 is a system block diagram showing the architecture of a DDR clock synchronization system 100A according to an embodiment of the present invention.

[0024] Figure 5 is a timing diagram showing the delay between the reference clock signal and the DLL output clock signal, and the delay between the input control command signal and the output control command signal.

[0025] Figure 6 1 is a signal timing diagram of the delay locked loop 102A with an automatic cycle function.

[0026] Description of labels:

[0027] 100, 100A DDR clock synchronization system, 101, 101A receiver, 102, 102A delay locked loop (DLL), 103, 103A logic unit, 104A clock tree, 105A automatic cycle controller, 1021, 1021A delay chain, 1022, 1022A controller, 1023, 1023A phase detector, 1024, 1024A replicator, 1025A, 1026A multiplexer. DETAILED DESCRIPTION

[0028] The specific implementation methods of the present disclosure will be described below. It should be noted that in the specific description of these implementation methods, in order to provide a concise description, it is impossible for this specification to provide a detailed description of all the features of the actual implementation methods. It should be understood that in the actual implementation of any implementation method, just as in the process of any engineering project or design project, in order to achieve the specific goals of the developer and to meet system-related or business-related restrictions, various specific decisions are often made, and this will also change from one implementation method to another. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for ordinary technicians in the field related to the content disclosed by the present disclosure, some changes in design, manufacturing or production based on the technical content disclosed in the present disclosure are just conventional technical means, and should not be understood as insufficient content of the present disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in the claims and the specification shall have the usual meaning understood by persons with ordinary skills in the technical field to which the present disclosure belongs. The words "first", "second" and similar words used in the patent application specification and the claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one" or "one" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalent elements, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0030] In the present disclosure, unless otherwise specified, all embodiments and preferred embodiments mentioned herein can be combined with each other to form a new technical solution. In the present disclosure, unless otherwise specified, all technical features and preferred features mentioned herein can be combined with each other to form a new technical solution.

[0031] Hereinafter, a delay locked loop circuit and a DDR chip including the delay locked loop circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a system block diagram showing the architecture of a conventional DDR clock synchronization system. Figure 1 , the architecture of the existing DDR clock synchronization system 100 and the structure of a delay locked loop (DLL) 102 are described. For the convenience of description, the delay locked loop is sometimes referred to as DLL below.

[0033] like Figure 1 As shown, the architecture 100 of the existing DDR clock synchronization system mainly includes a receiver 101 at an upper level, a delay locked loop (DLL) 102 at a middle level, and a logic cell 103 at a lower level.

[0034] Specifically, the receiver 101 at the upper level receives the clock signal and outputs a reference clock signal (Refclk) to the delay locked loop (DLL) 102 at the middle level. The DLL 102 receives the reference clock signal (Refclk) and outputs an adjusted clock signal (DLL_clk). Afterwards, the adjusted clock signal (DLL_clk) is input to the logic cell (Logic Cell) 103 at the lower level for further processing.

[0035] Next, the structure of the DLL 102 is described in detail. The delay locked loop (DLL) 102 includes a delay chain 1021 , a controller 1022 , a phase detector 1023 , and a replica 1024 .

[0036] Among them, the delay chain (Delay Line) 1021 is the core part of DLL 102, and its main function is to accurately adjust the delay of the input clock signal to ensure that the output clock signal is synchronized with the reference clock signal. The delay chain 1021 can usually be composed of a series of adjustable delay units, each of which can introduce a small, controllable delay. By combining these delay units, the delay chain can achieve accurate clock signal delay adjustment. As an example, the adjustable delay unit can be composed of a series of inverters (Inverter), each inverter consisting of an NMOS and a PMOS transistor.

[0037] The controller 1022 is used to generate a control signal, and the phase detector 1023 is used to detect the phase difference between the input clock signal and the fed-back clock signal. Specifically, by detecting the phase difference, the phase detector 1023 can provide a feedback signal to the controller 1022 to adjust the delay of the delay line 1021, thereby achieving synchronization of the clock signal. The controller 1022 adjusts the delay amount of the delay line 1021 according to the phase error signal provided by the phase detector 1023 to achieve synchronization of the clock signal, and they play a role in complementing each other.

[0038] In addition, the main function of the replicator (REPLICA) 1024 is to generate a feedback clock signal (Fbclk) for comparison with the reference clock signal (Refclk) to achieve synchronization of the clock signal. The reason for not directly inputting the clock signal is that the chip area is limited. In order to save area, a replicator is set up, and the output signal of the delay chain is directly replicated by the replicator and input to the phase detector as a feedback clock signal.

[0039] Next, the signal transmission of the DDR clock synchronization system is described.

[0040] First, the input clock signal (CK) is input to the receiver 101 , which outputs the reference clock signal (Refclk). The reference clock signal (Refclk) is input to the input end of the DLL 102 , which is input to one end of the phase detector 1023 in the DLL 102 and one end of the delay chain 1021 .

[0041] Then, after the clock signal (DLL_clk) outputted by the delay chain 1021 in the DLL 102 is inputted into the replicator 1024 (REPLICA), the replicator 1024 outputs the feedback clock signal (Fbclk) to the other end of the phase detector 1023 in the DLL 102 .

[0042] Next, the output result of the phase detector 1023 is input to the controller 1022 of the DLL 102 and further input to the delay chain 1021 to determine the required delay time.

[0043] Finally, the delay chain 1021 outputs DLL_clk to the logic unit 103 to generate a DQS signal with the same edge as the input clock signal (CK / Refclk).

[0044] At this point, the adjustment of the clock signal is completed, and the synchronous alignment operation of DQS and DQ is realized.

[0045] Next, the delay between the reference clock signal and the DLL output clock signal will be described.

[0046] Figure 2 is a timing diagram showing the delay between the reference clock signal and the DLL output clock signal. Figure 2 As shown, Refclk is the input reference clock signal, which is used as the reference for clock synchronization and is a square wave signal with a fixed period and duty cycle. The DLL output clock signal (DLL_clk) is the clock signal adjusted by the delay chain 1021. In the figure, DLL_clk is also a square wave signal with the same period and duty cycle as Refclk.

[0047] In the figure, the phase difference (Δt=t2-t1) between the reference clock signal and the DLL output clock signal is marked. The phase difference represents the time difference between the rising edge or falling edge of the two clock signals. In the figure, Δt represents the time difference between the rising edge of Refclk and the rising edge of DLL_clk. In order to achieve clock synchronization, the DLL should synchronize with Refclk by adjusting the phase of DLL_clk. Ideally, after adjustment, the rising edge of DLL_clk and the rising edge of Refclk should be completely aligned, that is, the phase difference Δt should be zero. If the phase difference Δt is not zero, the DLL will adjust the phase of DLL_clk through the delay chain 1021 to gradually reduce the phase difference until DLL_clk is synchronized with Refclk.

[0048] Figure 3 Schematic diagram showing the relationship between delay time and clock cycle. In order to achieve clock synchronization, the total delay time can be made an integer multiple of the clock cycle.

[0049] like Figure 3 As shown, t_in is the delay from the input clock signal (CK) to the reference clock signal (Refclk), t_dl l is the delay from the reference clock signal (Refclk) to the DLL output clock signal (DLL_clk), t_out is the delay from the DLL output clock signal (DLL_clk) to the data output signal (DQS), and the clock cycle is set to tck. In this case, tck×N=t_in+t_dll+t_out (N is a natural number) is satisfied. In this case, it can be ensured that DLL_clk and Refclk are on the same edge.

[0050] The above describes the architecture of the existing DDR clock synchronization system, which is only used for clock signal adjustment or clock adjustment of the control command (Cmd) signal, that is, it is only used to clock adjust the input reference clock signal (Refclk) and the output DQS signal (that is, to make their signals coincident), or to synchronize the Cmd signal accurately with the clock signal (to make their signals coincident), but does not take into account the simultaneous clock adjustment of the clock signal and multiple control command (Cmd) signals.

[0051] In addition, most clock signals are in square wave form, with clear rising and falling edges to indicate the time scale, and unlike control command signals, they have a very high frequency. Therefore, when clock adjustment (synchronization) is performed through the DLL circuit, the high-frequency clock signal causes greater loss to the electronic components in the DLL module.

[0052] In order to solve the above problems, in an embodiment of the present invention, a new DDR clock synchronization architecture is proposed.

[0053] Figure 4 1 is a system block diagram showing the architecture of a DDR clock synchronization system 100A according to an embodiment of the present invention.

[0054] like Figure 4 As shown, the DDR clock synchronization system 100A according to the embodiment of the present invention includes a receiver 101A, an automatic cycle controller 105A, a delay locked loop (DLL) 102A, a logic unit 103A and a clock tree (CLK tree) 104A.

[0055] The receiver 101A is located at the upper stage, which receives the clock (CK) signal and outputs a reference clock signal (Refclk_in) to the delay locked loop (DLL) 102A located in the middle. The DLL 102A receives the reference clock signal (Refclk_in) and outputs an adjusted clock signal (DLL_clk). Afterwards, the adjusted clock signal (DLL_clk) is input to the logic cell (Logic Cell) 103A and the clock tree 104A located at the lower stage for further processing.

[0056] Next, the structure of the delay locked loop (DLL) 102A is described in detail. The delay locked loop (DLL) 102A includes a delay chain 1021A, a controller 1022A, a phase detector 1023A, a replica 1024A, and multiplexers 1025A and 1026A.

[0057] Among them, the delay line 1021A is the core part of the DLL 102, and its main function is to accurately adjust the delay of the input clock signal to ensure that the output clock signal is synchronized with the reference clock signal. The delay chain 1021A can usually be composed of a series of adjustable delay units, each of which can introduce a small, controllable delay. By combining these delay units, the delay chain can achieve accurate clock signal delay adjustment. The adjustable delay unit can be composed of a series of inverters connected in series, and each inverter can be composed of an NMOS and a PMOS transistor.

[0058] In the embodiment of the present invention, as an example, the delay chain 1021A is composed of four delay chains (delay chain / 0, delay chain / 1, delay chain / 2, and delay chain / 3) having the same structure.

[0059] Different from the existing DDR clock synchronization system, in the DDR synchronous clock system 100A involved in the embodiment of the present invention, not only the reference clock signal (Refclk_in) is input to the delay chain, but also multiple control command signals Cmd_in are input to the delay chain. Specifically, in the embodiment of the present invention, the reference clock signal Refclk_in, the control command signal Cmd1_in, the control command signal Cmd2_in, and the control command signal Cmd3_in are input to the delay chain 1021A. In order to input these signals at the same time, a multiplexer 1025A is provided before the delay chain 1021A, and the multiplexer 1025A is used as a multiplexed input.

[0060] That is, in the embodiment of the present invention, the number of reference clock signals is 1, the number of control command signals is 3, and the number of delay chains is 4. That is, the number of delay chains is equal to the sum of the number of input reference clock signals and the number of multiple control command signals.

[0061] The controller 1022A is used to generate a control signal, and the phase detector 1023A is used to detect the phase difference between the input clock signal Refclk_in and the fed-back clock signal Fbclk. Specifically, by detecting the phase difference, the phase detector 1023A can provide a feedback signal to the controller 1022A to adjust the delay of the delay chain 1021A, thereby achieving synchronization of the clock signal. The controller 1022A adjusts the delay amount of the delay chain 1021A according to the phase error signal provided by the phase detector 1023A to achieve synchronization of the clock signal, and they play a role in complementing each other.

[0062] In addition, the main function of the replicator (REPLICA) 1024A is to generate a feedback clock signal (Fbclk) for comparison with the reference clock signal (Refclk_in) to achieve synchronization of the clock signal. The reason for not directly inputting the clock signal is that the chip area is limited. In order to save area, a replicator is set up, and the output signal of the delay chain is directly replicated by the replicator and input to the phase detector as a feedback clock signal.

[0063] like Figure 4 As shown, while the receiver 101A output is transmitted to the DLL delay chain / 0, the control command signals Cmd1_in, Cmd2_in, and Cmd3_in with the same gate delay are simultaneously transmitted to the same DLL delay chain / 1, delay chain / 2, and delay chain / 3 via the receiver 101A, and the control signal outputted by the controller 1022A is simultaneously transmitted to the four same delay chains, so that the signal passing through the delay chain 1021A has the same delay time. The output signal is outputted via the multiplexer 1026A, so 1026A becomes a multiplexed output, and DLL_clk, Cmd1_out, Cmd2_out, and Cmd3_out are outputted respectively.

[0064] Figure 5 is a timing diagram showing the delay between the reference clock signal and the DLL output clock signal, and the delay between the input control command signal and the output control command signal.

[0065] like Figure 5 As shown, the phase difference between the reference clock signal and the DLL output clock signal is Δt_clk=t2-t1. In addition, the phase difference between the input control command signal and the output control command signal is Δt_clk=t4-t3. In this embodiment, Δt_clk=Δt_clk, achieving a delay synchronization state between the clock signal DLL_clk and the control command signal Cmd_out. In this case, the clocks of the reference clock signal and the control command signal can be adjusted simultaneously to make their delays the same. In other words, the phase difference between the reference clock signal and the output clock signal is equal to the phase difference between the multiple control command signals and the multiple output control command signals.

[0066] like Figure 4As shown, when clock synchronization is performed only through the delay chains corresponding to each input signal, the MOS transistors and other devices constituting the delay chain are also continuously flipped because the clock signal is continuously flipped (toggle) in the delay chain / 0, thereby generating large power consumption and continuously causing loss to the life of the transistor. At the same time, in the remaining delay chains (delay chain / 1, delay chain / 2, delay chain / 3), the control command signal Cmd_in is only flipped at different timings, and unlike the clock signal, they do not have a very high frequency. The loss of the MOS transistors in the delay chains (delay chain / 1, delay chain / 2, delay chain / 3) passing through is much smaller than the transistors in the delay chain (delay chain / 0) passing through the clock signal. Therefore, the present invention adds an automatic cycle function based on system signal control. When the system signal is started, the control signal for controlling the multiplexers 1025A and 1025B is generated by the automatic cycle controller 105A to determine the delay chain through which the clock signal and the control command signal pass.

[0067] Figure 6 1 is a signal timing diagram of the delay locked loop 102A with an automatic cycle function.

[0068] like Figure 6 As shown, the delay chains used are controlled based on the falling edge of the system signal, so that all delay chains transmit the Clk signal and the Cmd signal. Therefore, the DLL function can be realized and the optimization of extending the working life of the chip can be achieved.

[0069] Specifically, if Figure 6 As shown, the falling edge of the system signal is used as a trigger to automatically switch the delay chain used, so that the entire delay function is cyclically performed in four delay chains with the same structure. Therefore, while realizing the function of DLL, the frequency of use of each delay chain is greatly reduced, thereby increasing its lifespan and thus extending the working life of the chip.

[0070] like Figure 4 As shown, the output DLL_clk and Cmd1_out, Cmd2_out, and Cmd3_out are output to the logic unit 103A and the clock tree 104A, respectively.

[0071] DLL_clk is input to the logic unit 103A to generate a DQS signal with the same edge as the input clock signal (CK / Refclk).

[0072] The outputs of multiple control command signals Cmd1_out, Cmd2_out, Cmd3_out (i.e., output control command signals) are input to the clock tree 104A. The clock tree is a type of clock distribution network, which is used to effectively distribute clock signals between various parts of the chip. In the process of generating the DQS signal, it is necessary to perform a logical conversion with the control command signal Cmd. In DDRJEDEC, there are different CWL regulations for different clock frequencies. In order to accurately perform clock synchronization alignment operations, the DLL delay chain outputs DLL_clk, which is used to capture the command signal through the clock tree CLK Tree. The clock CMD_clk is generated. In order to meet the setup / hold time of the flip-flop (Flip-Flop), it is also necessary to perform timing control on CMD_clk and the command signal Cmd.

[0073] Signals Cmd1_out, Cmd2_out, and Cmd3_out having the same edges as the input control command signals Cmd1_in, Cmd2_in, and Cmd3_in are output to the respective parts through the clock tree 104A.

[0074] In this embodiment, a case of one reference clock signal Refclk and three control command signals Cmd is shown, and four delay chains corresponding to them are set. However, the present invention is not limited thereto, and the number of control command signals Cmd is not limited to three, but may be more than three. In this case, delay chains matching the number of control command signals Cmd may be set.

[0075] In addition, the present invention provides a DDR memory chip, which includes: a storage cell array for storing data; a plurality of independent memory banks; a row address selector and a column address selector for selecting row and column addresses; an I / O buffer for signal conversion and temporary storage between the memory chip and an external controller; a mode register for configuring the working mode of the DDR memory during operation; a pre-fetch cache for increasing the amount of data transmitted within a clock cycle; a DDR clock synchronization system including a delay locked loop involved in an embodiment of the present invention; address and command control logic responsible for decoding command and address signals from the memory controller and transmitting them to appropriate internal modules; a power management module for processing and adjusting the power supply of the DDR memory chip; and a command interface for receiving and interpreting command inputs from the controller and activating corresponding operations internally.

[0076] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present invention, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present invention. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present invention, the various embodiments are not meant to be restrictive, but exemplary embodiments. In the case of reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. A DDR clock synchronization system, used for simultaneously adjusting a DDR clock signal and a plurality of control command signals, characterized in that: include: A receiver that receives the clock signal and outputs a reference clock signal to a delay-locked loop located at a lower stage; An automatic cycle controller, which outputs a system signal to the delay locked loop located at a lower level; a delay locked loop, the delay locked loop being connected to the receiver and the automatic cycle controller, receiving a reference clock signal input from the receiver and a plurality of control command signals input from the outside, and simultaneously adjusting the reference clock signal and the clocks of the plurality of control command signals based on a system signal input from the automatic cycle controller; a logic unit, the logic unit being located at a lower stage of the delay locked loop and receiving an output clock signal output from the delay locked loop; as well as a clock tree, the clock tree being located at a lower level of the delay locked loop and receiving a plurality of output control command signals output from the delay locked loop, The delay locked loop has a plurality of delay chains corresponding to the reference clock signal and the plurality of control command signals, and automatically switches the plurality of delay chains based on a system signal input by the automatic cycle controller, thereby cyclically adjusting the reference clock signal and adjusting the clocks of the plurality of control command signals in the plurality of delay chains in turn.

2. The DDR clock synchronization system according to claim 1, wherein: The delay locked loop comprises: a multiplexer as an input, which receives the reference clock signal input from the receiver and the plurality of control command signals input from the outside, and inputs these signals into the plurality of delay chains; a multiplexer as an output, which receives the output clock signals input from the plurality of delay chains and the plurality of output control command signals, and outputs these signals to the logic unit and the clock tree; A phase detector, the phase detector is used to detect the phase difference between the input reference clock signal and the feedback clock signal; a controller, the controller being used to generate a control signal and adjust the delay amounts of the plurality of delay chains according to the phase difference input from the phase detector; and A replicator is used to generate the feedback clock signal and output it to the phase detector.

3. The DDR clock synchronization system as claimed in claim 2, characterized in that: The number of the delay chains is equal to the sum of the number of the input reference clock signals and the number of the plurality of control command signals.

4. The DDR clock synchronization system as claimed in claim 2, characterized in that: The phase difference between the reference clock signal and the output clock signal is equal to the phase difference between the plurality of control command signals and the plurality of output control command signals.

5. The DDR clock synchronization system as claimed in claim 2, wherein: The number of the reference clock signals is 1, the number of the control command signals is 3, and the number of the delay chains is 4. The four delay chains have the same structure.

6. The DDR clock synchronization system as claimed in claim 2, characterized in that: The plurality of delay chains are automatically switched in sequence using the falling edge of the system signal as a trigger.

7. The DDR clock synchronization system as claimed in claim 2, characterized in that: If the delay from the clock signal to the reference clock signal is set to t_in, the delay from the reference clock signal to the output clock signal is set to t_dll, the delay from the output clock signal to the data output signal is set to t_out, and the clock cycle is set to tck, then tck×N=t_in+t_dll+t_out is satisfied, where N is a natural number.

8. The DDR clock synchronization system as claimed in claim 2, characterized in that: The delay chain consists of a series of adjustable delay units, each delay unit providing a fixed time delay.

9. The DDR clock synchronization system according to claim 8, wherein: The adjustable delay unit is composed of a series of inverters connected in series, and each inverter is composed of an NMOS and a PMOS transistor.

10. A DDR memory chip, characterized in that: include: A memory cell array for storing data; Multiple independent memory banks; A row address selector and a column address selector for selecting addresses of rows and columns; I / O buffer for signal conversion and temporary storage between memory chips and external controllers; A mode register used to configure the working mode of the DDR memory during operation; Prefetch cache for increasing the amount of data transferred within a clock cycle; The DDR clock synchronization system according to any one of claims 1 to 9; The address and command control logic responsible for decoding command and address signals from the memory controller and passing them to the appropriate internal modules; A power management module that handles and regulates the power supply to the DDR memory chips; as well as A command interface that receives and interprets command input from the controller and activates corresponding operations internally.

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