Multiplexing circuit, multiplexing module, display device and driving method

Abstract

The invention provides a multiplexing circuit, a multiplexing module, a display device and a driving method. The multiplexing circuit is electrically connected with M data voltage supply ends and multiple columns of data lines, the multiplexing circuit comprises N multiplexing control lines and N multiplexing circuits, and the nth multiplexing circuit comprises M multiplexing sub-circuits; the nth multiplexing control line comprises M control lines; an mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected with an mth control line included in the nth multiplexing control line, an mth data voltage supply end and a corresponding data line, and is used for writing a data voltage provided by the mth data voltage supply end into the corresponding data line under the control of a control signal provided by the mth control line; n and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M. According to the invention, under the condition that the resolution ratio of a display product is not changed, the use number of data drivers is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a multiplexing circuit, a multiplexing module, a display device and a driving method. Background Art

[0002] In the related art, in a display product, the number of data drivers is large, and the price of the data drivers is high, resulting in a high cost of current display products. Summary of the invention

[0003] The main purpose of the present invention is to provide a multiplexing circuit, a multiplexing module, a display device and a driving method to solve the problem of a large number of data drivers used in existing display products.

[0004] In one aspect, an embodiment of the present invention provides a multiplexing circuit, which is electrically connected to M data voltage supply terminals and multiple column data lines respectively, wherein the multiplexing circuit includes N multiplexing control lines and N multiplexing circuits, wherein the nth multiplexing circuit includes M multiplexing sub-circuits; and the nth multiplexing control line includes M control lines;

[0005] The mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected to the mth control line, the mth data voltage supply terminal and the corresponding data line included in the nth multiplexing control line, respectively, and is used to write the data voltage provided by the mth data voltage supply terminal into the corresponding data line under the control of the control signal provided by the mth control line;

[0006] Both N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

[0007] Optionally, the multiplexing circuit includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit, and a second multiplexing circuit;

[0008] The first multiplexed control line includes a first control line and a second control line; the second multiplexed control line includes a third control line and a fourth control line;

[0009] The first multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the second multiplexing circuit includes a third multiplexing sub-circuit and a fourth multiplexing sub-circuit;

[0010] The first multiplexing subcircuit is electrically connected to the first control line, the first data voltage supply terminal and the first column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the first column data line under the control of the first control signal provided by the first control line;

[0011] The second multiplexing subcircuit is electrically connected to the second control line, the second data voltage supply terminal and the second column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the second column data line under the control of the second control signal provided by the second control line;

[0012] The third multiplexing sub-circuit is electrically connected to the third control line, the first data voltage supply terminal and the third column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the third column data line under the control of the third control signal provided by the third control line;

[0013] The fourth multiplexing sub-circuit is electrically connected to the fourth control line, the second data voltage supply terminal and the fourth column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the fourth column data line under the control of a fourth control signal provided by the fourth control line.

[0014] Optionally, the first multiplexing sub-circuit includes a first transistor, and the second multiplexing sub-circuit includes a second transistor;

[0015] The gate of the first transistor is electrically connected to the first control line, the first electrode of the first transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the first transistor is electrically connected to the first column data line;

[0016] A gate of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the second transistor is electrically connected to the second column data line.

[0017] Optionally, both the first transistor and the second transistor are n-type transistors; or, both the first transistor and the second transistor are p-type transistors.

[0018] Optionally, the third multiplexing sub-circuit includes a third transistor, and the fourth multiplexing sub-circuit includes a fourth transistor;

[0019] The gate of the third transistor is electrically connected to the third control line, the first electrode of the third transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the third transistor is electrically connected to the third column data line;

[0020] A gate of the fourth transistor is electrically connected to the fourth control line, a first electrode of the fourth transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the fourth transistor is electrically connected to the fourth column data line.

[0021] Optionally, the third transistor and the fourth transistor are both n-type transistors; or, the third transistor and the fourth transistor are both p-type transistors.

[0022] An embodiment of the present invention further provides a multiplexing module, comprising a plurality of the above-mentioned multiplexing circuits.

[0023] An embodiment of the present invention further provides a display device, comprising a data driver, a plurality of columns of data lines and the above-mentioned multiplexing module;

[0024] The data driver is used to provide a data voltage to the multiplexing module through a data voltage supply terminal;

[0025] The data line is used to receive the data voltage provided by the multiplexing module.

[0026] Optionally, the data driver provides a control signal for each control line through at least one corresponding output channel.

[0027] Optionally, the display device includes a display panel, a data driver and a plurality of control lines;

[0028] The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel;

[0029] The data driver is further configured to provide a control signal input to the control line.

[0030] Optionally, the control line includes a first end and a second end;

[0031] The first output channel of the data driver is electrically connected to the first end, and the second output channel of the data driver is electrically connected to the second end. The data driver is used to provide a control signal to the first end through the first output channel and to provide a control signal to the second end through the second output channel.

[0032] Optionally, the display device includes a display panel, at least two data drivers and a plurality of control lines;

[0033] The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel;

[0034] The data driver is further configured to provide a control signal input to the control line.

[0035] Optionally, the control line is electrically connected to the at least two data drivers through at least three access points, and is used to receive a control signal provided by the data driver.

[0036] Optionally, the display device includes a first data driver and a second data driver;

[0037] The first output channel of the first data driver is electrically connected to the first end of the control line, and the first output channel of the second data driver is electrically connected to the second end of the control line;

[0038] The second output channel of the first data driver and the second output channel of the second data driver are both electrically connected to the middle node of the control line;

[0039] The first data driver is used to provide a control signal to the control line through its first output channel and its second output channel;

[0040] The second data driver is used for providing a control signal to the control line through a first output channel and a second output channel thereof.

[0041] Optionally, the display device according to at least one embodiment of the present invention further includes a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits;

[0042] The pixel circuit is electrically connected to the corresponding row gate line and the corresponding column data line respectively, and is used for controlling and receiving the data voltage provided by the corresponding column data line under the control of the gate driving signal provided by the corresponding row gate line.

[0043] An embodiment of the present invention further provides a driving method, which is applied to the above-mentioned display device, and the driving method includes:

[0044] The data driver provides a data voltage to the multiplexing module through a data voltage supply terminal;

[0045] The data line receives the data voltage provided by the multiplexing module.

[0046] Optionally, the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;

[0047] When the gate line of row 2a-1 is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on;

[0048] When the gate line in row 2a is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on.

[0049] Optionally, the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;

[0050] When the gate line of row 2a-1 is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on;

[0051] When the gate line in row 2a is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on.

[0052] The embodiment of the present invention uses at least two multiplexed control lines and one data voltage supply terminal to drive at least two columns of data lines, so that the number of data voltage supply terminals used is small, and the number of data drivers used can be reduced while ensuring that the resolution of the display product remains unchanged. At the same time, in order to reduce the load of the multiplexed control line, the multiplexed control line is set to include at least two control lines, and the at least two control lines are driven by different channels of the data driver. The number of transistors driven by each control line is reduced compared to the number of transistors driven by the related multiplexed control line. The load of the control line is reduced, which can effectively reduce the rise time and fall time of the control signal on the control line, and greatly improve the charging capacity of the control line. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a structural diagram of a multiplexing circuit according to at least one embodiment of the present invention;

[0054] Figure 2 is a circuit diagram of a multiplexing circuit according to at least one embodiment of the present invention;

[0055] Figure 3A is a schematic diagram of some transistors included in a multiplexing module according to at least one embodiment of the present invention;

[0056] Figure 3B is a waveform diagram of a first control signal provided by M11 in at least one embodiment of the present invention;

[0057] Figure 3C is a waveform diagram of a multiplexing control signal provided by a multiplexing control line in the related art;

[0058] Figure 4 yes Figure 3A A layout diagram of at least one embodiment shown;

[0059] Figure 5 yes Figure 4 A layout diagram of the gate metal layer in FIG.

[0060] Figure 6 yes Figure 4 A layout diagram of a semiconductor layer in FIG.

[0061] Figure 7 yes Figure 4Layout diagram of source and drain metal layers in FIG.

[0062] Figure 8 yes Figure 4 A layout diagram of a second conductive layer in FIG.

[0063] Fig. 9 is a structural diagram of a display device according to at least one embodiment of the present invention;

[0064] Fig.10 is a structural diagram of a display device according to at least one embodiment of the present invention;

[0065] Fig.11 yes Fig.10 A layout diagram of the middle portion of at least one embodiment shown;

[0066] Fig.12 yes Fig.11 A layout diagram of the gate metal layer in FIG.

[0067] Fig.13 yes Fig.11 Layout diagram of source and drain metal layers in FIG.

[0068] Fig.14 yes Fig.11 A layout diagram of a second conductive layer in FIG.

[0069] Fig.15 is a schematic diagram of the connection relationship between part of the pixel circuit and part of the multiplexing transistor included in the display device according to at least one embodiment of the present invention;

[0070] Fig.16 yes Fig.15 A timing diagram of operation of at least one embodiment shown;

[0071] Fig.17 yes Fig.15 A timing diagram of operation of at least one embodiment shown;

[0072] Fig.18 yes Fig.15 An operating timing diagram of at least one embodiment is shown. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0074] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0075] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0076] The multiplexing circuit described in the embodiment of the present invention is electrically connected to M data voltage supply terminals and multiple column data lines respectively, the multiplexing circuit includes N multiplexing control lines and N multiplexing circuits, the nth multiplexing circuit includes M multiplexing sub-circuits; the nth multiplexing control line includes M control lines;

[0077] The mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected to the mth control line, the mth data voltage supply terminal and the corresponding data line included in the nth multiplexing control line, respectively, and is used to write the data voltage provided by the mth data voltage supply terminal into the corresponding data line under the control of the control signal provided by the mth control line;

[0078] Both N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

[0079] In the related art, in TDDI (Touch and Display Driver Integration) products, the number of data drivers is large, and the price of data drivers is high, resulting in a high cost of current TDDI products. Based on this, an embodiment of the present invention proposes a data signal multiplexing circuit, which uses at least two multiplexing control lines and one data voltage supply terminal to drive at least two columns of data lines, so that the number of data voltage supply terminals used is small, and the number of data drivers used can be reduced while ensuring that the resolution of the display product remains unchanged. At the same time, in order to reduce the load of the multiplexing control line, the multiplexing control line is set to include at least two control lines, and the at least two control lines are driven by different channels of the data driver. The number of transistors driven by each control line is reduced compared to the number of transistors driven by the related multiplexing control line, and the load of the control line is reduced, which can effectively reduce the rise time and fall time of the control signal on the control line, and greatly improve the charging capacity of the control line.

[0080] In at least one embodiment of the present invention, N and M are both equal to 2 as an example, but the present invention is not limited thereto. In actual operation, N and M may be integers greater than 1.

[0081] The multiplexing circuit described in at least one embodiment of the present invention includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit;

[0082] The first multiplexed control line includes a first control line and a second control line; the second multiplexed control line includes a third control line and a fourth control line;

[0083] The first multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the second multiplexing circuit includes a third multiplexing sub-circuit and a fourth multiplexing sub-circuit;

[0084] The first multiplexing subcircuit is electrically connected to the first control line, the first data voltage supply terminal and the first column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the first column data line under the control of the first control signal provided by the first control line;

[0085] The second multiplexing subcircuit is electrically connected to the second control line, the second data voltage supply terminal and the second column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the second column data line under the control of the second control signal provided by the second control line;

[0086] The third multiplexing sub-circuit is electrically connected to the third control line, the first data voltage supply terminal and the third column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the third column data line under the control of the third control signal provided by the third control line;

[0087] The fourth multiplexing sub-circuit is electrically connected to the fourth control line, the second data voltage supply terminal and the fourth column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the fourth column data line under the control of a fourth control signal provided by the fourth control line.

[0088] In a specific implementation, the multiplexing circuit may include a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit, the first multiplexing control line may include a first control line and a second control line, the second multiplexing control line may include a third control line and a fourth control line, the first multiplexing sub-circuit writes the data voltage provided by the first data voltage supply end into the first column data line under the control of a first control signal, the second multiplexing sub-circuit writes the data voltage provided by the second data voltage supply end into the second column data line under the control of a second control signal, the third multiplexing sub-circuit writes the data voltage provided by the first data voltage supply end into the third column data line under the control of a third control signal; the fourth multiplexing sub-circuit writes the data voltage provided by the second data voltage supply end into the fourth column data line under the control of a fourth control signal.

[0089] like Figure 1 As shown, the multiplexing circuit according to at least one embodiment of the present invention is electrically connected to the first data voltage supply terminal S1, the second data voltage supply terminal S2, the first column data line D1, the second column data line D2, the third column data line D3 and the fourth column data line D4, respectively, and the multiplexing circuit includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit;

[0090] The first multiplexed control line includes a first control line M11 and a second control line M12, and the second multiplexed control line includes a third control line M21 and a fourth control line M22;

[0091] The first multiplexing circuit includes a first multiplexing sub-circuit 11 and a second multiplexing sub-circuit 12, and the second multiplexing circuit includes a third multiplexing sub-circuit 13 and a fourth multiplexing sub-circuit 14;

[0092] The first multiplexing sub-circuit 11 is electrically connected to the first control line M11, the first data voltage supply terminal S1 and the first column data line D1 respectively, and is used to write the data voltage provided by the first data voltage supply terminal S1 into the first column data line D1 under the control of the first control signal provided by the first control line M11;

[0093] The second multiplexing sub-circuit 12 is electrically connected to the second control line M12, the second data voltage supply terminal S2 and the second column data line D2 respectively, and is used to write the data voltage provided by the second data voltage supply terminal S2 into the second column data line D2 under the control of the second control signal provided by the second control line M12;

[0094] The third multiplexing sub-circuit 13 is electrically connected to the third control line M13, the first data voltage supply terminal S1 and the third column data line D3 respectively, and is used to write the data voltage provided by the first data voltage supply terminal S1 into the third column data line D3 under the control of the third control signal provided by the third control line M13;

[0095] The fourth multiplexing sub-circuit 14 is electrically connected to the fourth control line M14, the second data voltage supply terminal S2 and the fourth column data line D4 respectively, and is used to write the data voltage provided by the second data voltage supply terminal S2 into the fourth column data line D4 under the control of the fourth control signal provided by the fourth control line M14.

[0096] The present invention Figure 1When at least one embodiment of the multiplexing circuit shown is in operation, the first control signal provided by the first control line M11 and the second control signal provided by the second control line M12 can be the same, the third control signal provided by the third control line M13 and the fourth control signal provided by the fourth control line M14 can be the same, the first control line M11, the second control line M12, the third control line M13, and the fourth control line M14 are electrically connected to the first output channel of the data driver, the second output channel of the data driver, the third output channel of the data driver, and the fourth output channel of the data driver, respectively, and the corresponding output channels of the data driver provide control signals to each control line respectively, the number of transistors driven by each control line is halved compared to the number of transistors driven by the relevant multiplexed control line, the load of the control line is reduced, the rise time and fall time of the control signal on the control line can be effectively reduced, and the charging capacity of each control line is improved.

[0097] In the present invention Figure 1 In at least one embodiment of the multiplexing circuit shown, each control line may also be electrically connected to at least two output channels of the data driver to enhance the driving capability of the control line.

[0098] Optionally, the first multiplexing sub-circuit includes a first transistor, and the second multiplexing sub-circuit includes a second transistor;

[0099] The gate of the first transistor is electrically connected to the first control line, the first electrode of the first transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the first transistor is electrically connected to the first column data line;

[0100] A gate of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the second transistor is electrically connected to the second column data line.

[0101] Optionally, both the first transistor and the second transistor are n-type transistors; or, both the first transistor and the second transistor are p-type transistors.

[0102] Optionally, the third multiplexing sub-circuit includes a third transistor, and the fourth multiplexing sub-circuit includes a fourth transistor;

[0103] The gate of the third transistor is electrically connected to the third control line, the first electrode of the third transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the third transistor is electrically connected to the third column data line;

[0104] A gate of the fourth transistor is electrically connected to the fourth control line, a first electrode of the fourth transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the fourth transistor is electrically connected to the fourth column data line.

[0105] Optionally, the third transistor and the fourth transistor are both n-type transistors; or, the third transistor and the fourth transistor are both p-type transistors.

[0106] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the multiplexing circuit shown, the first multiplexing subcircuit includes a first transistor T1, and the second multiplexing subcircuit includes a second transistor T2;

[0107] The gate of the first transistor T1 is electrically connected to the first control line M11, the source of the first transistor T1 is electrically connected to the first data voltage supply terminal S1, and the drain of the first transistor T1 is electrically connected to the first column data line D1;

[0108] The gate of the second transistor T2 is electrically connected to the second control line M12, the source of the second transistor T2 is electrically connected to the second data voltage supply terminal S2, and the drain of the second transistor T2 is electrically connected to the second column data line D2;

[0109] The third multiplexing sub-circuit includes a third transistor T3, and the fourth multiplexing sub-circuit includes a fourth transistor T4;

[0110] The gate of the third transistor T3 is electrically connected to the third control line M13, the source of the third transistor T3 is electrically connected to the first data voltage supply terminal S1, and the drain of the third transistor T3 is electrically connected to the third column data line D3;

[0111] A gate of the fourth transistor T4 is electrically connected to the fourth control line M14 , a source of the fourth transistor T4 is electrically connected to the second data voltage supply terminal S2 , and a drain of the fourth transistor T4 is electrically connected to the fourth column data line D4 .

[0112] exist Figure 2 In at least one embodiment of the multiplexing circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0113] Figure 2 When at least one embodiment of the multiplexing circuit shown is in operation, a data providing cycle may include a first multiplexing phase and a second multiplexing phase;

[0114] In the first multiplexing stage, M11 and M12 both provide high voltage signals, T1 and T2 are both turned on, S1 is connected to D1, S2 is connected to D2, a data voltage is provided to D1 through S1, and a data voltage is provided to D2 through S2;

[0115] In the second multiplexing stage, M13 and M14 both provide high voltage signals, T3 and T4 are both turned on, S1 is connected to D3, S2 is connected to D4, a data voltage is provided to D3 through S1, and a data voltage is provided to D4 through S2.

[0116] The multiplexing module described in the embodiment of the present invention includes a plurality of the above-mentioned multiplexing circuits.

[0117] Figure 3A A schematic diagram of some transistors included in a multiplexing module according to at least one embodiment of the present invention is shown.

[0118] like Figure 3A As shown, the multiplexing module described in at least one embodiment of the present invention includes a first multiplexing circuit and a second multiplexing circuit;

[0119] The first multiplexing circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;

[0120] The second multiplexing circuit includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;

[0121] The gate of the first transistor T1 is electrically connected to the first control line M11, the source of the first transistor T1 is electrically connected to the first data voltage supply terminal S1, and the drain of the first transistor T1 is electrically connected to the first column data line D1;

[0122] The gate of the second transistor T2 is electrically connected to the second control line M12, the source of the second transistor T2 is electrically connected to the second data voltage supply terminal S2, and the drain of the second transistor T2 is electrically connected to the second column data line D2;

[0123] The gate of the third transistor T3 is electrically connected to the third control line M13, the source of the third transistor T3 is electrically connected to the first data voltage supply terminal S1, and the drain of the third transistor T3 is electrically connected to the third column data line D3;

[0124] The gate of the fourth transistor T4 is electrically connected to the fourth control line M14, the source of the fourth transistor T4 is electrically connected to the second data voltage supply terminal S2, and the drain of the fourth transistor T4 is electrically connected to the fourth column data line D4;

[0125] The gate of the fifth transistor T5 is electrically connected to the first control line M11, the source of the fifth transistor T5 is electrically connected to the third data voltage supply terminal S3, and the drain of the fifth transistor T5 is electrically connected to the fifth column data line D5;

[0126] The gate of the sixth transistor T6 is electrically connected to the second control line M12, the source of the sixth transistor T6 is electrically connected to the fourth data voltage supply terminal S4, and the drain of the sixth transistor T6 is electrically connected to the sixth column data line D6;

[0127] The gate of the seventh transistor T7 is electrically connected to the third control line M13, the source of the seventh transistor T7 is electrically connected to the third data voltage supply terminal S3, and the drain of the seventh transistor T7 is electrically connected to the seventh data line D7;

[0128] The gate of the eighth transistor T8 is electrically connected to the fourth control line M14, the source of the eighth transistor T8 is electrically connected to the fourth data voltage supply terminal S4, and the drain of the eighth transistor T8 is electrically connected to the eighth data line D8.

[0129] exist Figure 3A In at least one embodiment shown, T1 , T2 , T3 , T4 , T5 , T6 , T7 , and T8 are all n-type transistors, but the present invention is not limited thereto.

[0130] The present invention Figure 3A When at least one embodiment shown is in operation, a data provision cycle may include a first multiplexing phase and a second multiplexing phase;

[0131] In the first multiplexing stage, M11 and M12 both provide high voltage signals, T1, T2, T5 and T6 are all turned on, S1 is connected to D1, S2 is connected to D2, a data voltage is provided to D1 through S1, and a data voltage is provided to D2 through S2; S3 is connected to D5, S4 is connected to D6, a data voltage is provided to D5 through S3, and a data voltage is provided to D6 through S4;

[0132] In the second multiplexing stage, M13 and M14 both provide high voltage signals, T3, T4, T7 and T8 are all turned on, S1 is connected to D3, S2 is connected to D4, data voltage is provided to D3 through S1, and data voltage is provided to D4 through S2; S3 is connected to D7, S4 is connected to D8, data voltage is provided to D7 through S3, and data voltage is provided to D8 through S4.

[0133] The present invention Figure 3AAt least one embodiment shown uses half the number of transistors, and S1 drives D1 and D3, S2 drives D2 and D4. When S1 provides a positive polarity data voltage, D1 and D3 provide a positive polarity data voltage, and when S2 provides a negative polarity data voltage, D2 and D4 provide a negative polarity data voltage, thereby achieving the purpose of opposite polarity of data voltages on data lines adjacent to pixel areas.

[0134] Figure 3B is a waveform diagram of a first control signal provided by M11 in at least one embodiment of the present invention;

[0135] Figure 3C is a waveform diagram of a multiplexing control signal provided by a multiplexing control line in the related art.

[0136] contrast Figure 3B and Figure 3C The rise time and fall time of the first control signal provided by M11 are shorter, while in the related art, the rise time and fall time of the multiplexing control signal M1 provided by the multiplexing control line are longer.

[0137] In at least one embodiment of the present invention, the rise time of the first control signal provided by M11 can be 0.26μs, and the fall time of the first control signal provided by M11 can be 0.25μs. In the related art, the rise time of the multiplexed control signal M1 is 0.46μs, and the fall time of the multiplexed control signal M1 is 0.45μs. It can be seen from the above that in at least one embodiment of the present invention, the control signal is more beneficial to charging.

[0138] Figure 4 yes Figure 3A A layout diagram of at least one embodiment is shown.

[0139] Figure 5 yes Figure 4 Layout diagram of the gate metal layer in .

[0140] exist Figure 5 , labeled G1 is the gate of T1, labeled G2 is the gate of T2, labeled G3 is the gate of T3, labeled G4 is the gate of T4, labeled G5 is the gate of T5, labeled G6 is the gate of T6, labeled G7 is the gate of T7, and labeled G8 is the gate of T8.

[0141] Figure 6 yes Figure 4 Layout diagram of the semiconductor layers in .

[0142] exist Figure 6, labeled A1 is the active pattern of T1, labeled A2 is the active pattern of T2, labeled A3 is the active pattern of T3, labeled A4 is the active pattern of T4, labeled A5 is the active pattern of T5, labeled A6 is the active pattern of T6, labeled A7 is the active pattern of T7, and labeled A8 is the active pattern of T8.

[0143] Figure 7 yes Figure 4 Layout diagram of the source and drain metal layers.

[0144] exist Figure 7 , the source-drain pattern labeled SD1 is T1, the source-drain pattern labeled SD2 is T2, the source-drain pattern labeled SD3 is T3, the source-drain pattern labeled SD4 is T4, the source-drain pattern labeled SD5 is T5, the source-drain pattern labeled SD6 is T6, the source-drain pattern labeled SD7 is T7, and the source-drain pattern labeled SD8 is T8.

[0145] Figure 8 yes Figure 4 Layout diagram of the second conductive layer in .

[0146] exist Figure 4 In the embodiment, the gate metal layer, the semiconductor layer, the source-drain metal layer and the second conductive layer can be arranged in sequence along a direction away from the substrate, a first conductive layer can be provided between the source-drain metal layer and the second conductive layer, and the first conductive layer can be a common electrode layer of the entire layer; the second conductive layer can be a pixel electrode layer, and in the display area, the second conductive layer can include a pixel electrode; the first conductive layer and the second conductive layer can both be made of ITO (indium tin oxide), but are not limited to this.

[0147] In at least one embodiment of the present invention, a touch electrode layer may be disposed between the source / drain metal layer and the first conductive layer, but the present invention is not limited thereto.

[0148] The display device described in the embodiment of the present invention includes a data driver, a plurality of columns of data lines and the above-mentioned multiplexing module;

[0149] The data driver is used to provide a data voltage to the multiplexing module through a data voltage supply terminal;

[0150] The data line is used to receive the data voltage provided by the multiplexing module.

[0151] In an embodiment of the present invention, the display device may include a data driver and the above-mentioned multiplexing module, and the data driver provides a data voltage to a corresponding data line for the multiplexing resistor via a data voltage supply terminal.

[0152] Optionally, the data driver provides a control signal to each of the control lines through at least one corresponding output channel to enhance the driving capability of each control line.

[0153] In at least one embodiment of the present invention, the display device includes a display panel, a data driver and a plurality of control lines;

[0154] The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel;

[0155] The data driver is further configured to provide a control signal input to the control line.

[0156] In a specific implementation, the display device may include only one data driver, and the control line may be arranged between the data driver and the effective display area of ​​the display panel, and the data driver provides a control signal to the control line.

[0157] Optionally, the control line includes a first end and a second end;

[0158] The first output channel of the data driver is electrically connected to the first end, and the second output channel of the data driver is electrically connected to the second end. The data driver is used to provide a control signal to the first end through the first output channel and to provide a control signal to the second end through the second output channel.

[0159] In a specific implementation, when the display device includes a data driver, the data driver can be electrically connected to the first end of the control line through an output channel, and electrically connected to the second end of the control line through another output channel, and provide a control signal to the control line through the first end and the second end respectively, so as to enhance the driving capability of the control line.

[0160] In one embodiment of the present invention, when the display panel is a display product with a resolution of 1200×2000, the display panel includes 2000 rows of pixel circuits, and the number of data lines included in the display panel is 3600 columns. If one data voltage supply end of the data driver drives two columns of data lines, a data driver is required; at this time, the data driver can be electrically connected to the first end of the control line through an output channel, and electrically connected to the second end of the control line through another output channel to improve the driving capability of the control line.

[0161] like Fig. 9 As shown, the area labeled A0 is the effective display area, and the area labeled SI is the data driver;

[0162] The line labeled M11 is the first control line;

[0163] The data driver SI is disposed below A0, and the first control line M11 is disposed between the data driver SI and the effective display area A0;

[0164] The data driver SI is electrically connected to the first end of the first control line M11 through the first output channel CH1 located on the left side thereof;

[0165] The data driver SI is electrically connected to the second end of the first control line M11 through the second output channel CH2 located on the right side thereof;

[0166] Both ends of the first control line M11 are driven simultaneously.

[0167] In at least one embodiment of the present invention, the second control line M12 , the third control line M13 and the fourth control line M14 may be driven in the same manner as the first control line M11 , and are all driven simultaneously from both ends of the line.

[0168] In at least one embodiment of the present invention, the display device includes a display panel, at least two data drivers, and a plurality of control lines;

[0169] The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel;

[0170] The data driver is further configured to provide a control signal input to the control line.

[0171] In a specific implementation, when the display device includes at least two data drivers, the control line may be arranged between the data driver and the effective display area of ​​the display panel, and the data driver provides a control signal input to the control line.

[0172] In at least one embodiment of the present invention, the control line is electrically connected to the at least two data drivers through at least three access points, and is used to receive a control signal provided by the data driver.

[0173] In a specific implementation, the control line can be electrically connected to the at least two data drivers through at least three access points to receive a control signal, which can further enhance the driving capability of the control line.

[0174] Optionally, the display device includes a first data driver and a second data driver;

[0175] The first output channel of the first data driver is electrically connected to the first end of the control line, and the first output channel of the second data driver is electrically connected to the second end of the control line;

[0176] The second output channel of the first data driver and the second output channel of the second data driver are both electrically connected to the middle node of the control line;

[0177] The first data driver is used to provide a control signal to the control line through its first output channel and its second output channel;

[0178] The second data driver is used for providing a control signal to the control line through a first output channel and a second output channel thereof.

[0179] In a specific implementation, for a display panel with a resolution of 1840×2944, the number of rows of pixel circuits included in the display panel is 1840 rows, the number of data lines included in the display panel is 8832 columns, and a driving architecture that uses one data voltage supply terminal to drive two columns of data lines requires 4416 data voltage supply terminals; the number of channels of each data driver is 2400, so two data drivers are required.

[0180] like Fig.10 As shown, the effective display area is labeled A0, the first data driver is labeled SI1, the second data driver is labeled SI2; and the first control line is labeled M11;

[0181] The first control line M11 is disposed between the data driver and the effective display area A0;

[0182] The first output channel CH11 of the first data driver SI1 is electrically connected to the first end of the first control line M11, and the first output channel CH21 of the second data driver SI2 is electrically connected to the second end of the first control line M11;

[0183] The second output channel CH12 of the first data driver SI1 and the second output channel CH22 of the second data driver SI2 are both electrically connected to the middle node N0 of the control line;

[0184] The first data driver SI1 provides a control signal to the first control line M11 through CH11 and CH12;

[0185] The second data driver SI2 provides a control signal to the first control line M11 through CH21 and CH22.

[0186] In specific implementation, the driving method of the second control line M12, the driving method of the third control line M13 and the driving method of the fourth control line M14 are the same as the driving method of the first control line M11, and each line is connected to the driving signal at three positions to further enhance the driving capability of each control signal.

[0187] Fig.11 yes Fig.10 The layout diagram of the middle part in at least one embodiment shown shows the connection relationship between the connection line between two data drivers and the middle nodes of each control line.

[0188] exist Fig.11 , the first connection line labeled M01 is between the first source driver and the second source driver, the second connection line labeled M02 is between the first source driver and the second source driver, the third connection line labeled M03 is between the first source driver and the second source driver, and the connection line labeled M04 is between the first source driver and the second source driver;

[0189] M01 is electrically connected to M11 through the first connection portion L1, M02 is electrically connected to M12 through the second connection portion L2, M03 is electrically connected to M13 through the third connection portion L3, and M04 is electrically connected to M14 through the fourth connection portion L4.

[0190] Fig.12 yes Fig.11 Layout diagram of the gate metal layer in, M01, M02, M03, M04, M11, M12, M13 and M14 can all be formed in the gate metal layer.

[0191] Fig.13 yes Fig.11 Layout diagram of the source and drain metal layers.

[0192] Fig.14 yes Fig.11 Layout diagram of the second conductive layer in FIG. 1 , L1 , L2 , L3 , and L4 may be formed in the second conductive layer.

[0193] The display device described in at least one embodiment of the present invention further includes a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits;

[0194] The pixel circuit is electrically connected to the corresponding row gate line and the corresponding column data line respectively, and is used for controlling and receiving the data voltage provided by the corresponding column data line under the control of the gate driving signal provided by the corresponding row gate line.

[0195] In a specific implementation, the display device may include a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits. The pixel circuits receive data voltages provided by data lines under the control of gate drive signals.

[0196] The display device described in the embodiment of the present invention may be a TDDI product, but is not limited thereto. In actual operation, the display device may also be other types of display products.

[0197] The driving method described in the embodiment of the present invention is applied to the above-mentioned display device, and the driving method includes:

[0198] The data driver provides a data voltage to the multiplexing module through a data voltage supply terminal;

[0199] The data line receives the data voltage provided by the multiplexing module.

[0200] In at least one embodiment of the present invention, the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;

[0201] When the gate line of row 2a-1 is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on;

[0202] When the gate line in row 2a is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on.

[0203] Among them, the first multiplexing control line may include a first control line and a second control line, the second multiplexing control line may include a third control line and a fourth control line, the first control line and the second control line respectively control corresponding multiplexing transistors, and the third control line and the fourth control line respectively control corresponding multiplexing transistors.

[0204] In a specific implementation, when the odd-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to be turned on through the first multiplexing control line, and then the corresponding multiplexing transistors can be controlled to be turned on through the second multiplexing control line; after the even-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to be turned on through the second multiplexing control line, and then the corresponding multiplexing transistors can be controlled to be turned on through the first multiplexing control line. In this way, the frequency of the control signals on each multiplexing control line is low and the power consumption is small.

[0205] In at least one embodiment of the present invention, the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;

[0206] When the gate line of row 2a-1 is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on;

[0207] When the gate line in row 2a is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on.

[0208] Among them, the first multiplexing control line may include a first control line and a second control line, the second multiplexing control line may include a third control line and a fourth control line, the first control line and the second control line respectively control corresponding multiplexing transistors, and the third control line and the fourth control line respectively control corresponding multiplexing transistors.

[0209] In a specific implementation, when the odd-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to be turned on through the second multiplexing control line, and then the corresponding multiplexing transistors can be controlled to be turned on through the first multiplexing control line; after the even-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to be turned on through the first multiplexing control line, and then the corresponding multiplexing transistors can be controlled to be turned on through the second multiplexing control line. In this way, the frequency of the control signals on each multiplexing control line is low and the power consumption is small.

[0210] like Fig.15 As shown, the first multiplexing control line includes a first control line M11 that controls the first transistor T1, and the second multiplexing control line includes a third control line M13 that controls the third transistor T3;

[0211] The terminal labeled S1 is a first data voltage supply terminal;

[0212] The pixel circuit labeled P11 is the first row and first column, and the pixel circuit labeled P13 is the first row and third column;

[0213] P11 and P13 are both electrically connected to the first row gate line GT1, P11 is electrically connected to the first column data line D1, and P13 is electrically connected to the third column data line D3;

[0214] The pixel circuit labeled P21 is the second row and first column, and the pixel circuit labeled P23 is the second row and third column;

[0215] P21 and P23 are both electrically connected to the second row gate line GT2, P21 is electrically connected to the first column data line D1, and P23 is electrically connected to the third column data line D3;

[0216] The pixel circuit labeled P31 is the pixel circuit in the third row and first column, and the pixel circuit labeled P33 is the pixel circuit in the third row and third column;

[0217] Both P31 and P33 are electrically connected to the third row gate line GT3, P31 is electrically connected to the first column data line D1, and P33 is electrically connected to the third column data line D3.

[0218] Fig.15 At least one embodiment shown in the figure is in operation, when driving the first row of pixel circuits,

[0219] like Fig.16 As shown, the potential of the first gate driving signal output by GT1 first rises from a low voltage to a high voltage, and then the control signal output by M11 rises from a low voltage to a high voltage, and T1 is turned on to write the data voltage provided by S1 into the first column data line D1. When the potential of the first gate driving signal is a high voltage, P11 receives the data voltage provided by D1;

[0220] like Fig.17As shown, the potential of the first gate driving signal output by GT1 first rises from a low voltage to a high voltage, and then the control signal output by M13 rises from a low voltage to a high voltage, and T3 is turned on to write the data voltage provided by S1 into the third column data line D3. When the potential of the first gate driving signal is a high voltage, P13 receives the data voltage provided by D3;

[0221] T1 and T3 are n-type transistors.

[0222] In specific implementation, Fig.15 At least one embodiment shown in the figure can be driven in a bow-shaped manner during operation, that is, Fig.18 As shown,

[0223] GT1 is turned on first, then in the first time period P1, M11 outputs a high voltage signal, M11 first controls T1 to turn on, and writes the data voltage into P11, then in the second time period P2, M13 outputs a high voltage signal, M13 controls T3 to turn on, and writes the data voltage into P13;

[0224] Afterwards, GT2 is turned on, and then in the third time period P3, M13 outputs a high voltage signal, M13 first controls T3 to turn on, and writes the data voltage into P23, and then in the fourth time period P4, M11 outputs a high voltage signal, and M11 controls T1 to turn on, and writes the data voltage into P21;

[0225] Afterwards, GT3 is turned on, and then in the fifth time period P5, M11 outputs a high voltage signal, M11 first controls T1 to turn on, and writes the data voltage to P31, and then in the sixth time period P6, M13 outputs a high voltage signal, and M13 controls T3 to turn on, and writes the data voltage to P33.

[0226] Fig.18 yes Fig.15 An operating timing diagram of at least one embodiment is shown.

[0227] like Fig.18 As shown, the frequencies of the control signals provided by M11 and M13 are relatively low, which is beneficial to reducing power consumption.

[0228] In at least one embodiment of the present invention, the width-to-length ratio of each multiplexing transistor may be greater than or equal to 50 and less than or equal to 100, but is not limited thereto.

[0229] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A multiplexing circuit, electrically connected to M data voltage supply terminals and a plurality of columns of data lines, characterized in that: The multiplexing circuit includes N multiplexing control lines and N multiplexing circuits, the nth multiplexing circuit includes M multiplexing sub-circuits; the nth multiplexing control line includes M control lines; The mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected to the mth control line, the mth data voltage supply terminal and the corresponding data line included in the nth multiplexing control line, respectively, and is used to write the data voltage provided by the mth data voltage supply terminal into the corresponding data line under the control of the control signal provided by the mth control line; Both N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

2. The multiplexing circuit according to claim 1, characterized in that The multiplexing circuit includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit; The first multiplexed control line includes a first control line and a second control line; the second multiplexed control line includes a third control line and a fourth control line; The first multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the second multiplexing circuit includes a third multiplexing sub-circuit and a fourth multiplexing sub-circuit; The first multiplexing subcircuit is electrically connected to the first control line, the first data voltage supply terminal and the first column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the first column data line under the control of the first control signal provided by the first control line; The second multiplexing subcircuit is electrically connected to the second control line, the second data voltage supply terminal and the second column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the second column data line under the control of the second control signal provided by the second control line; The third multiplexing sub-circuit is electrically connected to the third control line, the first data voltage supply terminal and the third column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the third column data line under the control of the third control signal provided by the third control line; The fourth multiplexing sub-circuit is electrically connected to the fourth control line, the second data voltage supply terminal and the fourth column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the fourth column data line under the control of a fourth control signal provided by the fourth control line.

3. The multiplexing circuit according to claim 2, characterized in that The first multiplexing subcircuit includes a first transistor, and the second multiplexing subcircuit includes a second transistor; The gate of the first transistor is electrically connected to the first control line, the first electrode of the first transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the first transistor is electrically connected to the first column data line; A gate of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the second transistor is electrically connected to the second column data line.

4. The multiplexing circuit according to claim 3, characterized in that The first transistor and the second transistor are both n-type transistors; or, the first transistor and the second transistor are both p-type transistors.

5. The multiplexing circuit according to claim 2, characterized in that The third multiplexing sub-circuit includes a third transistor, and the fourth multiplexing sub-circuit includes a fourth transistor; The gate of the third transistor is electrically connected to the third control line, the first electrode of the third transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the third transistor is electrically connected to the third column data line; A gate of the fourth transistor is electrically connected to the fourth control line, a first electrode of the fourth transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the fourth transistor is electrically connected to the fourth column data line.

6. The multiplexing circuit according to claim 5, characterized in that The third transistor and the fourth transistor are both n-type transistors; or, the third transistor and the fourth transistor are both p-type transistors.

7. A multiplexing module, characterized in that: Comprising a plurality of multiplexing circuits as claimed in any one of claims 1 to 6.

8. A display device, characterized in that: comprising a data driver, a plurality of columns of data lines and a multiplexing module as claimed in claim 7; The data driver is used to provide a data voltage to the multiplexing module through a data voltage supply terminal; The data line is used to receive the data voltage provided by the multiplexing module.

9. The display device according to claim 8, wherein: The data driver provides a control signal to each control line through at least one corresponding output channel.

10. The display device according to claim 8, wherein: The display device includes a display panel, a data driver and a plurality of control lines; The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel; The data driver is further configured to provide a control signal input to the control line.

11. The display device according to claim 10, wherein: The control line includes a first end and a second end; The first output channel of the data driver is electrically connected to the first end, and the second output channel of the data driver is electrically connected to the second end. The data driver is used to provide a control signal to the first end through the first output channel and to provide a control signal to the second end through the second output channel.

12. The display device according to claim 9, wherein: The display device includes a display panel, at least two data drivers and a plurality of control lines; The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel; The data driver is further configured to provide a control signal input to the control line.

13. The display device according to claim 12, wherein: The control line is electrically connected to the at least two data drivers through at least three access points, and is used to receive a control signal provided by the data driver.

14. The display device according to claim 13, wherein: The display device includes a first data driver and a second data driver; The first output channel of the first data driver is electrically connected to the first end of the control line, and the first output channel of the second data driver is electrically connected to the second end of the control line; The second output channel of the first data driver and the second output channel of the second data driver are both electrically connected to the middle node of the control line; The first data driver is used to provide a control signal to the control line through its first output channel and its second output channel; The second data driver is used for providing a control signal to the control line through a first output channel and a second output channel thereof.

15. The display device according to any one of claims 8 to 14, characterized in that: Also includes a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits; The pixel circuit is electrically connected to the corresponding row gate line and the corresponding column data line respectively, and is used for controlling and receiving the data voltage provided by the corresponding column data line under the control of the gate driving signal provided by the corresponding row gate line.

16. A driving method, applied to the display device according to any one of claims 8 to 15, characterized in that: The driving method comprises: The data driver provides a data voltage to the multiplexing module through a data voltage supply terminal; The data line receives the data voltage provided by the multiplexing module.

17. The driving method according to claim 16, characterized in that: The display device further comprises a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer; When the gate line of row 2a-1 is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on; When the gate line in row 2a is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on.

18. The driving method according to claim 16, characterized in that: The display device further comprises a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer; When the gate line of row 2a-1 is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on; When the gate line in row 2a is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on.

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