Preparation method of strain channel FinFET

Abstract

The invention discloses a preparation method of a strain channel FinFET, and belongs to the technical field of integrated circuit manufacturing. According to the method, after the Fin line is manufactured, amorphous silicon is generated through an injection amorphization method, the amorphous silicon is recrystallized after a strain medium layer is adopted for covering and high-temperature annealing is conducted, at the moment, tensile stress / compressive stress needed by an N / PMOS can be formed between the crystalline silicon and a strain medium, and then the strain medium material is selectively removed, so that preparation of the strain channel FinFET is achieved. According to the invention, lattice mismatch between the strain dielectric material and the crystalline silicon is utilized to generate tensile stress or compressive stress required by a FinFET device, N / PMOS channel strain is realized by using a single strain material, the process of channel stress engineering is simplified, the process complexity is reduced, and the method has the potential of being applied to technical nodes of 14 nm and above.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, in particular to 14nm and above advanced technology nodes, and specifically relates to a preparation process of a strained channel FinFET. Background Art

[0002] Traditional MOSFET devices mainly improve device performance and the density of transistors per unit area by proportional reduction, while improving channel mobility, device driving performance and circuit switching speed by reducing gate length and applying stress. However, as process nodes continue to shrink, the short channel effect continues to strengthen. Traditional methods of improving the short channel effect will reduce carrier mobility and reduce device speed. Therefore, it is necessary to introduce new technologies to improve carrier mobility, thereby improving device performance and circuit switching speed.

[0003] In recent years, in order to address the problem of carrier reduction, the current mainstream FinFET structure mainly introduces stress through source and drain epitaxy to improve carrier mobility. Specifically, tensile stress is formed in the source and drain epitaxial silicon carbide (SiC) or doped silicon (SiGe) of NMOS to improve electron mobility. Compressive stress is formed in the source and drain epitaxial silicon germanium (Si1-xGex) of PMOS to improve hole mobility. However, N / PMOS source and drain epitaxy involves two etchings, two processes, and two photolithography, which increases the complexity and cost of the process flow and may cause process fluctuations. Therefore, it is urgent to develop a low-cost, simple process and reliable FinFET channel stress introduction method. Summary of the invention

[0004] In view of the above problems, the present invention provides a method for preparing a strained channel FinFET, comprising the following steps:

[0005] 1) Forming Fin lines on a semiconductor substrate;

[0006] 2) Using standard CMOS technology to form shallow trench isolation between Fins;

[0007] 3) Perform amorphization implantation on the Fin lines to form amorphous Fin lines;

[0008] 4) Depositing a strained dielectric layer to completely cover the amorphous Fin lines;

[0009] 5) High temperature annealing causes the amorphous Fin lines to crystallize and form stressed silicon;

[0010] 6) Photolithography forms an etching area, and selectively etches away the strained dielectric layer;

[0011] 7) Subsequently, a standard FinFET process is used to form a FinFET transistor.

[0012] Furthermore, in the above step 3), the amorphization implantation equipment is an ion implanter, and the implanted ions may be one of Ge, Si, Ar, H plasma, etc., and the implantation energy range is between 1 and 30 KeV;

[0013] Furthermore, the material of the strained dielectric layer in step 4) can be SiN x (x=1~1.5),Si y C z N4(y+z=3~4),SiO a N b (a=0~2, b=0~4), SiO2, etc., the strained dielectric layer deposition thickness is between 10 and 500 nm.

[0014] Furthermore, in the above step 4), the strained dielectric layer material deposition can be carried out by chemical vapor deposition (Chemical Vapor Deposition), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), atomic layer deposition (Atom Layer Deposition, ALD) plasma enhanced atomic layer deposition (Plasma Enhanced Atom Layer Deposition, PEALD) and the like.

[0015] Furthermore, in the above step 4), after the strained dielectric layer completely covers the amorphous Fin lines, part of the strained dielectric material is selectively etched away to control the magnitude of the FinFET channel stress.

[0016] Furthermore, the high temperature annealing method in step 5) can be one of rapid thermal annealing (RTA), laser annealing, flash annealing and spike annealing, and the temperature range of the high temperature annealing is 700°C to 1800°C.

[0017] Furthermore, the etching method in step 6) may be one of etching methods such as plasma etching, ion beam sputtering etching, reactive ion etching (RIE), inductively coupled plasma (ICP), wet etching, etc.

[0018] The advantages and positive effects of the present invention are as follows:

[0019] 1) After the Fin lines are made, the present invention generates amorphous silicon by injecting an amorphization method, and after covering with a strained dielectric layer and high-temperature annealing, the amorphous silicon is recrystallized. At this time, the tensile stress / compressive stress required for N / PMOS can be formed between the crystalline silicon and the strained dielectric, and then the strained dielectric material is selectively removed to achieve the preparation of strained channel FinFET. The present invention utilizes the lattice mismatch between the strained dielectric material and the crystalline silicon to generate the tensile stress or compressive stress required for the FinFET device, and achieves N / PMOS channel strain by using a single strained material, thereby reducing the process complexity.

[0020] 2) The process of channel stress engineering is simplified. Specifically, the traditional stress introduction process is two photolithography, two etchings, and two epitaxy, while the process adopted by the present invention is one photolithography, one etching, and one epitaxy.

[0021] 3) While reducing the number of process steps, the process fluctuations caused by more complex processes are avoided.

[0022] 4) There will not be many changes to the existing FinFET process, and the traditional FinFET process flow can still be used after stress engineering.

[0023] 5) In the case of small contact gate pitch (CPP), source-drain epitaxy may not even be used.

[0024] Based on the above characteristics, the preparation process of the strained channel FinFET of the present invention has the potential to be applied to technology nodes of 14 nm and above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1-Figure 7 Schematic diagram of each key process step of the strained channel FinFET of the present invention. In each figure, (a) is a top view, (b) is a cross-sectional view of the device along the A-A' direction (channel cross section) of (a), and (c) is a cross-sectional view of the device along the B-B' direction (Fin arrangement) of (a). Among them:

[0026] Figure 1 It is a schematic diagram of the steps of Fin etching;

[0027] Figure 2 A schematic diagram of the steps of forming shallow trench isolation between Fins using a standard process;

[0028] Figure 3 A schematic diagram of the steps of performing amorphization implantation on the Fin lines to form amorphous Fin lines;

[0029] Figure 4 Schematic diagram of the steps for depositing a strained material layer to completely cover the amorphous Fin lines;

[0030] Figure 5 A schematic diagram of the steps of selectively etching and removing a portion of the strained dielectric layer by photolithography to form an etching area;

[0031] Figure 6 Schematic diagram of the steps of high temperature annealing to crystallize amorphous Fin lines;

[0032] Figure 7 removing the strained dielectric layer for selective etching;

[0033] Figure 8 for Figure 1 to Figure 7 Illustration of the materials used. DETAILED DESCRIPTION

[0034] The present invention provides a process for preparing a strained channel FinFET, comprising the following steps:

[0035] 1) Etching Fin lines on the semiconductor substrate, such as Figure 1 As shown;

[0036] 2) Use standard CMOS technology to form shallow trench isolation between Fins, such as Figure 2 As shown;

[0037] 3) Perform amorphization implantation on the Fin lines to form amorphous Fin lines. The amorphization implantation equipment is an ion implanter. The implanted ions can be one of Ge, Si, Ar, H plasma, etc. The implantation energy range is between 1 and 30 KeV. Figure 3 As shown;

[0038] 4) Deposit a strained material layer to completely cover the amorphous Fin lines. The strained dielectric layer material can be SiN x (x=1~1.5),Si y C z N4(y+z=3~4),SiO a N b (a=0~2, b=0~4), SiO2, etc. The thickness of the strain dielectric layer deposition is between 10 and 500 nm. The strain layer material deposition can be carried out by chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition plasma enhanced atomic layer deposition, such as Figure 4 As shown;

[0039] In order to adjust the magnitude of the FinFET channel stress, the present invention can deposit a strained material layer to completely cover the amorphous Fin lines, and then selectively etch away part of the strained material layer; Figure 5 As shown;

[0040] 5) High temperature annealing crystallizes the amorphous Fin lines to form stressed silicon, wherein the temperature range of high temperature annealing is 700℃~1800℃, and the high temperature annealing method can be rapid thermal annealing, laser annealing, flash annealing or spike annealing, such as Figure 6 As shown;

[0041] 6) Photolithography forms an etching area, and selectively etches to remove the strained dielectric layer. The etching method can be plasma etching, ion beam sputtering etching, reactive plasma etching, or inductively coupled plasma, wet etching, etc. Figure 7 As shown;

[0042] 7) Subsequently, a standard FinFET process is used to form a FinFET transistor.

[0043] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for preparing a strained channel FinFET, comprising the following steps: 1) Forming Fin lines on a semiconductor substrate; 2) Using standard CMOS technology to form shallow trench isolation between Fins; 3) Perform amorphization implantation on the Fin lines to form amorphous Fin lines; 4) Depositing a strained dielectric layer to completely cover the amorphous Fin lines; 5) High temperature annealing causes the amorphous Fin lines to crystallize and form stressed silicon; 6) Photolithography forms an etching area, and selectively etches away the strained dielectric layer; 7) Subsequently, a standard FinFET process is used to form a FinFET transistor.

2. The preparation method according to claim 1, characterized in that The amorphization implantation in step 3) is specifically that the equipment is an ion implanter, the implanted ions are one of Ge, Si, Ar or H ions, and the implantation energy ranges between 1 and 30 KeV.

3. The preparation method according to claim 1, characterized in that: In step 4), the strain dielectric layer material is SiN x 、Si y C z N4、SiO a N b Or SiO2, the strain dielectric layer deposition thickness is between 10 and 500 nm.

4. The preparation method according to claim 1, characterized in that: In step 4), the strain dielectric layer material is deposited by chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or plasma enhanced atomic layer deposition.

5. The preparation method according to claim 1, characterized in that: In step 4), after the strained dielectric layer completely covers the amorphous Fin lines, part of the strained dielectric material is selectively etched away.

6. The preparation method according to claim 1, characterized in that: Step 5) The medium and high temperature annealing method adopts one of rapid thermal annealing, laser annealing, flash annealing and spike annealing, and the temperature range of high temperature annealing is between 700°C and 1800°C.

7. The preparation method according to claim 1, characterized in that: In step 6), the etching method is plasma etching, ion beam sputtering etching, reactive plasma etching, inductively coupled plasma or wet etching.

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