Preparation method of semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention discloses a preparation method of a semiconductor structure, relates to the technical field of semiconductors, and can reduce the manufacturing process complexity and cost of a mask layer and improve the product performance of the semiconductor structure prepared based on the mask layer. The preparation method comprises the following steps: providing a semiconductor substrate; forming a sacrificial structure on one side of the semiconductor substrate; the surface of one side, far away from the semiconductor substrate, of the sacrificial structure is higher than the surface of the semiconductor substrate in the direction perpendicular to and far away from the semiconductor substrate. And forming an initial hard mask layer on the side, away from the semiconductor substrate, of the sacrificial structure. And grinding one side of the initial hard mask layer away from the semiconductor substrate until the surface of one side of the sacrificial structure away from the semiconductor substrate is exposed. And removing the sacrificial structure, and reserving a part of the initial hard mask layer which does not cover the sacrificial structure to form a hard mask layer with an opening. The semiconductor substrate is etched using the hard mask layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the manufacturing process of semiconductor devices, as the size of the conductive signal line structure (e.g., the line width of the signal line) becomes smaller and smaller, the aspect ratio of the interconnection structure coupled with the conductive signal line increases, and the etching requirements of the interconnection structure need to be improved to form an interconnection structure with good electrical properties. Among them, the process and process conditions of forming the mask layer of the interconnection structure are one of the important factors affecting the electrical properties of the coupling between the interconnection structure and the conductive signal line. Summary of the invention

[0003] In view of this, a method for preparing a semiconductor structure provided in an embodiment of the present application can reduce the complexity and cost of the manufacturing process of the mask layer and improve the product performance of the semiconductor structure prepared based on the mask layer.

[0004] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0005] On the one hand, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising: providing a semiconductor substrate. Forming a sacrificial structure on one side of the semiconductor substrate; in a direction perpendicular to and away from the semiconductor substrate, the surface of the sacrificial structure away from the semiconductor substrate is higher than the surface of the semiconductor substrate. Forming an initial hard mask layer on the side of the sacrificial structure away from the semiconductor substrate. Grinding the side of the initial hard mask layer away from the semiconductor substrate until the surface of the side of the sacrificial structure away from the semiconductor substrate is exposed. Removing the sacrificial structure, retaining the portion of the initial hard mask layer that does not cover the sacrificial structure, to form a hard mask layer with an opening. Etching the semiconductor substrate using the hard mask layer.

[0006] In some examples, forming a sacrificial structure on one side of the semiconductor substrate includes: forming a sacrificial layer on one side of the semiconductor substrate, patterning the sacrificial layer to form a sacrificial structure; the sacrificial structure includes a plurality of sacrificial patterns arranged at intervals, and one sacrificial pattern corresponds to one opening.

[0007] In some examples, grinding the side of the initial hard mask layer away from the semiconductor substrate includes: performing chemical mechanical grinding on the side of the initial hard mask layer away from the semiconductor substrate to expose the surface of the sacrificial structure away from the semiconductor substrate.

[0008] In some examples, removing the sacrificial structure and retaining a portion of the initial hard mask layer that does not cover the sacrificial structure includes: removing the sacrificial structure by wet etching or dry etching.

[0009] In some examples, the forming of the sacrificial structure on one side of the semiconductor substrate includes: forming a barrier layer on a side of the sacrificial layer away from the semiconductor substrate. Forming an anti-reflection layer on a side of the barrier layer away from the sacrificial layer. Forming a photoresist layer on a side of the anti-reflection layer away from the barrier layer to form a mask pattern. Etching the sacrificial layer, the barrier layer, and the anti-reflection layer based on the mask pattern, and removing the mask pattern and the etched portions of the sacrificial layer, the barrier layer, and the anti-reflection layer to form the sacrificial structure.

[0010] In some examples, providing a semiconductor substrate includes: providing a conductive stack and a dielectric stack located on one side of the conductive stack; wherein the conductive stack includes at least one conductive layer and an insulating layer arranged alternately; the dielectric stack includes a first dielectric layer located on one side of the conductive stack, a second dielectric layer located on a side of the first dielectric layer away from the conductive stack, and a third dielectric layer located on a side of the second dielectric layer away from the first dielectric layer. The sacrificial structure is arranged on a side of the third dielectric layer away from the second dielectric layer.

[0011] The etching of the semiconductor substrate by using the hard mask layer comprises: etching the dielectric stack based on the opening of the hard mask layer until the conductive layer in the conductive stack is exposed.

[0012] In some examples, the material used for the hard mask layer includes titanium nitride; and / or the material used for the sacrificial structure includes silicon nitride.

[0013] In some examples, etching the semiconductor substrate using the hard mask layer includes: etching the dielectric stack based on the opening of the hard mask layer to form a groove; the ratio of the opening size of the groove to the size of the groove along the stacking direction of the dielectric stack is less than or equal to 5 / 7.

[0014] In some examples, the preparation method further includes: filling the groove with a conductive material to form an interconnect structure; the interconnect structure is coupled to a conductive layer in the conductive stack. After forming the interconnect structure, grinding and removing the hard mask layer.

[0015] In the method for preparing a semiconductor structure provided in an embodiment of the present application, an initial hard mask layer is formed on a sacrificial structure, and a portion of the surface of the initial hard mask layer on a side away from the semiconductor substrate corresponding to the sacrificial structure is also raised by a raised structure characterized by the sacrificial structure compared to the surface of the semiconductor substrate (that is, a recessed pattern corresponding to the sacrificial structure is formed on the initial hard mask layer in the opposite direction relative to the surface of the semiconductor substrate). Then, the raised portion of the initial hard mask layer is removed by grinding to expose the sacrificial structure, and the portion of the initial hard mask layer remaining on the semiconductor substrate is used for subsequent etching of the semiconductor substrate. Among them, the opening of the hard mask layer formed by removing the sacrificial structure is obtained based on the manufacturing order of the sacrificial structure and the initial hard mask layer and the pattern of the sacrificial structure. There is no need to perform dry etching (or wet etching) on ​​the initial hard mask layer and the configuration and operation control of related etching parameters, which not only reduces the process complexity of preparing the hard mask layer, but also, for the by-products generated after the etching process treats the hard mask material, it can avoid the problem of residual impurities caused by the process temperature for removing the by-products failing to reach the vaporization temperature, thereby reducing the adverse effects of impurities on the structure of the hard mask layer and the adverse effects on the stability and reliability of other structures in the subsequent semiconductor structure.

[0016] Moreover, in the process of removing impurities generated after the hard mask material is treated by dry etching (such as plasma gas) in the related art, the impurities are removed by gasification. Considering the high gasification temperature, it is easy for impurities to remain in the machine chamber, remain on the surface of the hard mask layer, or adhere to the inner wall of the machine chamber, and fall on the semiconductor structure in the subsequent process, affecting the product performance of the semiconductor structure. In addition, for impurities attached to the inner wall of the machine chamber, if there are many impurities, or the number of times the impurities are cleaned increases, the service life of the machine will be shortened. The preparation process steps of the improved hard mask layer adopted in this application are also conducive to extending the service life of the machine.

[0017] On the other hand, the present application further provides a semiconductor structure. The semiconductor structure is prepared by the method for preparing a semiconductor structure provided in any of the above examples.

[0018] The technical effect achieved by the semiconductor structure is the same as the technical effect of the method for preparing the semiconductor structure provided in any of the above examples, and will not be described in detail here. In addition, the semiconductor structure prepared by the method for preparing the semiconductor structure provided in any of the above examples has a simple process for the opening of the hard mask layer obtained by improving the preparation process of the hard mask layer, and has less or almost no impurities, which improves the etching accuracy of the hard mask layer, is conducive to improving the dimensional accuracy of the interconnection structure in the semiconductor structure prepared based on the hard mask layer, and improves the conductive reliability of the interconnection structure and the product performance of the semiconductor structure.

[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A cross-sectional view of a semiconductor structure provided in one embodiment of the present application Figure 1 ;

[0021] Figure 2 A schematic diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present application Figure 1 ;

[0022] Figure 3 (a)~ Figure 3 (i) is a schematic structural cross-sectional diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present application Figure 2 ;

[0024] Figure 5 A cross-sectional view of a semiconductor structure provided in one embodiment of the present application Figure 2 ;

[0025] Figure 6 A cross-sectional view of a semiconductor structure provided in one embodiment of the present application Figure 3 ;

[0026] Figure 7 A schematic diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present application Figure 3 . DETAILED DESCRIPTION

[0027] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0028] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0029] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0031] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0034] In the manufacturing process of semiconductor devices, as the size of the conductive signal line structure (e.g., the line width of the signal line) becomes smaller and smaller, the aspect ratio of the interconnection structure coupled with the conductive signal line increases, and the etching requirements of the interconnection structure need to be improved to form an interconnection structure with good electrical properties. Among them, the process and process conditions of forming the mask layer of the interconnection structure are one of the important factors affecting the electrical properties of the coupling between the interconnection structure and the conductive signal line.

[0035] For example, as the width of the signal line decreases and the etching depth-to-width ratio in the process of etching the signal line increases, the electrical properties of the signal line are increasingly affected. For example, in the process of using photoresist as a mask layer and using a photolithography process to make a signal line, due to the large thickness of the photoresist, the side walls of the openings in the photoresist layer block the light, reducing the amount of light entering. Especially when a large etching depth is required, it is easy to cause the depth of the material that undergoes exposure denaturation and the size of the opening of the corresponding photoresist layer to have a large error compared to actual needs, which in turn causes errors in the depth of the etched groove and the size of the opening, reducing the conductive properties of the interconnection structure and the signal line subsequently formed in the groove. In this way, the mask layer of the photoresist material is not conducive to the production of a groove structure with a high depth-to-width ratio.

[0036] As another example, in the case where deeper grooves need to be etched, a hard mask template can be used to implement a photolithography process. Based on the high hardness, high selectivity and good thermal stability of the hard mask material (for example, titanium nitride compound TiN), it is beneficial to improve the etching accuracy under the condition of satisfying the etching depth-to-width ratio. In the related art, in the actual process using a hard mask template as a mask layer, it is first necessary to use a photolithography process to form a protective pattern, and then use an etching process (for example, dry etching) based on the protective pattern to form a hard mask layer with an opening. Among them, etching the hard mask material layer will produce some by-products, which need to be cleaned before the subsequent process of the semiconductor structure is carried out. However, since the by-products produced by the reaction between the hard mask material and the etching gas have a high vaporization temperature, they are easily left on the surface of the hard mask material layer and in the chamber of the machine for etching the hard mask.

[0037] Thus, the impurities remaining on the surface of the hard mask will affect the size of the opening of the hard mask, affect the etching accuracy of the grooves with a depth-to-width ratio formed based on the hard mask, and affect the conductivity of the interconnection structure and signal lines formed in the grooves. In addition, the impurities remaining in the chamber of the machine for etching the hard mask will fall onto the semiconductor structure during the subsequent etching of the semiconductor structure, affecting the product performance of the semiconductor structure and the service life of the machine.

[0038] Among them, since the hard mask process needs to first form an opening structure with an etching pattern, it is necessary to configure and control various parameters of the etching hard mask. The process of this hard mask is complicated, which increases the complexity and process cost of the preparation method of the entire semiconductor structure and reduces the manufacturing efficiency of the semiconductor structure.

[0039] It is understandable that due to the high hardness, high selectivity and good thermal stability of the material properties of the hard mask (e.g., titanium nitride compound TiN), if wet etching is used, it is necessary to prepare specific chemical solutions and specific reaction conditions, which is costly. Moreover, wet etching is usually isotropic, which means that etching will proceed uniformly in all directions, which may cause critical dimension (CD) loss, which is unfavorable for the high-precision and high aspect ratio features pursued in semiconductor manufacturing. Therefore, in the technical field, photolithography and dry etching are usually used to make the opening pattern of the hard mask.

[0040] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure, which can reduce the complexity and cost of the manufacturing process of the mask layer and improve the product performance of the semiconductor structure prepared based on the mask layer.

[0041] In some embodiments, Figure 1 As shown, an embodiment of the present application provides a semiconductor structure 1000 .

[0042] For example, the semiconductor structure 1000 can be a chip, a die, or a wafer. It should be noted that the chip and the die can refer to the same structure (the names can be interchanged), or the die can be a chip that is not packaged. Different levels of chip structures are set according to requirements. For example, the chip, die, and wafer are three different levels of chip structures. The embodiments provided in this application are not limited to this, and semiconductor structures with grooves with a depth-to-width ratio can be implemented using the technology provided in this application. Subsequent examples all use "semiconductor structure" for illustrative purposes.

[0043] In some embodiments, Figure 1 As shown, the semiconductor structure 1000 includes a semiconductor substrate 100 and a plurality of interconnect structures 101 .

[0044] The semiconductor substrate 100 may be a semiconductor structure 100 that has not been subjected to deep hole etching technology and has not formed the interconnection structure 101 provided in the present application. Based on the above examples of the semiconductor structure 100, the present application does not specifically limit the material and layer structure of the semiconductor substrate 100.

[0045] The interconnection structure 101 is disposed in the semiconductor substrate 100. One side surface of the interconnection structure 101 along the thickness direction of the semiconductor substrate 100 may be exposed for realizing electrical connection with other different semiconductor substrates 100; the other side may be substantially flush with the surface of the semiconductor substrate 100 or extend deep into the semiconductor substrate 100 for electrical connection with the conductive layer in the semiconductor substrate 100. For example, the interconnection structure 101 may be made of at least one of copper Cu, aluminum Al, tin Sn and nickel Ni. For example, copper Cu is used.

[0046] It should be noted that the examples provided in this application do not impose any specific restrictions on the specific layer structure and internal conductive signal lines of the semiconductor structure 1000, which can be set according to actual needs. The following examples illustrate the preparation process of the semiconductor structure by manufacturing the structure of the hard mask layer and the structure related to the hard mask layer.

[0047] In the process of manufacturing the semiconductor structure 1000, in order to reduce the complexity and cost of the manufacturing process of the mask layer and improve the product performance of the semiconductor structure manufactured based on the mask layer, such as Figure 2 to Figure 7 As shown, the embodiment of the present application provides a method S100 to S800 for preparing a semiconductor structure 1000 .

[0048] S100: Figure 2 and Figure 3 As shown in (a) of FIG. 1 , a semiconductor substrate 100 is provided. For example, the semiconductor substrate 100 may be a composite layer of multiple layers of materials stacked. Figure 1 As shown, the semiconductor substrate 100 may include a conductive stack 110 formed with a conductive signal line and a dielectric stack 120, and the dielectric stack 120 provides a support for the subsequent production of the interconnect structure 101 and a production space for realizing the electrical connection with the signal line. The specific structure of the semiconductor substrate 100 can be set according to actual needs and is not limited here.

[0049] S200: Figure 2 and Figure 3 (b)~ Figure 3 As shown in (d) in FIG. 1 , a sacrificial structure 200 is formed on one side of the semiconductor substrate 100. In a direction vertically away from the semiconductor substrate 100, a surface of the sacrificial structure 200 away from the semiconductor substrate 100 is higher than a surface of the semiconductor substrate 100.

[0050] For example, Figure 3 As shown in (d) , the sacrificial structure 200 is a protruding structure compared to the surface of the semiconductor substrate 100 .

[0051] S300: Figure 2 As shown, an initial hard mask layer 300 is formed on a side of the sacrificial structure 200 away from the semiconductor substrate 100 .

[0052] For example, a deposition process may be used to form a hard mask material on the side of the sacrificial structure 200 away from the semiconductor substrate 100. For example, the hard mask material includes a titanium nitride compound. A physical vapor deposition process is used to deposit the titanium nitride compound material to form an initial hard mask layer 300 that covers the surface of the side of the sacrificial structure 200 away from the semiconductor substrate 100 and extends to the surface of the semiconductor substrate 100.

[0053] S400: Figure 2 As shown, the side of the initial hard mask layer 300 away from the semiconductor substrate 100 is ground until the surface of the sacrificial structure 200 away from the semiconductor substrate 100 is exposed.

[0054] For example, the distance between the surface of the initial hard mask layer 300 away from the semiconductor substrate 100 and the semiconductor substrate 100 is greater than the distance between the surface of the sacrificial structure 200 away from the semiconductor substrate 100 and the semiconductor substrate 100. A physical grinding process may be used to remove part of the material of the initial hard mask layer 300 away from the semiconductor substrate 100 until the distance between the surface of the initial hard mask layer 300 away from the semiconductor substrate 100 and the semiconductor substrate 100 is equal to the distance between the surface of the sacrificial structure 200 away from the semiconductor substrate 100 and the semiconductor substrate 100.

[0055] S500: Figure 2 and Figure 3 As shown in (g) , the sacrificial structure 200 is removed, and a portion of the initial hard mask layer 300 not covering the sacrificial structure 200 is retained, thereby forming a hard mask layer 310 having an opening 311 .

[0056] For example, after the sacrificial structure 200 is removed from the position where the initial mask layer 300 exposes the sacrificial structure 200, a through hole at the corresponding position is left, and the through hole exposes the layer structure below the sacrificial structure 200. In this way, the through hole is characterized as an opening 311 on the hard mask layer 310 for subsequent etching through the opening 311.

[0057] S600: Figure 2As shown, the semiconductor substrate 100 is etched using the hard mask layer 310. For example, the semiconductor substrate 100 is etched through the opening 311 using the hard mask layer 310 as a protective layer, so as to facilitate the subsequent formation of the interconnect structure 101 located in the semiconductor substrate 100 (see Figure 1 ), coupled with the conductive line.

[0058] The above method forms an initial hard mask layer 300 on the sacrificial structure 200, and through the convex structure of the sacrificial structure 200 compared to the surface of the semiconductor substrate 100, the portion of the surface of the initial hard mask layer 300 away from the semiconductor substrate 100 corresponding to the sacrificial structure 200 is also convex (that is, relative to the surface of the semiconductor substrate 100, a concave pattern corresponding to the sacrificial structure 200 is formed on the initial hard mask layer 300 in the opposite direction). Then, the convex portion of the initial hard mask layer 300 is removed by grinding to expose the sacrificial structure 200, and the portion of the initial hard mask layer 300 retained on the semiconductor substrate 100 is used for subsequent etching of the semiconductor substrate 100. Among them, the opening 311 of the hard mask layer 310 formed by removing the sacrificial structure 200 is obtained based on the manufacturing sequence of the sacrificial structure 200 and the initial hard mask layer 300 and the pattern of the sacrificial structure 200. It is not necessary to perform dry etching (or wet etching) on ​​the initial hard mask layer 300 and configure and operate the relevant etching parameters, which not only reduces the process complexity of preparing the hard mask layer 310, but also, for the by-products generated after the etching process treats the hard mask material, it can avoid the problem of residual impurities caused by the process temperature for removing the by-products failing to reach the vaporization temperature, thereby reducing the adverse effects of impurities on the structure of the hard mask layer 310 and the adverse effects on the stability and reliability of other structures in the subsequent semiconductor structure 1000.

[0059] Moreover, in the process of removing impurities generated after the hard mask material is treated by dry etching (such as plasma gas) in the related art, the impurities are removed by gasification. Considering the high gasification temperature, it is easy for impurities to remain in the machine chamber, remain on the surface of the hard mask layer, or adhere to the inner wall of the machine chamber, and fall on the semiconductor structure in the subsequent process, affecting the product performance of the semiconductor structure. In addition, for impurities attached to the inner wall of the machine chamber, if there are many impurities, or the number of times the impurities are cleaned increases, the service life of the machine will be shortened. The preparation process steps of the improved hard mask layer 310 adopted in this application are also conducive to extending the service life of the machine.

[0060] In addition, the process of the opening of the hard mask layer obtained based on the improved preparation process steps of the hard mask layer 310 is simple, and has fewer or almost no impurities, which improves the etching accuracy of the hard mask layer 310, is beneficial to improving the dimensional accuracy of the interconnection structure 101 within the semiconductor structure 1000 prepared based on the hard mask layer 310, and improves the conductive reliability of the interconnection structure 101 and the product performance of the semiconductor structure 1000.

[0061] In some examples, such as Figure 4 As shown, step S100: providing a semiconductor substrate includes S110.

[0062] S110: Figure 4 and Figure 5 As shown, a conductive stack 110 and a dielectric stack 120 located on one side of the conductive stack 110 are provided. The conductive stack 110 includes at least one conductive layer and an insulating layer (not shown in the figures of the present application, and can be arranged according to actual needs) arranged alternately. For example, the material used for the conductive layer includes one or more conductive single substances or compounds such as gold, silver, copper, aluminum, and tin. The material used for the insulating layer includes one or more inorganic materials such as glass, quartz, silicon carbide, and silicon oxide, and can also be an organic material such as epoxy resin or polyurethane.

[0063] like Figure 5 As shown, the dielectric stack 120 includes a first dielectric layer 121 located on one side of the conductive stack 110 , a second dielectric layer 122 located on a side of the first dielectric layer 121 away from the conductive stack 110 , and a third dielectric layer 123 located on a side of the second dielectric layer 122 away from the first dielectric layer 121 .

[0064] For example, the first dielectric layer 121 can be used as a barrier layer to prevent conductive particles in the conductive stack 110 from diffusing into the dielectric stack 120, thereby improving the reliability of the subsequent interconnect structure 101 formed in the dielectric stack 120. For example, the material used for the first dielectric layer 121 can include doped carbon nitride silicon.

[0065] The material used for the second dielectric layer 122 may include an insulating material with a low dielectric constant, which can reduce the signal delay and power consumption of the conductive circuit in the semiconductor structure. For example, the insulating material with a dielectric constant less than 2.5 can be formed on one side of the first dielectric layer 121 by chemical vapor deposition (CVD) or spin-on process.

[0066] The material of the third dielectric layer 123 may include one or more insulating materials such as silicon oxynitride SiON, silicon oxide SiO2, silicon nitride SiN or silicon carbide SiC. The third dielectric layer 123 may be formed on one side of the second dielectric layer 122 by chemical vapor deposition (CVD) or spin-on process.

[0067] Based on the structure of the semiconductor substrate 100, continue to refer to Figure 5 The sacrificial structure 200 is disposed on a side of the third dielectric layer 123 away from the second dielectric layer 122 .

[0068] It is understandable that if Figure 6 As shown, the third dielectric layer 123 is located between the low dielectric constant material layer (the second dielectric layer 122) and the hard mask layer 310, which can protect the second dielectric layer 122, reduce the probability of water and oxygen entering the second dielectric layer 122 through the opening 311 of the hard mask layer 310 after the hard mask layer 310 is formed (after the sacrificial structure 200 is removed), and improve the stability of the dielectric constant of the second dielectric layer 122.

[0069] In some examples, such as Figure 5 As shown, along the direction X perpendicular to the semiconductor substrate 100 , the size H1 of the sacrificial structure 200 may be less than or equal to 1 / 10 of the size H2 of the dielectric stack 120 .

[0070] For example, by setting the dimension H1 (i.e., thickness) of the sacrificial structure 200 along the direction X perpendicular to the semiconductor substrate 100, the thickness of the hard mask layer 310 formed based on the sacrificial structure 200 can be adjusted, for example, the thickness of the hard mask layer 310 is the same as the thickness of the sacrificial structure 200. In this way, by setting the sidewall height of the opening 311 of the hard mask layer 310 (i.e., the thickness of the sacrificial structure 200), the probability of blocking light due to the high height of the sidewall of the opening 311 is reduced, and the accuracy of the exposure effect of the layer structure below the sacrificial structure 200 is improved during the photolithography process using the hard mask layer 310.

[0071] For example, along the direction X perpendicular to the semiconductor substrate 100, the dimension H1 of the sacrificial structure 200 is equal to 1 / 10 of the dimension H2 of the dielectric stack 120. For example, the thickness H1 of the sacrificial structure 200 is 250 angstroms, and the thickness H2 of the dielectric stack 120 is 2500 angstroms.

[0072] For another example, along the direction X perpendicular to the semiconductor substrate 100, the dimension H1 of the sacrificial structure 200 is smaller than 1 / 10 of the dimension H2 of the dielectric stack 120. For example, the thickness H1 of the sacrificial structure 200 is 200 angstroms, and the thickness H2 of the dielectric stack 120 is 2750 angstroms.

[0073] It should be noted that the size of the thickness H1 of the above-mentioned sacrificial structure 200 and the size of the thickness H2 of the dielectric stack 120 are only used as examples to reflect the application scenario of the hard mask layer 310, and do not specifically limit the thickness of each dielectric layer in the semiconductor structure 1000, nor do they limit the thickness of the sacrificial structure 200, and the relative relationship between the thicknesses of the two, which can be set according to actual needs.

[0074] It is understandable that, considering the subsequent method of grinding the initialization hard mask layer 300 to expose the sacrificial structure 200, the grinding process will also have a certain impact on the thickness of the sacrificial structure 200. The thickness of the sacrificial structure 200 can be appropriately increased according to the actual thickness of the dielectric stack 120. Through the process of grinding the initialization hard mask layer 300, the thickness H1 of the retained sacrificial structure 200 (and the thickness of the initialization mask layer 300 after grinding) is less than or equal to 1 / 10 of the size H2 of the dielectric stack 120.

[0075] In some examples, such as Figure 4 As shown, step S200 : forming a sacrificial structure 200 on one side of the semiconductor substrate 100 includes S210 and S220 .

[0076] S210 : forming a sacrificial layer 210 on one side of the semiconductor substrate 100 .

[0077] For example, the sacrificial layer 210 may be formed by depositing a dielectric material.

[0078] For example, the dielectric material used for the sacrificial layer 210 includes silicon nitride. It is understood that the hardness of the silicon nitride material is relatively high, which is conducive to maintaining the surface flatness and reducing adverse damage during the subsequent grinding (e.g., chemical mechanical grinding) of the initial hard mask layer 300. The sacrificial layer 210 made of silicon nitride plays a key role in the chemical mechanical grinding process and provides a reliable reference for making a hard mask layer 310 that meets the required thickness.

[0079] S220: Figure 3 (b)~ Figure 3 As shown in (d) of FIG. 3 , the sacrificial layer 210 is patterned to form a sacrificial structure 200 . The sacrificial structure 200 includes a plurality of sacrificial patterns 201 arranged at intervals, and each sacrificial pattern 201 corresponds to one opening 311 .

[0080] For example, the sacrificial structure 200 may be formed by exposing and developing the sacrificial layer 210 .

[0081] In some examples, such as Figure 7 As shown, step S200: forming a sacrificial structure 200 on one side of the semiconductor substrate 100 includes S221-S224.

[0082] S221: Figure 3 As shown in (b) , a barrier layer 10 is formed on a side of the sacrificial layer 210 away from the semiconductor substrate 100 .

[0083] For example, the barrier layer 10 can be used to prevent impurities such as boron, phosphorus, arsenic, etc. from diffusing into the dielectric stack 120 at high temperatures, protect the stability of the material properties of the dielectric stack 120, and provide a stable environment for the subsequent interconnect structure 101 (see Figure 1 ) provides an electrical reliability environment. For example, the material used for the barrier layer 10 includes silicon oxide.

[0084] S222: Figure 3 As shown in (b) , an anti-reflection layer 20 is formed on a side of the barrier layer 10 away from the sacrificial layer 210 .

[0085] For example, the anti-reflection layer 20 is used to reduce light reflection, improve transmittance, and help improve the dimensional accuracy of the sacrificial structure 200. For example, the material used for the anti-reflection layer 20 may include one or more dielectric materials such as silicon dioxide SiO2, titanium oxide TiO2, and indium tin oxide ITO.

[0086] S223: Figure 3 As shown in (b) of FIG. 1 , a photoresist layer 30 is formed on a side of the anti-reflection layer 20 away from the barrier layer 10 to form a mask pattern 31 .

[0087] For example, the photoresist layer 30 may be formed by a spin coating process, and then the photoresist material may be denatured by a photolithography process, and then developed to form a mask pattern 31 .

[0088] S224: Figure 3 (c) and Figure 3 As shown in (d), after the sacrificial layer 210, the barrier layer 10 and the anti-reflection layer 20 are etched based on the mask pattern 31, the mask pattern 31, the etched barrier layer 10 and the anti-reflection layer 20, and part of the sacrificial layer 210 are removed to form a sacrificial structure 200.

[0089] For example, after etching the sacrificial layer 210, the barrier layer 10 and the anti-reflection layer 20, only the etched portion of the sacrificial layer 210 (i.e., the sacrificial structure 201) is retained. The mask pattern 31 is used to form the sacrificial pattern 201 of the sacrificial structure 200, and one mask pattern 31 corresponds to one sacrificial pattern 201, i.e., along the direction parallel to the semiconductor substrate 100, the size of the mask pattern 31 is equal to the size of the sacrificial pattern 201.

[0090] In the above process of forming the sacrificial structure 200, wet etching can be used to remove the mask pattern 31, the barrier layer 10 and the anti-reflection layer 20, and the etched portion of the sacrificial layer 210. Considering that the dielectric stack 120 is subsequently etched based on the opening 311 of the hard mask layer 310 to form the groove 1201 (see Figure 6) process can also use wet etching. In this way, the method for forming the semiconductor structure 1000 can use the same machine to perform parameter configuration and operation of wet etching. The steps are simple and there is no need to prepare additional machines with other process conditions (such as dry etching machines), so the process cost is low.

[0091] In some examples, such as Figure 4 As shown, step S400: grinding the side of the initial hard mask layer 300 away from the semiconductor substrate 100, including S410.

[0092] S410: Figure 3 (e) and Figure 3 As shown in (f) in FIG. 1 , chemical mechanical polishing is performed on the side of the initial hard mask layer 300 away from the semiconductor substrate 100 to expose the surface of the sacrificial structure 200 away from the semiconductor substrate 100 .

[0093] Chemical Mechanical Polishing (CMP) combines chemical etching and mechanical polishing to achieve global planarization of the surface of the initial hard mask layer 300 .

[0094] In addition, the initial hard mask layer 300 may also be processed by mechanical grinding, diamond tool grinding, back grinding, etc.

[0095] It is understandable that the impurities generated by chemical mechanical polishing of the material of the initial hard mask layer 300 are removed by liquid flushing, which is convenient to operate and has a good impurity removal effect. In addition, there is no need to configure the operating parameters of the process for etching the initial hard mask layer 300, and in the preparation process of the semiconductor structure 1000, the process of making the hard mask layer 310 is omitted, reducing the difficulty and complexity of the operation.

[0096] In some examples, such as Figure 4 As shown, step S500 : removing the sacrificial structure 200 , and retaining a portion of the initial hard mask layer 300 that does not cover the sacrificial structure 200 includes S510 .

[0097] S510: Figure 3 As shown in (g) in FIG. 1 , the sacrificial structure 200 is removed by wet etching or dry etching.

[0098] For example, the residual material after grinding the initial hard mask layer 300 has been removed in the process step of grinding the initial hard mask layer 300. For example, ultrapure water is used to rinse the grinded initial hard mask layer 300. Then, wet etching is performed to remove the sacrificial structure 200. The etching solution can also further rinse the residual material after grinding the initial hard mask layer 300.

[0099] As another example, the sacrificial structure 200 may be removed by dry etching and then rinsed with ultrapure water, which is beneficial for removing residual substances after etching the sacrificial structure 200.

[0100] The hard mask layer 310 prepared in the above steps S200 to S500 is obtained based on the manufacturing sequence of the sacrificial structure 200 and the initial hard mask layer 300 and the pattern of the sacrificial structure 200. It is not necessary to perform dry etching (or wet etching) on ​​the initial hard mask layer 300 and configure and operate the relevant etching parameters, which not only reduces the process complexity of preparing the hard mask layer 310, but also, for the by-products generated after the etching process treats the hard mask material, it is possible to avoid the problem of residual impurities caused by the process temperature for removing the by-products failing to reach the vaporization temperature, thereby reducing the adverse effects of impurities on the structure of the hard mask layer 310 and the adverse effects on the stability and reliability of other structures in the subsequent semiconductor structure 1000.

[0101] Moreover, in the process of removing impurities generated after the hard mask material is treated by dry etching (such as plasma gas) in the related art, the impurities are removed by gasification. Considering the high gasification temperature, it is easy for impurities to remain in the machine chamber, remain on the surface of the hard mask layer, or adhere to the inner wall of the machine chamber, and fall on the semiconductor structure in the subsequent process, affecting the product performance of the semiconductor structure. In addition, for impurities attached to the inner wall of the machine chamber, if there are many impurities, or the number of times the impurities are cleaned increases, the service life of the machine will be shortened. The preparation process steps of the improved hard mask layer 310 adopted in this application are also conducive to extending the service life of the machine.

[0102] In some examples, such as Figure 4 As shown, step S600: etching the semiconductor substrate 100 using the hard mask layer 310 includes S610.

[0103] S610: Figure 6 As shown, based on the opening 311 of the hard mask layer 310, the dielectric stack 120 is etched to expose the conductive layer ( Figure 6 not shown).

[0104] For example, considering that in the related art, the line width of the signal line is reduced, the depth-to-width ratio of the groove 1201 where the interconnection structure coupled to the signal line is located is increased, that is, the size of the opening 311 forming the groove 1201 is smaller. A plasma etching method of dry etching can be used to form a groove 1201 with a larger depth-to-width ratio through the opening 311, which is conducive to improving the electrical connection reliability between the subsequently formed interconnection structure 101 and the signal line. The depths of the multiple grooves 1201 can be the same or different. For example, the depths of the multiple grooves 1201 can be different, exposing the conductive layers of different layers in the conductive stack 110, so as to realize the interconnection structure 101 (see FIG. 1 ) formed in the groove 1201. Figure 3 (g)) in the figure is coupled with conductive layers of different layers.

[0105] For example, Figure 7 As shown, step S600: etching the semiconductor substrate 100 using the hard mask layer 310 includes S611.

[0106] S611: Based on the opening 311 of the hard mask layer 310, the dielectric stack 120 is etched to form a groove 1201 (see Figure 6 ). The ratio of the opening size of the groove 1201 to the size of the groove 1201 along the stacking direction Y of the dielectric stack 120 is less than or equal to 5 / 7.

[0107] In some examples, the opening of the groove 1201 may have different sizes along the stacking direction perpendicular to the dielectric stack 120. For example, the opening shape of the groove 1201 may include one or more polygons such as a circle, a square, a rectangle, or an arc. The ratio of the minimum size of the opening of the groove 1201 to the size along the stacking direction Y of the dielectric stack 120 is less than or equal to 5 / 7, which can indicate that the groove 1201 has a characteristic of a depth-to-width ratio.

[0108] In this way, the ratio of the dimension of the interconnect structure 101 formed in the groove 1201 along the stacking direction perpendicular to the dielectric stack 120 to the dimension of the groove 1201 along the stacking direction of the dielectric stack 120 is less than or equal to 5 / 7. The dimension of the interconnect structure 101 along the stacking direction perpendicular to the dielectric stack 120 can be characterized as the line width of the conductive signal line.

[0109] For example, the ratio of the opening size of the groove 1201 to the size of the groove 1201 along the stacking direction of the dielectric stack 120 may be 5 / 7, 2 / 7, 3 / 10 or 1 / 10, etc. The ratios of the opening sizes of different grooves 1201 to the size of the groove 1201 along the stacking direction of the dielectric stack 120 may be the same or different, and may be selected and set according to actual manufacturing requirements.

[0110] For example, the ratio of the opening size of the groove 1201 to the size of the groove 1201 along the stacking direction of the dielectric stack 120 may be 2 / 7.

[0111] Combined with the relationship between the size of the dielectric stack 120 and the size of the sacrificial structure 200 (i.e., the mask layer hard mask layer 310) along the stacking direction parallel to the dielectric stack 120 provided in the above example, it can be reflected that based on the thickness and material properties of the hard mask layer 310, a groove 1201 with an aspect ratio is made to form an interconnection structure 101 with a smaller line width, reflecting the key role of the hard mask layer 310 in the reliability of the semiconductor structure 1000, and also reflecting the importance of the specific operation method of the process of the hard mask layer 310 to the preparation of the semiconductor structure 1000.

[0112] The process of the opening of the hard mask layer obtained by improving the preparation process steps of the hard mask layer 310 is simple, and has less or almost no impurities, which improves the etching accuracy of the hard mask layer 310, is beneficial to improving the dimensional accuracy of the interconnection structure 101 in the semiconductor structure 1000 prepared based on the hard mask layer 310, and improves the conductive reliability of the interconnection structure 101 and the product performance of the semiconductor structure 1000.

[0113] It should be noted that the preparation process of the hard mask layer 310 provided in the example of the present application can also be applied to other application scenarios besides preparing the groove 1201 with a high aspect ratio based on the opening 311 of the hard mask layer 310. The preparation process of the hard mask layer 310 can improve the process simplicity of the hard mask layer 310, improve the preparation yield or accuracy of the hard mask layer 310, and reduce the adverse effects on the subsequent processes of other structures or related equipment. The example provided in the present application does not limit the specific application scenario of the preparation process of the hard mask layer 310.

[0114] In some examples, such as Figure 7 , Figure 3 (h) and Figure 3 As shown in (i), the preparation method also includes S700 and S800.

[0115] S700 : Fill the groove 1201 with a conductive material to form an interconnect structure 101 ; the interconnect structure 101 is coupled to a conductive layer (not shown in the drawings provided in this application) in the conductive stack 110 .

[0116] For example, Figure 3 As shown in (h), a deposition process is used to deposit a conductive material in the groove 1201 to obtain an initial interconnect structure 1011 (ie, including the interconnect structure 101 and a portion of the conductive material to be removed by grinding).

[0117] For example, the conductive material may include one or more of single metals or metal compounds such as copper, titanium, aluminum, and silver. For example, the conductive material includes copper.

[0118] It is understandable that the initial interconnection structure 1011 and the interconnection structure 101 are essentially the same structure. The examples provided in this application are described with different numbers and names, which can distinguish the differences in the interconnection structure 101 in different steps, and do not limit the need to deliberately change the specific shape or size of the interconnection structure 101. Instead, the conductive material filled in the deep groove along the direction perpendicular to the semiconductor substrate 100 formed by the groove 1201 and the opening 311 of the hard mask layer 310 constitutes the initial interconnection structure 1011; wherein, the conductive material filled only in the groove 1201 constitutes the interconnection structure 101.

[0119] S800 : After forming the interconnect structure 101 , the hard mask layer 310 is removed by grinding.

[0120] For example, Figure 3 (h) and Figure 3 As shown in (i), chemical mechanical polishing can be used to polish the hard mask layer 310 and the end of the interconnect structure 101 away from the semiconductor substrate 100 until the hard mask layer 310 is removed and the end surface of the interconnect structure 101 away from the semiconductor substrate 100 is planarized. When the hard mask layer 310 is removed, the conductive material in the opening 311 of the hard mask layer 310 is removed.

[0121] In this way, the removal of the hard mask layer 310 does not require the operation of other process machines, which simplifies the operation and improves the conductive reliability of the interconnect structure 101 .

[0122] It should be noted that the embodiments of the semiconductor structure provided in the present application and the embodiments of the method for manufacturing the semiconductor structure belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the semiconductor structure provided in the embodiments of the present application can already solve the technical problem to be solved by the present application; therefore, the method for manufacturing the semiconductor structure provided in the embodiments of the present application may not be limited by the semiconductor structure provided in the embodiments of the present application, and any semiconductor structure prepared by the method for manufacturing the semiconductor structure provided in the embodiments of the present application is within the scope of protection of the present application.

[0123] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate; forming a sacrificial structure on one side of the semiconductor substrate; Along a direction vertically and away from the semiconductor substrate, a surface of a side of the sacrificial structure away from the semiconductor substrate is higher than a surface of the semiconductor substrate; forming an initial hard mask layer on a side of the sacrificial structure away from the semiconductor substrate; Grinding the side of the initial hard mask layer away from the semiconductor substrate until the surface of the sacrificial structure away from the semiconductor substrate is exposed; removing the sacrificial structure and retaining a portion of the initial hard mask layer not covering the sacrificial structure to form a hard mask layer having an opening; The semiconductor substrate is etched using the hard mask layer.

2. The preparation method according to claim 1, characterized in that: The forming of a sacrificial structure on one side of the semiconductor substrate comprises: forming a sacrificial layer on one side of the semiconductor substrate; The sacrificial layer is patterned to form a sacrificial structure; the sacrificial structure includes a plurality of sacrificial patterns arranged at intervals, and one of the sacrificial patterns corresponds to one of the openings.

3. The preparation method according to claim 1, characterized in that: The grinding of the side of the initial hard mask layer away from the semiconductor substrate comprises: Chemical mechanical polishing is performed on a side of the initial hard mask layer away from the semiconductor substrate to expose a surface of the sacrificial structure away from the semiconductor substrate.

4. The preparation method according to claim 1, characterized in that: The removing the sacrificial structure and retaining a portion of the initial hard mask layer not covering the sacrificial structure comprises: The sacrificial structure is removed by wet etching or dry etching.

5. The preparation method according to claim 2, characterized in that: The forming of a sacrificial structure on one side of the semiconductor substrate comprises: forming a blocking layer on a side of the sacrificial layer away from the semiconductor substrate; forming an anti-reflection layer on a side of the barrier layer away from the sacrificial layer; forming a photoresist layer on a side of the anti-reflection layer away from the barrier layer to form a mask pattern; The sacrificial layer, the barrier layer and the anti-reflection layer are etched based on the mask pattern, and the mask pattern and the etched portions of the sacrificial layer, the barrier layer and the anti-reflection layer are removed to form the sacrificial structure.

6. The preparation method according to claim 1, characterized in that: The method provides a semiconductor substrate, comprising: A conductive stack and a dielectric stack located on one side of the conductive stack are provided; wherein the conductive stack includes at least one conductive layer and an insulating layer alternately arranged; the dielectric stack includes a first dielectric layer located on one side of the conductive stack, a second dielectric layer located on a side of the first dielectric layer away from the conductive stack, and a third dielectric layer located on a side of the second dielectric layer away from the first dielectric layer; The sacrificial structure is arranged on a side of the third dielectric layer away from the second dielectric layer; The etching of the semiconductor substrate using the hard mask layer comprises: Based on the opening of the hard mask layer, the dielectric stack is etched to expose the conductive layer in the conductive stack.

7. The preparation method according to claim 1, characterized in that: The material used for the hard mask layer includes titanium nitride; And / or, the material used for the sacrificial structure includes silicon nitride.

8. The preparation method according to claim 7, characterized in that: The etching of the semiconductor substrate using the hard mask layer comprises: Based on the opening of the hard mask layer, the dielectric stack is etched to form a groove; the ratio of the opening size of the groove to the size of the groove along the stacking direction of the dielectric stack is less than or equal to 5 / 7.

9. The preparation method according to claim 8, characterized in that: The preparation method further comprises: Filling the groove with a conductive material to form an interconnect structure; the interconnect structure is coupled to a conductive layer in the conductive stack; After forming the interconnect structure, the hard mask layer is removed by grinding.

10. A semiconductor structure, characterized in that: The invention comprises a structure prepared by the method for preparing a semiconductor structure as claimed in any one of claims 1 to 9.

Images