Silicon through hole structure, manufacturing method of silicon through hole back leakage hole, circuit board and electronic equipment

Abstract

The invention provides a through-silicon-via structure, a manufacturing method of a through-silicon-via back leak hole, a circuit board and electronic equipment. The through silicon via structure comprises a substrate, a metal column and a metal layer, wherein the substrate is provided with a through hole, the through hole is filled with the metal column, and an insulating layer is arranged between the metal column and the inner wall of the through hole. The metal layer is arranged on the surface of one side of the metal column. The diffusion rate of the metal in the metal layer in the substrate is smaller than the diffusion rate of the metal of the metal pillar in the substrate. According to the structure, the residue of metal copper in the substrate in the BVR process can be reduced, and the reliability of the chip is further improved.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a through silicon via structure, a method for manufacturing a through silicon via back leakage hole, a circuit board and an electronic device. Background Art

[0002] In the field of three-dimensional integrated circuit (3DIC) circuits, through silicon via (TSV) structures can usually be used to achieve stacking and connection of multiple chip structures in the height direction. In the process of processing and manufacturing through silicon vias, it is necessary to use wafer thinning technology to thin the bonded stacked thick silicon to a certain thickness to meet the subsequent process requirements. In the wafer thinning process, the TSV structure buried deep in silicon can be directly exposed through silicon grinding and thinning technology and ion etching. This process is called backside via reveal (BVR). The advantage of using BVR technology is that it guarantees the electrical reliability of the chip in subsequent process processing. However, since the metal pillars in the through silicon vias are usually copper pillars, the back etching process of silicon will cause the ion beam to directly bombard the metal copper surface, resulting in serious metal copper contamination of the substrate silicon, and the subsequent auxiliary wet cleaning is difficult to completely remove the copper contamination. Due to the easy diffusion of copper atoms in the silicon base, this poses a hidden danger to the subsequent chip electrical reliability, reduces the chip yield, and increases the chip production cost. Summary of the invention

[0003] The present application provides a through silicon via structure, a method for manufacturing a through silicon via back leakage hole, a circuit board and an electronic device to reduce the residual metal copper in the substrate during the BVR process, thereby improving the reliability of the chip.

[0004] In a first aspect, the present application provides a silicon through via structure. The silicon through via structure comprises: a substrate, a metal column and a metal layer; wherein the substrate is provided with a through hole, and the through hole is arranged along the thickness direction of the substrate. The metal column is filled in the through hole, and an insulating layer is arranged between the metal column and the inner wall of the through hole. The metal layer is arranged on a side surface of the metal column, and is arranged perpendicular to the height direction of the metal column. The diffusion rate of the metal in the metal layer in the substrate is less than the diffusion rate of the metal of the metal column in the substrate.

[0005] In the silicon through via of the present application, since the silicon through via of the substrate is filled with a metal column and a metal layer, and the metal layer covers the surface of the metal column. When the substrate is subjected to the BVR process, the metal of the metal layer will protect the metal column from damage, thereby preventing the metal ions in the metal column from entering the substrate. Among them, since the diffusion rate of the metal in the metal layer in the substrate is lower than the diffusion rate of the metal of the metal column in the substrate, even if some metal ions in the metal layer enter the substrate during the BVR process, due to its slow diffusion rate, even if the metal ions in the metal layer are sputtered into the substrate, the metal substance in the metal layer is not easy to diffuse in the substrate, thereby avoiding the problem of reduced chip reliability due to metal contamination.

[0006] In one possible implementation, the metal in the metal column is copper, and the metal in the metal layer is selected from one of Pb, Sr, Ta, Zr, Ti, Cr, Ru, Mo, W, Ir, Ce, Pt, Co, Ni or Fe, or an alloy containing at least one of the above metals. The metal layer serves as a protective layer for the metal column, and the metal in its components may have a lower migration rate in the substrate than copper. Therefore, the surface of the copper layer of the metal layer is covered with a metal layer, and when the substrate is back-etched, the copper in the metal column can be prevented from sputtering into the substrate to affect the reliability of the chip. In a preferred embodiment of the present application, the metal of the metal layer can be selected from one of Pb, Ti, Ru, Mo or Co, so as to reduce the processing cost while preventing copper from entering the substrate to improve the reliability of the chip.

[0007] In a possible implementation, the thickness of the metal layer is greater than or equal to 200 nm and less than or equal to 20% of the height of the through hole. The metal column is the main material for filling the through hole, and its thickness is relatively thick, which is basically consistent with the hole depth of the through hole. The metal column plays a major role in the electrical connection performance in the structure of the chip. The metal layer is a coating covering the surface of the metal column, and its main function is to protect the metal column during the back etching process of the substrate, so its thickness is relatively thin.

[0008] In a second aspect, the present application provides a method for manufacturing a through silicon via structure, the manufacturing method comprising:

[0009] A substrate having a blind hole is provided; wherein the hole depth direction of the blind hole is the thickness direction of the substrate, the blind hole is filled with a metal column formed of a first metal, and an insulating layer is formed between the hole wall of the blind hole and the metal column;

[0010] removing a portion of the substrate at the bottom of the blind hole until the blind hole forms a through hole to expose the metal column;

[0011] forming a metal layer on the surface of the metal column;

[0012] The substrate is further etched along the depth direction of the through hole to a desired size.

[0013] The method for manufacturing a through silicon via structure of the present application forms a metal layer on the surface of a metal column. In the subsequent etching process of the substrate, the metal layer can be used as a protective layer for the metal column to prevent the metal of the metal column from entering the substrate due to etching and causing contamination to the substrate.

[0014] In an optional implementation, a grinding or cutting process is used to remove a portion of the substrate at the bottom of the blind hole until the blind hole forms a through hole.

[0015] In an optional implementation manner, forming the metal layer on the surface of the metal column includes: forming the metal layer by sputtering, chemical vapor deposition or physical vapor deposition.

[0016] In an optional implementation, the precursors used to form the metal layer by chemical vapor deposition include: pentacarbonyl iron, octacarbonyl dicobalt, tetracarbonyl nickel, hexafluoroacetylacetonate palladium, allyl cyclopentadienyl palladium, bisphenyl chromium, trimethyl (methylcyclopentadienyl) platinum, acetylacetonate ruthenium, acetylacetonate dicarbonyl rhodium, IrH (PF 3 ) 4 、Cr(PF 3 ) 6 、Mo(PF 3 ) 6 or W(PF 3 ) 6 One of them.

[0017] In a third aspect, the present application further provides a method for manufacturing a through silicon via structure, the manufacturing method comprising:

[0018] A substrate having a blind hole is provided; wherein the depth direction of the blind hole is the thickness direction of the substrate, an insulating layer is formed on the inner wall of the blind hole, a metal layer is provided at the bottom of the blind hole, and a metal column is provided on the surface of the metal layer;

[0019] removing a portion of the substrate at the bottom of the blind hole until the blind hole forms a through hole to expose the metal layer;

[0020] The substrate is continuously etched along the hole depth direction of the through hole to a desired size and a portion of the metal column is exposed.

[0021] The method for manufacturing a through silicon via structure of the present application first forms a metal layer and a metal column in the blind hole in sequence, wherein the metal layer is arranged close to the back of the substrate in the direction of the hole depth of the blind hole, and when the back side of the substrate is etched, the metal layer can be used as a protective layer for the metal column to prevent the metal of the metal column from entering the substrate due to etching and causing contamination to the substrate.

[0022] In an optional implementation, a grinding process is used to remove a portion of the substrate at the bottom of the blind hole until the blind hole forms a through hole.

[0023] In an optional implementation, the substrate is bonded to a carrier, the carrier includes a base and conductor wirings disposed on the base, and at least a portion of the metal pillars are connected to the conductor wirings.

[0024] In a fourth aspect, the present application provides a circuit board, which includes at least two chips and a through silicon via structure of the present application or a through silicon via structure formed by the manufacturing method of the present application, wherein the at least two chips are connected via the through silicon via structure.

[0025] In a fifth aspect, the present application provides an electronic device, which includes the circuit board of the present application.

[0026] The electronic device of the present application can reduce the metal in the metal column with a higher migration rate from entering the substrate when the substrate is subjected to the BVR process during the manufacturing process, and replace it with the metal in the metal layer with a lower migration rate. Since the metal in the metal layer has a lower migration rate in the substrate, it is basically limited to the surface layer of the substrate and will not affect the functional area of ​​the substrate, thereby helping to improve the reliability of the chip.

[0027] The electronic device of the present application, since it includes the circuit board of the present application, can achieve the technical effects described with reference to the corresponding effects in the above-mentioned first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of a partial structure of a three-dimensional circuit board;

[0029] Figure 2 is a schematic diagram of a through silicon via structure;

[0030] Figure 3 A schematic diagram of a manufacturing process of a through silicon via structure;

[0031] Figure 4 A schematic diagram of a process for manufacturing a through silicon via back side leakage according to an embodiment;

[0032] Figure 5 A schematic diagram of a method for manufacturing a through silicon via according to an embodiment;

[0033] Figure 6 The present invention is a schematic diagram of a process flow of a method for manufacturing back side leakage of a through silicon via according to an embodiment.

[0034] Reference numerals:

[0035] 11-substrate; 11a-front side; 11b-back side; 111-through hole; 112-blind hole; 12-metal pillar; 13-metal layer; 14-dielectric layer;

[0036] 15-silicon oxide layer; 21-chip. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0038] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used in the specification and appended claims of the present application, the singular expressions "a", "an", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context.

[0039] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0040] A three-dimensional circuit board usually includes a plurality of chips stacked in the height direction, wherein any two chips can be electrically connected via a through silicon via structure. Figure 1 Figure 1 is a schematic diagram of a partial structure of a three-dimensional circuit board. Figure 1 As shown, the circuit board may include a plurality of chips 21, Figure 1 Only one chip 21 is shown in the figure. A through silicon via structure may be provided above the chip 21. Other chips 21 may be stacked and connected above the through silicon via structure. The figure will not be repeated here.

[0041] Figure 2 Figure 1 is a schematic diagram of a through silicon via structure. Figure 2 As shown, the silicon through via structure of the embodiment of the present application includes a substrate 11, which can be a silicon substrate. A plurality of through holes 111 can be provided in the substrate 11. A metal column 12 can be provided in each through hole 111. Figure 1 and Figure 2The metal pillar 12 is used to form a conductive path between two chips 21 stacked in the thickness direction. The metal pillars 12 of different through holes 111 can be electrically connected according to the circuit setting. The metal pillar 12 can be a copper pillar. Since the metal pillar 12 is a conductive medium and the substrate 11 is a semiconductor medium, an insulating layer (not shown in the figure) can be provided between the metal pillar 12 and the substrate 11. The insulating layer can be a silicon oxide layer, which can be formed on the inner wall surface of the through hole 111.

[0042] Reference Figure 2 , a metal layer 13 is deposited on the surface of the metal column 12. The metal layer 13 can serve as a protective layer to protect the metal column 12. The thickness of the metal layer 13 can be greater than or equal to 200nm and less than or equal to 20% of the height of the through hole. Among them, the metal column 12 plays a major conductive role, so the metal column 12 basically fills the entire through hole 111. The conductivity of the metal layer 13 is lower than that of the metal column 12, and it mainly plays a role in protecting the metal column 12. Therefore, the thickness of the metal layer 13 can be thinner.

[0043] In the embodiment of the present application, the diffusion rate of the metal in the metal layer 13 in the substrate 11 is less than the diffusion rate of the metal in the metal column 12 in the substrate 11. In the process of manufacturing the circuit board, after the through silicon via structure is bonded to the chip 21, it is usually necessary to perform back etching on the through silicon via to obtain the required size and design structure. In the traditional silicon back etching process, when the silicon substrate 11 is thinned and etched, the metal column 12 will inevitably be bombarded. The metal substance in the metal column 12, such as copper, will enter the substrate 11. Since the diffusion rate of copper in the silicon substrate 11 is relatively high, as the copper migrates in the silicon substrate 11, it will affect the electrical properties of the substrate 11, thereby reducing the reliability of the chip 21. Therefore, by providing the metal layer 13 on the surface of the metal column 12, the metal in the metal column 12 will no longer be bombarded and enter the substrate 11 during the thinning and etching of the silicon substrate 11 due to the protective effect of the metal layer 13. Part of the metal in the metal layer 13 will enter the substrate 11. Since the diffusion rate of the metal in the metal layer 13 in the substrate 11 is relatively low, most of the metal will stay on the surface of the substrate 11, and less second metal will diffuse into the interior of the substrate 11, which will not affect the electrical properties of the substrate 11. This can help improve the reliability of the chip 21.

[0044] Among them, the second metal in the metal layer 13 can be selected from one of Pb, Sr, Ta, Zr, Ti, Cr, Ru, Mo, W, Ir, Ce, Pt, Co, Ni or Fe, or an alloy containing any of the above metals. The second metal is preferably selected from one of Pb, Sr, Ta, Zr, Ti, Cr, Ru, Mo, W, Ir, Ce, Pt, or an alloy containing any of the above metals. The migration rate of the above metal atoms in the silicon substrate 11 is much lower than that of copper. Therefore, the above substances are used to protect the surface of the copper layer during the silicon etching process, thereby reducing the generation of silicon-based copper residues and ensuring the reliability of the electrical performance of the subsequent chip 21.

[0045] like Figure 2 As shown, the silicon through via structure of the embodiment of the present application can be covered with a dielectric layer 14 on the surface of the metal layer 13 and the surface of the substrate 11, and the dielectric layer 14 is used to protect the substrate 11 and the metal layer 13. The dielectric layer 14 may include a stacked silicon oxide layer or a silicon nitride layer. When other chips 21 are connected on top of the silicon through via structure, at least a portion of the dielectric layer 14 on the surface of the metal layer 13 can be etched away, and then the silicon through via structure and the other chips 21 are bonded. It can be understood that the specific removal position of the dielectric layer 14 can be determined according to the specific design structure of the circuit board, and will not be described in detail here.

[0046] In the process of manufacturing the through silicon via structure and the BVR process, a metal layer 13 can be formed on the surface of the metal pillar 12, and the formed metal layer 13 is used to protect the metal pillar 12. The through silicon via manufacturing process and the BVR process are explained below with reference to the accompanying drawings.

[0047] The present application discloses a method for manufacturing a through silicon via structure. The method comprises: providing a substrate having a blind hole, forming an insulating layer on the hole wall of the blind hole, and filling the blind hole with a first metal to form a metal column; etching a portion of the substrate at the bottom of the blind hole to expose the metal column; forming a metal layer on the surface of the metal column; and after continuing to etch the substrate, depositing a protective layer on the surface of the substrate and the metal layer.

[0048] Figure 3 Figure 1 is a schematic diagram of the manufacturing process of a through silicon via structure. Figure 3 As shown, the method for manufacturing the through silicon via structure in the embodiment of the present application includes:

[0049] S11, providing a substrate 11 having a blind hole 112, the substrate 11 is a silicon substrate 11, and the structure of the substrate 11 is as follows Figure 3As shown in (a). The substrate is divided into a front side 11a and a back side 11b. The front side 11a is used for bonding with the chip 21, and the back side 11b is used for processing and making through holes. An insulating layer (not shown in the figure) is formed on the hole wall of the blind hole 112, and a metal column 12 formed by a first metal is filled in the blind hole 112; the insulating layer is a silicon oxide layer, the first metal is copper, and the metal column formed by the first metal is a copper column.

[0050] S12, such as Figure 3 As shown in (b), a portion of the substrate 11 is removed at the bottom side of the blind hole 112, that is, at the back side 11b of the substrate 11, and the blind hole forms a through hole 111 to expose the metal column 12; wherein, the method of removing a portion of the substrate 11 includes but is not limited to a grinding or cutting process. The grinding process can achieve large-size cutting and improve processing efficiency.

[0051] S13, such as Figure 3 As shown in (c), a metal layer 13 is formed on the surface of the metal pillar 12 on the back side 11b of the substrate.

[0052] S14, such as Figure 3 As shown in (d), the back side 11b of the substrate 11 is further etched to thin the substrate 11; after thinning, part of the metal pillar 12 can be exposed from the surface of the substrate 11. During the process, the substrate 11 can be etched by plasma etching, laser etching, etc. Plasma etching or laser etching can have a high processing accuracy, so that the structure of the through silicon via meets the design requirements.

[0053] S15, such as Figure 3 As shown in (e), a dielectric layer 14 is deposited on the surface of the substrate 11 and the metal layer 13, and the dielectric layer 14 is used to protect the surface of the through silicon via structure to facilitate subsequent processing. The dielectric layer 14 may include a stacked silicon nitride layer and a silicon oxide layer, and the silicon nitride layer and the silicon oxide layer are used to protect the substrate 11, the metal pillar 12, and the metal layer 13.

[0054] S16, such as Figure 3 As shown in (f), when the dielectric layer 14 is relatively thick, a thinning process may be used to thin the dielectric layer 14.

[0055] It is understood that in step S13, the metal layer 13 can be formed on the surface of the metal pillar 12 by chemical vapor deposition or physical vapor deposition. When the metal layer 13 is formed by chemical vapor deposition, the metal precursors used include: pentacarbonyl iron Fe(CO) 5 , Dicobalt octacarbonyl Co 2 (CO) 8 、Tetracarbonyl nickel Ni(CO) 4 、Hexafluoroacetylacetonate palladium Pd(C 5 HF6 O 2 ) 5 , Allylcyclopentadienylpalladium (C 5 H 5 )Pd(C 3 H 5 ), diphenyl chromium (C 6 H 6 )Cr, trimethyl(methylcyclopentadienyl)platinum C 5 H 4 CH 3 ))Pt(CH 3 ) 3 、Ruthenium acetylacetonateRu(O 2 C 5 H 7 ) 3 、Acetylacetonatodicarbonylrhodium Rh(CO) 2 (acac), IrH(PF 3 ) 4 、Cr(PF 3 ) 6 、Mo(PF 3 ) 6 or W(PF 3 ) 6 One of them.

[0056] use Figure 3 The process steps of the illustrated embodiment obtain a through silicon via structure, which can be subsequently bonded with a chip to form a circuit board with different connection structures.

[0057] Figure 4 FIG. 1 is a schematic diagram of a method for making a through silicon via back leakage according to an embodiment of the present invention. Figure 4 As shown, the through silicon via back side leakage process of this embodiment includes the following steps:

[0058] S21, providing a substrate 11 having a blind hole 112 and a substrate 11 bonded to the substrate 11, the substrate comprising a front surface 11a and a back surface 11b. The front surface 11a is bonded to the chip 21. The substrate 11 and the chip 21 can be electrically connected via metal wiring, such as copper wire. A silicon oxide layer 15 can be provided between the substrate 11 and the chip 21, and the silicon oxide layer 15 can seal and protect the metal wiring between the substrate 11 and the chip 21. The substrate 11 is a silicon substrate 11, and the structure of the substrate 11 is as follows Figure 4 As shown in (a). The back side 11b of the substrate 11 is used for processing and manufacturing through holes. An insulating layer (not shown in the figure) is formed on the hole wall of the blind hole 112, and a metal column 12 formed of a first metal is filled in the blind hole 112; the insulating layer is a silicon oxide layer, the first metal is copper, and the metal column formed by the first metal is a copper column.

[0059] S32, such as Figure 4 As shown in (b), a portion of the substrate 11 is removed at the bottom side of the blind hole 112, that is, at the back side 11b of the substrate 11, and the blind hole forms a through hole 111 to expose the metal column 12; wherein, the method of removing a portion of the substrate 11 includes but is not limited to a grinding or cutting process. The grinding process can achieve large-size cutting and improve processing efficiency.

[0060] S33, such as Figure 4 As shown in (c), a metal layer 13 is formed on the surface of the metal pillar 12 on the back side 11b of the substrate.

[0061] S24, such as Figure 4 As shown in (d), the back side 11b of the substrate 11 is further etched to thin the substrate 11; after thinning, part of the metal pillar 12 can be exposed from the surface of the substrate 11. During the process, the substrate 11 can be etched by plasma etching, laser etching, etc. Plasma etching or laser etching can have a high processing accuracy, so that the structure of the through silicon via meets the design requirements.

[0062] S25, such as Figure 4 As shown in (e), a dielectric layer 14 is deposited on the surface of the substrate 11 and the metal layer 13, and the dielectric layer 14 is used to protect the surface of the through silicon via structure to facilitate subsequent processing. The dielectric layer 14 may include a stacked silicon nitride layer and a silicon oxide layer, and the silicon nitride layer and the silicon oxide layer are used to protect the substrate 11, the metal pillar 12, and the metal layer 13.

[0063] S26, such as Figure 4 As shown in (f), when the dielectric layer 14 is relatively thick, a thinning process may be used to thin the dielectric layer 14.

[0064] Among them, using Figure 4 The process steps shown can directly perform BVR production on the combined structure of the bonded substrate and chip.

[0065] Based on the same technical concept, the embodiment of the present application also provides a method for manufacturing a through silicon via structure. The manufacturing method includes: providing a substrate with a blind hole, forming an insulating layer on the inner wall of the blind hole, first depositing a metal layer in the blind hole, and then depositing the metal column on the surface of the metal layer; etching a portion of the silicon substrate at the bottom of the blind hole to expose the metal layer; and depositing a dielectric layer on the surface of the substrate and the metal layer.

[0066] Figure 5 FIG. 1 is a schematic diagram of a method for making a through silicon via according to an embodiment of the present invention. Figure 5 As shown, the method for manufacturing the through silicon via structure in the embodiment of the present application includes:

[0067] S31, providing a substrate 11, the substrate 11 is a silicon substrate 11, and the structure of the substrate 11 is as follows Figure 5 As shown in (a) in FIG. 1 , the substrate 11 includes a front surface 11 a and a back surface 11 b. The front surface 11 a of the substrate 11 is provided with a silicon oxide layer 15 .

[0068] S32, such as Figure 5 As shown in (b) of FIG. 1 , etching is performed from the front surface 11 a of the substrate 11 toward the back surface 11 b of the substrate 11 to form a blind hole 112 in the substrate 11 .

[0069] S33, such as Figure 5 As shown in (c) in the figure, an insulating layer (not shown in the figure) is formed on the hole wall of the blind hole, and a metal layer 13 and a metal column 12 are sequentially deposited in the blind hole. The metal layer 13 is located at the bottom of the blind hole, and the metal column 12 is located on the upper part of the metal layer 13. The insulating layer can be a silicon oxide layer, and the metal column 12 is a copper column. The bottom side of the blind hole is close to the back side 11b of the substrate 11, and the opening side of the blind hole is located on the front side 11a of the substrate 11.

[0070] S34, such as Figure 5 As shown in (d), a portion of the substrate 11 is removed on the back side 11b of the substrate 11 to expose the metal layer 13, and the blind hole of the substrate 11 is etched to form a through hole. The method of removing a portion of the substrate 11 includes but is not limited to grinding or cutting process. The grinding or cutting process can achieve large-size cutting and improve processing efficiency.

[0071] S35, such as Figure 5 As shown in (e) in FIG. 1 , a dielectric layer 14 is deposited on the surface of the substrate 11 and the metal layer 13 . The dielectric layer 14 may include a silicon nitride layer and a silicon oxide layer to protect the substrate 11 , the metal pillar 12 and the metal layer 13 .

[0072] S36, such as Figure 5 As shown in (f) in FIG. 1 , when the dielectric layer 14 is relatively thick, a thinning process may be used to thin the dielectric layer 14 .

[0073] use Figure 5 The process steps of the illustrated embodiment obtain a through silicon via structure, which can be subsequently bonded with a chip to form a circuit board with different connection structures.

[0074] Figure 6 FIG. 1 is a schematic diagram of a method for making a through silicon via back leakage according to an embodiment of the present invention. Figure 6 As shown, the method for manufacturing the back side leakage of the through silicon via in the embodiment of the present application includes:

[0075] S41, providing a substrate 11, the substrate 11 is a silicon substrate 11, and the structure of the substrate 11 is as follows Figure 6As shown in (a) in FIG. 1 , the substrate 11 includes a front surface 11 a and a back surface 11 b. The front surface 11 a of the substrate 11 is provided with a silicon oxide layer 15 .

[0076] S42, such as Figure 6 As shown in (b) of FIG. 1 , etching is performed from the front surface 11 a of the substrate 11 toward the back surface 11 b of the substrate 11 to form a blind hole 112 in the substrate 11 .

[0077] S43, such as Figure 6 As shown in (c) in FIG. 1 , an insulating layer (not shown in the figure) is formed on the hole wall of the blind hole 112, and a metal layer 13 and a metal column 12 are sequentially deposited in the blind hole 112. The metal layer 13 is located at the bottom of the blind hole 112, and the metal column 12 is located on the upper part of the metal layer 13. The insulating layer can be a silicon oxide layer 15, and the metal column 12 is a copper column. The bottom side of the blind hole 112 is close to the back side 11b of the substrate 11, and the opening side of the blind hole 112 is located on the front side 11a of the substrate 11.

[0078] S44, such as Figure 6 As shown in (d) in FIG. 1 , on the front side of the substrate 11 , the metal pillars 12 in different blind holes 112 are electrically connected and bonded to the chip 21 .

[0079] S45, such as Figure 6 As shown in (e), a portion of the substrate 11 is removed from the bottom side of the blind hole 112 to expose a portion of the metal layer 13, and the blind hole of the substrate 11 is etched to form a through hole. The method of removing a portion of the substrate 11 includes but is not limited to grinding or cutting processes. The grinding or cutting process can achieve large-size cutting and improve processing efficiency.

[0080] S46, such as Figure 6 As shown in (f) in FIG. 1 , the back side of the substrate 11 is further etched to thin the substrate 11. After thinning, most of the metal layer 13 can be exposed from the surface of the substrate. After etching, part of the metal pillar 12 can also be exposed from the surface of the substrate 11. In this process, the substrate 11 can be etched by plasma etching, laser etching, or the like. Plasma etching or laser etching can have a high processing accuracy, so that the structure of the through silicon via meets the design requirements.

[0081] S47, such as Figure 6 As shown in (g) in FIG. 1 , a dielectric layer 14 is deposited on the surface of the substrate 11 and the metal layer 13 . The dielectric layer 14 may include a silicon nitride layer and a silicon oxide layer to protect the substrate 11 , the metal pillar 12 and the metal layer 13 .

[0082] S48, such as Figure 6 As shown in (h) in FIG. 1 , when the dielectric layer 14 is relatively thick, a thinning process may be used to thin the dielectric layer 14 .

[0083] use Figure 6 The process steps shown can firstly bond the substrate of the through silicon via structure to the chip during the manufacturing process, and then perform BVR production on the bonded combined structure.

[0084] in, Figure 3 and Figure 4 The corresponding manufacturing method, during the manufacturing process, first partially etches the silicon substrate 11, then deposits the metal layer 13, and then thins the substrate 11. This process is not affected by the thinning thickness of the substrate 11, and can be applied to application scenarios where the etching depth is greater than 20 μm. Figure 5 and Figure 6 The corresponding manufacturing method, since the metal pillar 12 and the metal layer 13 have been pre-deposited in the blind hole 112 of the substrate 11 during the manufacturing process, the thinning thickness of the substrate 11 is limited by the position of the metal layer 13. Therefore, the manufacturing method can be applied to application scenarios where the etching depth is less than 20μm.

[0085] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A through silicon via structure, characterized in that: include: A substrate having a through hole, wherein the through hole is arranged along a thickness direction of the substrate; A metal column filled in the through hole and provided with an insulating layer between the metal column and the inner wall of the through hole; A metal layer is disposed on a side surface of the metal column and is vertically disposed to a height direction of the metal column; A diffusion rate of the metal in the metal layer in the substrate is lower than a diffusion rate of the metal in the metal pillar in the substrate.

2. The through silicon via structure according to claim 1, characterized in that: The metal in the metal column is copper, and the metal in the metal layer is selected from one of Pb, Sr, Ta, Zr, Ti, Cr, Ru, Mo, W, Ir, Ce, Pt, Co, Ni or Fe, or an alloy containing at least one of the above metals.

3. The through silicon via structure according to claim 2, characterized in that: The thickness of the metal layer is greater than or equal to 200 nm and less than or equal to 20% of the height of the through hole.

4. A method for making a through silicon via back leakage hole, characterized in that: include: A substrate having a blind hole is provided; wherein the hole depth direction of the blind hole is the thickness direction of the substrate, the blind hole is filled with a metal column formed of a first metal, and an insulating layer is formed between the hole wall of the blind hole and the metal column; removing a portion of the substrate at the bottom of the blind hole until the blind hole forms a through hole to expose the metal column; forming a metal layer on the surface of the metal column; The substrate is further etched along the depth direction of the through hole to a desired size.

5. The method according to claim 4, characterized in that: Forming the metal layer on the surface of the metal column comprises: The metal layer is formed by sputtering, chemical vapor deposition, or physical vapor deposition.

6. The method according to claim 5, characterized in that: The precursor used in forming the metal layer by chemical vapor deposition includes: One of iron pentacarbonyl, dicobalt octacarbonyl, nickel tetracarbonyl, palladium hexafluoroacetylacetonate, allylcyclopentadienylpalladium, bis(phenylchromium), trimethyl(methylcyclopentadienyl)platinum, ruthenium acetylacetonate, rhodium acetylacetonate dicarbonyl, IrH(PF3)4, Cr(PF3)6, Mo(PF3)6 or W(PF3)6.

7. A method for making a through silicon via back leakage hole, characterized in that: include: A substrate having a blind hole is provided; wherein the depth direction of the blind hole is the thickness direction of the substrate, an insulating layer is formed on the inner wall of the blind hole, a metal layer is provided at the bottom of the blind hole, and a metal column is provided on the surface of the metal layer; removing a portion of the substrate at the bottom of the blind hole until the blind hole forms a through hole to expose the metal layer; The substrate is continuously etched along the hole depth direction of the through hole to a desired size and a portion of the metal column is exposed.

8. The method according to claim 7, characterized in that: A grinding process is used to remove a portion of the substrate at the bottom of the blind hole until the blind hole forms a through hole.

9. The production method according to any one of claims 4 to 8, characterized in that: The substrate is bonded to a carrier, the carrier comprises a base and conductor wiring arranged on the base, and at least part of the metal pillars are connected to the conductor wiring.

10. A circuit board, characterized in that: The invention comprises at least two chips and a through silicon via structure as claimed in any one of claims 1 to 3 or a through silicon via structure formed by the manufacturing method as claimed in any one of claims 4 to 8, wherein the at least two chips are connected through the through silicon via structure.

11. An electronic device, characterized in that: Comprising the circuit board as claimed in claim 10.

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