Semiconductor device, preparation method, read-write method and memory

Abstract

The invention provides a semiconductor device, a preparation method, a read-write method and a memory. The semiconductor device comprises a substrate, an active column, a memory cell and a gate word line structure. Wherein the active column is arranged on the substrate, and the active column extends along a first direction far away from the substrate. The number of the memory cells is multiple, the multiple memory cells are arranged in parallel along the first direction, and the memory cells are coupled to the side walls of the active columns. The number of the gate word line structures is multiple, the multiple gate word line structures are arranged side by side in the first direction at intervals and used for controlling on-off of channels in the active columns, and a storage unit is arranged between every two adjacent gate word line structures. The semiconductor device can avoid the problem that a planar device is miniature in size, so that the storage density of the device is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method, a reading and writing method, and a memory. Background Art

[0002] With the rapid development of semiconductor storage technology, improving the device density of semiconductor devices is an important direction to improve device performance. Traditional dynamic random access memory (DRAM) is a planar device. If the storage density needs to be increased, the size of a single transistor needs to be reduced to save area. However, as the size decreases, the effectiveness of transistors and capacitors will also be affected accordingly. At present, the size of transistors has gradually approached the limit, which limits the further improvement of storage density. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor device that can improve storage density in response to the problems in the above-mentioned background technology.

[0004] According to some embodiments of the present disclosure, there is provided a semiconductor device, comprising:

[0005] substrate;

[0006] An active column, wherein the active column is disposed on the substrate and extends along a first direction away from the substrate;

[0007] A storage unit, wherein there are a plurality of the storage units, the plurality of the storage units are arranged in parallel along the first direction, and the storage units are coupled to the sidewalls of the active pillars; and

[0008] A gate word line structure, wherein there are a plurality of gate word line structures, the plurality of gate word line structures are arranged in parallel and at intervals along the first direction and are used to control the on and off of the channel in the active column, and the storage unit is arranged between two adjacent gate word line structures.

[0009] In some embodiments of the present disclosure, the memory cell includes a capacitor, the semiconductor device further includes an isolation structure, and the gate word line structure and the capacitor are separated by the isolation structure.

[0010] In some embodiments of the present disclosure, the capacitor includes a first electrode, a dielectric layer, and a second electrode, the dielectric layer is disposed between the first electrode and the second electrode, and the first electrode is disposed in contact with a sidewall of the active pillar.

[0011] In some embodiments of the present disclosure, the first electrode and the active pillar are made of the same material.

[0012] In some embodiments of the present disclosure, the memory cell is disposed around the active pillar, and the gate word line structure is disposed around the active pillar.

[0013] In some embodiments of the present disclosure, the plurality of active pillars are arranged in parallel and at intervals along a second direction intersecting the first direction, each gate word line structure also extends along the second direction, and the gate word line structure is used to control the on and off of channels in the plurality of active pillars arranged in parallel in the second direction.

[0014] In some embodiments of the present disclosure, the semiconductor device further includes a common electrode, which is disposed between two adjacent active pillars, and the storage units coupled to two adjacent active pillars are both electrically connected to the common electrode.

[0015] In some embodiments of the present disclosure, the active pillar is in the shape of a hollow pillar, and the semiconductor device further includes a filling dielectric layer disposed in the inner space of the active pillar; or,

[0016] The active column is in a solid column shape.

[0017] In another aspect, a method for preparing a semiconductor device as described in any of the above embodiments comprises the following steps:

[0018] Forming a plurality of first sacrificial layers and a plurality of second sacrificial layers on a substrate, wherein the first sacrificial layers and the second sacrificial layers are alternately stacked in a first direction, and an isolation structure is provided between each of the first sacrificial layers and the second sacrificial layers adjacent thereto;

[0019] Etching the multiple layers of the first sacrificial layer and the multiple layers of the second sacrificial layer along the first direction to form a first etching hole penetrating the multiple layers of the first sacrificial layer and the multiple layers of the second sacrificial layer;

[0020] Etching the first sacrificial layer exposed in the first etching hole, and forming the storage unit in the area where the removed first sacrificial layer is located;

[0021] forming the active pillar extending along the first direction in the first etched hole; and,

[0022] The second sacrificial layer is removed, and the gate word line structure is formed in the region where the removed second sacrificial layer is located.

[0023] In some embodiments of the present disclosure, in the step of forming the first etching holes, a plurality of the first etching holes arranged in parallel and at intervals along a second direction intersecting the first direction are formed;

[0024] In the step of forming the active pillars, the active pillars are correspondingly formed in each of the first etching holes.

[0025] In some embodiments of the present disclosure, the step of forming the storage unit includes:

[0026] Depositing a sacrificial material layer, a dielectric layer and a first electrode in sequence in the region where the removed first sacrificial layer is located;

[0027] Etching multiple layers of the first sacrificial layer and multiple layers of the second sacrificial layer along the first direction on a side of the dielectric layer away from the active pillar to form a second etching hole exposing the sacrificial material layer; and

[0028] The sacrificial material layer exposed in the second etching hole is etched, and a second electrode is formed in the region where the removed sacrificial material layer is located.

[0029] In some embodiments of the present disclosure, in the step of etching the first sacrificial layer exposed in the first etching holes, a portion of the first sacrificial layer located between two adjacent first etching holes is retained;

[0030] In the step of forming the second etching hole, the remaining first sacrificial layer is etched along the first direction to expose the sacrificial material layers on both sides thereof.

[0031] In some embodiments of the present disclosure, after forming the second electrode, a step of forming a common electrode in the second etching hole is further included, and the common electrode is electrically connected to the second electrodes located on both sides thereof.

[0032] In some embodiments of the present disclosure, before etching the sacrificial material layer, the method further includes: etching the exposed portion of the sacrificial material layer in the first etching hole, and backfilling an insulating spacer in the region where the removed portion of the sacrificial material layer is located.

[0033] In yet another aspect, a method for reading and writing a semiconductor device, which performs at least one of a reading operation and a writing operation on the semiconductor device according to any one of the above embodiments;

[0034] The reading operation includes: selecting the active pillar, controlling all the gate word line structures on the active pillar to be in a closed state and supplying power to the active pillar, then sequentially opening the gate word line structures in a direction close to the substrate, and sequentially reading the information stored in the corresponding storage cells;

[0035] The write operation includes: selecting the active pillar, controlling all the gate word line structures on the active pillar to be in an open state and supplying power to the active pillar, closing the gate word line structures in sequence in a direction away from the substrate, and writing information to the corresponding storage cells in sequence.

[0036] In yet another aspect, a memory comprises the semiconductor device as described in any one of the above embodiments.

[0037] The semiconductor device in at least one embodiment of the present disclosure includes an active column, a plurality of storage cells and a plurality of gate word line structures, wherein the active column extends along a first direction, the plurality of storage cells are arranged in parallel along the first direction and coupled to the sidewall of the active column, and the plurality of gate word line structures are also arranged in parallel along the first direction and used to control the active column. By applying pressure to the plurality of gate word line structures, the channel in the active column can be pinched off to achieve isolation of the plurality of storage cells, which ensures the information storage and reading functions of the storage cells in the semiconductor device. In addition, the sidewalls of the active column are coupled with a plurality of stacked storage cells, which can avoid the problem of size miniaturization suffered by planar devices, thereby significantly improving the storage density of the device.

[0038] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0040] Figure 1 is a schematic diagram of a cross-sectional structure of a semiconductor device;

[0041] Figure 2 For Figure 1 A schematic diagram of a circuit structure corresponding to the semiconductor device shown;

[0042] Figure 3 A schematic diagram of the steps of a method for preparing a semiconductor device;

[0043] Figure 4 A schematic diagram of a cross-sectional structure of forming multiple first sacrificial layers and multiple second sacrificial layers on a substrate;

[0044] Figure 5 For Figure 4A schematic diagram of a structure in which the sidewalls of a plurality of first sacrificial layers form a step-like structure based on the structure shown;

[0045] Figure 6 For Figure 5 A schematic diagram of a structure in which a first etching hole is formed on the basis of the structure shown;

[0046] Figure 7 For Figure 6 The corresponding top view structural diagram;

[0047] Figure 8 For Figure 6 A schematic diagram of a structure in which a first sacrificial layer is etched based on the structure shown;

[0048] Fig. 9 For Figure 8 A schematic diagram of a structure in which a sacrificial material layer, a dielectric layer and a first electrode are deposited on the basis of the structure shown;

[0049] Fig.10 For Fig. 9 A schematic diagram of a structure in which a portion of the sacrificial material layer is etched and the insulating spacer is backfilled based on the structure shown;

[0050] Fig.11 For Fig.10 A schematic diagram of a structure in which an active column is formed on the basis of the structure shown;

[0051] Fig.12 For Fig.11 A schematic diagram of a structure in which a second etching hole is formed on the basis of the structure shown;

[0052] Fig.13 For Fig.12 A schematic diagram of a structure in which a second electrode is formed on the basis of the structure shown;

[0053] Fig.14 For Fig.13 The corresponding top view structural diagram;

[0054] Fig.15 For Fig.13 A schematic diagram of a structure in which the second sacrificial layer is removed based on the structure shown;

[0055] Fig.16 For Fig.15 The corresponding top view structural diagram;

[0056] Fig.17 For Fig.15 Schematic diagram of a gate word line structure formed on the basis of the structure shown.

[0057] The reference numerals and their meanings are as follows:

[0058] 100, substrate; 101, first etching hole; 102, second etching hole; 103, gate etching groove; 110, active pillar; 120, capacitor; 121, first electrode; 122, capacitor dielectric layer; 123, second electrode; 130, gate word line structure; 131, gate conductive part; 132, gate dielectric part; 210, word line lead; 220, bit line structure; 230, common conductor; 140, filling dielectric layer; 150, common electrode; 310, first sacrificial layer; 320, second sacrificial layer; 330, isolation structure; 340, blocking layer; 350, sacrificial material layer; 360, insulating spacer. DETAILED DESCRIPTION

[0059] To facilitate understanding of the present invention, a more comprehensive description of the present invention is provided below. The preferred embodiments of the present invention are given herein. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the content of the present invention more thorough and comprehensive.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this document pertains. The terms used herein in the specification of this document are only for describing specific embodiments and are not intended to limit this document.

[0061] It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to, or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to, or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion.

[0062] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to other elements or features. It should be understood that the spatially relative terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used may be interpreted accordingly.

[0063] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "a", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0064] The present disclosure provides a semiconductor device, which includes: a substrate, an active column, a memory cell and a gate word line structure. The active column is arranged on the substrate, and the active column extends along a first direction away from the substrate. There are multiple memory cells, and the multiple memory cells are arranged in parallel along the first direction, and the memory cells are coupled to the sidewalls of the active column. There are multiple gate word line structures, and the multiple gate word line structures are arranged in parallel and spaced apart along the first direction and are used to control the on and off of the channel in the active column, and a memory cell is arranged between two adjacent gate word line structures.

[0065] The semiconductor device includes an active column, a plurality of storage cells and a plurality of gate word line structures. The active column extends along a first direction. The plurality of storage cells are arranged in parallel along the first direction and coupled to the side wall of the active column. The plurality of gate word line structures are also arranged in parallel along the first direction and used to control the active column. By applying pressure to the plurality of gate word line structures, the channel in the active column can be pinched off to achieve isolation of the plurality of storage cells, which ensures the information storage and reading functions of the storage cells in the semiconductor device. In addition, the side wall of the active column is coupled with a plurality of stacked storage cells, which can avoid the problem of size miniaturization suffered by planar devices, thereby significantly improving the storage density of the device.

[0066] Figure 1Schematic diagram of the cross-sectional structure of a semiconductor device disclosed in the present invention. Figure 1 As shown, the semiconductor device includes a substrate 100, an active pillar 110, a memory cell and a gate word line structure 130. The active pillar 110 is disposed on the substrate 100, and the active pillar 110 extends along a first direction away from the substrate 100. There are multiple memory cells, and the multiple memory cells are arranged in parallel along the first direction, and the memory cells are coupled to the sidewalls of the active pillar 110. There are multiple gate word line structures 130, and the multiple gate word line structures 130 are arranged in parallel and spaced apart along the first direction and are used to control the on and off of the channel in the active pillar 110, and a memory cell is arranged between two adjacent gate word line structures 130.

[0067] In this embodiment, the first direction may be a direction perpendicular to the surface of the substrate 100. Figure 1 As shown, the first direction may be the direction shown by the z-axis. The axial direction of the active pillar 110 is along the first direction, and the channel in the active pillar 110 may be along the axial direction of the active pillar 110 and located in the sidewall of the active pillar 110. The storage unit is used to store information, and the plurality of gate word line structures 130 are used to control the on and off of the channel in the active pillar 110. For example, by controlling the voltage of each gate word line structure 130, it is possible to pinch off a specific portion of the channel in the active pillar 110, thereby isolating a plurality of storage units coupled to the same active pillar 110.

[0068] It can be understood that the structure of the memory cell is directly related to the storage method of the semiconductor device. Figure 1 As shown, as some examples of this embodiment, the storage unit includes a capacitor 120, and the semiconductor device also includes an isolation structure 330, and the gate word line structure 130 and the capacitor 120 are separated by the isolation structure 330. The capacitor 120 is a volatile storage structure, which can be used to represent the information carried according to the amount of charge stored therein. Since the capacitor 120 and the gate word line structure 130 are both arranged in parallel in the first direction, and both need to be powered on, the isolation structure 330 is arranged between the two to avoid crosstalk between the two.

[0069] Reference Figure 1 As shown, as some examples of this embodiment, the capacitor 120 includes a first electrode 121 , a dielectric layer and a second electrode 123 , the dielectric layer is disposed between the first electrode 121 and the second electrode 123 , and the first electrode 121 is disposed in contact with the sidewall of the active pillar 110 .

[0070] In this example, the first electrode 121 and the second electrode 123 may be independently selected from a conductive material. For example, the materials of the first electrode 121 and the second electrode 123 may be independently selected from one or more of metal and polysilicon. The metal may include but is not limited to at least one of gold, silver, copper, tungsten and aluminum.

[0071] In this example, the first electrode 121 and the active pillar 110 are made of the same material to reduce the interface problem between the first electrode 121 and the active pillar 110 as much as possible, so that the contact between the two is more stable and the contact resistance is smaller.

[0072] Furthermore, the material of the first electrode 121 may be polysilicon, and the material of the active pillar 110 may also be polysilicon.

[0073] In this example, the dielectric layer is used to insulate and space the first electrode 121 and the second electrode 123. Further, the dielectric layer may be selected from one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0074] Reference Figure 1 As shown in some examples of this embodiment, the memory cells are arranged around the active pillars 110. The memory cells are arranged around the active pillars 110 so that the structure of the memory cells relative to the active pillars 110 is more symmetrical and the space outside the active pillars 110 can be more fully utilized.

[0075] Reference Figure 1 As shown in some examples of this embodiment, the gate word line structure 130 is disposed around the active pillar 110. The gate word line structure 130 is disposed around the active pillar 110, so that the space of the outer area of ​​the active pillar 110 can be more fully utilized, and it is also beneficial to ensure that the gate word line structure 130 effectively controls the channel in the active pillar 110.

[0076] Reference Figure 1 As shown in some examples of this embodiment, there may be a plurality of active pillars 110, and the plurality of active pillars 110 are arranged in parallel and at intervals along a second direction intersecting the first direction. Figure 1 As shown, the second direction may be the direction shown by the x-axis. Arranging a plurality of parallel active pillars 110 in the second direction can further improve the storage density of the semiconductor device. Furthermore, the second direction may be perpendicular to the first direction.

[0077] Further, refer to Figure 1 As shown, in this example, each gate word line structure 130 also extends along the second direction, and the gate word line structure 130 is used to control the on and off of channels in a plurality of active pillars 110 arranged in parallel in the second direction.

[0078] Reference Figure 1As shown in some examples of this embodiment, the semiconductor device may further include a bit line structure 220. The bit line structure 220 may be electrically connected to the active pillar 110, and the bit line structure 220 may extend along a third direction intersecting both the first direction and the second direction. The third direction may be as shown in FIG. Figure 1 Further, the first direction, the second direction and the third direction may be perpendicular to each other.

[0079] Reference Figure 1 As shown, as some examples of this embodiment, the bit line structure 220 may be disposed on a side of the active pillar 110 away from the substrate 100 .

[0080] As some examples of this embodiment, the semiconductor device may further include a plurality of active pillars 110 arranged in parallel and spaced apart in the third direction, and the bit line structure 220 may be electrically connected to the plurality of active pillars 110 arranged in parallel in the third direction.

[0081] It can be understood that when operating the semiconductor device, the bit line structure 220 and the gate word line structure 130 can be used to select the on or off region of the channel in a specific active pillar 110, thereby performing read and write operations on a specific memory cell.

[0082] Reference Figure 1 As shown in some examples of this embodiment, the semiconductor device further includes a common electrode 150, which is disposed between two adjacent active pillars 110, and the memory cells coupled to the two adjacent active pillars 110 are electrically connected to the common electrode 150. The common electrode 150 can be used to supply power to a plurality of memory cells at the same time, so as to further save the area occupied by the semiconductor device.

[0083] Reference Figure 1 As shown, in this example, the common electrode 150 may extend along the first direction.

[0084] In this example, the semiconductor device may include a plurality of common electrodes 150 arranged in parallel in the third direction, and the plurality of common electrodes 150 are electrically connected to each other, so as to conduct the plurality of common electrodes 150 to an external circuit at the same time.

[0085] In this example, when the capacitor 120 is used as a storage unit, the first electrode 121 of the capacitor 120 may be electrically connected to the active pillar 110 , and the second electrode 123 of the capacitor 120 may be electrically connected to the common electrode 150 .

[0086] Reference Figure 1As shown, as some examples of this embodiment, the gate word line structure 130 may include a gate conductive portion 131 and a gate dielectric portion 132 , and the gate dielectric portion 132 may be disposed between the gate conductive portion 131 and the active pillar 110 to insulate and space the gate conductive portion 131 from the active pillar 110 .

[0087] In this example, the gate dielectric portion 132 may also be disposed between the gate conductive portion 131 and the common electrode 150 to insulate and space the gate conductive portion 131 from the common electrode 150 .

[0088] Further, in this example, the gate dielectric portion 132 may be disposed around the gate conductive portion 131 to separate the gate conductive portion 131 from other surrounding structures.

[0089] Reference Figure 1 As shown, as some examples of this embodiment, the active pillar 110 is in a hollow column shape, and the semiconductor device further includes a filling dielectric layer 140 disposed in the inner space of the active pillar 110 .

[0090] In other examples, the active pillar 110 may also be in the shape of a solid pillar.

[0091] Reference Figure 1 As shown in some examples of this embodiment, the semiconductor device may further include a plurality of word line lead-out lines 210, and the plurality of word line lead-out lines 210 may be electrically connected to a plurality of gate word line structures 130, respectively, and each gate word line structure 130 is electrically connected to at least one word line lead-out line 210. The structural design of the word line lead-out line 210 can lead the gate word line structure 130 buried in the lower layer of the structure to an external circuit, thereby ensuring the normal operation of each gate word line structure 130.

[0092] Reference Figure 1 As shown, as some examples of this embodiment, the word line lead 210 can extend along the first direction, and the bottom end of the word line lead 210 can contact the corresponding gate word line structure 130 to make the two electrically connected. The top end of the word line lead 210 can be exposed on the surface of the isolation structure 330 to facilitate connection to an external circuit.

[0093] As some examples of this embodiment, a plurality of word line lead lines 210 may be arranged in parallel and at intervals along the second direction.

[0094] On the other hand, the present disclosure further provides a reading and writing method of a semiconductor device, which performs at least one of a reading operation and a writing operation on the semiconductor device in the above embodiment.

[0095] The reading operation includes: selecting an active column, controlling all gate word line structures on the active column to be in a closed state and supplying power to the active column, then opening the gate word line structures in sequence along the direction close to the substrate, and reading the information stored in the corresponding storage cells in sequence.

[0096] The write operation includes: selecting an active column, controlling all gate word line structures on the active column to be in an open state and supplying power to the active column, closing the gate word line structures in sequence in a direction away from the substrate, and writing information to corresponding storage cells in sequence.

[0097] Figure 2 For Figure 1 Schematic diagram of the circuit structure corresponding to the semiconductor device shown. Figure 2 Two active pillars are shown in the figure, and each active pillar is connected to a bit line structure, which is marked as BL1 and BL2 from left to right. Five storage cells are coupled to each active pillar, which are marked as C11~C15 and C21~C25 in the direction away from the substrate. Accordingly, the semiconductor device is provided with six gate word line structures for controlling the channel, which are marked as WL0~WL5 in the direction away from the substrate.

[0098] As some examples of this embodiment, Figure 1 and Figure 2 As shown, when performing a read operation, the active column can be powered through the bit line structure BL1 or BL2 to control the gate word line structure WL0~WL5 to be in a closed state, so that the channel of the entire active column is in a closed state. Then, the gate word line structure WL5 is first opened to read the information stored in the storage cell C15 or C25, and then the gate word line structure WL4 is opened to read the information stored in the storage cell C14 or C24. By analogy, the reading of the information on the storage cells C11~C15 or the storage cells C21~C25 can be completed.

[0099] As some examples of this embodiment, Figure 1 and Figure 2 As shown, when performing a write operation, the active column can be powered through the bit line structure BL1 or BL2 to control the gate word line structure WL0~WL5 to be in an open state. Then, the gate word line structure WL0 is first closed, and information is written to the storage cell C11 or C21, and then the gate word line structure WL1 is closed, and information is written to the storage cell C12 or C22. And so on, the writing of information on the storage cells C11~C15 or the storage cells C21~C25 can be completed.

[0100] It is understandable that for the sake of convenience, Figure 1~Figure 2In the semiconductor device shown, only five memory cells are coupled to the same active pillar. However, in an actual semiconductor device, more memory cells may be coupled to the same active pillar, and more gate word line structures may be provided accordingly.

[0101] In addition, the traditional planar dynamic random access memory can realize random reading of information of each storage unit. In the semiconductor device disclosed in the present invention, multiple storage units coupled on the same active column read information in a sequential manner. Although the speed of reading the information of a single storage unit is slightly slow, the storage density can be significantly improved due to the multi-layer stacked structure, so it can provide a significantly larger storage capacity. The semiconductor device can be produced in a manufacturing process in combination with a stacked logic operation device with a higher device density, and used as its temporary register, and the number of stacked devices makes up for the disadvantage of the lower speed of a single device, thereby obtaining performance far exceeding that of a planar device.

[0102] Furthermore, the present disclosure also provides a method for preparing a semiconductor device. Figure 3 Schematic diagram of the steps of the preparation method. Figure 3 As shown, the preparation method includes steps S1 to S4, which are specifically as follows.

[0103] In step S1 , a plurality of first sacrificial layers 310 and a plurality of second sacrificial layers 320 are formed on a substrate 100 , wherein the first sacrificial layers 310 and the second sacrificial layers 320 are alternately stacked in a first direction.

[0104] Figure 4 FIG. 1 is a schematic cross-sectional structure diagram of forming a plurality of first sacrificial layers 310 and a plurality of second sacrificial layers 320 on a substrate 100. Figure 4 As shown, the first sacrificial layer 310 and the second sacrificial layer 320 are alternately formed on the substrate 100. The first sacrificial layer 310 is mainly used to occupy the area where the memory cell formed later is located, and the second sacrificial layer 320 is mainly used to occupy the area where the gate word line structure 130 formed later is located.

[0105] As some examples of this embodiment, the first sacrificial layer 310 and the second sacrificial layer 320 are made of different materials so that they can be removed in different processes.

[0106] As some examples of this embodiment, the material of the first sacrificial layer 310 may include a silicon-germanium alloy. The first sacrificial layer 310 may be formed by a chemical vapor deposition method.

[0107] As some examples of this embodiment, the material of the second sacrificial layer 320 may include silicon nitride. The second sacrificial layer 320 may be formed by chemical vapor deposition.

[0108] Reference Figure 4 As shown in some examples of this embodiment, between the steps of forming the first sacrificial layer 310 and the steps of forming the second sacrificial layer 320, a schematic diagram of forming an isolation structure 330 may also be included. An isolation structure 330 is provided between each first sacrificial layer 310 and the second sacrificial layer 320 adjacent thereto, and the isolation structure 330 is mainly used to insulate and space the memory cells and gate word line structures 130 to be formed later.

[0109] In this example, the material of the isolation structure 330 is different from the material of the first sacrificial layer 310 and the material of the second sacrificial layer 320. For example, the material of the isolation structure 330 may include silicon oxide. The isolation structure 330 may be formed by chemical vapor deposition.

[0110] As some examples of this embodiment, after the step of forming a plurality of first sacrificial layers 310 and second sacrificial layers 320 , a step of forming a step-shaped structure on the sidewalls of the plurality of first sacrificial layers 310 is further included. Figure 5 For Figure 4 A schematic diagram of a structure in which the sidewalls of the plurality of first sacrificial layers 310 are formed into a stepped structure based on the structure shown in FIG. Figure 5 As shown, along a first direction away from the substrate 100 , the sidewalls of each first sacrificial layer 310 gradually shift inward to form a step-like structure.

[0111] In this example, etching can be performed to form a step-like structure on the sidewalls of the plurality of first sacrificial layers 310. For example, etching can be performed multiple times along the first direction, etching to the first sacrificial layer 310 closest to the substrate 100 in the first etching, expanding the etching area and etching to the first sacrificial layer 310 next closest to the substrate 100 in the second etching, and so on, etching and expanding the etching area successively until etching to the first sacrificial layer 310 farthest from the substrate 100, that is, a step-like structure can be formed.

[0112] Reference Figure 5 As shown, after forming the stepped structure, a barrier layer 340 may be formed to shield each first sacrificial layer 310. The material of the barrier layer 340 may be the same as that of the isolation structure 330. The barrier layer 340 protects the first sacrificial layer 310 from the top and may also serve as an isolation material between a plurality of word line lead lines 210.

[0113] Step S2 , etching the multiple layers of the first sacrificial layer 310 and the multiple layers of the second sacrificial layer 320 along the first direction to form a first etching hole 101 penetrating the multiple layers of the first sacrificial layer 310 and the multiple layers of the second sacrificial layer 320 .

[0114] Figure 6 For Figure 5A schematic diagram of a structure in which a first etching hole 101 is formed on the basis of the structure shown in FIG. Figure 6 As shown, the first etched hole 101 penetrates the first sacrificial layer 310 and the second sacrificial layer 320, and the axial direction of the first etched hole 101 is along the first direction. Further, the first etched hole 101 also penetrates the isolation structure 330, and the substrate 100 can be exposed in the first etched hole 101. The first etched hole 101 is mainly used to expose the first sacrificial layer 310 so as to start etching the first sacrificial layer 310 along the sidewall, and the first etched hole 101 is also used as a preparation area for the subsequent active pillar 110.

[0115] As some examples of this embodiment, the first sacrificial layer 310 and the second sacrificial layer 320 may be etched by dry etching to ensure the uniformity of the aperture of the first etched hole 101 as much as possible.

[0116] Figure 7 For Figure 6 The corresponding top view of the structure. Figure 7 As shown, there may be a plurality of first etching holes 101, and the plurality of first etching holes 101 may be arranged in an array. The plurality of first etching holes 101 may be arranged in parallel in a second direction and a third direction intersecting the first direction to form an array structure. The third direction may be as shown in FIG. Figure 7 The direction shown by the y-axis.

[0117] Reference Figure 7 As shown, as some examples of this embodiment, the cross section of the first etched hole 101 may be circular. In other examples, the cross section of the first etched hole 101 may also be square, or the cross section of the first etched hole 101 may also be other shapes.

[0118] Step S3 , etching the exposed first sacrificial layer 310 in the first etched hole 101 , forming an active pillar 110 extending along a first direction in the first etched hole 101 , and forming a memory cell in the region where the removed first sacrificial layer 310 is located.

[0119] Figure 8 For Figure 6 The schematic diagram of the structure of etching the first sacrificial layer 310 based on the structure shown in FIG. Figure 8 As shown, the first sacrificial layer 310 is removed along the direction away from the axis of the first etching hole 101, and the region for forming the memory cell is exposed. During the etching of the first sacrificial layer 310, a portion of the first etching layer may be retained.

[0120] As some examples of this embodiment, the steps of forming the memory cell include: sequentially depositing a sacrificial material layer 350, a capacitor dielectric layer 122, and a first electrode 121 in the region where the removed first sacrificial layer 310 is located. Etching multiple layers of the first sacrificial layer 310 and multiple layers of the second sacrificial layer 320 along a first direction on a side of the capacitor dielectric layer 122 away from the active pillar 110 to form a second etching hole 102 exposing the sacrificial material layer 350. And, etching the exposed sacrificial material layer 350 in the second etching hole 102, and forming a second electrode 123 in the region where the removed sacrificial material layer 350 is located.

[0121] Fig. 9 For Figure 8 A schematic diagram of a structure in which a sacrificial material layer 350, a capacitor dielectric layer 122 and a first electrode 121 are deposited on the basis of the structure shown in FIG. Fig. 9 As shown, the sacrificial material layer 350 is attached to the retained first sacrificial layer 310 and the isolation structure 330, the deposited material layer has pores, the capacitor dielectric layer 122 is attached to the sacrificial material layer 350, the capacitor dielectric layer 122 also has pores, and the first electrode 121 is attached to the side of the capacitor dielectric layer 122 away from the sacrificial material layer 350.

[0122] exist Fig. 9 In the embodiment, the sacrificial material layer 350 is mainly used to occupy the area where the second electrode 123 to be formed subsequently is located, and is removed in the subsequent preparation process to facilitate the formation of the second electrode 123.

[0123] As some examples of this embodiment, the material of the sacrificial material layer 350 may be the same as that of the first sacrificial layer 310. For example, the material of the sacrificial material layer 350 may include silicon germanium.

[0124] As some examples of this embodiment, the material of the capacitor dielectric layer 122 may be an insulating material. For example, the material of the capacitor dielectric layer 122 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0125] As some examples of this embodiment, the material of the first electrode 121 may include polysilicon.

[0126] As some examples of this embodiment, the sacrificial material layer 350 may be formed by chemical vapor deposition. It is understood that during the deposition process, the sacrificial material layer 350 will also extend and adhere to the hole wall of the first etched hole 101, and will also extend and deposit on the topmost isolation structure 330.

[0127] As some examples of this embodiment, the capacitor dielectric layer 122 may be formed by chemical vapor deposition. It is understood that during the deposition process, the capacitor dielectric layer 122 will also extend and adhere to the hole wall of the first etched hole 101, and will also extend and deposit on the topmost isolation structure 330.

[0128] As some examples of this embodiment, the first electrode 121 may be formed by chemical vapor deposition. It is understood that during the deposition process, the first electrode 121 will extend and adhere to the hole wall of the first etched hole 101, and will also extend and deposit on the topmost isolation structure 330.

[0129] In this embodiment, after depositing the sacrificial material layer 350, the capacitor dielectric layer 122 and the first electrode 121, the following further includes: removing the material attached to the hole wall of the first etched hole 101 and extending and deposited on the topmost isolation structure 330, so as to form Fig. 9 The structure shown.

[0130] Furthermore, as some examples of this embodiment, before etching the sacrificial material layer 350 , the method further includes: etching the exposed portion of the sacrificial material layer 350 in the first etching hole 101 , and backfilling the insulating spacer 360 in the area where the removed portion of the sacrificial material layer 350 is located.

[0131] Fig.10 For Fig. 9 A schematic diagram of a structure in which a portion of the sacrificial material layer 350 is etched and the insulating spacer 360 is backfilled based on the structure shown. Fig. 9 and Fig.10 As shown, the portion of the sacrificial material layer 350 exposed in the first etched hole 101 is removed, and the region is backfilled with an insulating spacer 360. The insulating spacer 360 is mainly used to insulate and space the active pillar 110 and the second electrode 123 to be formed later.

[0132] As some examples of this embodiment, the method of etching the exposed portion of the sacrificial material layer 350 in the first etching hole 101 may be wet etching. By controlling the etching time, the etching amount can be controlled.

[0133] As some examples of this embodiment, the backfilled insulating spacer 360 may be the same material as the pre-formed isolation structure 330 , for example, the insulating spacer 360 may be selected from silicon oxide.

[0134] As some examples of this embodiment, the way of backfilling the insulating spacer 360 may be a chemical vapor deposition method.

[0135] After the insulating spacer 360 is backfilled, the active pillar 110 may be formed first, and then the second electrode 123 may be formed. Fig.11For Fig.10 A schematic diagram of a structure of an active pillar 110 formed on the basis of the structure shown in FIG. Fig.11 As shown, the active pillar 110 is formed in the first etched hole 101 .

[0136] As some examples of this embodiment, the active pillar 110 may be a hollow column. The steps of forming the active pillar 110 include: sequentially depositing a semiconductor material and a filling dielectric material in the first etched hole 101, and then depositing a semiconductor material on the top surface of the filling dielectric material to form the active pillar 110. The semiconductor materials deposited twice may together form the active pillar 110, and the filling dielectric material may serve as a filling dielectric layer 140 filled in the active pillar 110.

[0137] In other examples, the semiconductor material may be directly filled into the first etched hole 101 to form a solid column-shaped active pillar 110 .

[0138] As some examples of this embodiment, the semiconductor material of the active pillar 110 may include polysilicon.

[0139] Fig.12 For Fig.11 A schematic diagram of a structure in which a second etching hole 102 is formed on the basis of the structure shown in FIG. Fig.12 As shown in some examples of this embodiment, in the step of forming the second etched hole 102, the remaining first sacrificial layer 310 can be etched along the first direction to expose the sacrificial material layer 350 located on both sides thereof. Further, the second etched hole 102 can be formed between two active pillars 110 adjacent to each other in the second direction. The purpose of forming the second etched hole 102 is to expose the formed sacrificial material layer 350 so as to facilitate etching and removal thereof and fill the second electrode 123.

[0140] As some examples of this embodiment, the second etching hole 102 may be formed by dry etching.

[0141] Fig.13 For Fig.12 A schematic diagram of a structure in which a second electrode 123 is formed on the basis of the structure shown in FIG. Fig.13 As shown, the sacrificial material layer 350 is removed, and the second electrode 123 is formed in the region where the removed sacrificial material layer 350 is located.

[0142] As some examples of this embodiment, the sacrificial material layer 350 may be removed by wet etching.

[0143] As some examples of this embodiment, after removing the sacrificial material layer 350, a conductive material may be deposited in the region where the sacrificial material layer 350 is located to form the second electrode 123. Furthermore, the conductive material may be deposited by chemical vapor deposition.

[0144] As some examples of this embodiment, the conductive material deposited when forming the second electrode 123 may be selected from metal materials, such as one or more of gold, silver, copper, tungsten and aluminum.

[0145] It can be understood that the formed second electrode 123, the capacitor dielectric layer 122 and the first electrode 121 can form a capacitor 120, and the capacitor 120 can be used as a memory cell. Thus, a memory cell and an active pillar 110 can be formed.

[0146] Further, refer to Fig.13 As shown in some examples of this embodiment, after forming the second electrode 123, the step of forming a common electrode 150 in the second etched hole 102 is also included, and the common electrode 150 is electrically connected to the second electrodes 123 located on both sides thereof. The material of the common electrode 150 can be the same as that of the second electrode 123. After forming the second electrode 123, a conductive material can be continuously deposited in the second etched hole 102, that is, the common electrode 150 can be formed.

[0147] Fig.14 For Fig.13 The corresponding top view structure diagram. Fig.13 and Fig.14 As shown, the common electrode 150 is formed in the second etched hole 102 . The common electrode 150 is disposed between two adjacent active pillars 110 , and the memory cells coupled to the two adjacent active pillars 110 are electrically connected to the common electrode 150 .

[0148] Step S4 , removing the second sacrificial layer 320 , and forming a gate word line structure 130 in the region where the removed second sacrificial layer 320 is located.

[0149] Fig.15 For Fig.13 The schematic diagram of the structure shown in FIG. 1 is a schematic diagram of a structure in which the second sacrificial layer 320 is removed from the structure shown in FIG. Fig.15 As shown, the second sacrificial layer 320 is removed.

[0150] Fig.16 For Fig.15 The corresponding top view structure diagram. Fig.15 and Fig.16As shown in some examples of this embodiment, before removing the second sacrificial layer 320, the region between two active pillars 110 adjacent to each other in the third direction may be etched to form a gate etching groove 103 exposing the second sacrificial layer 320. The gate etching groove 103 may be in the shape of a long strip and extend along the second direction, so as to facilitate the subsequent formation of a gate word line structure 130 extending along the second direction.

[0151] As some examples of this embodiment, the second sacrificial layer 320 may be etched by wet etching.

[0152] Fig.17 For Fig.15 A schematic diagram of forming a gate word line structure 130 based on the structure shown in FIG. Fig.17 As shown, as some examples of this embodiment, the step of forming the gate word line structure 130 includes: depositing an insulating spacer 360 and a conductive material in sequence in the area where the removed second sacrificial layer 320 is located to form a gate dielectric portion 132 and a gate conductive portion 131, respectively.

[0153] As some examples of this embodiment, the material of the gate dielectric portion 132 may include a high dielectric constant material, such as hafnium oxide. The gate dielectric portion 132 may be formed by chemical vapor deposition.

[0154] As some examples of this embodiment, the material of the gate conductive part 131 may include a metal material, such as one or more of gold, silver, copper, tungsten and aluminum. The gate conductive part 131 may be formed by chemical vapor deposition.

[0155] It can be understood that, corresponding to the plurality of second sacrificial layers 320 , a plurality of gate word line structures 130 can be formed simultaneously in this step.

[0156] As some examples of this embodiment, after forming the gate word line structure 130, the following may be further included: removing the material deposited extending in the gate etch groove 103, and backfilling the insulating spacer 360 in the gate etch groove 103. The purpose of removing the material deposited extending in the gate etch groove 103 is to avoid electrical connection between multiple gate word line structures 130, and the purpose of backfilling the insulating spacer 360 is to isolate the formed gate word line structure 130 from other structures.

[0157] As some examples of this embodiment, after forming the gate word line structure 130, a step of forming a word line lead 210 may be further included. In the step of forming the word line lead 210, etching may be performed along a first direction with the aid of a pre-formed step-shaped structure to form word line lead holes that respectively expose a plurality of gate word line structures 130, and then the word line lead 210 is formed in the word line lead holes.

[0158] As some examples of this embodiment, after forming the gate word line structure 130 , a bit line structure 220 extending along the third direction may be further formed, and the bit line structure 220 may be electrically connected to a plurality of active pillars 110 arranged in parallel in the third direction.

[0159] As some examples of this embodiment, after forming the gate word line structure 130, a common wire 230 electrically connected to each memory cell may be formed. The common wire 230 may be electrically connected to each memory cell through the common electrode 150. Furthermore, the common wire 230 may also extend along the third direction.

[0160] It can be understood that through the preparation method described in the above steps S1 to S4, the following can be formed: Figure 1 The semiconductor device shown.

[0161] Furthermore, the present disclosure also provides a memory, which includes the semiconductor device in the above embodiment.

[0162] Please note that the above embodiments are for illustrative purposes only and are not meant to be limiting of this document.

[0163] It should be understood that, unless otherwise specified herein, there is no strict order restriction for the execution of the steps, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the preparation process may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0164] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0165] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A semiconductor device, characterized in that: include: substrate; An active column, wherein the active column is disposed on the substrate and extends along a first direction away from the substrate; A storage unit, wherein there are a plurality of the storage units, the plurality of the storage units are arranged in parallel along the first direction, and the storage units are coupled to the sidewalls of the active pillars; and A gate word line structure, wherein there are a plurality of gate word line structures, the plurality of gate word line structures are arranged in parallel and at intervals along the first direction and are used to control the on and off of the channel in the active column, and the storage unit is arranged between two adjacent gate word line structures.

2. The semiconductor device according to claim 1, wherein: The storage unit includes a capacitor, and the semiconductor device further includes an isolation structure, wherein the gate word line structure and the capacitor are spaced apart by the isolation structure.

3. The semiconductor device according to claim 2, characterized in that The capacitor includes a first electrode, a dielectric layer, and a second electrode. The dielectric layer is disposed between the first electrode and the second electrode. The first electrode is disposed in contact with a sidewall of the active pillar.

4. The semiconductor device according to claim 3, characterized in that The first electrode is made of the same material as the active pillar.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The memory cell is disposed around the active pillar, and the gate word line structure is disposed around the active pillar.

6. The semiconductor device according to claim 5, characterized in that There are multiple active pillars, and the multiple active pillars are arranged in parallel and at intervals along a second direction intersecting the first direction. Each gate word line structure also extends along the second direction, and the gate word line structure is used to control the on and off of channels in the multiple active pillars arranged in parallel in the second direction.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises a common electrode, which is arranged between two adjacent active pillars, and the storage units coupled to the two adjacent active pillars are electrically connected to the common electrode.

8. The semiconductor device according to any one of claims 1 to 4 and 6 to 7, characterized in that: The active pillar is in a hollow pillar shape, and the semiconductor device further comprises a filling dielectric layer arranged in the inner space of the active pillar; or, The active column is in a solid column shape.

9. A method for preparing a semiconductor device according to any one of claims 1 to 8, characterized in that: The steps include: Forming a plurality of first sacrificial layers and a plurality of second sacrificial layers on a substrate, wherein the first sacrificial layers and the second sacrificial layers are alternately stacked in a first direction, and an isolation structure is provided between each of the first sacrificial layers and the second sacrificial layers adjacent thereto; Etching the multiple layers of the first sacrificial layer and the multiple layers of the second sacrificial layer along the first direction to form a first etching hole penetrating the multiple layers of the first sacrificial layer and the multiple layers of the second sacrificial layer; Etching the first sacrificial layer exposed in the first etching hole, and forming the storage unit in the area where the removed first sacrificial layer is located; forming the active pillar extending along the first direction in the first etched hole; as well as, The second sacrificial layer is removed, and the gate word line structure is formed in the region where the removed second sacrificial layer is located.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: In the step of forming the first etching holes, a plurality of the first etching holes are formed which are arranged in parallel and spaced apart along a second direction intersecting the first direction; In the step of forming the active pillars, the active pillars are correspondingly formed in each of the first etching holes.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The steps of forming the storage unit include: Depositing a sacrificial material layer, a dielectric layer and a first electrode in sequence in the region where the removed first sacrificial layer is located; Etching multiple layers of the first sacrificial layer and multiple layers of the second sacrificial layer along the first direction on a side of the dielectric layer away from the active pillar to form a second etching hole exposing the sacrificial material layer; and The sacrificial material layer exposed in the second etching hole is etched, and a second electrode is formed in the region where the removed sacrificial material layer is located.

12. The method for preparing a semiconductor device according to claim 11, characterized in that In the step of etching the first sacrificial layer exposed in the first etching holes, a portion of the first sacrificial layer located between two adjacent first etching holes is retained; In the step of forming the second etching hole, the remaining first sacrificial layer is etched along the first direction to expose the sacrificial material layers on both sides thereof.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: After forming the second electrode, the method further includes forming a common electrode in the second etching hole, wherein the common electrode is electrically connected to the second electrodes located on both sides thereof.

14. The method for preparing a semiconductor device according to claim 11, characterized in that: Before etching the sacrificial material layer, the method further includes: etching the exposed portion of the sacrificial material layer in the first etching hole, and backfilling an insulating spacer in the region where the removed portion of the sacrificial material layer is located.

15. A method for reading and writing a semiconductor device, characterized in that: Performing at least one of a read operation and a write operation on the semiconductor device according to any one of claims 1 to 8; The reading operation includes: selecting the active pillar, controlling all the gate word line structures on the active pillar to be in a closed state and supplying power to the active pillar, then sequentially opening the gate word line structures in a direction close to the substrate, and sequentially reading the information stored in the corresponding storage cells; The write operation includes: selecting the active pillar, controlling all the gate word line structures on the active pillar to be in an open state and supplying power to the active pillar, closing the gate word line structures in sequence in a direction away from the substrate, and writing information to the corresponding storage cells in sequence.

16. A memory, characterized in that: Comprising a semiconductor device as described in any one of claims 1 to 8.

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