Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate comprises a substrate body, a plurality of pixel circuit units and a functional circuit, the substrate body comprises a display area and a non-display area, the pixel circuit units are located on one side of the substrate body and located in the display area, gaps are formed between the pixel circuit units, and at least part of the functional circuit is located in the gaps. According to the array substrate, the gaps are formed between the pixel circuit units, the functional circuits are at least partially arranged in the gaps, the functional circuits originally located in the non-display area can be transferred to the display area, the area of the non-display area can be reduced, and a narrow frame or even no frame is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of display technology, the application of display devices is becoming more and more extensive, and correspondingly, the requirements for display devices are becoming higher and higher.

[0003] However, the performance of existing display devices needs to be improved. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide an array substrate that is conducive to achieving a narrow frame.

[0005] Based on the above purpose, the present application provides an array substrate, which includes:

[0006] A substrate, the substrate comprising a display area and a non-display area;

[0007] A plurality of pixel circuit units, wherein the plurality of pixel circuit units are located on one side of the substrate and in the display area, and gaps are formed between the pixel circuit units;

[0008] A functional circuit is at least partially located in the gap.

[0009] In one embodiment, a plurality of the pixel circuit units are arranged on the substrate along a first direction and a second direction;

[0010] In the first direction, the gap is formed between any two adjacent pixel circuit units; and / or

[0011] In the second direction, the gap is formed between any two adjacent pixel circuit units;

[0012] wherein the first direction and the second direction intersect;

[0013] Preferably, the first direction is perpendicular to the second direction;

[0014] Preferably, the functional circuit includes a plurality of functional modules, and different functional modules are distributed in different gaps.

[0015] In one embodiment, the array substrate further includes:

[0016] A driving layer, wherein the pixel circuit unit is located on the driving layer, and the driving layer includes an active layer located on one side of the substrate, and a plurality of metal layers located on a side of the active layer away from the substrate;

[0017] Preferably, an insulating layer is provided between the plurality of metal layers.

[0018] In one embodiment, the multiple metal layers include a first metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked on the substrate, and the functional circuit is distributed in at least one of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer.

[0019] In one embodiment, the array substrate further includes:

[0020] a first electrode, the first electrode being located at a side of the driving layer away from the substrate;

[0021] A shielding layer, located between the first electrode and the driving layer;

[0022] Preferably, an insulating layer is provided between the first electrode and the shielding layer;

[0023] Preferably, the first electrode is an anode.

[0024] In one embodiment, the shielding layer is provided with a via hole, and the first electrode is electrically connected to the pixel circuit unit through the via hole;

[0025] Preferably, each of the pixel circuit units corresponds to one via hole.

[0026] In one embodiment, the non-display area further includes a bonding area, and the bonding area is provided with a driving module and a circuit board.

[0027] In one embodiment, the functional circuit includes at least one of a GIP circuit, an ESD circuit, a DEMUX circuit, a CT circuit, an ELVSS line, and an ELVDD line.

[0028] Based on the same inventive concept, the present application also discloses a display panel, which includes the array substrate described in any of the above embodiments.

[0029] Based on the same inventive concept, the present application also discloses a display device, which includes the above-mentioned display panel.

[0030] Compared with the prior art, the array substrate provided in the present application forms gaps between pixel circuit units and at least partially disposes the functional circuits in the gaps, thereby realizing the transfer of the functional circuits originally located in the non-display area to the display area, which is beneficial to reducing the area of ​​the non-display area and achieving a narrow border or even no border. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a schematic diagram of a related array substrate;

[0033] Figure 2 A schematic diagram of an array substrate provided in one embodiment of the present application;

[0034] Figure 3 A schematic diagram of a partial structure of an array substrate provided in one embodiment of the present application;

[0035] Figure 4 A schematic diagram of a partial structure of an array substrate provided in another embodiment of the present application;

[0036] Figure 5 A schematic diagram of a partial structure of an array substrate provided in another embodiment of the present application;

[0037] Figure 6 A schematic diagram of a partial structure of an array substrate provided in another embodiment of the present application;

[0038] Figure 7 A schematic diagram of the structure of a functional circuit in an array substrate provided in another embodiment of the present application;

[0039] Figure 8 A schematic diagram of a partial structure of an array substrate provided in another embodiment of the present application;

[0040] Fig. 9 A schematic diagram of a partial structure of an array substrate provided in another embodiment of the present application;

[0041] Fig.10 A schematic diagram of the layer structure of an array substrate provided in another embodiment of the present application;

[0042] Fig.11 A schematic diagram of the layer structure of an array substrate provided in another embodiment of the present application;

[0043] Fig.12 A circuit diagram of a pixel circuit unit provided in accordance with another embodiment of the present application.

[0044] Marking Description:

[0045] 100. Array substrate;

[0046] 1. Substrate; 11. Display area; 12. Non-display area; 121. GIP circuit; 122. ESD circuit; 123. Demux circuit; 124. Driver module; 125. ELVSS routing; 13. Bonding area;

[0047] 2. pixel circuit unit; 21. gap;

[0048] 3. Functional circuit;

[0049] 4. driving layer; 41. active layer; 42. first metal layer; 43. second metal layer; 44. third metal layer; 45. fourth metal layer;

[0050] 5. first electrode; 6. shielding layer; 61. via hole; 7. insulating layer;

[0051] 81. Input unit; 82. Output unit; 83. Pull-up unit; 84. Pull-up maintaining unit; 85. Pull-down unit; 86. Pull-down maintaining unit. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0053] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0054] OLED (Organic Light-Emitting Diode) is an active light-emitting device with a sandwich structure consisting of multiple organic layers and electrodes on both sides. At present, display screens based on AMOLED (Active-matrix organic light-emitting diode) have been commercialized in the fields of smart phones, watches and laptops.

[0055] Reference Figure 1 , is a schematic diagram of a related array substrate 100, which is suitable for an OLED display screen. The array substrate 100 includes a display area 11 and a non-display area 12. The non-display area 12 includes four frame areas. The four frame areas contain different functional circuits and wirings, resulting in a larger frame width, which cannot meet consumers' growing demand for narrow frame.

[0056] Specifically, Figure 1 In the figure, the left and right border areas include ELVSS (negative power supply) wiring 125 and multiple groups of GIP (Gate In Panel) circuits 121 and other signal wirings, resulting in a larger width of the left and right border areas; the upper border area includes ESD (Electrostatic Discharge) circuit 122 and ELVSS wiring 125, and may also include ELVDD (positive power supply) wiring and CT (Capacitance Touch) circuit, resulting in a larger width of the upper border area; the lower border area includes ELVDD circuit, Demux (demultiplexing) circuit 123, Fanout (fan-out) wiring and driving module (IC) 124, etc., resulting in a larger width of the lower border area.

[0057] Based on this, the present application provides an array substrate solution to solve the above technical problems, as detailed in the following embodiments.

[0058] Reference Figure 2 and 3 As shown, an embodiment of the present application discloses an array substrate 100, which includes: a substrate 1, a plurality of pixel circuit units 2 and a functional circuit 3, the substrate 1 includes a display area 11 and a non-display area 12, the plurality of pixel circuit units 2 are located on one side of the substrate 1 and in the display area 11, gaps 21 are formed between the pixel circuit units 2, and the functional circuit 3 is at least partially located in the gap 21.

[0059] The array substrate 100 provided in this embodiment forms a gap 21 between the pixel circuit units 2 and at least partially disposes the functional circuit 3 in the gap 21, so that the functional circuit 3 originally located in the non-display area 12 can be transferred to the display area 11, which is beneficial to reducing the area of ​​the non-display area 12 and achieving a narrow frame or even no frame.

[0060] The substrate 1 may be a rigid substrate made of materials such as glass, silicon, sapphire, etc., or a flexible substrate made of materials such as polyimide PI, etc.

[0061] Specifically, when the functional circuit 3 is partially located in the gap 21, the array substrate 100 can achieve a narrow frame, and when the functional circuit 3 is completely located in the gap 21, the array substrate 100 can achieve a borderless frame. Further, the gap 21 can be set between any two pixel circuit units 2, and different gaps 21 can be connected to form a large gap, which is not specifically limited.

[0062] In one embodiment, the functional circuit 3 includes at least one of a GIP circuit, an ESD circuit, a DEMUX circuit, a CT circuit, an ELVSS wiring, and an ELVDD wiring.

[0063] Exemplarily, the GIP circuit, ESD circuit, DEMUX circuit, ELVSS routing and ELVDD routing are all arranged in the gap 21. Exemplarily, the GIP circuit, ESD circuit, DEMUX circuit, and CT circuit are arranged in the gap 21, and the ELVSS routing and ELVDD routing are arranged in the non-display area 12. Exemplarily, the GIP circuit and ESD circuit are arranged in the gap 21, and the DEMUX circuit, CT circuit, ELVSS routing and ELVDD routing are arranged in the non-display area 12. In other embodiments, the circuit can also be split, and part of the split circuit is arranged in the gap 21, and part of the circuit is arranged in the non-display area 12. The above settings can all play a role in reducing the border width. In other embodiments, the specific setting method of the functional circuit 3 is not limited.

[0064] Among them, the adjacent gaps 21 can be set between a plurality of closely arranged pixel circuit units 2, referring to Figure 3 Further, the gap 21 may be rectangular, and the extension direction of the gap 21 may be the first direction (such as the X direction in the figure) or the second direction (such as the Y direction in the figure). At the same time, a plurality of gaps 21 may be provided, wherein the extension directions of the plurality of gaps 21 may be the same first direction, or the same second direction, or the extension direction of some gaps 21 may be the first direction, and the extension direction of some gaps may be the second direction, and the specific details are not limited.

[0065] Reference Figure 4As shown, in one embodiment, a plurality of pixel circuit units 2 are arranged along a first direction and a second direction on a substrate 1, and in the first direction, a gap 21 is formed between any two adjacent pixel circuit units 2; wherein the first direction and the second direction intersect. Specifically, the pixel circuit units 2 are still closely arranged along the second direction, and only the pixel circuit units 2 originally closely arranged along the first direction are spatially compressed to form a gap 21 between adjacent pixel circuit units 2, and the position of the light-emitting unit corresponding to each pixel circuit unit 2 can remain unchanged, thereby, the functional circuit 3 can be transferred from the non-display area 12 to the gap 21 in the display area 11. Preferably, the first direction and the second direction are perpendicular.

[0066] Reference Figure 5 As shown, in one embodiment, a plurality of pixel circuit units 2 are arranged along a first direction and a second direction on a substrate 1, and a gap 21 is formed between any two adjacent pixel circuit units 2 in the second direction; wherein the first direction and the second direction intersect. Specifically, the pixel circuit units 2 are still closely arranged along the first direction, and only the pixel circuit units 2 originally closely arranged along the second direction are spatially compressed to form a gap 21 between adjacent pixel circuit units 2.

[0067] Reference Figure 6 As shown, in one embodiment, a plurality of pixel circuit units 2 are arranged along a first direction and a second direction on a substrate 1, and a gap 21 is formed between any two adjacent pixel circuit units 2 in the first direction and the second direction; wherein the first direction and the second direction intersect. Specifically, the pixel circuit units 2 originally closely arranged along the first direction are spatially compressed, and the pixel circuit units 2 originally closely arranged along the second direction are spatially compressed, and adjacent pixel circuit units 2 form gaps 21 in the first direction and the second direction. In this embodiment, the arrangement of the pixel circuit units 2 on the array substrate 100 is more uniform, and at the same time, the arrangement of the functional circuits 3 on the array substrate 100 is also more uniform, which is conducive to improving the display effect.

[0068] In one embodiment, the functional circuit 3 includes a plurality of functional modules, and different functional modules are distributed in different gaps 21. Specifically, the functional circuit 3 is also divided according to different functions. For example, referring to Figure 7 As shown, the GIP circuit 121 can be divided into an input unit 81, an output unit 82, a pull-up unit 83, a pull-up sustaining unit 84, a pull-down unit 85, and a pull-down sustaining unit 86. The input unit 81, the output unit 82, the pull-up unit 83, the pull-up sustaining unit 84, the pull-down unit 85, and the pull-down sustaining unit 86 are distributed in different gaps 21.

[0069] Reference Figure 8As shown, in a specific embodiment, a plurality of pixel circuit units 2 are arranged along a first direction and a second direction on a substrate 1. In the first direction, a gap 21 is formed between any two adjacent pixel circuit units 2. In the second direction, the pixel circuit units 2 are closely arranged. At this time, the input unit 81, the output unit 82, the pull-up unit 83, the pull-up maintaining unit 84, the pull-down unit 85 and the pull-down maintaining unit 86 can be sequentially distributed in each gap 21 spaced along the first direction and arranged cyclically, or the order of the input unit 81, the output unit 82, the pull-up unit 83, the pull-up maintaining unit 84, the pull-down unit 85 and the pull-down maintaining unit 86 can be disrupted and distributed in each gap 21. The specific arrangement method can be set as needed and is not specifically limited.

[0070] Reference Fig. 9 As shown, in a specific embodiment, a plurality of pixel circuit units 2 are arranged along the first direction and the second direction on the substrate 1, and a gap 21 is formed between any two adjacent pixel circuit units 2 in the first direction and the second direction. At this time, the input unit 81, the output unit 82, the pull-up unit 83, the pull-up maintaining unit 84, the pull-down unit 85 and the pull-down maintaining unit 86 can be sequentially distributed in each gap 21 arranged at intervals along the first direction, and arranged cyclically. At the same time, the input unit 81, the output unit 82, the pull-up unit 83, the pull-up maintaining unit 84, the pull-down unit 85 and the pull-down maintaining unit 86 are also arranged in each gap 21 arranged at intervals along the first direction. The specific arrangement method can be set as needed and is not specifically limited.

[0071] Reference Fig.10 As shown, in one embodiment, the array substrate 100 also includes a driving layer 4, the pixel circuit unit 2 is located in the driving layer 4, and the driving layer 4 includes an active layer 41 located on one side of the substrate 1, and a plurality of metal layers located on the side of the active layer 41 away from the substrate 1. Among them, the active layer 41 can be made of semiconductor materials such as polysilicon, and a conductive channel can be formed through the semiconductor material in the active layer 41, so as to control the on and off of the current and realize precise regulation of the pixel display state. Among them, different metal layers are used to realize different routing functions. Preferably, an insulating layer is provided between the multiple metal layers, and the insulating layer can avoid short circuits due to direct contact between different metal layers, ensure that the electrical characteristics of each metal layer are not disturbed, and maintain normal circuit functions. At the same time, the signal interference between adjacent metal layers is reduced, and the display quality is improved.

[0072] In one embodiment, the multiple metal layers include a first metal layer 42, a second metal layer 43, a third metal layer 44 and a fourth metal layer 45 stacked on a substrate 1, and the functional circuit 3 is distributed in at least one of the first metal layer 42, the second metal layer 43, the third metal layer 44 and the fourth metal layer 45.

[0073] Among them, the first metal layer 42 is usually used to form the gate of the transistor in the pixel circuit unit, the first metal layer 42 and the second metal layer 43 are usually used to form the first plate and the second plate of the storage capacitor in the pixel circuit unit, the third metal layer 44 is usually used to form the source / drain, bridge wire and metal power line of the transistor, the fourth metal layer 45 is usually used to form the metal power line, and the metal power lines in the third metal layer 44 are connected into a mesh to achieve the purpose of reducing delay.

[0074] Exemplarily, the functional circuit 3 is distributed in the first metal layer 42 and the second metal layer 43 , or in the third metal layer 44 and the fourth metal layer 45 , without specific limitation.

[0075] Reference Fig.11 As shown, in one embodiment, the array substrate 100 further includes a first electrode 5 and a shielding layer 6, the first electrode 5 is located on the side of the driving layer 4 away from the substrate 1, and the shielding layer 6 is located between the first electrode 5 and the driving layer 4. Specifically, since the functional circuit 3 is arranged in the gap 21, the metal wiring in the gap 21 is relatively dense, and then when the screen is off, the dense metal wiring will reflect strong light, resulting in Mura (uneven display) problems, thereby affecting the user's experience. Therefore, a shielding layer 6 is arranged between the first electrode 5 and the driving layer 4 to block the light, thereby effectively solving the Mura problem when the screen is off. Optionally, the first electrode 5 can be an anode.

[0076] Please continue to refer to Fig.11 As shown, in one embodiment, an insulating layer 7 is provided between the first electrode 5 and the shielding layer 6. The insulating layer 7 serves to isolate the first electrode 5 from the shielding layer 6. At the same time, the insulating layer 7 also serves to flatten the first electrode 5, thereby facilitating the preparation of the first electrode 5.

[0077] Preferably, the shielding layer 6 is provided with a via hole 61, and the first electrode 5 is electrically connected to the pixel circuit unit 2 through the via hole 61, so that the pixel circuit unit 2 drives the upper light-emitting unit to emit light. Figure 3 As shown, preferably, each pixel circuit unit 2 corresponds to a via hole 61, and the shielding layer 6 is processed on the entire surface except for the via hole 61. Each pixel circuit unit 2 is electrically connected to the corresponding first electrode 5 above through a via hole 61, thereby driving the corresponding light-emitting unit above to emit light. This solution can ensure the light blocking effect without affecting signal transmission.

[0078] Please continue to refer to Figure 2As shown, in one embodiment, the non-display area 12 further includes a bonding area 13, and the bonding area 13 is provided with a driving module 124 and a circuit board, and the circuit board can be connected to the display area 11 through a fan-out line. Furthermore, a bending area is also provided between the bonding area 13 and the display area 11, and the bonding area 13 is placed on the back of the array substrate 100 by bending the bending area, thereby reducing the width of the frame (usually the lower frame) at this position, thereby achieving an extremely narrow lower frame.

[0079] In one embodiment, the pixel circuit unit 2 is a 7T1C circuit. Fig.12 As shown, a common 7T1C circuit includes 7 TFTs (Thin Film Transistor), namely T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst, T1 is a driving transistor, the control ends of T4 and T7 are electrically connected to the first scan line to receive the first scan signal SCAN1, the control ends of T5 and T6 are electrically connected to the enable control end to receive the enable control signal EM, and the control ends of T2 and T3 are electrically connected to the second scan line to receive the second scan signal SCAN2. The connection relationship is detailed in FIG. Fig.12 In other embodiments, the pixel circuit unit 2 may be a 7T2C circuit, an 8T1C circuit or other circuits, which are not specifically limited.

[0080] Another embodiment of the present application discloses a display panel, which includes the array substrate 100 in the above embodiment.

[0081] The present embodiment provides a display panel, wherein the array substrate 100 forms a gap 21 between the pixel circuit units 2 and at least partially disposes the functional circuit 3 in the gap 21, thereby enabling the functional circuit 3 originally located in the non-display area 12 to be transferred to the display area 11, which is beneficial to reducing the area of ​​the non-display area 12, achieving a narrow frame or even no frame, and is beneficial to improving the performance of the display panel.

[0082] Another embodiment of the present application discloses a display device, which includes the display panel in the above embodiment. The display device can be mounted on a smart device (such as a mobile phone, VR device, computer, TV, car display, etc.).

[0083] The display device provided in this embodiment has an array substrate 100 in its display panel, which forms a gap 21 between the pixel circuit units 2 and at least partially disposes the functional circuit 3 in the gap 21, so that the functional circuit 3 originally located in the non-display area 12 can be transferred to the display area 11, which is beneficial to reducing the area of ​​the non-display area 12, achieving a narrow frame or even no frame, and is beneficial to improving the performance of the display device.

[0084] Although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0085] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0086] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: A substrate, the substrate comprising a display area and a non-display area; A plurality of pixel circuit units, wherein the plurality of pixel circuit units are located on one side of the substrate and in the display area, and gaps are formed between the pixel circuit units; A functional circuit is at least partially located in the gap.

2. The array substrate according to claim 1, characterized in that: A plurality of the pixel circuit units are arranged on the substrate along a first direction and a second direction; In the first direction, the gap is formed between any two adjacent pixel circuit units; and / or In the second direction, the gap is formed between any two adjacent pixel circuit units; wherein the first direction and the second direction intersect; Preferably, the first direction is perpendicular to the second direction; Preferably, the functional circuit includes a plurality of functional modules, and different functional modules are distributed in different gaps.

3. The array substrate according to claim 1, characterized in that: The array substrate further includes: A driving layer, wherein the pixel circuit unit is located on the driving layer, and the driving layer includes an active layer located on one side of the substrate, and a plurality of metal layers located on a side of the active layer away from the substrate; Preferably, an insulating layer is provided between the plurality of metal layers.

4. The array substrate according to claim 3, characterized in that: The multiple metal layers include a first metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked on the substrate, and the functional circuit is distributed in at least one of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer.

5. The array substrate according to claim 3, characterized in that: The array substrate further includes: a first electrode, the first electrode being located at a side of the driving layer away from the substrate; A shielding layer, located between the first electrode and the driving layer; Preferably, an insulating layer is provided between the first electrode and the shielding layer; Preferably, the first electrode is an anode.

6. The array substrate according to claim 5, characterized in that: The shielding layer is provided with a via hole, and the first electrode is electrically connected to the pixel circuit unit through the via hole; Preferably, each of the pixel circuit units corresponds to one via hole.

7. The array substrate according to claim 1, wherein: The non-display area further includes a bonding area, and the bonding area is provided with a driving module and a circuit board.

8. The array substrate according to claim 1, wherein: The functional circuit includes at least one of a GIP circuit, an ESD circuit, a DEMUX circuit, a CT circuit, an ELVSS wiring and an ELVDD wiring.

9. A display panel, characterized in that: include: An array substrate as described in any one of claims 1 to 8.

10. A display device, characterized in that: include: The display panel as claimed in claim 9.

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