Storage and calculation integrated majority voting logic gate circuit based on ferroelectric field effect transistor

Abstract

The utility model discloses a storage and calculation integrated majority voting logic gate circuit based on ferroelectric field effect transistors. The storage and calculation integrated majority voting logic gate circuit comprises an input module, an operation module, a discharge module and an output module, the input module receives three voltage signals and transmits the three voltage signals to the operation module according to a time sequence; the operation module comprises a ferroelectric field effect transistor, formation and damage of a conducting channel of the ferroelectric field effect transistor are directionally changed according to voltage signals received by a grid electrode and a source electrode, a nonvolatile operation relation with an external voltage signal as input and on-off of an internal channel as output is established, a logic input variable form is unified, and majority voting logic operation is executed. The discharging module adjusts a voltage signal of the operation module in a reading stage to prevent misreading; the output module accurately reads a nonvolatile operation result as a voltage signal; the circuit has the advantages that the storable majority voting logic function can be realized with a small number of transistors, the logic input variable form is unified, and the operation cascading capability and the circuit expandability are improved.

Description

Technical Field

[0001] The utility model belongs to the field of digital circuits, and relates to a storage-computation integrated logic gate circuit design technology, and in particular to a storage-computation integrated majority voting logic gate circuit based on a ferroelectric field-effect transistor (FeFET). Background Art

[0002] In digital integrated circuits, basic arithmetic units such as adders and multipliers are responsible for performing a large number of data accumulation operations. In these arithmetic circuits, majority voting logic gates are important components. The majority voting logic gate has three input ports. When more than half of the input values ​​are true, the output is true. This "majority voting" feature enables it to complete the summation of three values. Therefore, the efficient implementation of majority voting logic gates has become an important direction for optimizing the performance of arithmetic circuits.

[0003] In recent years, with the rapid development of big data and artificial intelligence technology, the demand for computing power is growing at an unprecedented rate. When the traditional von Neumann computing architecture faces problems such as "power consumption wall" and "storage wall" due to "separation of storage and computing", the Computation in Memory (CiM) architecture uses the idea of ​​integrating computing functions directly into the memory, which has become one of the effective ways to reduce data transfer energy consumption and significantly improve computing efficiency.

[0004] The realization of a storage-computing integrated architecture requires the support of specific non-volatile storage media. Non-volatile memory, that is, data stored will not be lost when the power is off, includes traditional flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), and ferroelectric field effect transistors (FeFET). Among these non-volatile memories, ferroelectric field effect transistors have received special attention due to their low power consumption, high switching ratio, and compatibility with existing CMOS processes.

[0005] In addition, in the design of logic circuits based on ferroelectric field effect transistors, their non-volatile switch states are usually regarded as internal inputs, and volatile gate voltage signals are regarded as external inputs, that is, two different physical quantities are equivalent to the same logic input variables for two-input logic operations. Since the physical representation of the logic input variables is different and incompatible with traditional CMOS circuits, additional conversion circuits are required to realize the operation cascade, which not only increases the complexity of circuit design but also limits the realization of the storage and calculation integrated majority voting logic gate, restricting the application of ferroelectric field effect transistors in arithmetic circuits with "high-speed computing" as the requirement.

[0006] How to use ferroelectric field effect transistors to construct integrated storage and computing arithmetic circuits, overcome the dependence on conversion circuits while ensuring the correctness of logical functions, and efficiently realize the majority voting logic gate function is a key issue related to the performance optimization and practical development of integrated storage and computing arithmetic circuits. Summary of the invention

[0007] The technical problem to be solved by the utility model is that, in view of the problems in the existing storage-computation integrated circuit design, such as the non-uniform physical form of the logic input variables, the reliance on the conversion circuit to realize the operation cascade, the inability to efficiently realize the majority logic voting function, and the low calculation efficiency of the arithmetic circuit, a storage-computation integrated majority voting logic gate circuit based on the ferroelectric field effect transistor is provided, taking the ferroelectric field effect transistor as an example. The utility model utilizes the calculation ability of the gate and source of the ferroelectric field effect transistor for independent input, unifies the physical form of the logic input variables; and realizes the storage-computation integrated majority voting logic operation by time division multiplexing, reduces the number of transistors, and improves the calculation efficiency of the arithmetic circuit.

[0008] The technical solution adopted by the utility model to solve the above-mentioned technical problems is: a storage and calculation integrated majority voting logic gate circuit based on ferroelectric field effect transistors, characterized in that: it includes an input module, an operation module, a discharge module, and an output module; the input module receives voltage signals from three data signal input terminals, and transmits the voltage signals to the operation module in two ways according to the time sequence; the operation module includes a ferroelectric field effect transistor, whose gate and source respectively receive two voltage signals from the input module, and is used to realize non-volatile on-off conversion of the signal path according to the voltage signals received by its gate and source, so as to perform storage and calculation integrated majority voting logic operations; the discharge module adjusts the voltage signal input to the operation module during the readout stage to prevent misreading of the operation result output by the operation module during the readout stage; the output module reads the operation result of the operation module and outputs it.

[0009] It is further defined that the input module has three data signal input terminals, one data selection control input terminal, one input control input terminal and two output terminals, the operation module has two signal input terminals and one output terminal, the discharge module has two signal input terminals, one output control input terminal and one ground output terminal, and the output module has one signal input terminal, one power input terminal, one output control input terminal and one logic gate output terminal; the first output terminal of the input module is respectively connected to the first signal input terminal of the operation module and the discharge module, the second output terminal of the input module is respectively connected to the second signal input terminal of the operation module and the discharge module, the output terminal of the operation module is connected to the signal input terminal of the output module, the ground output terminal of the discharge module is grounded, and the power input terminal of the output module is connected to the power supply. Here, the input and output configurations of each module are defined, so that the circuit is more modularized and convenient for circuit integration and expansion; and through the specific connection relationship, the effective transmission and processing of the voltage signal in the circuit is ensured.

[0010] Specifically, the input module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first inverter, a first PMOS transistor, and a second PMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the first data signal input terminal of the input module, the source of the first NMOS transistor is connected to the second data signal input terminal of the input module, the source of the second NMOS transistor is connected to the third data signal input terminal of the input module, and the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor are connected to the first data signal input terminal of the input module. The gates of the first PMOS transistor and the first NMOS transistor are respectively connected to the data selection control input terminal of the input module, the drain of the first PMOS transistor and the drain of the first NMOS transistor are respectively connected to the source of the third NMOS transistor, the drain of the second PMOS transistor and the drain of the second NMOS transistor are respectively connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the source of the fourth NMOS transistor, the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are respectively connected to the input control input terminal of the input module, the drain of the third NMOS transistor is connected to the first output terminal of the input module, and the drain of the fourth NMOS transistor is connected to the second output terminal of the input module. Here, the composition and connection relationship of the input module are specifically given, and the receiving and transmitting process of the voltage signal is optimized.

[0011] Specifically, the gate of the ferroelectric field effect transistor is connected to the first signal input terminal of the operation module, the source of the ferroelectric field effect transistor is connected to the second signal input terminal of the operation module, and the drain of the ferroelectric field effect transistor is connected to the output terminal of the operation module. Here, the connection mode of the ferroelectric field effect transistor in the operation module is defined, so that the ferroelectric field effect transistor can change the formation and destruction of its conductive channel according to the voltage signal received by its gate and source, establish a non-volatile operation relationship with an external voltage signal as input and an internal channel on and off as output, unify the physical form of the logical input variable, overcome the dependence on the conversion circuit, and improve the operation accuracy.

[0012] Specifically, the discharge module includes a fifth NMOS transistor and a sixth NMOS transistor, the drain of the fifth NMOS transistor is connected to the first signal input terminal of the discharge module, the drain of the sixth NMOS transistor is connected to the second signal input terminal of the discharge module, the gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor are respectively connected to the output control input terminal of the discharge module, and the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are respectively connected to the ground output terminal of the discharge module. Here, the specific composition and connection relationship of the discharge module are specifically given, the input voltage signal of the operation module in the readout stage is optimized, misreading is prevented, and the accuracy and reliability of data are improved.

[0013] Specifically, the output module includes a seventh NMOS transistor, a third PMOS transistor, and a second inverter, the source of the seventh NMOS transistor is connected to the signal input terminal of the output module, the drain of the third PMOS transistor is connected to the power input terminal of the output module, the gate of the seventh NMOS transistor and the gate of the third PMOS transistor are respectively connected to the output control input terminal of the output module, the drain of the seventh NMOS transistor and the source of the third PMOS transistor are respectively connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the logic gate output terminal of the output module. Here, the composition and connection relationship of the output module are specifically given, which realizes the accurate reading of the non-volatile operation result as a voltage signal, and creates high-speed calculation conditions for logic cascading without the need for a conversion circuit.

[0014] Preferably, the ferroelectric field effect transistor is an N-type ferroelectric field effect transistor, the gate and source of the ferroelectric field effect transistor can be independently used as external voltage signal input terminals, and the formation and destruction of the conductive channel between the source and the drain can be controlled according to the voltage difference between the gate and the source; the ferroelectric field effect transistor can apply a forward bias voltage greater than a threshold value V between the gate and the source THWhen the gate and source voltages are removed, a conductive channel is formed between the source and the drain, and the "on" state is maintained, and the state is retained after the gate and source voltages are removed; the ferroelectric field effect transistor can apply a reverse bias voltage greater than the threshold value V between the gate and the source TL When the gate and source voltages are removed, the conductive channel between the source and drain is destroyed, and the "off" state is maintained. This state is retained even after the gate and source voltages are removed. Ferroelectric field effect transistors can treat the gate and source as logic input terminals, and realize different switching states under different voltage conditions at both ends, which is equivalent to improving the logic operation capability. By treating the switching state as the result of the logic operation, the real-time storage of the operation result is realized.

[0015] Compared with the prior art, the advantages of the utility model are:

[0016] The input module in the circuit of the utility model realizes the time-sharing input of the voltage signal, realizes the majority voting operation based on three external voltage signals, and the operation result is stored in the ferroelectric field effect transistor in situ. Compared with the CMOS majority voting logic gate without storage function, 10 PMOS transistors and 10 NMOS transistors are required to realize the same operation function, and at least two inverters are required to form an interlocking unit to realize the effective storage of the operation result. If the CMOS majority voting logic gate is directly used to realize the digital logic circuit design, an arithmetic circuit including k majority voting logic gates requires 10k NMOS transistors, 10k PMOS transistors and 2k inverters, but if the circuit of the utility model is used, only 7k NMOS transistors, 3k PMOS transistors, k ferroelectric field effect transistors and 2k inverters are needed. When k is larger, the number of transistors used by the circuit of the utility model is more saved, and the area of ​​the arithmetic circuit involved is more saved.

[0017] In addition, compared with the existing storage-computation integrated circuit design constructed with ferroelectric field effect transistors, the present invention completely uses external voltage signals in the same voltage range as logic input variables, and the logic operation results can also be read out as output signals in the same voltage range for cascade transmission. Therefore, the problem of inconsistent physical forms and difficulty in realizing operation cascade in the existing storage-computation integrated circuit design using internal switch states and external voltage signals as logic input variables is overcome, the conversion process required for collaborative calculation of multiple voltages and physical quantities is reduced, the calculation complexity is reduced, and the calculation efficiency is optimized.

[0018] In summary, the utility model uses the gate and source of the ferroelectric field effect transistor as independent operation input terminals, and uses time-division multiplexing to realize the majority voting logic gate function of three external voltage signals. It not only realizes the storable majority voting logic function with a smaller number of transistors, but also unifies the physical form of the logic input variables. It can realize operation cascading without additional conversion circuits, improves the operation cascading capability and circuit scalability, and optimizes the computational efficiency of the storage and calculation integrated arithmetic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of an N-type ferroelectric field effect transistor;

[0020] Figure 2 is a schematic diagram of an NMOS transistor;

[0021] Figure 3 is a schematic diagram of a PMOS transistor;

[0022] Figure 4 is a schematic diagram of an inverter;

[0023] Figure 5 It is a schematic diagram of a majority voting logic gate circuit based on ferroelectric field effect transistors and storing and computing in one according to the utility model;

[0024] Figure 6 for Figure 5 Timing simulation results of the storage-computation-in-one majority voting logic gate circuit. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present utility model clearer, the technical solution in the embodiments of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings in the examples of the present utility model.

[0026] The utility model proposes a storage-computation integrated majority voting logic gate circuit based on ferroelectric field effect transistors, which utilizes N-type ferroelectric field effect transistors, NMOS transistors, PMOS transistors and inverters to realize the storage-computation integrated majority voting logic gate circuit. The summation operation can be realized by cascading the storage-computation integrated majority voting logic gate circuit based on ferroelectric field effect transistors.

[0027] Figure 1 A schematic diagram of an N-type ferroelectric field effect transistor is given, where the g terminal is the gate of the N-type ferroelectric field effect transistor, the s terminal is the source of the N-type ferroelectric field effect transistor, and the d terminal is the drain of the N-type ferroelectric field effect transistor. When a forward bias voltage is applied between the g terminal and the s terminal of the N-type ferroelectric field effect transistor, and the forward bias voltage is greater than the threshold V THWhen a reverse bias voltage is applied between the g and s terminals of the N-type ferroelectric field effect transistor, and the reverse bias voltage is greater than the threshold V TL When , the conductive channel between the source and drain of the N-type ferroelectric field effect transistor disappears, making the N-type ferroelectric field effect transistor in an "off" state, and this state remains after the voltages at the g and s terminals are removed.

[0028] Figure 2 A schematic diagram of an NMOS transistor is given, where g N The terminal is the gate of the NMOS transistor, s N The end is the source of the NMOS transistor, d N The terminal is the drain of the NMOS transistor. The on-off state of the NMOS transistor depends on the gate g N The voltage applied. N The voltage applied to the terminal is greater than its threshold voltage V thn When N end and d N A conductive channel is formed between the two terminals, and the NMOS transistor is in the "on" state; when g N The voltage applied to the terminal is less than its threshold voltage V thn When N end and d N The conductive channel between the terminals disappears and the NMOS transistor is in the "off" state.

[0029] Figure 3 A schematic diagram of a PMOS transistor is given, where g P The end is the gate of the PMOS transistor, s P The end is the source of the PMOS transistor, d P The end is the drain of the PMOS transistor. The on-off state of the PMOS transistor depends on the gate g P The voltage applied. P End and s P The voltage applied between the terminals is less than its threshold voltage V thp When P end and d P A conductive channel is formed between the two ends, and the PMOS transistor is in the "on" state; when g P End and s P The voltage applied between the terminals is greater than its threshold voltage V thp When P end and d P The conductive channel between the terminals disappears and the PMOS transistor is in the "off" state.

[0030] Figure 4 A schematic diagram of an inverter is given, in which the in terminal is the input terminal and the out terminal is the output terminal. When a high-level voltage is input to the input terminal, the output terminal of the inverter outputs a low-level voltage; conversely, when a low-level voltage is input to the input terminal, the output terminal of the inverter outputs a high-level voltage.

[0031] This embodiment proposes a storage and calculation integrated majority voting logic gate circuit based on ferroelectric field effect transistors, such as Figure 5 As shown, it includes an input module 1, an operation module 2, a discharge module 3, and an output module 4; the input module 1 receives voltage signals from three data signal input terminals a, b, and c, and transmits the voltage signals to the operation module 2 in two paths according to a time sequence; the operation module 2 includes a ferroelectric field effect transistor Fe1, whose gate and source respectively receive two voltage signals from the input module 1, and is used to realize non-volatile on-off switching of the signal path according to the voltage signals received by its gate and source, so as to perform a majority voting logic operation of storage and calculation; the discharge module 3 adjusts the voltage signal input to the operation module 2 during the readout stage to prevent misreading of the operation result output by the operation module 2 during the readout stage; the output module 4 reads the operation result of the operation module 2 and outputs it.

[0032] It is further defined that the input module 1 has three data signal input terminals, namely the first data signal input terminal a, the second data signal input terminal b, and the third data signal input terminal c, a data selection control input terminal SL, an input control input terminal WL, and two output terminals, namely the first output terminal and the second output terminal; the operation module 2 has two signal input terminals, namely the first signal input terminal and the second signal input terminal, and an output terminal; the discharge module 3 has two signal input terminals, namely the first signal input terminal and the second signal input terminal, an output control input terminal RL and a ground output terminal; the output module 4 has a signal input terminal, a power input terminal, an output control input terminal RL and a logic gate output terminal f. The first output terminal of the input module 1 is connected to the first signal input terminal of the operation module 2 and the discharge module 3, respectively; the second output terminal of the input module 1 is connected to the second signal input terminal of the operation module 2 and the discharge module 3, respectively; the output terminal of the operation module 2 is connected to the signal input terminal of the output module 4, the ground output terminal of the discharge module 3 is grounded, and the power input terminal of the output module 4 is connected to the power supply V dd The three data signal input terminals a, b, and c of the input module 1 are the three input terminals of the storage-computation integrated majority voting logic gate circuit, and the logic gate output terminal f of the output module 4 is the output terminal of the storage-computation integrated majority voting logic gate circuit. Here, the input and output configurations of each module are defined, making the circuit more modular and convenient for circuit integration and expansion; and through the specific connection relationship, the effective transmission and processing of the voltage signal in the circuit is ensured.

[0033] Specifically, the input module 1 includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first inverter INV1, a first PMOS transistor P1, and a second PMOS transistor P2. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are respectively connected to the first data signal input terminal a of the input module 1, the source of the first NMOS transistor N1 is connected to the second data signal input terminal b of the input module 1, the source of the second NMOS transistor N2 is connected to the third data signal input terminal c of the input module 1, and the gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2, the gate of the first NMOS transistor N1, and the gate of the second NMOS transistor P2 are connected to the third data signal input terminal c of the input module 1. The gate of transistor N2 is respectively connected to the data selection control input terminal SL of input module 1, the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 are respectively connected to the source of the third NMOS transistor N3, the drain of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 are respectively connected to the input terminal of the first inverter INV1, the output terminal of the first inverter INV1 is connected to the source of the fourth NMOS transistor N4, the gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4 are respectively connected to the input control input terminal WL of input module 1, the drain of the third NMOS transistor N3 is connected to the first output terminal of input module 1, and the drain of the fourth NMOS transistor N4 is connected to the second output terminal of input module 1. Here, the composition and connection relationship of the input module 1 are specifically given, and the receiving and transmitting process of the voltage signal is optimized.

[0034] Specifically, the gate of the ferroelectric field effect transistor Fe1 is connected to the first signal input terminal of the operation module 2, the source of the ferroelectric field effect transistor Fe1 is connected to the second signal input terminal of the operation module 2, and the drain of the ferroelectric field effect transistor Fe1 is connected to the output terminal of the operation module 2. Here, the connection mode of the ferroelectric field effect transistor Fe1 in the operation module 2 is defined, so that the ferroelectric field effect transistor Fe1 can change the formation and destruction of its conductive channel according to the voltage signal received by its gate and source, establish a non-volatile operation relationship with an external voltage signal as input and an internal channel on-off as output, unify the physical form of the logical input variable, overcome the dependence on the conversion circuit, and improve the operation accuracy.

[0035] Specifically, the discharge module 3 includes a fifth NMOS transistor N5 and a sixth NMOS transistor N6, the drain of the fifth NMOS transistor N5 is connected to the first signal input terminal of the discharge module 3, the drain of the sixth NMOS transistor N6 is connected to the second signal input terminal of the discharge module 3, the gate of the fifth NMOS transistor N5 and the gate of the sixth NMOS transistor N6 are respectively connected to the output control input terminal RL of the discharge module 3, the source of the fifth NMOS transistor N5 and the source of the sixth NMOS transistor N6 are respectively connected to the ground output terminal of the discharge module 3, that is, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 share the output control input terminal RL and the ground output terminal of the discharge module 3. Here, the specific composition and connection relationship of the discharge module 3 are specifically given, the input terminal voltage signal of the operation module 2 in the readout stage is optimized, misreading is prevented, and the accuracy and reliability of data are improved.

[0036] Specifically, the output module 4 includes a seventh NMOS transistor N7, a third PMOS transistor P3, and a second inverter INV2. The source of the seventh NMOS transistor N7 is connected to the signal input terminal of the output module 4, the drain of the third PMOS transistor P3 is connected to the power input terminal of the output module 4, the gate of the seventh NMOS transistor N7 and the gate of the third PMOS transistor P3 are respectively connected to the output control input terminal RL of the output module 4, the drain of the seventh NMOS transistor N7 and the source of the third PMOS transistor P3 are respectively connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the logic gate output terminal f of the output module 4. Here, the composition and connection relationship of the output module 4 are specifically given, which realizes the accurate reading of the non-volatile operation result as a voltage signal, and creates high-speed calculation conditions without conversion circuits for the cascading and expansion of logical operations.

[0037] Preferably, the ferroelectric field effect transistor Fe1 uses an N-type ferroelectric field effect transistor, and the gate and source of the ferroelectric field effect transistor Fe1 can be independently used as external voltage signal input terminals, and the formation and destruction of the conductive channel between the source and the drain can be controlled according to the voltage difference between the gate and the source. The ferroelectric field effect transistor Fe1 can regard the gate and the source as logic input terminals, and realize different switching states under different voltage conditions at both ends, which is equivalent to improving the logic operation capability, and regards the switch state as the result of the logic operation, thereby realizing the real-time storage of the operation result.

[0038] To further illustrate the feasibility of the utility model based on the storage and calculation integrated majority voting logic gate circuit, Figure 5 The simulation experiment is carried out based on the storage and computing integrated majority voting logic gate circuit shown.

[0039] In the simulation experiment, "0" is used to represent a logic low level voltage signal, and "1" is used to represent a logic high level voltage signal. Figure 6 Yes Figure 5 The simulation results of the storage and computing integrated majority voting logic gate circuit are shown, wherein the voltage signals sequentially input at the first data signal input terminal a are {0, 0, 0, 0, 1, 1, 1, 1}, the voltage signals sequentially input at the second data signal input terminal b are {0, 0, 1, 1, 0, 0, 1, 1}, and the voltage signals sequentially input at the third data signal input terminal c are {0, 1, 0, 1, 0, 1, 0, 1}.

[0040] Figure 6 In the first cycle L1, at the moment T1, the data selection control input terminal SL inputs a low level, and the signal {0} of the first data signal input terminal a is transmitted to the source of the third NMOS transistor N3 and the input terminal of the first inverter INV1. At this time, the output control input terminal RL inputs a low level, and the corresponding input control input terminal WL inputs a high level. The signal {0} is applied to the gate of the ferroelectric field effect transistor Fe1. The signal {0} is inverted by the first inverter INV1 and converted to {1} and applied to the source of the ferroelectric field effect transistor Fe1, so that its gate and source voltages are reversed, so the ferroelectric field effect transistor Fe1 is in the off state. At time T2, the data selection control input terminal SL inputs a high level, the signal {0} of the second data signal input terminal b is transmitted to the source of the third NMOS transistor N3, and the signal {0} of the third data signal input terminal c is transmitted to the input terminal of the first inverter INV1. At this time, the input control input terminal WL is effective at a high level, the voltage difference between the gate and the source of the ferroelectric field effect transistor Fe1 remains unchanged, and the ferroelectric field effect transistor Fe1 remains in the off state. At time T1-T2, the output control input terminal RL inputs a low level, the third PMOS transistor P3 is turned on, and the input terminal of the second inverter INV2 is connected to the power supply V dd Charging, the seventh NMOS transistor N7 is disconnected. At time T3, the input control input terminal WL is low level, the output control input terminal RL is high level, the third NMOS transistor N3 is disconnected from the gate of the ferroelectric field effect transistor Fe1, the fourth NMOS transistor N4 is disconnected from the source of the ferroelectric field effect transistor Fe1, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are both turned on, forming a connection between the gate and source of the ferroelectric field effect transistor Fe1 to the ground, the seventh NMOS transistor N7 is turned on, and the third PMOS transistor P3 is turned off, forming a path from the drain of the ferroelectric field effect transistor Fe1 to the input terminal of the second inverter INV2. Because the ferroelectric field effect transistor Fe1 is disconnected, the input signal of the second inverter INV2 remains unchanged, and the output maintains a low level, that is, the value of the logic gate output terminal f is "0".

[0041] At the moment T1 of the fourth cycle L4, the data selection control input terminal SL inputs a low level, and the signal {0} of the first data signal input terminal a is transmitted to the source of the third NMOS transistor N3 and the input terminal of the first inverter INV1. At this time, the output control input terminal RL inputs a low level, and the corresponding input control input terminal WL inputs a high level. The signal {0} is applied to the gate of the ferroelectric field effect transistor Fe1. The signal {0} is inverted by the first inverter INV1 and converted to {1} and applied to the source of the ferroelectric field effect transistor Fe1, so that its gate and source voltages are reversed, so the ferroelectric field effect transistor Fe1 is in the off state. At the moment T2, the data selection control input terminal SL is a high level, the signal {1} ​​of the second data signal input terminal b is transmitted to the source of the third NMOS transistor N3, and the signal {1} ​​of the third data signal input terminal c is transmitted to the input terminal of the first inverter INV1. After inversion, the first inverter INV1 outputs the signal {0}. At this time, the input control input terminal WL is high level and effective, the voltage of the gate and source of the ferroelectric field effect transistor Fe1 is changed to forward bias, and the ferroelectric field effect transistor Fe1 is changed to the on state. At the time T1-T2, the output control input terminal RL is low level, the third PMOS transistor P3 is turned on, and the input terminal of the second inverter INV2 is connected to the power supply V dd Charging, the seventh NMOS transistor N7 is disconnected. At time T3, the input control input terminal WL is low level, the output control input terminal RL is high level, the third NMOS transistor N3 is disconnected from the gate of the ferroelectric field effect transistor Fe1, the fourth NMOS transistor N4 is disconnected from the source of the ferroelectric field effect transistor Fe1, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are turned on, forming a connection between the gate and source of the ferroelectric field effect transistor Fe1 and the ground, the seventh NMOS transistor N7 is turned on, and the third PMOS transistor P3 is turned off, forming a path from the drain of the ferroelectric field effect transistor Fe1 to the input terminal of the second inverter INV2. Because the ferroelectric field effect transistor Fe1 is turned on, the input signal of the second inverter INV2 is pulled down to a low level, and the output becomes a high level, that is, the value of the logic gate output terminal f is "1".

[0042] At the moment T1 of the fifth cycle L5, the data selection control input terminal SL inputs a low level, and the signal {1} ​​of the first data signal input terminal a is transmitted to the source of the third NMOS transistor N3 and the input terminal of the first inverter INV1. At this time, the output control input terminal RL inputs a low level, and the corresponding input control input terminal WL inputs a high level. The signal {1} ​​is applied to the gate of the ferroelectric field effect transistor Fe1. The signal {1} ​​is inverted by the first inverter INV1 and converted to {0} and applied to the source of the ferroelectric field effect transistor Fe1, so that its gate and source voltages are forward biased, so the ferroelectric field effect transistor Fe1 is in the on state. At the moment T2, the data selection control input terminal SL is a high level, the signal {0} of the second data signal input terminal b is transmitted to the source of the third NMOS transistor N3, and the signal {0} of the third data signal input terminal c is transmitted to the input terminal of the first inverter INV1. After inversion, the first inverter INV1 outputs the signal {1}. At this time, the input control input terminal WL is high level and effective, the voltage of the gate and source of the ferroelectric field effect transistor Fe1 is changed to reverse bias, and the ferroelectric field effect transistor Fe1 is changed to the off state. At the time T1-T2, the output control input terminal RL is low level, the third PMOS transistor P3 is turned on, and the input terminal of the second inverter INV2 is connected to the power supply V dd Charging, the seventh NMOS transistor N7 is disconnected. At time T3, the input control input terminal WL is low level, the output control input terminal RL is high level, the third NMOS transistor N3 is disconnected from the gate of the ferroelectric field effect transistor Fe1, the fourth NMOS transistor N4 is disconnected from the source of the ferroelectric field effect transistor Fe1, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are turned on, forming a connection between the gate and source of the ferroelectric field effect transistor Fe1 and the ground, the seventh NMOS transistor N7 is turned on, and the third PMOS transistor P3 is turned off, forming a path from the drain of the ferroelectric field effect transistor Fe1 to the input terminal of the second inverter INV2. Because the ferroelectric field effect transistor Fe1 is disconnected, the input signal of the second inverter INV2 remains unchanged, and the output maintains a low level, that is, the value of the logic gate output terminal f is "0".

Claims

1. A storage and calculation integrated majority voting logic gate circuit based on ferroelectric field effect transistors, characterized in that: It includes an input module, an operation module, a discharge module, and an output module; the input module receives voltage signals from three data signal input terminals, and transmits the voltage signals to the operation module in two paths according to a time sequence; the operation module includes a ferroelectric field effect transistor, whose gate and source respectively receive two voltage signals from the input module, and is used to realize non-volatile on-off switching of the signal path according to the voltage signals received by its gate and source, so as to perform a majority voting logic operation of storage and calculation; the discharge module adjusts the voltage signal input to the operation module in the readout stage to prevent misreading of the operation result output by the operation module in the readout stage; the output module reads the operation result of the operation module and outputs it.

2. The storage-computation-integrated majority voting logic gate circuit based on ferroelectric field effect transistors according to claim 1 is characterized in that: The input module has three data signal input terminals, one data selection control input terminal, one input control input terminal and two output terminals, the operation module has two signal input terminals and one output terminal, the discharge module has two signal input terminals, one output control input terminal and one ground output terminal, and the output module has one signal input terminal, one power input terminal, one output control input terminal and one logic gate output terminal; the first output terminal of the input module is respectively connected to the first signal input terminal of the operation module and the discharge module, the second output terminal of the input module is respectively connected to the second signal input terminal of the operation module and the discharge module, the output terminal of the operation module is connected to the signal input terminal of the output module, the ground output terminal of the discharge module is grounded, and the power input terminal of the output module is connected to the power supply.

3. The storage-computation-in-one majority voting logic gate circuit based on ferroelectric field effect transistors according to claim 2 is characterized in that: The input module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first inverter, a first PMOS transistor, and a second PMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the first data signal input terminal of the input module, the source of the first NMOS transistor is connected to the second data signal input terminal of the input module, the source of the second NMOS transistor is connected to the third data signal input terminal of the input module, and the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor are respectively connected to the first data signal input terminal of the input module. The first PMOS transistor and the first NMOS transistor are respectively connected to the data selection control input terminal of the input module, the drain of the first PMOS transistor and the drain of the first NMOS transistor are respectively connected to the source of the third NMOS transistor, the drain of the second PMOS transistor and the drain of the second NMOS transistor are respectively connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the source of the fourth NMOS transistor, the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are respectively connected to the input control input terminal of the input module, the drain of the third NMOS transistor is connected to the first output terminal of the input module, and the drain of the fourth NMOS transistor is connected to the second output terminal of the input module.

4. The storage-computation-integrated majority voting logic gate circuit based on ferroelectric field effect transistors according to claim 2 or 3, characterized in that: The gate of the ferroelectric field effect transistor is connected to the first signal input terminal of the operation module, the source of the ferroelectric field effect transistor is connected to the second signal input terminal of the operation module, and the drain of the ferroelectric field effect transistor is connected to the output terminal of the operation module.

5. The storage-computation-integrated majority voting logic gate circuit based on ferroelectric field effect transistors according to claim 4 is characterized in that: The discharge module includes a fifth NMOS transistor and a sixth NMOS transistor, the drain of the fifth NMOS transistor is connected to the first signal input terminal of the discharge module, the drain of the sixth NMOS transistor is connected to the second signal input terminal of the discharge module, the gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor are respectively connected to the output control input terminal of the discharge module, and the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are respectively connected to the ground output terminal of the discharge module.

6. The storage-computation-integrated majority voting logic gate circuit based on ferroelectric field effect transistors according to claim 5, characterized in that: The output module includes a seventh NMOS transistor, a third PMOS transistor, and a second inverter, wherein the source of the seventh NMOS transistor is connected to the signal input terminal of the output module, the drain of the third PMOS transistor is connected to the power input terminal of the output module, the gate of the seventh NMOS transistor and the gate of the third PMOS transistor are respectively connected to the output control input terminal of the output module, the drain of the seventh NMOS transistor and the source of the third PMOS transistor are respectively connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the logic gate output terminal of the output module.

7. The storage-computation-integrated majority voting logic gate circuit based on ferroelectric field effect transistors according to claim 2, characterized in that: The ferroelectric field effect transistor is an N-type ferroelectric field effect transistor.

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