Semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor device and a preparation method thereof, which are used for avoiding short circuit of a magnetic tunnel junction. The semiconductor device at least comprises a spin orbit moment layer, a magnetic tunnel junction and a redeposit insulating layer covering the side wall of the magnetic tunnel junction, wherein the free layer of the magnetic tunnel junction is adjacent to the spin orbit moment layer; an initial magnetic tunnel junction, an initial redeposit layer deposited on the side wall of the initial magnetic tunnel junction and a dielectric layer are synchronously etched to form the magnetic tunnel junction, and a redeposit insulating layer is formed on the side wall of the magnetic tunnel junction through reverse sputtering; in the redeposit insulating layer, the proportion of the components of the dielectric layer is larger than the sum of the proportion of the components of the initial magnetic tunnel junction and the proportion of the components of the initial redeposit layer, so that the redeposit insulating layer is insulated. According to the semiconductor device, the conductive initial redeposit layer is eliminated, and the insulated redeposit insulating layer is formed, so that short circuit of the magnetic tunnel junction is avoided, and the yield of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, for example, to semiconductor devices and methods for manufacturing the same. Background Art

[0002] At present, with the continuous development of magnetoresistive random access memory, MRAM technology has undergone three generations of changes. Among them, the third-generation magnetic memory, spin-orbit torque magnetic random access memory (SOT-MRAM), usually includes a spin-orbit moment layer and a magnetic tunnel junction (MTJ) set on the spin-orbit moment layer. In the preparation process of SOT-MRAM, how to produce a small-sized magnetic tunnel junction is a problem that needs to be solved urgently.

[0003] The related art discloses a method for manufacturing a small-sized magnetic random access memory, which comprises setting a sacrificial layer on a metal mask layer, opening an opening on the sacrificial layer to fill a second hard mask layer, and then etching a second hard mask cylinder to form a lattice pattern, thereby realizing the manufacture of a small-sized magnetic tunnel junction.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art: In the process of etching to form a magnetic tunnel junction, it is inevitable that a redeposited layer will be formed by back sputtering on the side wall of the magnetic tunnel junction. The redeposited layer will cause the magnetic tunnel junction to short-circuit, affecting the yield of the semiconductor device.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, so as to remove an initial redeposited layer covering the sidewall of a magnetic tunnel junction, thereby avoiding a short circuit of the magnetic tunnel junction and improving the yield of the semiconductor device.

[0008] In some embodiments, a semiconductor device comprises at least a spin-orbit moment layer, a magnetic tunnel junction, and a redeposited insulating layer covering the side wall of the magnetic tunnel junction, which are stacked in sequence; wherein the free layer of the magnetic tunnel junction is arranged adjacent to the spin-orbit moment layer; a magnetic tunnel junction is formed by synchronously etching an initial magnetic tunnel junction, an initial redeposited layer and a dielectric layer deposited on the side wall of the initial magnetic tunnel junction, and a redeposited insulating layer is formed by back sputtering on the side wall of the magnetic tunnel junction; in the redeposited insulating layer, the proportion of the dielectric layer component is greater than the sum of the proportion of the initial magnetic tunnel junction component and the proportion of the initial redeposited layer component, so that the redeposited insulating layer is insulated.

[0009] Optionally, the semiconductor device further includes a mask layer disposed above the magnetic tunnel junction.

[0010] The semiconductor device provided by the embodiments of the present disclosure can achieve the following technical effects: In the process of forming the initial magnetic tunnel junction by the initial etching, the conductive initial redeposition layer is deposited on the side wall of the initial magnetic tunnel junction, and the dielectric layer is first deposited and covered on the side wall of the initial redeposition layer. At this time, the magnetic tunnel junction is formed by synchronously etching the initial magnetic tunnel junction, the initial redeposition layer and the dielectric layer. At this time, the redeposition insulating layer formed by reverse sputtering on the side wall of the magnetic tunnel junction includes the dielectric layer component, the initial redeposition layer component and the initial magnetic tunnel junction component that are reversely sputtered to the side wall of the magnetic tunnel junction. Since the proportion of the insulating dielectric layer component is greater than the sum of the proportion of the initial magnetic tunnel junction component and the proportion of the initial redeposition layer component, the redeposition insulating layer exhibits insulating characteristics. In this way, on the one hand, the conductive initial redeposition layer is eliminated, and an insulating redeposition insulating layer is formed, thereby avoiding a short circuit of the magnetic tunnel junction. On the other hand, the redeposition insulating layer covers the side wall of the magnetic tunnel junction, providing a protective function for the magnetic tunnel junction, which is conducive to improving the stability of the magnetic tunnel junction. On the other hand, since the size of the magnetic tunnel junction is smaller than the initial magnetic tunnel junction, the size of the magnetic tunnel junction and the semiconductor device is reduced, the flip efficiency is improved, and the power consumption is reduced. In addition, when the size of the magnetic tunnel junction decreases, the surface magnetic anisotropy increases, the multi-domain structure gradually changes into a single domain, and the magnetization direction tends to be unified, thereby improving the performance of the magnetic tunnel junction and the coercive force Hc of the semiconductor device.

[0011] In some embodiments, a method for preparing a semiconductor device includes at least the following steps: etching above a spin-orbit moment layer to form an initial magnetic tunnel junction and an initial redeposited layer sputtered on the side wall of the initial magnetic tunnel junction, and forming a dielectric layer on the side wall of the initial redeposited layer; simultaneously etching the initial magnetic tunnel junction, the initial redeposited layer deposited on the side wall of the initial magnetic tunnel junction, and the dielectric layer to form a magnetic tunnel junction, and sputtering on the side wall of the magnetic tunnel junction to form a redeposited insulating layer; wherein, in the redeposited insulating layer, the proportion of the dielectric layer component is greater than the sum of the proportion of the initial magnetic tunnel junction component and the proportion of the initial redeposited layer component, so that the redeposited insulating layer is insulated.

[0012] Optionally, etching above the spin-orbit moment layer to form an initial magnetic tunnel junction includes at least: depositing an initial magnetic tunnel junction film layer and a first mask layer in sequence above the spin-orbit moment layer; and etching the initial magnetic tunnel junction film layer using the first mask layer as a mask to form an initial magnetic tunnel junction.

[0013] Optionally, the initial magnetic tunnel junction, the initial redeposited layer and the dielectric layer deposited on the side wall of the initial magnetic tunnel junction are simultaneously etched, which at least includes: forming a second mask layer above the first mask layer, and the line width of the second mask layer is smaller than the line width of the initial magnetic tunnel junction; using the second mask layer as a mask, the first mask layer, the initial magnetic tunnel junction, the initial redeposited layer and the dielectric layer are simultaneously etched to form a magnetic tunnel junction, and reverse sputtering is performed on the side wall of the magnetic tunnel junction to form a redeposited insulating layer.

[0014] Optionally, the initial magnetic tunnel junction, the initial redeposited layer and the dielectric layer deposited on the side wall of the initial magnetic tunnel junction are simultaneously etched, which at least includes: removing the first mask layer so that the initial magnetic tunnel junction and the dielectric layer enclose a second groove; stacking a third mask layer and a fourth mask layer in sequence in the second groove, and the thickness of the third mask layer is less than half of the line width of the second groove; using the fourth mask layer as a mask, etching the third mask layer, the initial magnetic tunnel junction, the initial redeposited layer and the dielectric layer to form a magnetic tunnel junction, and back sputtering on the side wall of the magnetic tunnel junction to form a redeposited insulating layer.

[0015] The preparation method provided in the embodiments of the present disclosure can achieve the following technical effects: In the process of forming the initial magnetic tunnel junction by the initial etching, the conductive initial redeposition layer is deposited on the side wall of the initial magnetic tunnel junction, and the dielectric layer is first deposited and covered on the side wall of the initial redeposition layer. At this time, the magnetic tunnel junction is formed by synchronously etching the initial magnetic tunnel junction, the initial redeposition layer and the dielectric layer. At this time, the redeposition insulating layer formed by reverse sputtering on the side wall of the magnetic tunnel junction includes the dielectric layer component, the initial redeposition layer component and the initial magnetic tunnel junction component that are reversely sputtered to the side wall of the magnetic tunnel junction. Since the proportion of the insulating dielectric layer component is greater than the sum of the proportion of the initial magnetic tunnel junction component and the proportion of the initial redeposition layer component, the redeposition insulating layer exhibits insulating characteristics. In this way, on the one hand, a second etching is performed with the second mask layer or the fourth mask layer having a line width smaller than the line width of the initial magnetic tunnel junction as a mask, the conductive initial redeposition layer is eliminated, and an insulating redeposition insulating layer is formed, thereby avoiding a short circuit of the magnetic tunnel junction. On the other hand, the redeposition insulating layer covers the side wall of the magnetic tunnel junction, providing a protective function for the magnetic tunnel junction, which is conducive to improving the stability of the magnetic tunnel junction. On the other hand, a second etching is performed using a second mask layer or a fourth mask layer whose line width is smaller than the line width of the initial magnetic tunnel junction as a mask, so that the size of the magnetic tunnel junction is smaller than the initial magnetic tunnel junction, thereby reducing the size of the magnetic tunnel junction and the semiconductor device, improving the switching efficiency, and reducing power consumption. In addition, when the size of the magnetic tunnel junction is reduced, the surface magnetic anisotropy energy increases, the multi-domain structure gradually changes to a single domain, and the magnetization direction tends to be unified, thereby improving the performance of the magnetic tunnel junction and the coercive force Hc of the semiconductor device.

[0016] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein: Figure 1 is a structural cross-sectional view of a semiconductor device provided by an embodiment of the present disclosure; Figure 2 is a structural cross-sectional view of another semiconductor device provided by an embodiment of the present disclosure; Figure 3 is a structural cross-sectional view of another semiconductor device provided by an embodiment of the present disclosure; Figure 4 is a schematic diagram of a method for preparing a semiconductor device provided by an embodiment of the present disclosure; Figure 5 is a schematic diagram of another method for preparing a semiconductor device provided by an embodiment of the present disclosure; Figure 6is a structural cross-sectional view of a semiconductor device formed after the magnetic tunnel junction film layer is initially etched according to an embodiment of the present disclosure; Figure 7 The embodiment of the present disclosure provides Figure 6 A structural cross-sectional view of a semiconductor device formed after a dielectric layer is deposited on the basis of the semiconductor device; Figure 8 The embodiment of the present disclosure provides Figure 7 A structural cross-sectional view of a semiconductor device in which a first mask layer is etched to form a first groove based on the semiconductor device; Fig. 9 The embodiment of the present disclosure provides Figure 8 A structural cross-sectional view of a semiconductor device formed by depositing a second mask layer on the basis of the semiconductor device; Fig.10 The embodiment of the present disclosure provides Fig. 9 A structural cross-sectional view of a semiconductor device formed by performing CMP (Chemical Mechanical Polishing) on ​​the first mask layer and the second mask layer based on the present invention; Fig.11 The embodiment of the present disclosure provides Fig.10 A structural cross-sectional view of a semiconductor device formed by CMP-grinding the first mask layer and the second mask layer based on the present invention; Fig.12 The embodiment of the present disclosure provides Fig.11 A structural cross-sectional view of a semiconductor device formed by etching the first mask layer and the dielectric layer using the second mask layer as a mask; Fig.13 The embodiment of the present disclosure provides Fig.12 Based on the second mask layer, the initial magnetic tunnel junction and the dielectric layer are etched to form Figure 1 A cross-sectional view of the structure of the semiconductor device shown; Fig.14 It is a structural cross-sectional view of a semiconductor device formed after the magnetic tunnel junction film layer is initially etched when the free layer is set as a synthetic antiferromagnetic layer provided by an embodiment of the present disclosure; Fig.15 The embodiment of the present disclosure provides Fig.14 A structural cross-sectional view of a semiconductor device formed by depositing a dielectric layer on the basis of the semiconductor device; Fig.16 The embodiment of the present disclosure provides Fig.15 A structural cross-sectional view of a semiconductor device formed by depositing a second mask layer on the basis of the semiconductor device and then grinding the first mask layer and the second mask layer by CMP; Fig.17 The embodiment of the present disclosure provides Fig.16Based on the second mask layer as a mask, the first mask layer, the initial magnetic tunnel junction, and the dielectric layer are etched to form Figure 2 A cross-sectional view of the structure of the semiconductor device shown; Fig.18 The embodiment of the present disclosure provides Figure 7 or Fig.15 A structural cross-sectional view of a semiconductor device formed after the first mask layer is removed on the basis of the semiconductor device to form a second groove; Fig.19 The embodiment of the present disclosure provides Fig.18 A structural cross-sectional view of a semiconductor device formed after depositing a third mask layer based on the present invention; Fig. 20 The embodiment of the present disclosure provides Fig.19 A structural cross-sectional view of a semiconductor device formed after depositing a fourth mask layer based on the present invention; Fig.21 The embodiment of the present disclosure provides Fig. 20 A structural cross-sectional view of a semiconductor device formed after CMP grinding the third mask layer and the fourth mask layer on the basis of FIG. Fig. 22 The embodiment of the present disclosure provides Fig.21 Based on the fourth mask layer as a mask, the third mask layer, the initial magnetic tunnel junction, and the dielectric layer are etched to form Figure 3 A structural cross-sectional view of a semiconductor device shown.

[0018] Reference numerals: 1: spin-orbit moment layer; 20: initial magnetic tunnel junction; 2: magnetic tunnel junction; 21: free layer; 210: synthetic antiferromagnetic layer; 211: lower magnetic layer; 212: intermediate coupling layer; 213: upper magnetic layer; 22: barrier layer; 23: reference layer; 24: pinned layer; 3: initial redeposited layer; 4: mask layer; 41: first mask layer; 411: first groove; 412: second groove; 42: second mask layer; 43: third mask layer; 44: fourth mask layer; 5: dielectric layer; 6: redeposited insulating layer. DETAILED DESCRIPTION

[0019] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0020] The terms "first", "second", etc. in the description of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0021] In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements, or components to have specific orientations, or to be constructed and operated in specific orientations. Moreover, in addition to being used to indicate orientations or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0022] In the embodiments of the present disclosure, the term "and / or" is a description of the association relationship between objects, indicating that three relationships may exist. For example, A and / or B means: A or B, or, A and B.

[0023] It should be noted that the embodiments or implementation methods in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0024] An embodiment of the present application provides a semiconductor device, which may be a spin-orbit moment magnetic memory. The semiconductor device is a SOT-MRAM as an example for introduction below.

[0025] In the process of preparing semiconductor devices, Figure 6 As shown, after the initial magnetic tunnel junction film layer is first etched, the initial magnetic tunnel junction 20 is formed. During the etching process, it is inevitable that the initial magnetic tunnel junction film layer is back-sputtered on the side wall of the initial magnetic tunnel junction 20 to form an initial redeposited layer 3. The main component of the initial redeposited layer 3 is the conductive component of the initial magnetic tunnel junction film layer. Therefore, the initial redeposited layer 3 covering the side wall of the initial magnetic tunnel junction 20 will become conductive, so that the free layer 21 and the reference layer 23 of the initial magnetic tunnel junction 20 are connected, thereby causing the magnetic tunnel junction to short-circuit, affecting the yield of the semiconductor device.

[0026] It should be noted that the meaning of reverse sputtering is as follows: the particles generated when the etched film layer or structure is usually etched by a physical removal method such as ion beam etching (IBE) or reactive ion etching (RIE) cannot be as highly volatile as chemical etching, which means that these particles will not be discharged in time and will be redeposited near the film layer or structure that has not been etched, forming redepositions. In this application, the above process is summarized as reverse sputtering.

[0027] When etching forms the initial magnetic tunnel junction 20, the etched film layer is the initial magnetic tunnel junction film layer, and the unetched structure is the area in the initial magnetic tunnel junction film layer where the initial magnetic tunnel junction 20 is formed. Therefore, the components of the initial magnetic tunnel junction film layer will be sputtered back to the side walls of the initial magnetic tunnel junction 20 to form an initial redeposited layer 3, that is, the main components of the initial redeposited layer 3 are the components of the initial magnetic tunnel junction film layer.

[0028] To avoid magnetic tunnel junction short circuit, combined Figure 1 As shown, an embodiment of the present disclosure provides a semiconductor device, comprising at least a spin-orbit moment layer 1, a magnetic tunnel junction 2, and a redeposited insulating layer 6 covering the side wall of the magnetic tunnel junction 2, which are stacked in sequence; wherein the free layer 21 of the magnetic tunnel junction 2 is arranged adjacent to the spin-orbit moment layer 1; the magnetic tunnel junction 2 is formed by synchronously etching the initial magnetic tunnel junction 20, the initial redeposited layer 3 deposited on the side wall of the initial magnetic tunnel junction 20, and the dielectric layer 5, and the redeposited insulating layer 6 is formed by back sputtering on the side wall of the magnetic tunnel junction 2; in the redeposited insulating layer 6, the proportion of the dielectric layer 5 is greater than the sum of the proportion of the initial magnetic tunnel junction 20 and the proportion of the initial redeposited layer 3, so that the redeposited insulating layer 6 is insulated.

[0029] When etching forms the magnetic tunnel junction 2, the etched film layers are the initial magnetic tunnel junction 20, the initial redeposited layer 3 and the dielectric layer 5, and the unetched structure is the region of the initial magnetic tunnel junction 20 where the magnetic tunnel junction 2 is formed. Therefore, the components of the initial magnetic tunnel junction 20 will be back-sputtered to the side walls of the magnetic tunnel junction 2 to form a redeposited insulating layer 6, that is, the main components of the redeposited insulating layer 6 are the components of the initial magnetic tunnel junction 20, and contain a small amount of the initial redeposited layer 3 components and the dielectric layer 5 components.

[0030] It should be noted that the semiconductor device includes a substrate, a spin-orbit moment layer 1 disposed on the substrate, and a magnetic tunnel junction 2 disposed on the spin-orbit moment layer 1. The magnetic tunnel junction 2 includes a free layer 21, a barrier layer 22, and a reference layer 23 stacked in sequence. Among them, the free layer 21 has a variable magnetic moment, and the reference layer 23 has a fixed magnetic moment. When the magnetic moments of the free layer 21 and the reference layer 23 are parallel, the junction resistance of the magnetic tunnel junction 2 is low resistance, which can be represented by the binary number "0"; when the magnetic moments of the free layer 21 and the reference layer 23 are antiparallel, the junction resistance of the magnetic tunnel junction 2 is high resistance, which can be represented by the binary number "1"; due to the spin-orbit moment effect, when current flows through the spin-orbit moment layer 1, a spin-orbit moment is generated, and under the influence of the spin Hall effect and the Rashba effect, the charge flow is converted into a spin current, and the spin current then diffuses to the free layer 21. The magnetic moment of the free layer 21 is directional flipped under the action of the spin current to realize data reading and writing. Since the write current does not pass through the barrier layer 22, the SOT-MRAM has a longer service life.

[0031] The spin-orbit moment layer 1 includes at least one of a conductive layer with a strong spin-orbit coupling effect, a heavy metal material with a spin-on property, or a topological insulator; the conductive layer with a strong spin-orbit coupling effect includes one or more combinations of Pt (platinum), Pd (palladium), Hf (hafnium), Au (gold), AuPt (gold-platinum alloy), PtHf (platinum-hafnium alloy), PtCr (platinum-chromium alloy), PtMn (platinum-manganese alloy), FeMn (iron-manganese alloy), and NiMn (nickel-manganese alloy); the heavy metal material with a spin-on property includes one or more combinations of Ta (tantalum), W (tungsten), Hf (hafnium), Ir (iridium), IrMn (iridium-manganese alloy), WOx (tungsten oxide), WN (tungsten nitride), W(O, N) (a mixture of tungsten oxide and nitride), TaN (tantalum nitride), and TaB (tantalum boride); the topological insulator includes Bi x Se 1-x ,Bi x Sb 1-x , one or more combinations of (Bi, Sb)2Te3.

[0032] Among them, the magnetic tunnel junction 2 includes but is not limited to a free layer 21, a barrier layer 22, and a reference layer 23 stacked in sequence. The material of the barrier layer 22 is set to be insulating MgO (magnesium oxide). In actual use, the magnetic tunnel junction 2 can add other functional film layers according to actual needs to achieve corresponding needs, such as setting a pinning layer 24 above the reference layer 23 to improve the magnetoresistance performance of the magnetic tunnel junction 2 and the semiconductor device, which will not be repeated here. The top view shape of the magnetic tunnel junction includes but is not limited to: any one of an ellipse, a circle or a rectangle.

[0033] By using the semiconductor device provided by the embodiment of the present disclosure, on the one hand, the conductive initial redeposited layer 3 is eliminated, and an insulating redeposited insulating layer 6 is formed, thereby avoiding a short circuit of the magnetic tunnel junction 2. On the other hand, the redeposited insulating layer 6 covers the sidewalls of the magnetic tunnel junction 2, providing a protective function for the magnetic tunnel junction 2, thereby facilitating improving the stability of the magnetic tunnel junction 2. On the other hand, since the size of the magnetic tunnel junction 2 is smaller than the initial magnetic tunnel junction 20, the size of the magnetic tunnel junction 2 and the semiconductor device is reduced, the flipping efficiency is improved, and the power consumption is reduced. In addition, when the size of the magnetic tunnel junction 2 is reduced, the surface magnetic anisotropy energy increases, the multi-domain structure gradually changes to a single domain, and the magnetization direction tends to be unified, thereby improving the performance of the magnetic tunnel junction 2 and the coercive force Hc of the semiconductor device.

[0034] Optionally, the material of the dielectric layer 5 includes but is not limited to: SiO (silicon monoxide), and / or, SiN (silicon nitride), and / or, SiON (silicon oxynitride). By setting the dielectric layer 5 with insulating material, it is beneficial to improve the insulating properties of the dielectric layer 5 components in the redeposited insulating layer 6, thereby improving the insulating properties of the redeposited insulating layer 6, and further avoiding a short circuit in the magnetic tunnel junction 2.

[0035] Optionally, the composition ratio of the dielectric layer 5 is much greater than the sum of the composition ratio of the initial magnetic tunnel junction 20 and the composition ratio of the initial redeposited layer 3, which is beneficial to improving the insulation performance of the redeposited insulating layer 6 and better avoiding short circuit of the magnetic tunnel junction 2 and the semiconductor device.

[0036] Optionally, combined Figure 1-Figure 3 As shown, the semiconductor device further includes a mask layer 4 disposed above the magnetic tunnel junction 2. Specifically, the mask layer 4 is configured as a hard mask layer. The material of the hard mask layer includes but is not limited to: TiN (titanium nitride), and / or TAN (tantalum nitride), and / or TA (tantalum).

[0037] In this way, on the first hand, the mask layer 4 can be used as a mask for etching to form the magnetic tunnel junction 2 and the re-deposited insulating layer 6, which is beneficial to improving the etching process accuracy while avoiding the short circuit of the magnetic tunnel junction 2. On the second hand, the mask layer 4 can be used as an electrode connected to the reference layer 23 above the magnetic tunnel junction 2, which is beneficial to simplify the structure. On the third hand, the mask layer 4 can be used as a protective layer for the magnetic tunnel junction 2 to improve the stability of the semiconductor device. On the fourth hand, the existence of the mask layer 4 provides structural support for etching the magnetic tunnel junction 2 again, thereby improving the process margin.

[0038] Optionally, the present application proposes at least two structures of the mask layer, but in practice, the structures include but are not limited to these two. The following specifically introduces these two structures: The first structural form, refer to Figure 1 and Figure 2As shown, the mask layer 4 includes at least a first mask layer 41 and a second mask layer 42; wherein, the first mask layer 41 is arranged above the magnetic tunnel junction 2, and a first groove 411 is arranged at the top of the first mask layer 41, and the second mask layer 42 is arranged in the first groove 411, and the line width of the magnetic tunnel junction 2 is determined by the line width at the top of the first groove 411.

[0039] It should be noted that the line width in the present application means the width of a certain structure or film layer along the horizontal direction, such as the line width of the magnetic tunnel junction 2, which is the width of the magnetic tunnel junction 2 along the horizontal direction; the line width at the top of the first groove 411, which is the width of the top of the first groove 411 along the horizontal direction; the explanation of the line width of other structures or film layers is similar and will not be repeated here.

[0040] In this way, the second mask layer 42 is disposed in the first groove 411, so the line width at the top of the second mask layer 42 is determined by the line width at the top of the first groove 411. The second mask layer 42 can be used as a mask for etching the initial magnetic tunnel junction 20, the initial redeposition layer 3, and the dielectric layer 5, so the line width at the top of the second mask layer can determine the line width of the magnetic tunnel junction 2. In this way, the line width of the magnetic tunnel junction 2 can be determined by the line width at the top of the first groove 411. In actual use, the line width at the top of the first groove 411 can be reduced to reduce the size of the magnetic tunnel junction 2, thereby reducing the size of the semiconductor device. Reducing the size of the magnetic tunnel junction 2 is beneficial to improving the performance of the magnetic tunnel junction 2 and the Hc of the semiconductor device.

[0041] The second structural form, refer to Figure 3 , the mask layer 4 at least includes a third mask layer 43 and a fourth mask layer 44; wherein, the height of the dielectric layer 5 is greater than the height of the initial magnetic tunnel junction 20, so that the two are surrounded to form a second groove 412, the third mask layer 43 and the fourth mask layer 44 are deposited in the second groove 412, the third mask layer 43 is arranged above the magnetic tunnel junction 2, and the fourth mask layer 44 is arranged above the third mask layer 43, and the line width of the fourth mask layer 44 is determined by the thickness of the third mask layer 43.

[0042] In this way, when the third mask layer 43 and the fourth mask layer 44 are sequentially deposited in the second groove 412 formed by the dielectric layer 5 and the initial magnetic tunnel junction 20, the third mask layer 43 covers the bottom and sidewalls of the second groove 412, and the thickness of the third mask layer 43 determines the line width of the third mask layer 43 covering the sidewalls, and the fourth mask layer 44 is deposited between the third mask layer 43 covering the sidewalls and the bottom of the second groove 412. In this way, the line width of the third mask layer 43 covering the sidewalls can determine the line width of the fourth mask layer 44, and then the line width of the fourth mask layer 44 is determined by the thickness of the third mask layer 43 (that is, the thickness of the third mask layer 43 is negatively correlated with the line width of the fourth mask layer 44). The fourth mask layer 44 can be used as a mask for etching the initial magnetic tunnel junction 20, the initial redeposition layer 3, and the dielectric layer 5. Therefore, the line width of the fourth mask layer 44 can determine the line width of the magnetic tunnel junction 2, and then the line width of the magnetic tunnel junction 2 can be determined by the thickness of the third mask layer 43. In actual application, the thickness of the third mask layer 43 can be increased to reduce the size of the magnetic tunnel junction 2, thereby reducing the size of the semiconductor device. Reducing the size of the magnetic tunnel junction 2 is conducive to improving the performance of the magnetic tunnel junction 2 and the Hc of the semiconductor device.

[0043] It should be noted that “first mask layer 41”, “second mask layer 42”, “third mask layer 43”, “fourth mask layer 44”, “first groove 411” and “second groove 412” are merely exemplary expressions. The number of mask layers and the number of grooves include but are not limited to two. In actual application, the number of mask layers and the number of grooves can be adjusted and set according to actual needs, which will not be repeated here.

[0044] In some other embodiments, combined with Figure 2 and Figure 3 As shown, the free layer 21 can also be set as a synthetic antiferromagnetic layer 210. Specifically, the synthetic antiferromagnetic layer 210 includes a lower magnetic layer 211, an intermediate coupling layer 212, and an upper magnetic layer 213 stacked in sequence. The lower magnetic layer 211 is arranged adjacent to the spin-orbit moment layer 1, which is beneficial to improving the antimagnetic performance of the magnetic tunnel junction 2.

[0045] Next, based on the structure of the semiconductor device described above, the preparation method thereof is further described. Figure 4 , Figure 6-Figure 13 As shown, the embodiment of the present disclosure provides a Figure 1 The method for preparing the semiconductor device shown comprises at least the following steps: S101, etching to form an initial magnetic tunnel junction 20 above the spin-orbit moment layer 1 and an initial re-deposited layer 3 sputtered on the sidewalls of the initial magnetic tunnel junction 20, and forming a dielectric layer 5 on the sidewalls of the initial re-deposited layer 3; S102, synchronously etching the initial magnetic tunnel junction 20, the initial re-deposited layer 3 and the dielectric layer 5 deposited on the sidewalls of the initial magnetic tunnel junction 20 to form a magnetic tunnel junction 2, and re-sputtering the sidewalls of the magnetic tunnel junction 2 to form a re-deposited insulating layer 6; In the redeposited insulating layer 6 , the proportion of the dielectric layer 5 is greater than the sum of the proportion of the initial magnetic tunnel junction 20 and the proportion of the initial redeposited layer 3 , so that the redeposited insulating layer 6 is insulated.

[0046] The method for preparing a semiconductor device provided by the embodiment of the present disclosure is adopted. On the one hand, a second mask layer or a fourth mask layer having a line width smaller than the line width of the initial magnetic tunnel junction is used as a mask for secondary etching to eliminate the conductive initial redeposition layer 3 and form an insulating redeposition insulating layer 6, thereby avoiding a short circuit of the magnetic tunnel junction 2. On the other hand, the redeposition insulating layer 6 covers the sidewalls of the magnetic tunnel junction 2, providing a protective function for the magnetic tunnel junction 2, thereby facilitating the improvement of the stability of the magnetic tunnel junction 2. On the other hand, a second mask layer 42 or a fourth mask layer 44 having a line width smaller than the line width of the initial magnetic tunnel junction is used as a mask for secondary etching, so that the size of the magnetic tunnel junction 2 is smaller than the initial magnetic tunnel junction 20, thereby reducing the size of the magnetic tunnel junction 2 and the semiconductor device, improving the flipping efficiency, and reducing the power consumption. In addition, when the size of the magnetic tunnel junction is reduced, the surface magnetic anisotropy energy increases, the multi-domain structure gradually changes to a single domain, and the magnetization direction tends to be unified, thereby improving the performance of the magnetic tunnel junction and the semiconductor device Hc.

[0047] Optionally, combined Figure 6 As shown, etching to form an initial magnetic tunnel junction 20 above the spin-orbit moment layer 1 at least includes: depositing an initial magnetic tunnel junction film layer and a first mask layer 41 in sequence above the spin-orbit moment layer 1; etching the initial magnetic tunnel junction film layer using the first mask layer 41 as a mask to form the initial magnetic tunnel junction 20.

[0048] In this way, after the deposition process and the initial etching process, the initial magnetic tunnel junction film layer is initially etched to form the initial magnetic tunnel junction 20. However, during the initial etching to form the initial magnetic tunnel junction 20, the etched initial magnetic tunnel junction film layer will be sputtered back on the side wall of the initial magnetic tunnel junction 20 to form an initial redeposited layer 3. The initial redeposited layer 3 is conductive, which can easily cause a short circuit between the initial magnetic tunnel junction 20 and the semiconductor device.

[0049] Optionally, combined Figure 7As shown, forming a dielectric layer 5 on the side wall of the initial redeposited layer 3 at least includes: depositing the dielectric layer 5 on the initial redeposited layer 3 and the first mask layer 41, so that the dielectric layer 5 completely covers the side wall of the initial redeposited layer 3 and the first mask layer 41, so as to achieve a condition that the composition ratio of the dielectric layer 5 is greater than the sum of the composition ratio of the initial magnetic tunnel junction 20 and the composition ratio of the initial redeposited layer 3, and then flattening the dielectric layer 5 to expose the upper surface of the first mask layer 41, so as to obtain the following Figure 7 The structure shown in FIG. 1 still needs to meet the condition that the composition ratio of the dielectric layer 5 is greater than the sum of the composition ratio of the initial magnetic tunnel junction 20 and the composition ratio of the initial redeposition layer 3 .

[0050] Specifically, the planarization process includes: setting the grinding endpoint layer as the first mask layer 41 , and performing a CMP process on the dielectric layer 5 .

[0051] Specifically, after the dielectric layer 5 is planarized, the thickness of the dielectric layer 5 is equal to the height of the top of the first mask layer 41. This is conducive to exposing the upper surface of the first mask layer 41, so as to form the second mask layer 42 above the first mask layer 41. At the same time, the dielectric layer 5 wraps the side wall of the initial redeposited layer 3, so that during the subsequent secondary etching, the initial magnetic tunnel junction 20 and the initial redeposited layer 3 are simultaneously etched to form the redeposited insulating layer 6.

[0052] Optionally, the present application proposes at least two methods for implementing step S101, but in practice, these two methods are not limited to the two methods. The following describes these two methods in detail: The first method, refer to Figure 8-Figure 13 As shown, the initial magnetic tunnel junction 20, the initial redeposition layer 3 and the dielectric layer 5 deposited on the sidewall of the initial magnetic tunnel junction 20 are simultaneously etched, at least comprising: combining Figure 8-Figure 11 As shown, a second mask layer 42 is formed on the first mask layer 41, and the line width of the second mask layer 42 is smaller than the line width of the initial magnetic tunnel junction 20; Fig.12 and Fig.13 As shown, using the second mask layer 42 as a mask, the first mask layer 41, the initial magnetic tunnel junction 20, the initial redeposited material layer 3 and the dielectric layer 5 are simultaneously etched to form a magnetic tunnel junction 2, and a redeposited material insulating layer 6 is formed by reverse sputtering on the side wall of the magnetic tunnel junction 2.

[0053] Specifically, the dielectric layer 5 and the initial redeposited layer 3 are completely etched, and the initial magnetic tunnel junction 20 is partially etched. In this way, a second mask layer 42 with a line width smaller than the initial magnetic tunnel junction 20 is first formed on the first mask layer 41, and then a second etching is performed using the second mask layer 42 as a mask to reversely sputter the side wall of the magnetic tunnel junction 2 to form a redeposited insulating layer 6, thereby avoiding a short circuit of the magnetic tunnel junction 2. And the size of the obtained magnetic tunnel junction 2 is smaller than or equal to the initial magnetic tunnel junction 20, which is conducive to further reducing the size of the magnetic tunnel junction 2 and the semiconductor device. Reducing the size of the magnetic tunnel junction 2 is conducive to improving the performance of the magnetic tunnel junction 2 and the Hc of the semiconductor device.

[0054] Specifically, combined Fig. 9 As shown, the process used to form the second mask layer 42 in the first groove 411 includes but is not limited to a deposition process, wherein the thickness of the second mask layer 42 deposited on the first mask layer 41 is greater than or equal to the minimum grindable thickness threshold of the CMP process, thereby providing a structural basis for further adjusting the line width of the second mask layer 42 through the subsequent CMP process.

[0055] Specifically, the line width of the dielectric layer 5 on either side of the side wall of the initial magnetic tunnel junction 20 is greater than the sum of the line width of the initial redeposited layer 3 on the same side and the line width of the etched area on the same side of the initial magnetic tunnel junction 20. In this way, during the secondary etching process, the components of the dielectric layer 5, the initial redeposited layer 3, and the initial magnetic tunnel junction 20 are back-sputtered to the side wall of the magnetic tunnel junction 2 to form the redeposited insulating layer 6. By limiting the line width relationship of the dielectric layer 5, the initial redeposited layer 3, and the initial magnetic tunnel junction 20, the proportion of the insulating dielectric layer 5 components back-sputtered to the side wall of the magnetic tunnel junction 2 can be greater than the sum of the proportions of the initial magnetic tunnel junction 20 components and the proportions of the initial redeposited layer 3 components, which is beneficial to improving the insulation performance of the redeposited insulating layer 6.

[0056] Alternatively, specifically, the dielectric layer 5 completely covers the side walls of the initial redeposited layer 3 to achieve a condition where the proportion of the dielectric layer 5 component is greater than the sum of the proportion of the initial magnetic tunnel junction 20 component and the proportion of the initial redeposited layer 3 component, thereby ensuring that during etching, the proportion of the dielectric layer 5 component in the redeposited insulating layer 6 that is back-sputtered to the side walls of the magnetic tunnel junction has a proportion greater than the sum of the proportion of the initial magnetic tunnel junction 20 component and the proportion of the initial redeposited layer 3 component.

[0057] Specifically, combined Figure 8-Figure 11 As shown, forming a second mask layer 42 on the first mask layer 41 at least includes: combining Figure 8 As shown, a first groove 411 is formed at the top of the first mask layer 41, and combined with Fig. 9 As shown, a second mask layer 42 is formed in the first groove 411; Fig.10 and Fig.11As shown, the first mask layer 41 and the second mask layer 42 are planarized so that the line width at the top of the first groove 411 is less than or equal to the line width of the initial magnetic tunnel junction 20; wherein the line width at the top of the first groove 411 is determined by the duration of the planarization treatment and / or the shape of the first groove 411.

[0058] Specifically, the process used for the planarization process includes but is not limited to grinding by CMP process. In this way, due to the existence of the first groove 411, there is a step difference on the upper surface of the first mask layer 41, that is, there is a height difference between the two side planes and the middle plane of the upper surface of the first mask layer 41. Therefore, the second mask layer 42 deposited on the first mask layer 41 also has a step difference, that is, there is a height difference between the two side planes and the middle plane of the upper surface of the second mask layer 42. Fig.11 The CMP grinding process shown completely removes the second mask layer 42 on the dielectric layer 5, so that the second mask layer 42 is completely set in the first groove 411. By controlling the mask time of the CMP process, the CMP grinding amount can be further controlled, thereby controlling the height of the first groove 411. If the shape of the first groove 411 is set to change the line width with the height, the line width setting at the top of the first groove 411 can be controlled by the grinding time of the CMP process and / or the shape of the first groove 411, and the line width at the top of the second mask layer 42 is determined by the line width at the top of the first groove 411, and then the line width at the top of the second mask layer 42 can be controlled. The second mask layer 42 can be used as a mask for etching the initial magnetic tunnel junction 20, the initial redeposited layer 3, and the dielectric layer 5, so the line width at the top of the second mask layer can determine the line width of the magnetic tunnel junction 2. In this way, the line width at the top of the first groove 411 is determined by the duration of the planarization process and / or the shape of the first groove 411, and then the line width of the magnetic tunnel junction 2 is determined by the line width at the top of the first groove 411. In actual use, the line width at the top of the first groove 411 can be reduced to reduce the size of the magnetic tunnel junction 2, thereby reducing the size of the semiconductor device. Reducing the size of the magnetic tunnel junction 2 is conducive to improving the performance of the magnetic tunnel junction 2 and the Hc of the semiconductor device. In addition, controlling the size of the mask through the CMP process to control the size of the magnetic tunnel junction 2 is conducive to reducing the process difficulty of etching the magnetic tunnel junction 2.

[0059] More specifically, combined with Figure 8As shown, forming a first groove 411 at the top of the first mask layer 41 at least includes: using a self-alignment process, taking the first mask layer 41 or the pinning layer 24 disposed between the first mask layer 41 and the reference layer 23 as the etching end point, and selectively etching the first mask layer 41; wherein the etching rate of the first mask layer 41 is greater than the etching rate of the dielectric layer 5. In this way, by reasonably setting the etching selectivity ratio between the first mask layer 41 and the dielectric layer 5, the shape of the first groove 411 obtained by etching is adjusted, and the byproducts generated during etching passivate the sidewall of the first groove 411, so that the sidewall of the first groove 411 forms a larger angle with the vertical direction.

[0060] More specifically, combined with Figure 8 As shown, the cross-sectional shape of the first groove 411 along the vertical direction can be a trapezoidal shape that is wide at the top and narrow at the bottom, that is, the angle between the sidewall of the first groove 411 and the bottom is an obtuse angle, and the angle between the sidewall of the first groove 411 and the vertical direction is an acute angle.

[0061] More specifically, the angle between the sidewall of the first groove 411 and the vertical direction is in the range of 5° to 80°. The angle between the sidewall of the first groove 411 and the vertical direction can be 5°, 20°, 40°, 60°, 80°, or any value within the above range, all of which fall within the protection scope of the present application. In this way, the shape of the first groove 411 is defined to be wide at the top and narrow at the bottom, so that the line width of the second mask layer 42 in the first groove is wide at the top and narrow at the bottom, which is conducive to adjusting the line width of the magnetic tunnel junction 2 according to actual needs.

[0062] Specifically, combined Fig.12 and Fig.13 As shown, when the first mask layer 41, the initial magnetic tunnel junction 20, the initial redeposited layer 3 and the dielectric layer 5 are simultaneously etched using the second mask layer 42 as a mask, the etching rate of the second mask layer 42 is greater than the etching rates of the first mask layer 41 and the dielectric layer 5, and the etching end point is set to the pinned layer 24 set between the first mask layer 41 and the reference layer 23, and the dielectric layer 5 and the initial redeposited layer 3 above the spin-orbit moment layer 1 are completely removed.

[0063] In this way, the second mask layer 42 has a high selectivity with the first mask layer 41 and the dielectric layer 5. At this time, the area not protected by the second mask layer 42 will be etched, the dielectric layer 5 will be completely removed, the line width of the first mask layer 41 will be reduced, the initial redeposited layer 3 will be completely removed, the line width of the initial magnetic tunnel junction 20 will be reduced to form a magnetic tunnel junction 2, and the secondary etching will back-sputter the dielectric layer 5, the initial redeposited layer 3, and the initial magnetic tunnel junction 20 on the side wall of the magnetic tunnel junction 2 to form a redeposited insulating layer 6. Since the proportion of the etched dielectric layer 5 is the largest, which is greater than the sum of the proportions of the components of the etched initial redeposited layer 3 and the initial magnetic tunnel junction 20 to form the redeposited insulating layer 6, the redeposited insulating layer 6 exhibits insulating properties, thereby avoiding short circuits of the magnetic tunnel junction 2. Setting the etching endpoint to the film layer above the reference layer 23 is conducive to protecting the magnetic tunnel junction 2 from being over-etched.

[0064] The second way is to form Figure 1-Figure 3 The semiconductor device shown, combined with Figure 18-Figure 22 As shown, the initial magnetic tunnel junction 20, the initial redeposition layer 3 and the dielectric layer 5 deposited on the sidewall of the initial magnetic tunnel junction 20 are simultaneously etched, at least comprising: combining Fig.18 As shown, the first mask layer 41 is removed so that the initial magnetic tunnel junction 20 and the dielectric layer 5 are surrounded by a second groove 412; Figure 19-21 As shown, a third mask layer 43 and a fourth mask layer 44 are sequentially stacked in the second groove 412, and the thickness of the third mask layer 43 is less than half of the line width of the second groove 412; Fig. 22 As shown, the third mask layer 43, the initial magnetic tunnel junction 20, the initial redeposited material layer 3 and the dielectric layer 5 are etched using the fourth mask layer 44 as a mask to form a magnetic tunnel junction 2, and a redeposited material insulating layer 6 is formed by reverse sputtering on the side wall of the magnetic tunnel junction 2.

[0065] In this way, when the third mask layer 43 and the fourth mask layer 44 are sequentially deposited in the second groove 412 formed by the dielectric layer 5 and the initial magnetic tunnel junction 20, the third mask layer 43 covers the bottom and sidewalls of the second groove 412, and the thickness of the third mask layer 43 determines the line width of the third mask layer 43 covering the sidewalls, and the fourth mask layer 44 is deposited between the third mask layer 43 covering the sidewalls and the bottom of the second groove 412, so the line width of the fourth mask layer 44 is the difference between half of the line width of the second groove 412 and the thickness of the third mask layer 43. In this way, the line width of the third mask layer 43 covering the sidewalls can determine the line width of the fourth mask layer 44, and then the line width of the fourth mask layer 44 is determined by the thickness of the third mask layer 43. The fourth mask layer 44 can be used as a mask for etching the initial magnetic tunnel junction 20, the initial redeposition layer 3, and the dielectric layer 5. Therefore, the line width of the fourth mask layer 44 can determine the line width of the magnetic tunnel junction 2, and then the line width of the magnetic tunnel junction 2 can be determined by the thickness of the third mask layer 43. The size of the magnetic tunnel junction 2 can be controlled by a more controllable film forming process, and there is no need to use the CMP process to grind the third mask layer 43 and the fourth mask layer 44 in the second groove 412, which is conducive to reducing the difficulty of the CMP process and improving the CMP process window, thereby greatly reducing the process difficulty. In addition, in actual application, the thickness of the third mask layer 43 can be increased to reduce the size of the magnetic tunnel junction 2, thereby reducing the size of the semiconductor device. Reducing the size of the magnetic tunnel junction 2 is conducive to improving the performance of the magnetic tunnel junction 2 and the Hc of the semiconductor device.

[0066] Specifically, combined Fig.18 As shown, removing the first mask layer 41 at least includes: the height of the top of the first mask layer 41 is equal to the height of the dielectric layer 5; selectively etching the first mask layer 41 to completely remove the first mask layer 41, so that the initial magnetic tunnel junction 20 and the dielectric layer 5 are surrounded by a second groove 412. More specifically, the cross-sectional shape of the second groove 412 along the vertical direction is a vertical groove, that is, the sidewall of the second groove 412 is perpendicular to the bottom, and the sidewall of the second groove 412 is parallel to the vertical direction.

[0067] In this way, the second groove 412 is a vertical groove, and its line width in the vertical direction is the same. The line width of the fourth mask layer 44 can be more accurately adjusted through the thickness of the third mask layer 43 and the line width of the second groove 412, so that the line width of the magnetic tunnel junction 2 can be more accurately adjusted through a more controllable film forming process, which is beneficial to improve the process accuracy of etching the magnetic tunnel junction 2 and reduce the process difficulty.

[0068] Specifically, combined Figure 19-21 As shown, the third mask layer 43 and the fourth mask layer 44 are sequentially stacked in the second groove 412, including: Fig.19 and Fig. 20As shown, a third mask layer 43 and a fourth mask layer 44 are sequentially deposited on the upper surfaces of the initial magnetic tunnel junction 20 and the dielectric layer 5, wherein the thickness of the third mask layer 43 is less than half of the line width of the second groove 412, and the fourth mask layer 44 has high step coverage; Fig.21 As shown, the dielectric layer 5 is ground to stop the layer, and the third mask layer 43 and the fourth mask layer 44 are planarized and ground using a CMP process, so that the third mask layer 43 and the fourth mask layer 44 on the upper surface of the dielectric layer 5 are completely removed, and the third mask layer 43 and the fourth mask layer 44 inside the second groove 412 are retained, so that the side wall and the bottom of the fourth mask layer 44 are surrounded by the third mask layer 43.

[0069] In this way, the formation Fig. 20 The fourth mask layer 44 with high step coverage shown in the figure, by limiting the thickness of the third mask layer 43 to be less than half of the line width of the second groove 412, so that the space for depositing the fourth mask layer 44 is reserved in the second groove 412. After the third mask layer 43 and the fourth mask layer 44 are planarized by the CMP process, the line width of the fourth mask layer 44 retained in the second groove 412 is the difference between half of the line width of the second groove 412 and the thickness of the third mask layer 43. Since the line width of the fourth mask layer 44 can determine the line width of the magnetic tunnel junction 2, the line width of the magnetic tunnel junction 2 can be determined by the thickness of the third mask layer 43. The size of the magnetic tunnel junction 2 can be controlled by a more controllable film forming process, and there is no need to use the CMP process to over-grind the third mask layer 43 and the fourth mask layer 44 in the second groove 412, which is conducive to reducing the difficulty of the CMP process and improving the CMP process window, thereby greatly reducing the process difficulty.

[0070] Specifically, combined Fig. 22 As shown, the third mask layer 43, the initial magnetic tunnel junction 20, the initial redeposited layer 3 and the dielectric layer 5 are etched using the fourth mask layer 44 as a mask, including: the etching rate of the fourth mask layer 44 is greater than the etching rates of the third mask layer 43 and the dielectric layer 5, the etching end point is set to the third mask layer 43 or the pinned layer 24 set between the first mask layer 41 and the reference layer 23, and the dielectric layer 5 and the initial redeposited layer 3 above the spin-orbit moment layer 1 are completely removed.

[0071] In this way, the fourth mask layer 44 has a high selectivity with the third mask layer 43 and the dielectric layer 5. At this time, the area not protected by the third mask layer 43 will be etched, the dielectric layer 5 will be completely removed, the line width of the third mask layer 43 will be reduced, the initial redeposited layer 3 will be completely removed, the line width of the initial magnetic tunnel junction 20 will be reduced to form a magnetic tunnel junction 2, and the secondary etching will back-sputter the dielectric layer 5, the initial redeposited layer 3, and the initial magnetic tunnel junction 20 on the side wall of the magnetic tunnel junction 2 to form a redeposited insulating layer 6. Since the proportion of the etched dielectric layer 5 is the largest, which is greater than the sum of the proportions of the components of the etched initial redeposited layer 3 and the initial magnetic tunnel junction 20 to form the redeposited insulating layer 6, the redeposited insulating layer 6 exhibits insulating properties, thereby preventing the magnetic tunnel junction 2 from short-circuiting. Setting the etching end point to the film layer above the reference layer 23 is conducive to protecting the magnetic tunnel junction 2 from being over-etched.

[0072] Combination Figure 4 As shown, when the free layer 21 is set as a synthetic antiferromagnetic layer 210, the combination Figure 2 , Figure 3 , Figure 5 , Figure 14-Figure 22 As shown, the embodiment of the present disclosure provides another method for preparing a semiconductor device, which at least includes the following steps: S201, using the lower magnetic layer 211 as an etching stop layer, etching to form an initial magnetic tunnel junction 20 and an initial redeposition layer 3 sputtered on the sidewall of the initial magnetic tunnel junction 20 above the spin-orbit moment layer 1, so that the line width of the lower magnetic layer 211 is equal to the line width of the spin-orbit moment and is larger than the line width of other film layers of the initial magnetic tunnel junction 20; S202, forming a dielectric layer 5 on the initial re-deposition layer 3 sidewalls and the lower magnetic layer 211; S203, using the spin-orbit moment layer 1 as an etching stop layer, synchronously etching the initial magnetic tunnel junction 20, the initial redeposited layer 3 and the dielectric layer 5 deposited on the sidewall of the initial magnetic tunnel junction 20 to form a magnetic tunnel junction 2, and reversely sputtering to form a redeposited insulating layer 6 on the sidewall of the magnetic tunnel junction 2, so that the line width of the lower magnetic layer 211 is consistent with the line width of other film layers of the magnetic tunnel junction 2, so as to expose the upper surface of the spin-orbit moment layer 1; In the redeposited insulating layer 6 , the proportion of the dielectric layer 5 is greater than the sum of the proportion of the initial magnetic tunnel junction 20 and the proportion of the initial redeposited layer 3 , so that the redeposited insulating layer 6 is insulated.

[0073] The method for preparing a semiconductor device provided by an embodiment of the present disclosure is adopted, and a second mask layer or a fourth mask layer having a line width smaller than the line width of the initial magnetic tunnel junction is used as a mask for secondary etching. On the one hand, the conductive initial redeposition layer 3 is eliminated, and an insulating redeposition insulating layer 6 is formed, thereby avoiding a short circuit of the magnetic tunnel junction 2. On the other hand, the redeposition insulating layer 6 covers the sidewalls of the magnetic tunnel junction 2, providing a protective function for the magnetic tunnel junction 2, thereby facilitating the improvement of the stability of the magnetic tunnel junction 2. On the third hand, a second mask layer or a fourth mask layer having a line width smaller than the line width of the initial magnetic tunnel junction is used as a mask for secondary etching, so that the size of the magnetic tunnel junction 2 is smaller than the initial magnetic tunnel junction 20, thereby reducing the size of the magnetic tunnel junction 2 and the semiconductor device, improving the flipping efficiency, and reducing the power consumption. In addition, when the size of the magnetic tunnel junction 2 is reduced, the surface magnetic anisotropy energy increases, the multi-domain structure gradually changes to a single domain, and the magnetization direction tends to be unified, thereby improving the performance of the magnetic tunnel junction 2 and the coercive force Hc of the semiconductor device. Fourth, during the initial etching, the spin-orbit moment layer 1 is not etched due to the protection of the lower magnetic layer 211, and therefore the spin-orbit moment layer 1 is only etched once. This helps to reduce the number of etching times for the spin-orbit moment layer 1, thereby avoiding over-etching of the spin-orbit moment layer 1 and protecting the spin-orbit moment layer 1.

[0074] Optionally, the present application proposes at least two methods for implementing step S203, but in practice, these two methods are not limited to the two methods. The following describes these two methods in detail: The first method, refer to Figure 15-17 As shown, the initial magnetic tunnel junction 20, the initial redeposition layer 3 and the dielectric layer 5 deposited on the sidewall of the initial magnetic tunnel junction 20 are simultaneously etched, at least comprising: combining Fig.16 As shown, a second mask layer 42 is formed on the first mask layer 41, and the line width of the second mask layer 42 is smaller than the line width of the initial magnetic tunnel junction 20; Fig.17 As shown, using the second mask layer 42 as a mask, the first mask layer 41, the initial magnetic tunnel junction 20, the initial redeposited material layer 3 and the dielectric layer 5 are simultaneously etched to form a magnetic tunnel junction 2, and a redeposited material insulating layer 6 is formed by reverse sputtering on the side wall of the magnetic tunnel junction 2.

[0075] In this way, a second mask layer 42 having a line width smaller than the initial magnetic tunnel junction 20 is first formed on the first mask layer 41, and then a second etching is performed using the second mask layer 42 as a mask to form a redeposited insulating layer 6 on the sidewall of the magnetic tunnel junction 2, thereby preventing the magnetic tunnel junction 2 from short-circuiting. The size of the obtained magnetic tunnel junction 2 is smaller than or equal to the initial magnetic tunnel junction 20, which is conducive to further reducing the size of the magnetic tunnel junction 2 and the semiconductor device. Reducing the size of the magnetic tunnel junction 2 is conducive to improving the performance of the magnetic tunnel junction 2 and the Hc of the semiconductor device.

[0076] It should be noted that the detailed steps of etching the initial magnetic tunnel junction 20, the dielectric layer 5, and the initial redeposited layer 3 based on the structure of the first mask layer 41 and the second mask layer 42 have been explained in the previous embodiments and will not be repeated here.

[0077] The second method, refer to Figure 18-Figure 22 As shown, the initial magnetic tunnel junction 20, the initial redeposition layer 3 and the dielectric layer 5 deposited on the sidewall of the initial magnetic tunnel junction 20 are simultaneously etched, at least comprising: combining Fig.18 As shown, the first mask layer 41 is removed so that the initial magnetic tunnel junction 20 and the dielectric layer 5 are surrounded by a second groove 412; Figure 19-21 As shown, a third mask layer 43 and a fourth mask layer 44 are sequentially stacked in the second groove 412, and the thickness of the third mask layer 43 is less than half of the line width of the second groove 412; Fig. 22 As shown, the third mask layer 43, the initial magnetic tunnel junction 20, the initial redeposited material layer 3 and the dielectric layer 5 are etched using the fourth mask layer 44 as a mask to form a magnetic tunnel junction 2, and a redeposited material insulating layer 6 is formed by reverse sputtering on the side wall of the magnetic tunnel junction 2.

[0078] In this way, when the third mask layer 43 and the fourth mask layer 44 are sequentially deposited in the second groove 412 formed by the dielectric layer 5 and the initial magnetic tunnel junction 20, the third mask layer 43 covers the bottom and sidewalls of the second groove 412, and the thickness of the third mask layer 43 determines the line width of the third mask layer 43 covering the sidewalls, and the fourth mask layer 44 is deposited between the third mask layer 43 covering the sidewalls and the bottom of the second groove 412, so the line width of the fourth mask layer 44 is the difference between half of the line width of the second groove 412 and the thickness of the third mask layer 43. In this way, the line width of the third mask layer 43 covering the sidewalls can determine the line width of the fourth mask layer 44, and then the line width of the fourth mask layer 44 is determined by the thickness of the third mask layer 43. The fourth mask layer 44 can be used as a mask for etching the initial magnetic tunnel junction 20, the initial redeposition layer 3, and the dielectric layer 5. Therefore, the line width of the fourth mask layer 44 can determine the line width of the magnetic tunnel junction 2, and then the line width of the magnetic tunnel junction 2 can be determined by the thickness of the third mask layer 43. The size of the magnetic tunnel junction 2 can be controlled by a more controllable film forming process, and there is no need to use the CMP process to grind the third mask layer 43 and the fourth mask layer 44 in the second groove, which is conducive to reducing the difficulty of the CMP process and improving the CMP process window, thereby greatly reducing the process difficulty. In addition, in actual application, the thickness of the third mask layer 43 can be increased to reduce the size of the magnetic tunnel junction 2, thereby reducing the size of the semiconductor device. Reducing the size of the magnetic tunnel junction 2 is conducive to improving the performance of the magnetic tunnel junction 2 and the Hc of the semiconductor device.

[0079] It should be noted that the detailed steps for etching the initial magnetic tunnel junction 20, the dielectric layer 5, and the initial redeposited layer 3 based on the structure of the first mask layer 41, the third mask layer 43, and the fourth mask layer 44 have been explained in the previous embodiments and will not be repeated here.

[0080] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof.

Claims

1. A semiconductor device, characterized in that: At least comprising a spin-orbit moment layer, a magnetic tunnel junction, and a redeposited insulating layer covering the side wall of the magnetic tunnel junction, which are stacked in sequence; Wherein, the free layer of the magnetic tunnel junction is arranged adjacent to the spin-orbit moment layer; The magnetic tunnel junction is formed by simultaneously etching an initial magnetic tunnel junction, an initial redeposited layer and a dielectric layer deposited on the sidewall of the initial magnetic tunnel junction, and back sputtering to form the redeposited insulating layer on the sidewall of the magnetic tunnel junction; In the redeposited insulating layer, the proportion of the dielectric layer component is greater than the sum of the proportion of the initial magnetic tunnel junction component and the proportion of the initial redeposited layer component, so that the redeposited insulating layer is insulated.

2. The semiconductor device according to claim 1, wherein: The semiconductor device also includes a mask layer disposed above the magnetic tunnel junction.

3. The semiconductor device according to claim 2, characterized in that The mask layer comprises at least a first mask layer and a second mask layer; The first mask layer is arranged above the magnetic tunnel junction, and a first groove is arranged at the top of the first mask layer. The second mask layer is arranged in the first groove, and the line width of the magnetic tunnel junction is determined by the line width at the top of the first groove.

4. The semiconductor device according to claim 2, characterized in that The mask layer comprises at least a third mask layer and a fourth mask layer; Among them, the height of the dielectric layer is greater than the height of the initial magnetic tunnel junction, so that the two are enclosed to form a second groove, the third mask layer and the fourth mask layer are deposited in the second groove, the third mask layer is arranged above the magnetic tunnel junction, and the fourth mask layer is arranged above the third mask layer, and the line width of the fourth mask layer is determined by the thickness of the third mask layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The free layer is configured as a synthetic antiferromagnetic layer.

6. A method for preparing a semiconductor device, characterized in that: At least the following steps are included: Etching to form an initial magnetic tunnel junction and an initial redeposited layer which is back-sputtered on a sidewall of the initial magnetic tunnel junction above the spin-orbit moment layer, and forming a dielectric layer on a sidewall of the initial redeposited layer; Simultaneously etching the initial magnetic tunnel junction, the initial redeposited layer deposited on the sidewall of the initial magnetic tunnel junction, and the dielectric layer to form a magnetic tunnel junction, and reversely sputtering on the sidewall of the magnetic tunnel junction to form a redeposited insulating layer; Among them, in the redeposited insulating layer, the proportion of the dielectric layer component is greater than the sum of the proportion of the initial magnetic tunnel junction component and the proportion of the initial redeposited layer component, so that the redeposited insulating layer is insulated.

7. The preparation method according to claim 6, characterized in that: Etching on the spin-orbit moment layer to form the initial magnetic tunnel junction comprises at least: Depositing an initial magnetic tunnel junction film layer and a first mask layer in sequence above the spin-orbit moment layer; The initial magnetic tunnel junction film layer is etched using the first mask layer as a mask to form the initial magnetic tunnel junction.

8. The preparation method according to claim 7, characterized in that: Synchronously etching the initial magnetic tunnel junction, the initial redeposited material layer deposited on the sidewall of the initial magnetic tunnel junction, and the dielectric layer, comprising at least: forming a second mask layer above the first mask layer, wherein the line width of the second mask layer is smaller than the line width of the initial magnetic tunnel junction; Using the second mask layer as a mask, the first mask layer, the initial magnetic tunnel junction, the initial redeposited layer and the dielectric layer are simultaneously etched to form the magnetic tunnel junction, and the redeposited insulating layer is formed by reverse sputtering on the sidewall of the magnetic tunnel junction.

9. The preparation method according to claim 8, characterized in that: Forming the second mask layer above the first mask layer at least includes: forming a first groove at the top of the first mask layer, and forming the second mask layer in the first groove; performing a planarization process on the first mask layer and the second mask layer so that the line width of the top of the first groove is less than or equal to the line width of the initial magnetic tunnel junction; The line width of the top of the first groove is determined by the duration of the planarization process and / or the shape of the first groove.

10. The preparation method according to claim 7, characterized in that: Synchronously etching the initial magnetic tunnel junction, the initial redeposited material layer deposited on the sidewall of the initial magnetic tunnel junction, and the dielectric layer, comprising at least: removing the first mask layer so that the initial magnetic tunnel junction and the dielectric layer enclose a second groove; A third mask layer and a fourth mask layer are sequentially stacked in the second groove, and a thickness of the third mask layer is less than half of a line width of the second groove; Using the fourth mask layer as a mask, the third mask layer, the initial magnetic tunnel junction, the initial redeposited layer and the dielectric layer are etched to form the magnetic tunnel junction, and the redeposited insulating layer is formed by reverse sputtering on the sidewall of the magnetic tunnel junction.

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