Test circuit and test method for dynamic resistance of power device

Abstract

The invention provides a test circuit and a test method for dynamic resistance of a power device, and the test circuit comprises a to-be-tested device of which the control end receives a control signal, the first end is connected with the first end of a sampling device, and the second end is connected with a reference ground; the control end of the sampling device receives a control signal, and the second end is connected with the reference ground through the first resistor and serves as a voltage measuring point; the first end of the second resistor is connected with the first end of the to-be-tested device and the first end of the sampling device, and the second end receives the high-voltage signal and serves as a current measuring point; and the measuring module is used for measuring a voltage value at the voltage measuring point and measuring a current value at the current measuring point so as to calculate the dynamic resistance of the to-be-measured device based on the voltage value and the current value. According to the test circuit and the test method for the dynamic resistance of the power device, the problem that the dynamic resistance of a gallium nitride power device cannot be tested in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a test circuit and a test method for dynamic resistance of a power device. Background Art

[0002] As an important representative of the third generation of semiconductor devices, gallium nitride (GaN) power devices have very broad application prospects and market opportunities in the field of high-frequency, high-efficiency, and high-power density power electronic conversion due to their excellent material properties. However, affected by device surface traps and buffer layer traps, the current mainstream GaN power devices still face the problem of dynamic resistance degradation during high-voltage switching, which brings uncertainty to the converter design and loss estimation based on GaN power devices. Therefore, the characterization of the dynamic resistance performance of GaN power devices in high-frequency switching applications has become a hot topic of extensive attention and research in academia and industry in recent years.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a test circuit and a test method for the dynamic resistance of a power device, so as to solve the problem that the dynamic resistance of a gallium nitride power device cannot be tested in the prior art.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a test circuit for dynamic resistance of a power device, the test circuit comprising:

[0006] A device under test, a sampling device, a first resistor, a second resistor and a measuring module;

[0007] The control end of the device under test receives a control signal, the first end of the device under test is connected to the first end of the sampling device, and the second end of the device under test is connected to a reference ground;

[0008] The control end of the sampling device receives the control signal, and the second end of the sampling device is connected to the reference ground via the first resistor and serves as a voltage measurement point;

[0009] The first end of the second resistor is connected to the first end of the device under test and the first end of the sampling device, and the second end of the second resistor receives the high voltage signal and serves as a current measurement point;

[0010] The measuring module measures a voltage value at the voltage measuring point and a current value at the current measuring point, so as to calculate the dynamic resistance of the device under test based on the voltage value and the current value.

[0011] Optionally, the test circuit further includes a third resistor connected between the control terminal and the second terminal of the device under test.

[0012] Optionally, the test circuit further includes a delay module connected between the control signal and the control terminal of the sampling device, and configured to perform delay processing on the control signal.

[0013] Optionally, the delay module includes a fourth resistor and a first diode, the first end of the fourth resistor receives the control signal, the second end of the fourth resistor is connected to the control end of the sampling device, the cathode end of the first diode is connected to the first end of the fourth resistor, and the anode end of the first diode is connected to the second end of the fourth resistor.

[0014] Optionally, the test circuit further includes an absorption module connected to the first end of the device under test and configured to absorb a peak voltage at the first end of the device under test.

[0015] Optionally, the absorption module includes a second diode, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor, the anode end of the second diode is connected to the first end of the device under test, the cathode end of the second diode is connected to the reference ground via the fifth resistor and the first capacitor in sequence, and the sixth resistor and the second capacitor are respectively connected in parallel to the two ends of the fifth resistor.

[0016] Optionally, the test circuit also includes a control module for providing the control signal; wherein the control module includes a signal generator, a seventh resistor, a first transistor and a second transistor, the drive signal output by the signal generator is connected to the base of the first transistor and the base of the second transistor via the seventh resistor, the collector of the first transistor receives a first low-voltage signal, the emitter of the first transistor is connected to the emitter of the second transistor and outputs the control signal, and the collector of the second transistor receives a second low-voltage signal; or, the control module also includes an eighth resistor, which is connected in series between the emitter of the first transistor and the emitter of the second transistor, and at this time, the control signal is output from the connection node between the eighth resistor and the second transistor.

[0017] Optionally, the test circuit also includes a low-voltage module for providing the first low-voltage signal and the second low-voltage signal; wherein the low-voltage module includes a three-channel DC voltage source, a third capacitor and a fourth capacitor, the first channel end of the three-channel DC voltage source is connected to the first end of the third capacitor and serves as the first low-voltage output end, the second channel end of the three-channel DC voltage source is connected to the second end of the third capacitor and the first end of the fourth capacitor and connected to a reference ground, and the third channel end of the three-channel DC voltage source is connected to the second end of the fourth capacitor and serves as the second low-voltage output end.

[0018] Optionally, the test circuit also includes a high-voltage module for providing the high-voltage signal; wherein the high-voltage module includes a two-channel high-voltage DC source and a fifth capacitor, the first channel end of the two-channel high-voltage DC source is connected to the first end of the fifth capacitor and serves as a high-voltage output end, and the second channel end of the two-channel high-voltage DC source is connected to the second end of the fifth capacitor and connected to a reference ground.

[0019] Optionally, when the test circuit further includes an absorption module and the absorption module includes a second diode, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor, the first capacitor is used to replace the fifth capacitor.

[0020] Optionally, the device under test and the sampling device are of the same device type, including a normally-off depletion-mode gallium nitride device, an enhancement-mode gallium nitride device or a super junction MOS device; the ratio of the resistance value of the first resistor to the internal resistance value of the device under test is greater than or equal to 200, the ratio of the resistance value of the first resistor to the internal resistance value of the sampling device is greater than or equal to 100, and the second resistor is implemented in the form of resistors in parallel.

[0021] The present invention also provides a testing method based on the above-mentioned testing circuit, the testing method comprising:

[0022] Adjusting the temperature of the device under test to a preset temperature;

[0023] The voltage value is measured at the voltage measuring point and the current value is measured at the current measuring point by the measuring module, so as to calculate the dynamic resistance of the device under test based on the ratio of the voltage value to the current value.

[0024] Optionally, the testing method further comprises: adjusting the preset temperature, and testing the dynamic resistance of the device under test at different preset temperatures.

[0025] As described above, the test circuit and test method of the dynamic resistance of power devices of the present invention can test the dynamic resistance of power devices such as normally-off depletion-mode gallium nitride devices, enhancement-mode gallium nitride devices, and super junction MOS devices. In addition, the circuit is simple and easy to build, and the test is flexible and convenient with high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of the structure of the test circuit of the present invention.

[0027] Figure 2 Shown is a flow chart of the testing method of the present invention.

[0028] Figure 3 Shown is a schematic diagram of a curve showing the change of the dynamic resistance of the device under test with temperature measured based on the present invention.

[0029] Figure 4 The figure shows the curve of the dynamic resistance normalization coefficient given in the product specification of the device under test changing with temperature.

[0030] Figure 5 Display as Figure 4 Schematic diagram of the corresponding relationship between the normalization coefficient and the dynamic resistance.

[0031] Component number description

[0032] 100 Test Circuit

[0033] 110 Measurement Module

[0034] 120 Delay Module

[0035] 130 Absorption Module

[0036] 140 Control Module

[0037] 141 Signal Generator

[0038] 150 Low voltage module

[0039] 151 Three-channel DC voltage source

[0040] 160 High Voltage Module

[0041] 161 Two-channel high voltage DC source DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] See also Figures 1 to 5It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] like Figure 1 As shown, this embodiment provides a test circuit 100 for dynamic resistance of a power device, including a device under test DUT, a sampling device SQ, a first resistor R1 , a second resistor R2 and a measurement module 110 .

[0045] The control end of the device under test DUT receives the control signal CTL, the first end of the device under test DUT is connected to the first end of the sampling device SQ, and the second end of the device under test DUT is connected to the reference ground. In one embodiment, the device under test DUT includes a normally closed depletion mode (D-MODE) gallium nitride device, an enhancement mode (E-MODE) gallium nitride device or a super junction MOS device. Of course, it is also feasible to include other types of power devices, and there is no limitation on this. Further, the device under test DUT is an N-type device. In this case, the control end is the gate end, the first end is the drain end, and the second end is the source end; when the control signal CTL is at a high level, the device under test DUT is turned on.

[0046] The control end of the sampling device SQ receives the control signal CTL, the first end of the sampling device SQ is connected to the first end of the device under test DUT, and the second end of the sampling device SQ is connected to the reference ground via the first resistor R1 and serves as the voltage measurement point DV. In one embodiment, the sampling device SQ is of the same device type as the device under test DUT, including a normally closed depletion mode (D-MODE) gallium nitride device, an enhancement mode (E-MODE) gallium nitride device or a super junction MOS device. Of course, it is also feasible to include other types of power devices, and there is no limitation on this. Further, the sampling device SQ is an N-type device, in which case the control end is the gate end, the first end is the drain end, and the second end is the source end; when the control signal CTL is at a high level, the sampling device SQ is turned on.

[0047] The first resistor R1 is used as a sampling resistor to sample the drain-source voltage drop of the device under test DUT after it is turned on; wherein the ratio of the resistance value of the first resistor R1 to the internal resistance value of the device under test DUT is greater than or equal to 200, and the ratio of the resistance value of the first resistor R1 to the internal resistance value of the sampling device SQ is greater than or equal to 100, that is, R1 / RDUT≥200, R1 / RSQ≥100, R1 is the resistance value of the first resistor, RDUT is the internal resistance value of the device under test, and RSQ is the internal resistance value of the sampling device. In practical applications, the internal resistance value of the device under test DUT is usually between 50mΩ and 1Ω, and the internal resistance value of the sampling device SQ is usually around 2Ω, therefore, the resistance value of the first resistor R1 can be designed to be above 200Ω, for example, 220Ω.

[0048] The first end of the second resistor R2 is connected to the first end of the device under test DUT and the first end of the sampling device SQ, and the second end of the second resistor R2 receives the high-voltage signal HVDC and serves as the current measurement point DI; wherein the second resistor R2 is used as a current limiting resistor to limit the current flowing through the device under test DUT. In one embodiment, the second resistor R2 is implemented in the form of resistors in parallel. For example, the second resistor R2 is implemented by four resistors R21 to R24 in parallel to reduce power consumption. In this embodiment, the value of the current flowing through the device under test DUT is determined by the voltage value of the high-voltage signal HVDC and the resistance value of the second resistor R2. In actual applications, when the voltage value of the high-voltage signal HVDC is between 100V and 400V, the resistance value of the second resistor R2 is usually designed to be 250Ω. At this time, the second resistor R2 can be implemented by four 1KΩ resistors in parallel.

[0049] The measurement module 110 measures the voltage value V0 at the voltage measuring point DV and measures the current value I0 at the current measuring point DI, so as to calculate the dynamic resistance of the device under test DUT based on the voltage value V0 and the current value I0. In one embodiment, the measurement module 110 includes an oscilloscope, and the voltage value V0 is measured by the voltage probe of the oscilloscope, and the current value I0 is measured by the current probe of the oscilloscope; of course, other devices capable of measuring voltage and current are also feasible. In addition, it is also feasible to measure voltage and current by different devices, and there is no restriction on this. In practical applications, the current value I0 may not be measured by the current measuring point DI, but calculated by the voltage value of the high-voltage signal HVDC and the resistance value of the second resistor R2. At this time, the measurement module 110 only measures the voltage value V0 at the voltage measuring point DV.

[0050] As an optional solution, the test circuit 100 of this embodiment also includes a third resistor R3, which is connected between the control end and the second end of the device under test DUT, that is, the first end of the third resistor R3 is connected to the control end of the device under test DUT, and the second end of the third resistor R3 is connected to the second end of the device under test DUT; wherein the third resistor R3 is used as a pull-down resistor of the device under test DUT to prevent the device under test DUT from being mistakenly turned on; in actual applications, the resistance value of the third resistor R3 is usually selected to be 10KΩ.

[0051] As an optional solution, the test circuit 100 of this embodiment also includes a delay module 120, which is connected between the control signal CTL and the control end of the sampling device SQ, and is used to delay the control signal CTL and provide it to the sampling device SQ, so that the sampling device SQ is turned on after the device under test DUT is fully turned on, so as to avoid affecting the test of the dynamic resistance of the device under test DUT. In one embodiment, the delay module 120 includes a fourth resistor R4 and a first diode D1; wherein the first end of the fourth resistor R4 receives the control signal CTL, the second end of the fourth resistor R4 is connected to the control end of the sampling device SQ, the cathode end of the first diode D1 is connected to the first end of the fourth resistor R4, and the anode end of the first diode D1 is connected to the second end of the fourth resistor R4. In the above-mentioned delay module 120, the delay time of the control signal CTL is determined by the resistance value of the fourth resistor R4; in actual applications, the resistance value of the fourth resistor R4 is usually selected as 100Ω, so as to reasonably design the delay time and ensure that the sampling device SQ is turned on immediately after the device under test DUT is fully turned on.

[0052] As an optional solution, the test circuit 100 of this embodiment also includes an absorption module 130, which is connected to the first end of the device under test DUT and is used to absorb the peak voltage of the first end of the device under test DUT. In one embodiment, the absorption module 130 includes a second diode D2, a fifth resistor R5, a sixth resistor R6, a first capacitor C1 and a second capacitor C2; wherein the anode end of the second diode D2 is connected to the first end of the device under test DUT, the cathode end of the second diode D2 is connected to the reference ground via the fifth resistor R5 and the first capacitor C1 in sequence, and the sixth resistor R6 and the second capacitor C2 are respectively connected in parallel to the two ends of the fifth resistor R5; in actual applications, the resistance value of the fifth resistor R5 is usually selected as 100KΩ, the resistance value of the sixth resistor R6 is usually selected as 100KΩ, the capacitance value of the first capacitor C1 is usually selected as 10μF, and the capacitance value of the second capacitor C2 is usually selected as 2200pF.

[0053] As an optional solution, the test circuit 100 of this embodiment further includes a control module 140 for providing a control signal CTL to the device under test DUT and the sampling device SQ to facilitate switch control. In one embodiment, the control module 140 includes a signal generator 141, a seventh resistor R7, a first transistor Q1 and a second transistor Q2; wherein the signal generator 141 is used to provide a driving signal, and the driving signal output by the signal generator 141 is connected to the base of the first transistor Q1 and the base of the second transistor Q2 via the seventh resistor R7, the collector of the first transistor Q1 receives the first low-voltage signal LVDC1, the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2 and outputs the control signal CTL, and the collector of the second transistor Q2 receives the second low-voltage signal LVDC2; in the above embodiment, the first transistor Q1 and the second transistor Q2 form a totem pole structure, when the driving signal is high level, the output control signal CTL is high level, and when the driving signal is low level, the output control signal CTL is low level. Further, the control module 140 also includes an eighth resistor R8, which is connected in series between the emitter of the first transistor Q1 and the emitter of the second transistor Q2. At this time, the control signal CTL is output by the connection node of the eighth resistor R8 and the second transistor Q2, that is, the first end of the eighth resistor R8 is connected to the emitter of the first transistor Q1, and the second end of the eighth resistor R8 is connected to the emitter of the second transistor Q2 and outputs the control signal CTL; by adding the eighth resistor R8, the purpose of anti-interference can be achieved. In practical applications, the resistance value of the seventh resistor R7 is usually selected as 47Ω, and the resistance value of the eighth resistor R8 is usually selected as 10Ω.

[0054] As an optional solution, the test circuit 100 of this embodiment further includes a low voltage module 150, which is used to provide a first low voltage signal LVDC1 and a second low voltage signal LVDC2 to the control module 140. In one implementation, the low voltage module 150 includes a three-channel DC voltage source 151, a third capacitor C3, and a fourth capacitor C4; wherein the first channel end of the three-channel DC voltage source 151 is connected to the first end of the third capacitor C3 and serves as a first low voltage output end to output the first low voltage signal LVDC1, the second channel end of the three-channel DC voltage source 151 is connected to the second end of the third capacitor C3 and the first end of the fourth capacitor C4 and connected to the reference ground, and the third channel end of the three-channel DC voltage source 151 is connected to the second end of the fourth capacitor C4 and serves as a second low voltage output end to output the second low voltage signal LVDC2. In the three-channel DC voltage source 151, the first channel end provides a positive voltage, the second channel end provides a ground voltage, and the third channel end provides a negative voltage. Different combinations of low-voltage signal outputs can be achieved based on channel selection. For example, if the first channel end and the second channel end are selected to be effective, the first low-voltage signal LVDC1 is a positive voltage and the second low-voltage signal LVDC2 is a ground voltage. If the first channel end and the third channel end are selected to be effective, the first low-voltage signal LVDC1 is a positive voltage and the second low-voltage signal LVDC2 is a negative voltage. Which combination of low-voltage signal outputs is specifically selected is determined by the type of the device under test DUT. For example, when the device under test DUT is a normally closed depletion mode (D-MODE) gallium nitride device or a super junction MOS device, selecting the first channel end and the second channel end of the three-channel DC voltage source 151 is effective. When the device under test DUT is an enhancement mode (E-MODE) gallium nitride device, selecting the first channel end and the third channel end of the three-channel DC voltage source 151 is effective. In practical applications, the voltage range provided by the three-channel DC voltage source 151 is between -30V and +30V, and the capacitance of the third capacitor C3 is usually selected as 1 μF, and the capacitance of the fourth capacitor C4 is usually selected as 1 μF.

[0055] As an optional solution, the test circuit 100 of this embodiment further includes a high voltage module 160 for providing a high voltage signal HVDC to the second resistor R2. In one embodiment, the high voltage module 160 includes a two-channel high voltage DC source 161 and a fifth capacitor C5 (not shown in the figure); wherein the first channel end of the two-channel high voltage DC source 161 is connected to the first end of the fifth capacitor C5 and serves as a high voltage output end to output the high voltage signal HVDC, and the second channel end of the two-channel high voltage DC source 161 is connected to the second end of the fifth capacitor C5 and connected to the reference ground. When the test circuit 100 of this embodiment includes an absorption module 130 and the absorption module 130 includes a second diode D2, a fifth resistor R5, a sixth resistor R6, a first capacitor C1 and a second capacitor C2, the first capacitor C1 is used to replace the fifth capacitor C5. At this time, the absorption module 130 and the high voltage module 160 share the first capacitor C1, and the high voltage module 160 no longer includes the fifth capacitor C5; in actual applications, the voltage range provided by the two-channel high voltage DC source 161 is between 0V and 600V.

[0056] It should be noted that when the above-mentioned optional schemes are applied to this embodiment, any one of the third resistor R3, delay module 120, absorption module 130, control module 140, low voltage module 150, and high voltage module 160 can be applied to this embodiment, or at least two of them can be applied to this embodiment. The selection should be based on specific needs and there is no limitation on this.

[0057] like Figure 2 As shown, this embodiment also provides a testing method implemented based on the testing circuit 100 as described above, including the following steps.

[0058] Step S1, adjust the temperature of the device under test DUT to a preset temperature, that is, adjust the device junction temperature of the device under test DUT to a preset temperature; temperature adjustment of the device under test DUT alone can avoid the influence of temperature change on other parts of the test circuit 100. In practical applications, the device under test DUT can be heated alone by a heating device to achieve temperature adjustment of the device under test DUT; if necessary, a temperature measuring device such as a thermocouple can be installed on the surface of the device under test DUT to measure the temperature, so as to achieve accurate temperature adjustment.

[0059] In step S2 , the measuring module 110 measures a voltage value V0 at the voltage measuring point DV and a current value I0 at the current measuring point DI, so as to calculate the dynamic resistance of the device under test DUT based on the ratio of the voltage value V0 to the current value I0 .

[0060] Combination Figure 1It can be known that during the test process, when the control signal CTL is at a high level, the device under test DUT and the sampling device SQ are turned on; since the device under test DUT and the sampling device SQ are connected in parallel, the internal resistance RDUT of the device under test DUT and the internal resistance RSQ of the sampling device SQ are connected in parallel. At this time:

[0061] The first resistor R1 and the internal resistance RSQ of the sampling device SQ are connected in series. Since RSQ << R1, the internal resistance of the sampling device SQ can be ignored; the first resistor R1 and the internal resistance RDUT of the device under test DUT are connected in parallel, and the voltages are equal. Therefore, the voltage across the first resistor R1 (i.e., the voltage value at the voltage measurement point) is the drain-source voltage drop across the device under test DUT; and since RDUT << R1, all the current flows through the device under test DUT, and the current value at the current measurement point is the current flowing through the device under test DUT; thus, the dynamic resistance of the device under test DUT can be calculated based on the ratio of the voltage value V0 to the current value I0.

[0062] In practical applications, the current flowing through the device under test DUT may not need to be measured by the current measurement point DI, but can be calculated through the voltage value of the high-voltage signal HVDC and the resistance value of the second resistor R2. At this time, the measurement module 110 only needs to measure the voltage value V0 at the voltage measurement point DV.

[0063] As an alternative solution, the test method of this embodiment further includes step S3, adjusting the preset temperature, and testing the dynamic resistance of the device under test DUT at different preset temperatures, that is, repeating steps S1 and S2 to implement the dynamic resistance test of the device under test DUT at different preset temperatures, so as to verify the dynamic performance of the device under test DUT.

[0064] Based on the test circuit and test method of this embodiment, the dynamic resistance of the device under test DUT is tested to illustrate the feasibility of the solution of this embodiment.

[0065] When the device under test DUT is a normally closed depletion-mode (D-MODE) gallium nitride device or a superjunction MOS device: the three-channel DC voltage source 151 selects the first channel terminal and the second channel terminal to be effective, where LVDC1 = 10V, LVDC2 = GND, HVDC = 100V - 400V, and the amplitude of the drive signal output by the signal generator 141 is 10V, the duty cycle is 1%, and the frequency is 100Hz; thus, based on the above test conditions, the dynamic resistance test of the device under test DUT is completed.

[0066] When the device under test DUT is an enhanced mode (E-MODE) gallium nitride device: the three-channel DC voltage source 151 selects the first channel end and the third channel end to be effective, wherein LVDC1=10V, LVDC2=-2V, HVDC=100V~400V, and the signal generator 141 outputs a driving signal with an amplitude of 10V, a duty cycle of 1%, and a frequency of 100Hz; thus, based on the above test conditions, the dynamic resistance test of the device under test DUT is completed.

[0067] Taking the DUT as a normally closed depletion mode (D-MODE) GaN device as an example, the curve of dynamic resistance versus temperature measured at HVDC = 100V is as follows: Figure 3 shown; from Figure 3 It can be seen that the dynamic resistance measured at 25°C is about 240mΩ, and the dynamic resistance measured at 150°C is about 470mΩ, which is close to the specifications provided by the manufacturer (the specifications give: the dynamic resistance at 25°C is 240mΩ, and the dynamic resistance at 150°C is 492mΩ, such as Figure 4 and Figure 5 As shown); it can be seen that it is feasible to perform dynamic resistance testing on the device under test DUT based on the test circuit and test method of this embodiment.

[0068] In summary, the test circuit and test method of the dynamic resistance of a power device of the present invention can test the dynamic resistance of power devices such as normally-off depletion-mode gallium nitride devices, enhancement-mode gallium nitride devices, and superjunction MOS devices, and the circuit is simple and easy to build, and the test is flexible and convenient with high accuracy. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A test circuit for dynamic resistance of a power device, characterized in that: The test circuit comprises: A device under test, a sampling device, a first resistor, a second resistor and a measuring module; The control end of the device under test receives a control signal, the first end of the device under test is connected to the first end of the sampling device, and the second end of the device under test is connected to a reference ground; The control end of the sampling device receives the control signal, and the second end of the sampling device is connected to the reference ground via the first resistor and serves as a voltage measurement point; The first end of the second resistor is connected to the first end of the device under test and the first end of the sampling device, and the second end of the second resistor receives the high voltage signal and serves as a current measurement point; The measuring module measures a voltage value at the voltage measuring point and a current value at the current measuring point, so as to calculate the dynamic resistance of the device under test based on the voltage value and the current value.

2. The power device dynamic resistance test circuit according to claim 1, characterized in that: The test circuit further includes a third resistor connected between the control terminal and the second terminal of the device under test.

3. The test circuit for dynamic resistance of a power device according to claim 1, characterized in that: The test circuit also includes a delay module connected between the control signal and the control end of the sampling device, and used for delaying the control signal.

4. The power device dynamic resistance test circuit according to claim 3, characterized in that: The delay module includes a fourth resistor and a first diode, the first end of the fourth resistor receives the control signal, the second end of the fourth resistor is connected to the control end of the sampling device, the cathode end of the first diode is connected to the first end of the fourth resistor, and the anode end of the first diode is connected to the second end of the fourth resistor.

5. The test circuit of the dynamic resistance of a power device according to claim 1, characterized in that: The test circuit further comprises an absorption module connected to the first end of the device under test and used for absorbing the peak voltage at the first end of the device under test.

6. The power device dynamic resistance test circuit according to claim 5, characterized in that: The absorption module includes a second diode, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor. The anode end of the second diode is connected to the first end of the device under test, and the cathode end of the second diode is connected to the reference ground via the fifth resistor and the first capacitor in sequence. The sixth resistor and the second capacitor are respectively connected in parallel to the two ends of the fifth resistor.

7. The power device dynamic resistance test circuit according to claim 1, characterized in that: The test circuit also includes a control module for providing the control signal; wherein the control module includes a signal generator, a seventh resistor, a first transistor and a second transistor, the drive signal output by the signal generator is connected to the base of the first transistor and the base of the second transistor via the seventh resistor, the collector of the first transistor receives a first low-voltage signal, the emitter of the first transistor is connected to the emitter of the second transistor and outputs the control signal, and the collector of the second transistor receives a second low-voltage signal; or, the control module also includes an eighth resistor, which is connected in series between the emitter of the first transistor and the emitter of the second transistor, and at this time, the control signal is output from the connection node between the eighth resistor and the second transistor.

8. The test circuit for dynamic resistance of a power device according to claim 7, characterized in that: The test circuit also includes a low-voltage module for providing the first low-voltage signal and the second low-voltage signal; wherein the low-voltage module includes a three-channel DC voltage source, a third capacitor and a fourth capacitor, the first channel end of the three-channel DC voltage source is connected to the first end of the third capacitor and serves as a first low-voltage output end, the second channel end of the three-channel DC voltage source is connected to the second end of the third capacitor and the first end of the fourth capacitor and connected to a reference ground, and the third channel end of the three-channel DC voltage source is connected to the second end of the fourth capacitor and serves as a second low-voltage output end.

9. The power device dynamic resistance test circuit according to any one of claims 1 to 8, characterized in that: The test circuit also includes a high-voltage module for providing the high-voltage signal; wherein the high-voltage module includes a two-channel high-voltage DC source and a fifth capacitor, the first channel end of the two-channel high-voltage DC source is connected to the first end of the fifth capacitor and serves as a high-voltage output end, and the second channel end of the two-channel high-voltage DC source is connected to the second end of the fifth capacitor and connected to a reference ground.

10. The power device dynamic resistance test circuit according to claim 9, characterized in that: When the test circuit further includes an absorption module and the absorption module includes a second diode, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor, the first capacitor is used to replace the fifth capacitor.

11. The test circuit of the dynamic resistance of a power device according to claim 1, characterized in that: The device type of the device under test is the same as that of the sampling device, including a normally-off depletion-mode gallium nitride device, an enhancement-mode gallium nitride device or a super junction MOS device; the ratio of the resistance value of the first resistor to the internal resistance value of the device under test is greater than or equal to 200, the ratio of the resistance value of the first resistor to the internal resistance value of the sampling device is greater than or equal to 100, and the second resistor is implemented in the form of resistors in parallel.

12. A test method implemented based on the test circuit according to any one of claims 1 to 11, characterized in that: The test method includes: Adjusting the temperature of the device under test to a preset temperature; The voltage value is measured at the voltage measuring point and the current value is measured at the current measuring point by the measuring module, so as to calculate the dynamic resistance of the device under test based on the ratio of the voltage value to the current value.

13. The testing method according to claim 12, characterized in that: The testing method further includes: adjusting the preset temperature, and testing the dynamic resistance of the device under test at different preset temperatures.

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