A cross-memory page difference compatible operation method based on memory access instruction reconstruction

Abstract

The present invention discloses a cross-memory page difference compatible operation method based on memory access instruction reconstruction. By modifying the dynamic instruction conversion engine (DIT) or dynamic binary translation engine of the target system, when executing an executable file compiled and generated by a source system, for memory access instructions that do not meet the memory page size requirements of the target system, the memory access instructions are reconstructed in the conversion process by modifying address offset parameters or using instruction combination replacement, thereby realizing the compatible operation of executable files in systems with memory page differences without source code.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer software development, and in particular relates to a cross-memory page difference compatible operation method based on memory access instruction reconstruction. Background Art

[0002] Memory page is a mechanism used to manage memory in computer operating systems. It divides physical memory into fixed-size blocks, each of which is called a memory page. The size of a memory page depends on the design of the operating system and the hardware architecture. Common memory page sizes include 4K, 16K, 2MB, 1GB, etc. In an operating system with a memory page size of 4K, operations such as memory allocation and address mapping are performed in units of 4K; while in an operating system with a memory page size of 16K, it is performed in units of 16K. When an executable file is running, it may involve operations such as memory allocation, loading library files, and dynamic memory management, which may be affected in operating systems with different memory page sizes. Specifically, when an executable file is compiled in an operating system with a memory page size of 4K, the compiler and linker will generate code and data layout based on the assumption of 4K memory pages. For example, pointer offsets and memory alignment in the code may be set according to the granularity of 4K memory pages.

[0003] However, when the executable file needs to be executed in a target operating system with a different memory page size from the operating system on which it was compiled, execution exceptions may occur due to the difference in memory page size. Usually, the best solution available is to recompile the executable file on a target operating system with a memory page size of 16K, so that the compiler and linker can be optimized according to the memory page characteristics of the target operating system to ensure that the program can fully utilize the memory management mechanism of the target operating system. However, this method requires the complete source code of the executable file, which is difficult to achieve in many cases. Summary of the invention

[0004] In view of this, the present invention provides a cross-memory page difference compatible operation method based on memory access instruction reconstruction, which realizes the compatible operation of executable files in a system with memory page differences without source code.

[0005] The present invention provides a cross-memory page difference compatible operation method based on memory access instruction reconstruction, which specifically includes the following steps:

[0006] Step 1: Execute the executable file compiled by the source system on the target system, and the first memory page size of the source system is different from the second memory page size of the target system;

[0007] Step 2, perform dynamic instruction conversion on the executable file, record the memory access instruction in each basic block as the target instruction, extract the address offset in the target instruction parameter and record it as the first address offset, if the type of the first address offset is an immediate value, execute step 3, if the type of the first address offset is a register, obtain the name of the register and record it as the target register to execute step 5;

[0008] Step 3: For the first address offset that is divisible by the first memory page size, 2 n times as the intermediate address offset. If the length of the intermediate address offset exceeds the parameter length limit of the target instruction, execute step 4; otherwise, execute step 6;

[0009] Step 4: If there is an instruction with the same semantics as the target instruction and supporting a parameter length not less than the length of the intermediate address offset, the intermediate address offset is used as the second address offset, and the target instruction and the first address offset are replaced by the instruction and the second address offset, and step 6 is executed; otherwise, the target instruction is replaced by the first instruction combination consisting of the save instruction and the indirect addressing instruction, and step 6 is executed;

[0010] Step 5, reverse decompile from the target instruction to the first instruction that modifies the target register, record the instruction as the first instruction, if the first instruction is in the loop body, use the end instruction of the loop body as the marking instruction, otherwise use the first instruction as the marking instruction; insert a call instruction of the register value repair function after the marking instruction, wherein the register value repair function takes the target register as an input parameter, reads the value in the target register, and converts the value to be aligned based on the second memory page size when the value is aligned based on the first memory page size;

[0011] Step 6: Complete the conversion of all memory access instructions in the executable file to obtain target code that can run on the target system.

[0012] Furthermore, the first memory page size is 4K.

[0013] Furthermore, the cross-memory page difference compatible operation method also includes:

[0014] Step 3.1 registers a first exception handling function at the execution entry of the target code. When a memory alignment exception occurs during the execution of the target code, the instruction that generates the exception is recorded as an exception instruction, and the address offset of the instruction is recorded as the exception address offset. The first exception handling function records 2 of the exception address offset as the exception address offset. n times as the repair address offset. If the length of the repair address offset is greater than the parameter length limit of the exception instruction, execute step 3.2; otherwise, convert the exception address offset to the repair address offset, and execute from the exception address offset after the exception is restored;

[0015] Step 3.2, replace the abnormal instruction with the second instruction combination consisting of the save instruction and the indirect addressing instruction. When the length of the second instruction combination is greater than the length of the abnormal instruction, execute step 3.3. When it is equal, write the second instruction combination to the address corresponding to the abnormal address offset. When it is less than the length, add a ‌NOP instruction after the second instruction combination and write it to the address corresponding to the abnormal address offset. After recovering from the abnormality, execute from the abnormal address offset.

[0016] Step 3.3, establish a target instruction cache, the length of the target instruction cache is the sum of the length of the second instruction combination and the length of the first jump instruction, write the second instruction combination and the first jump instruction into the target instruction cache, the jump target address of the first jump instruction is the sum of the exception address offset and the exception instruction length; if the length of the exception instruction is not less than the length of the second jump instruction, write the second jump instruction and the corresponding ‌NOP instruction at the exception address offset, the jump target address of the second jump instruction is the address of the target instruction cache, and execute from the address of the target instruction cache after recovering from the exception; otherwise, directly recover from the exception and execute from the address of the target instruction cache.

[0017] Furthermore, a mapping relationship between the abnormal instruction and the address of the target instruction cache is established, and the abnormal instruction is recovered according to the mapping relationship and then executed from the address of the target instruction cache.

[0018] Furthermore, in step 4, the first instruction combination consists of instructions required to split the intermediate address offset.

[0019] Furthermore, the first instruction combination consists of a MOV instruction and an ORR instruction. Beneficial Effects

[0020] 1. The present invention modifies the dynamic instruction translation engine (DIT) or dynamic binary translation engine of the target system. When executing an executable file compiled by a source system, for memory access instructions that do not meet the memory page size requirements of the target system, the memory access instructions are reconstructed by modifying address offset parameters or using instruction combination replacement during the conversion process, thereby achieving compatible operation of executable files in systems with memory page differences without source code.

[0021] 2. The present invention adds a memory access exception processing mechanism to the converted target code to realize the memory access instruction reconstruction of the dynamically generated code, and further improves the reliability of the compatible operation of the executable file in the system with memory page differences. DETAILED DESCRIPTION

[0022] The present invention is described in detail with reference to the following embodiments.

[0023] The present invention provides a cross-memory page difference compatible operation method based on memory access instruction reconstruction, the core idea of ​​which is: by modifying the dynamic instruction conversion engine (DIT) or dynamic binary translation engine of the target system, when executing the executable file compiled and generated by the source system, for the memory access instructions that do not meet the memory page size requirements of the target system, the memory access instructions are reconstructed in the conversion process by modifying the address offset parameters or using instruction combination replacement, etc., so that the executable file can be compatible with the system with memory page differences without source code. In addition, in order to further improve the reliability of compatible operation, a memory access exception processing mechanism is added to the target code to realize the memory access instruction reconstruction of the dynamically generated code.

[0024] The present invention provides a cross-memory page difference compatible operation method based on memory access instruction reconstruction, which specifically includes the following steps:

[0025] Step 1: record the operating system that completes the compilation of the executable file as the source system, record the operating system that needs to execute the executable file as the target system, the memory page size of the target system is different from that of the source system, record the memory page size of the source system as the first memory page size, and record the memory page size of the target system as the second memory page size.

[0026] Specifically, the memory page size of the source system may be 4K.

[0027] Step 2, execute the executable file in the target system, perform dynamic instruction conversion on the executable file, traverse the instructions in each basic block to obtain the memory access instruction and record it as the target instruction, extract the address offset in the target instruction parameter and record it as the first address offset, if the type of the first address offset is an immediate number, execute step 3, if the type of the first address offset is a register, obtain the name of the register and record it as the target register to execute step 5.

[0028] Among them, traversing the instructions in each basic block to obtain the memory access instruction can be achieved by modifying the dynamic instruction conversion engine (DIT) or the dynamic binary translation engine in the target system.

[0029] Step 3: For the first address offset that is divisible by the first memory page size, convert 2 of the first address offset n Times as the intermediate address offset. If the length of the intermediate address offset exceeds the parameter length limit of the target instruction, execute step 4; otherwise, use the intermediate address offset as the second address offset of the target system obtained by conversion, and execute step 6.

[0030] Step 4. Search the instruction set to see if there is an instruction with the same semantics as the target instruction and supporting a parameter length not less than the length of the intermediate address offset. If so, use the intermediate address offset as the second address offset, and use the instruction and the second address offset to replace the target instruction and the first address offset; otherwise, split the memory access instruction into a save instruction for saving the immediate value to the register and an indirect addressing instruction, that is, first save the intermediate address offset to the register and then use the indirect addressing instruction to perform the memory access operation according to the value in the register, and use the first instruction combination consisting of the save instruction and the indirect addressing instruction to replace the target instruction.

[0031] The intermediate address offset is decomposed, and the low-order and high-order data are loaded respectively using a first instruction combination consisting of multiple instructions, and the target instruction and the first address offset are replaced by the first instruction combination and the corresponding decomposed intermediate address offset, and then step 6 is executed.

[0032] In addition, the memory access instruction can be split into instructions for saving immediate values ​​in registers and indirect addressing instructions, that is, the intermediate address offset is first saved in the register and then the indirect addressing instruction is used to perform the memory access operation according to the value in the register.

[0033] Among them, the intermediate address offset is too long, that is, it cannot be directly processed by one instruction, and it can be decomposed. For example, in the ARM architecture, the MOV instruction can be used to load the lower 8 bits of the immediate value, and then the ORR or BIC instruction can be used to combine the upper 8 bits of the immediate value.

[0034] Step 5: reverse decompile from the target instruction to the first instruction that modifies the target register, record the instruction as the first instruction, and if the first instruction is in the loop body, use the end instruction of the loop body as the marking instruction, otherwise use the first instruction as the marking instruction; insert the call instruction of the register value repair function after the marking instruction. The register value repair function takes the target register as an input parameter, reads the value in the target register, and converts the value to the second memory page size alignment when the value is based on the first memory page size alignment.

[0035] Furthermore, in order to avoid omissions in the above-mentioned address offset processing process and unprocessed memory access instructions in the dynamically generated code, the present invention adds a memory access exception processing function to the target code obtained by the above-mentioned processing process to ensure the normal execution of memory access instructions in the target system.

[0036] Step 6: Complete the dynamic instruction conversion to obtain the target code, register the first exception handling function at the execution entry of the target code, and when a memory alignment exception occurs during the execution of the target code, the first exception handling function obtains the instruction that generates the exception and records it as the exception instruction, and records the address offset of the instruction as the exception address offset; and registers the first exception handling function as the exception instruction. n Times as the repair address offset. If the length of the repair address offset is greater than the parameter length limit of the exception instruction, execute step 7; otherwise, convert the exception address offset into the repair address offset.

[0037] Step 7, use the second instruction combination and the corresponding decomposed repair address offset to replace the abnormal instruction and the abnormal address offset; when the length of the second instruction combination is greater than the length of the abnormal instruction, execute step 8; when the length of the second instruction combination is equal to the length of the abnormal instruction, write the second instruction combination to the address corresponding to the abnormal address offset; when the length of the second instruction combination is less than the length of the abnormal instruction, add a ‌NOP instruction after the second instruction combination; execute from the abnormal address offset after recovering from the exception.

[0038] Step 8, establish a target instruction cache, the length of the target instruction cache is the sum of the length of the second instruction combination and the length of the jump instruction, and write the second instruction combination and the first jump instruction into the target instruction cache, the jump target address of the jump instruction is the sum of the exception address offset and the length of the exception instruction; if the length of the exception instruction is not less than the length of the jump instruction, write the second jump instruction and the corresponding ‌NOP instruction at the exception address offset, the jump target address of the second jump instruction is the address of the target instruction cache, and execute from the address of the target instruction cache after recovering from the exception; otherwise, directly recover from the address of the target instruction cache after recovering from the exception.

[0039] Since an exception is triggered each time the target code is executed to the exception address offset, in order to further improve execution efficiency, the present invention can also establish a mapping relationship between the exception instruction and the address of the target instruction cache, so as to achieve a rapid jump to the target instruction cache for execution after the exception is triggered. Example

[0040] In this embodiment, a cross-memory page difference compatible operation method based on memory access instruction reconstruction provided by the present invention is adopted to realize the compatible operation of an executable file from a source system with a memory page size of 4K to a target system with a memory page size of 16K, which specifically includes the following steps:

[0041] In this embodiment, COMPILING_OS_PAGE is the first memory page size, and RUNNING_OS_PAGE is the second memory page size.

[0042] S1. Modify the basic block conversion module of the DIT engine, traverse each instruction of each basic block, analyze the memory access instructions, and recalculate parameters such as address offset according to the current system memory page size 16K. Each instruction of each basic block is recorded as instr and judged. If instr is a read / write memory instruction, the type of address offset is judged. If the address offset is an immediate value, execute S2. If the address offset is stored in a register, execute S5.

[0043] It can be seen from the existing addressing methods that there are only two ways to express the address offset of the memory access instruction. One is to save the address offset in a register, and the other is that the address offset itself is a constant, that is, an immediate value.

[0044] S2. Extract the address offset and record it as the value of offset. For example, in the instruction mov eax, [ebx + 0x1000], 0x1000 is the value of the constant offset. Determine whether this constant offset offset is based on COMPILING_OS_PAGE, that is, determine whether offset is an integer multiple of COMPILING_OS_PAGE, that is, whether offset % COMPILING_OS_PAGE is equal to zero. If it is zero, execute S3, otherwise execute S5.

[0045] S3. Convert the constant offset to the RUNNING_OS_PAGE memory page format. Generally, it needs to be increased by 2 of the original value. n times.

[0046] S4. Convert and generate the address offset in the target code. That is, when writing the DIT to write the current instruction into the target code buffer, the offset has been changed to a multiple of RUNNING_OS_PAGE. The specific steps are as follows:

[0047] Different instruction set architectures may handle memory access instructions and address offsets differently. For example, in some RISC instruction set architectures, such as ARM, the address offset of the memory access instruction may be in a specific encoding format or bit width limit. Therefore, when performing address offset conversion, it is necessary to ensure that the converted address offset can correctly adapt to the target instruction set architecture. If the converted address offset exceeds the range allowed by the instruction, determine whether there is an instruction that supports a longer address offset (adjusted offset). If so, modify the opcode of the target instruction to that instruction; otherwise, split the memory access instruction and use indirect addressing to access the memory by storing the offset in a register and then using indirect addressing instructions to access the memory.

[0048] S5. If the address offset is a value in a register, which is provided by the register when it is running, the register is recorded as offsetReg, and the change of the value in the register is tracked. Starting from the current instruction, reverse decompile to the instruction that modifies offsetReg closest to the current instruction, and perform the following steps:

[0049] During the decompilation process, the basic block is analyzed to determine whether this instruction is in the loop body. If this instruction is in the loop body, the value of the register is obtained through loop calculation. In the loop structure, the register may be updated according to the change of the loop variable. In this case, the register value repair function cannot be inserted directly after the offsetReg instruction is modified. Instead, the end instruction of the loop needs to be found through basic block analysis after this instruction, and the call instruction of the register value repair function is inserted after the loop end instruction; otherwise, the call instruction of the register value repair function is directly inserted after this instruction.

[0050] The input parameter of the register value repair function is offsetReg. When the register value repair function is called, it is determined in real time whether the value of offsetReg is based on COMPILING_OS_PAGE alignment. If so, it is converted to RUNNING_OS_PAGE alignment; if not, it is not processed.

[0051] S6. At the very beginning of the target code instruction execution, that is, the entry point where the converted code starts to execute, insert a memory access exception processing function to handle the memory alignment exception to prevent omissions in the previous instruction address offset processing, such as the dynamically generated code not being converted. The specific steps are as follows:

[0052] S6.1. Register an exception handling function. In Linux, call signal(SIGBUS, handle_memory_alignment_exception). handle_memory_alignment_exception is the memory alignment exception handling function. SIGBUS exceptions include more than just alignment exceptions.

[0053] S6.2. The steps performed in handle_memory_alignment_exception are as follows:

[0054] The SIGBUS signal has an associated si_code value, which provides the specific cause of the error. For memory alignment issues, the value of si_code is usually BUS_ADRALN, which means invalid address alignment.

[0055] Determine whether the current exception is a memory alignment exception. If it is a memory alignment exception, then:

[0056] Get the instruction address where the exception occurs, record it as exceptionAddress, extract the corresponding instruction, record it as exceptionInstruction, and generate the target instruction aligned according to RUNNING_OS_PAGE, record it as alignedInstructions, according to the method of processing instruction address operands in S1 and S2;

[0057] Among them, alignedInstructions may have more than one instruction, that is, exceptionInstruction will be split into multiple instructions, so the length of alignedInstructions may be longer than exceptionInstruction, then perform the following judgment:

[0058] S6.2.1. If the length of alignedInstructions is longer than exceptionInstruction, a target instruction buffer is generated, denoted as targetInstrBuffer, whose length is the length of alignedInstructions plus the length of a jump instruction;

[0059] S6.2.2. Write alignedInstructions into targetInstrBuffer and add a jump instruction after it. The target address of the jump instruction is exceptionAddress+length(exceptionInstruction);

[0060] S6.2.3. Determine whether length(exceptionInstruction) is less than the length of the jump instruction. If it is, write a jump instruction at exceptionAddress, followed by the corresponding NOP instruction. The target address of the jump instruction is targetInstrBuffer.

[0061] Resume the execution of the exception. The execution address after the exception is resumed is exceptionAddress. If it is less than, resume the execution of the exception. The execution address after the exception is resumed is targetInstrBuffer.

[0062] In this case, each execution to exceptionAddress may trigger an exception, so a mapping from exceptionInstruction to targetInstrBuffer can be established, so that decoding and target code generation do not need to be performed every time.

[0063] Otherwise, if the length of alignedInstructions is less than or equal to exceptionInstruction, then:

[0064] Write alignedInstructions to the location of exceptionInstruction, that is, exceptionAddress. If the length of alignedInstructions is less than exceptionInstruction, fill in the corresponding NOP instruction after alignedInstructions.

[0065] Resume the execution of the exception. The execution address after the exception is resumed is exceptionAddress.

[0066] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A cross-memory page difference compatible operation method based on memory access instruction reconstruction, characterized in that: The specific steps include: Step 1: Execute the executable file compiled by the source system on the target system, and the first memory page size of the source system is different from the second memory page size of the target system; Step 2, perform dynamic instruction conversion on the executable file, record the memory access instruction in each basic block as the target instruction, extract the address offset in the target instruction parameter and record it as the first address offset, if the type of the first address offset is an immediate value, execute step 3, if the type of the first address offset is a register, obtain the name of the register and record it as the target register to execute step 5; Step 3: For a first address offset that is divisible by the first memory page size, n times as the intermediate address offset. If the length of the intermediate address offset exceeds the parameter length limit of the target instruction, execute step 4; otherwise, execute step 6; Step 4: If there is an instruction with the same semantics as the target instruction and supporting a parameter length not less than the length of the intermediate address offset, the intermediate address offset is used as the second address offset, and the target instruction and the first address offset are replaced by the instruction and the second address offset, and step 6 is executed; otherwise, the target instruction is replaced by the first instruction combination consisting of the save instruction and the indirect addressing instruction, and step 6 is executed; Step 5, reverse decompile from the target instruction to the first instruction that modifies the target register, record the instruction as the first instruction, if the first instruction is in the loop body, use the end instruction of the loop body as the marking instruction, otherwise use the first instruction as the marking instruction; insert a call instruction of the register value repair function after the marking instruction, wherein the register value repair function takes the target register as an input parameter, reads the value in the target register, and converts the value to be aligned based on the second memory page size when the value is aligned based on the first memory page size; Step 6: Complete the conversion of all memory access instructions in the executable file to obtain target code that can run on the target system.

2. The cross-memory page difference compatible operation method according to claim 1, characterized in that: The first memory page size is 4K.

3. The cross-memory page difference compatible operation method according to claim 1, characterized in that: The cross-memory page difference compatible operation method also includes: Step 3.1 registers a first exception handling function at the execution entry of the target code. When a memory alignment exception occurs during the execution of the target code, the instruction that generates the exception is recorded as an exception instruction, and the address offset of the instruction is recorded as the exception address offset. The first exception handling function records 2 of the exception address offset as the exception address offset. n times as the repair address offset. If the length of the repair address offset is greater than the parameter length limit of the exception instruction, execute step 3.2; otherwise, convert the exception address offset to the repair address offset, and execute from the exception address offset after the exception is restored; Step 3.2, replace the abnormal instruction with the second instruction combination consisting of the save instruction and the indirect addressing instruction. When the length of the second instruction combination is greater than the length of the abnormal instruction, execute step 3.

3. When it is equal, write the second instruction combination to the address corresponding to the abnormal address offset. When it is less than the length, add a NOP instruction after the second instruction combination and write it to the address corresponding to the abnormal address offset. After recovering from the abnormality, execute from the abnormal address offset. Step 3.3, establish a target instruction cache, the jump target address of the first jump instruction is the sum of the exception address offset and the exception instruction length, the length of the target instruction cache is the sum of the length of the second instruction combination and the length of the first jump instruction, the second instruction combination and the first jump instruction are written into the target instruction cache; the jump target address of the second jump instruction is the address of the target instruction cache, if the length of the exception instruction is not less than the length of the second jump instruction, the second jump instruction and the corresponding NOP instruction are written at the exception address offset, and the exception is recovered and then executed from the address of the target instruction cache; otherwise, the exception is directly recovered and then executed from the address of the target instruction cache.

4. The cross-memory page difference compatible operation method according to claim 3 is characterized in that: A mapping relationship between the exception instruction and the address of the target instruction cache is established, and the instruction is executed from the address of the target instruction cache after the exception is recovered according to the mapping relationship.

5. The cross-memory page difference compatible operation method according to claim 1, characterized in that: In step 4, the first instruction combination consists of instructions required for splitting the intermediate address offset.

6. The cross-memory page difference compatible operation method according to claim 5, characterized in that: The first instruction combination consists of a MOV instruction and an ORR instruction.