Simulation verification model capable of flexibly configuring addressing mode based on I2C interface IP verification

Abstract

The invention discloses a simulation verification model with a flexibly configurable addressing mode based on I2C interface IP verification in the technical field of IP design verification in a semiconductor integrated circuit, and the model comprises a data response sending / receiving module which is used for responding to a device address and a memory address; the data response sending / receiving module contains an I2C protocol transmission state machine which is used for state skipping of I2C write transmission and read transmission and controlling the sending or receiving state of the data response sending / receiving module; the I2C protocol generally transmits addressing bytes firstly, that is, addressing is carried out on devices mounted on a bus, two addressing modes specified by the I2C protocol are provided, the addressing modes are 7 bit and 10 bit, and data transmission can be started after the corresponding devices respond to addresses. The I2C interface simulation of a 7-bit addressing mode and a 10-bit addressing mode is supported, so that the system-level simulation of the I2C module is more convenient and faster, and wider verification requirements are met.

Description

Technical Field

[0001] The present invention relates to the technical field of IP design verification in semiconductor integrated circuits, and in particular to a simulation verification model with flexibly configurable addressing modes based on I2C interface IP verification. Background Art

[0002] The I2C (Inter-Integrated Circuit) interface is a serial, half-duplex interface bus introduced by Philips. It can realize synchronous serial communication between microprocessors and peripheral chips. It is mainly used in short-distance, low-speed communication scenarios. It is more commonly used for data interaction of storage devices such as EEPROM and control of peripheral devices such as sensors and display screens. The I2C interface bus only needs two bidirectional signal lines to realize data transmission, a clock line SCL is used for clock synchronization of both communicating parties, and a data line SDA is used to send and receive data. The I2C bus interface has a simple hardware structure, simple PCB wiring, saves pin resources, and reduces system costs. Therefore, it has been widely used in many fields.

[0003] Devices connected to the I2C bus are divided into hosts and slaves. The host can initiate and end a data communication, while the slave can only be called passively. Since the I2C bus only uses two signal lines for data transmission and multiple I2C devices can be connected to the bus, each I2C device has a specific and unique device address. The host sends the device address to the bus, and the corresponding slave responds to the address to complete the device addressing.

[0004] The on-chip I2C bus interface usually uses an I2C interface IP, which is mounted on the on-chip system bus to interact with the processor core. Its system-level verification method usually involves the processor sending instructions and data to the I2C IP through the system bus to control the I2C IP to generate the SCL clock and transmit the SDA data. SCL and SDA are connected to a dedicated simulation model, which simulates the logical behavior of a device with an I2C interface. The basic functions include receiving, sending, and storing I2C data, sending responses to the I2C IP, etc., as well as additional logical behaviors for verifying other functions of the I2C IP, which is used to assist in verifying the correctness of the I2C interface data transmission.

[0005] There are two types of I2C device addresses, 7-bit address and 10-bit address, so I2C transmission also has two addressing modes, namely 7-bit addressing and 10-bit addressing. After inquiry, most I2C devices use 7-bit device addresses, but some products such as some sensors still use 10-bit device addresses. At present, the general simulation model usually simulates the read and write transmission format of the I2C device EEPROM, that is, it only supports 7-bit addressing mode. There are currently no patents and papers that support both 7-bit and 10-bit addressing modes. For some I2C 10-bit addressing mode verification requirements, it is usually not met. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a simulation verification model with flexibly configurable addressing modes based on I2C interface IP verification, which can simulate 7-bit addressing mode and 10-bit addressing mode simultaneously in a verification environment.

[0007] To achieve the above object, the present invention is implemented by adopting the following technical solutions: In a first aspect, the present invention provides a simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification, including a data response sending / receiving module for responding to device addresses and memory addresses; the data response sending / receiving module contains an I2C protocol transmission state machine for state jumps of I2C write transmission and read transmission, and controls the sending or receiving state of the data response sending / receiving module; the I2C protocol transmission state machine includes: DA_H device address high byte status, DA_L device address low byte status, MA_H memory address high byte status, MA_L memory address low byte status, W_D write data status, R_D read data status and NS unselected status; If the data response send / receive module detects the START bit sent by the host, it jumps to the DA_H device address high byte state; When the DA_H device address is in high byte state, the signal mode is set to RECV; If the data received by the current byte is bit [7:3] 11110, the addressing mode of the I2C transmission is determined to be the 10-bit addressing mode; if the data received by the current byte is the set 7-bit device address, the addressing mode of the I2C transmission is determined to be the 7-bit addressing mode; If the addressing mode is 10-bit addressing mode, and the data bits [2:1] of the current byte received are bits [9:8] of the set 10-bit device address, the address is initially matched; If the address is preliminarily matched and the 0th bit of the data received in the current byte is 1, jump to the R_D read data state, set the signal mode to SEND, and prepare to send data; If the address is preliminarily matched and the 0th bit of the data received in the current byte is 0, jump to the DA_L device address low byte state, keep the signal mode as RECV, and continue to receive the device address low byte; If the addressing mode is 7-bit addressing mode, jump to the MA_H memory address high byte state and prepare to receive the memory address high byte; If the addressing mode is not 10-bit addressing mode or 7-bit addressing mode, jump to NS unselected state, set the signal mode to PASSIVE, and simulate and verify that the model is not addressed; When the MA_H memory address is in high byte state, the signal mode is RECV, and after waiting for the signal done, it enters the MA_L memory address low byte state and continues to receive the memory address low byte; When the MA_L memory address is in the low byte state, the signal mode is RECV, and after waiting for the signal done, it enters the W_D data writing state, and the I2C bus is ready to write data to the simulation verification model; When W_D is in the data writing state, the signal mode is RECV. After all data is written, the host sends a STOP bit. When R_D is in the data reading state, the signal mode is SEND. After all data are read out, the host sends a STOP bit. NS is in the unselected state, which lasts for one SCL cycle before jumping back to the DA_H device address high byte state; Among them, if the data response sending / receiving module detects the STOP bit sent by the host, it jumps to the NS unselected state; when the data response sending / receiving module sends a signal done, it represents that one byte transmission is completed.

[0008] Optionally, the two tri-state gates of the data response sending / receiving module are externally connected to SDA and SCL of the host I2C interface IP.

[0009] Optionally, an assign statement is used to realize the connection of the two tri-state gates; If the signal scl_oe is true, SCL is 0, otherwise, SCL is in high impedance state; Assign the value of SCL to the signal scl_in; If the signal sda_oe is true, SDA is 0, otherwise, SDA is in high impedance state; Assign the value of SDA to the signal sda_in; Among them, the signal scl_oe and the signal sda_oe are enable signals of SCL and SDA; the signal scl_in and the signal sda_in are interactive signals of the three-state gate.

[0010] Optionally, the data response sending / receiving module further includes a data response sending / receiving state machine; the data response sending / receiving state machine includes: IDLE idle state, RECV_START receive start bit state, RECV_DATA receive data state, SEND_ACK send response bit state, SEND_DATA send data state, RECV_ACK receive response bit state, WAIT_STOP wait stop bit state; In the IDLE idle state, when the signal sda_in changes from high level to low level, it means that the data response sending / receiving module detects the START bit sent by the host and jumps to the RECV_START receiving start bit state; When RECV_START receives the start bit state, the data response send / receive module receives the START bit on the I2C bus, which lasts for one SCL cycle and jumps to the RECV_DATA receive data state; When in the RECV_DATA receiving data state, the data response send / receive module receives the data on the I2C bus, and the counter counts the number of received data bits. When the count reaches 7, it jumps to the SEND_ACK sending response bit state; When the SEND_ACK send response bit state, the data response send / receive module sends a response ACK or a non-response NAK to the I2C bus; if the signal mode is SEND, it jumps to the SEND_DATA send data state and sends a done signal. If the mode is PASSIVE, it jumps to the WAIT_STOP wait stop bit state and sends a done signal. When in the SEND_DATA data sending state, the data response sending / receiving module sends data to the I2C bus, and the counter counts the number of bits of the sent data. When the count reaches 7, it jumps to the RECV_ACK receiving response bit state; When RECV_ACK receives the response bit state, the data response sending / receiving module receives the response ACK or non-response NAK sent on the I2C bus; if the signal mode is SEND, it jumps to the SEND_DATA data sending state and sends a done signal. If the mode is PASSIVE, it jumps to the WAIT_STOP waiting stop bit state and sends a done signal. In the WAIT_STOP waiting stop bit state, when sda_in changes from low level to high level, it means that the data response sending / receiving module detects the STOP bit sent by the host and jumps to the IDLE idle state; Among them, if the data response sending / receiving module detects the STOP bit sent by the host, it jumps to the IDLE idle state.

[0011] Optionally, if the RESTART bit sent by the host is detected in the RECV_DATA receiving data state, it jumps to the RECV_START receiving start bit state.

[0012] Optionally, when SCL is high, SDA changes from high to low for the START bit; when SCL is high, SDA changes from low to high for the STOP bit; during data transmission, when SCL is high, SDA changes from high to low for the RESTART bit.

[0013] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a simulation verification model with flexibly configurable addressing modes based on I2C interface IP verification, which can simulate 7-bit addressing mode and 10-bit addressing mode simultaneously in a verification environment. The model can judge whether the address is 7-bit or 10-bit according to the addressing mode characteristics specified in the protocol. It can receive, send and store I2C data and respond to the address, data and instructions issued by the host, complete I2C read and write transmission, make the system-level simulation of the I2C module more convenient and quick, and meet a wider range of verification needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural diagram of an I2C IP system-level verification environment provided by an embodiment of the present invention; Figure 2 Schematic diagram of I2C bus lines and connection methods provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of the connection of the I2C interface signal tri-state gates provided by an embodiment of the present invention; Figure 4 This is a schematic diagram of the START and STOP bits of the I2C interface protocol provided by an embodiment of the present invention; Figure 5 This is a schematic diagram of the I2C interface protocol data transmission format provided by an embodiment of the present invention; Figure 6 is a schematic diagram of a data response sending / receiving state machine provided by an embodiment of the present invention; Figure 7 is a schematic diagram of a 7bit / 10bit addressing mode provided by an embodiment of the present invention; Figure 8It is a schematic diagram of the read and write transmission format of an EEPROM device provided by an embodiment of the present invention; Fig. 9 It is a schematic diagram of an I2C protocol transmission state machine provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0016] Embodiment 1:

[0017] The embodiment of the present invention designs a simulation verification model that can be used to verify the read and write behavior of I2C 7-bit and 10-bit addressing modes. The model can interact with IP as a slave. Its functions include but are not limited to receiving and detecting START, RESTART and STOP bits; receiving and judging 7-bit or 10-bit device addresses and sending responses; receiving and sending I2C data; containing a memory module to store I2C data; receiving or sending I2C responses, etc. The structure diagram of the I2C IP system-level verification environment is as follows: Figure 1 shown.

[0018] Figure 1 In the figure, tb is testbench, chip_top is the top layer of RTL design of a chip, I2C IP is the I2C interface IP integrated in the chip, and I2C Simulation Model is the simulation verification model. Because the I2C bus is a half-duplex bus, but there is only one data line, bidirectional data transmission is required. The 6 I2C signal lines of the I2C interface IP chip_top layer are connected to two tri-state gates to change the transmission direction. The signal processed by the tri-state gate is a standard I2C interface signal, which is connected to the simulation model.

[0019] (1) Three-state gate design description like Figure 2 As shown in the figure, the I2C bus can be connected to multiple hosts and slaves. When multiple I2C devices are connected together through the I2C bus, it is required that the I2C devices can realize line AND. Therefore, the I2C pins of the chip usually use open-drain output to realize line AND. As long as the pin level of one I2C device is low, the corresponding SCL or SDA bus will also become a low level. However, the open-drain output does not have the output capability of high level, so a pull-up resistor needs to be added to the output end. When the chip SDA and SCL pin output MOS tubes are turned off, the output state is high impedance. The existence of the pull-up resistor makes the level on the I2C signal line high.

[0020] Because there are multiple devices on the I2C bus, the devices are connected to the bus in high impedance. In this way, the bus is automatically released when the device is not occupying the bus, so that other devices can obtain the right to use the bus. Therefore, the device port must be connected to the bus through a tri-state buffer. When the device is not occupying the bus, the output is in high impedance. Because the simulation model is an I2C slave device mounted on the bus, a tri-state gate connection is also made for the I2C signal inside the model.

[0021] like Figure 3 As shown in the figure, the I2C interface signal tri-state gate connection diagram is shown. The tri-state gate connection is realized directly by using the assign statement in the model.

[0022] assign SCL = scl_oe? 1'b0 : 1'bz; assign scl_in = SCL; assign SDA = sda_oe? 1'b0 : 1'bz; assign sda_in = SDA; In the testbench, define SCL and SDA as tri1 type to achieve pull-up.

[0023] (2) Data response sending / receiving module design description The functions implemented by this module include: realizing the processing of interface signals by three-state gates, including the state machine for receiving and sending data or responding to bits; data shifting and counting; identifying the START, RESTART and STOP bits on the bus; controlling the level of sda_oe, that is, controlling when the model occupies the bus and when it releases the bus.

[0024] like Figure 4 As shown in the figure, the I2C interface protocol stipulates that when SCL is high, SDA changes from high to low, which is the START bit; when SCL is high, SDA changes from low to high, which is the STOP bit. The RESTART bit usually occurs during data transmission to change the direction of data transmission. Its sign is also when SCL is high, SDA changes from high to low. Therefore, the edge change of SDA level can be used as the basis for the model to detect START, RESTART and STOP bits.

[0025] The I2C interface protocol stipulates that the bus transmits data in bytes, that is, it takes 9 clock cycles to transmit one byte of data, of which the first 8 bits are data bits and the 9th bit is the response bit. The response bit is sent by the receiver and is valid at a low level. The transmission format of each byte is as follows: Figure 5 shown.

[0026] The model needs to receive and send data and responses. Therefore, the data response sending and receiving state machine is designed as follows Figure 6 shown.

[0027] Figure 6 There are 7 states in the state machine, namely IDLE idle state; RECV_START receive start bit state; RECV_DATA receive data state; SEND_ACK send response bit state; SEND_DATA send data state; RECV_ACK receive response bit state; WAIT_STOP wait stop bit state.

[0028] Since the host may initiate the STOP bit at any time, it will jump to the IDLE state immediately after detecting the STOP bit on the bus at any time, indicating that the current transmission is completed and waiting for the next transmission to start.

[0029] Figure 6 In the IDLE state, when sda_in changes from high level to low level, it represents the START bit, that is, jumps to the RECV_START state; Figure 6 In the RECV_START state, the model receives the START bit on the bus. Since START lasts for one SCL cycle, RECV_START also lasts for one SCL cycle. Since the first byte of each transmission is usually addressed by the host sending the device address, the host sends and the slave receives, so it jumps to the RECV_DATA state; Figure 6 In the RECV_DATA state, the model receives data on the bus. The counter starts counting. Since each data is 8 bits, it jumps when the counter is 7. The model will send a response to the bus, so the state jumps to SEND_ACK. If the RESTART bit is detected in this state, it jumps back to the RECV_START state.

[0030] Figure 6 In the SEND_ACK state, the model sends ACK or NAK to the bus. The mode is controlled by the I2C protocol transmission state machine below, and the state jump depends on the mode value. This state sends a done signal, indicating that the transmission of one byte is completed.

[0031] Figure 6 In the SEND_DATA state, the model sends data to the bus. The counter starts counting, and since each data is 8 bits, it jumps when the counter is 7. The model will receive the response sent by the host to the bus, so the state jumps to RECV_ACK.

[0032] Figure 6In the RECV_ACK state, the model receives the ACK or NAK sent by the host to the bus. The mode is controlled by the I2C protocol transmission state machine below, and the state jump depends on the mode value. This state sends a done signal, indicating that the transmission of one byte is completed.

[0033] Figure 6 When in the WAIT_STOP state, it means that the last byte has been transmitted, and the model no longer occupies the bus. It enters this state and waits for the host to send the STOP bit. After detecting the STOP bit, it returns to the IDLE state, the transmission is completed, and the bus is released.

[0034] (3) Simulation model design description The functions implemented by this module include: integrated data response send / receive module to respond to device addresses and internal memory addresses; built-in I2C protocol transmission state machine: realize state transition of I2C write transmission and read transmission, realize data storage, and control the sending or receiving state of the data response send / receive module.

[0035] The I2C protocol usually transmits the address byte first, that is, addresses the device mounted on the bus. After the corresponding device responds to the address, data transmission can begin. There are two addressing modes specified in the I2C protocol, 7-bit and 10-bit, with the following format: Figure 7 shown.

[0036] Figure 7 In the 10-bit addressing mode, the first five bits of the first byte are 11110, which can be used as the basis for determining the addressing mode. As long as the first five bits of the first byte of each transmission are 11110, it can be determined as a 10-bit addressing mode transmission.

[0037] Figure 8 The multi-byte read and write transmission format of the common I2C device EEPROM, i.e., electrically erasable programmable read-only memory, is used. The simulation model designed in this embodiment simulates the read and write logic behavior of the EEPROM and can realize single-byte and multi-byte read and write transmission. Figure 8 Design the I2C protocol transmission state machine as follows Fig. 9 shown.

[0038] Fig. 9 The state machine has 7 states, namely DA_H: device address high byte state; DA_L: device address low byte state; MA_H: memory address high byte state; MA_L: memory address low byte state; W_D: write data state; R_D: read data state; NS: unselected state, data response send / receive module detects the START bit at any time, the state machine immediately jumps to DA_H state; After detecting STOP, it will jump to NS state immediately. All state jumps occur when the data response sending / receiving module sends a done signal, which means that one byte transmission is completed.

[0039] Fig. 9 When in the DA_H state, the mode signal is set to RECV. If the [7:3] bits of the data received in this byte are 11110, it is judged as a 10-bit addressing mode. If the [2:1] bits match the [9:8] bits of the set 10-bit device address, the address is preliminarily matched. The 0th bit of the data indicates a read or write transmission. If it is a write, it jumps to DA_L and keeps the mode signal to RECV, and continues to receive the low-byte device address. If it is a read, it jumps to R_D and sets the mode signal to SEND to prepare to send data. If the received data is equal to the set 7-bit device address, it jumps directly to MA_H to prepare to receive the memory address. If none of them match, it jumps to the NS state and the mode signal is set to PASSIVE, indicating that the model has not been addressed.

[0040] Fig. 9 In the DA_L state, the mode signal is RECV. If the data of this byte matches the [7:0]th bit of the set 10-bit device address, the 10-bit device address is addressed, and the state jumps to MA_H, ready to receive the memory address; if it does not match, it jumps to NS, and the mode signal is set to PASSIVE, indicating that the model has not been addressed.

[0041] Fig. 9 In the MA_H state, the mode signal is RECV, and after waiting for the done signal, it enters MA_L and continues to receive the low byte of the memory address; Fig. 9 In the MA_L state, the mode signal is RECV, and after waiting for the done signal, it enters W_D, and the bus is ready to write data to the model; Fig. 9 In the W_D state, the mode signal is RECV. After waiting for all data to be written, the host sends a STOP bit and enters the NS state after detecting the STOP bit. Fig. 9 In the R_D state, the mode signal is SEND. After waiting for all data to be read out, the host sends a STOP bit and enters the NS state after detecting the STOP bit. Fig. 9 When in the NS state, the state lasts for one SCL cycle and then jumps back to DA_H, waiting for the next transmission to start.

[0042] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0043] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification, characterized in that: It includes a data response sending / receiving module for responding to device addresses and memory addresses; the data response sending / receiving module contains an I2C protocol transmission state machine for state jumps of I2C write transmission and read transmission, and controls the sending or receiving state of the data response sending / receiving module; The I2C protocol transmission state machine includes: DA_H device address high byte status, DA_L device address low byte status, MA_H memory address high byte status, MA_L memory address low byte status, W_D write data status, R_D read data status and NS unselected status; If the data response send / receive module detects the START bit sent by the host, it jumps to the DA_H device address high byte state; When the DA_H device address is in high byte state, the signal mode is set to RECV; If the data received by the current byte is bit [7:3] 11110, the addressing mode of the I2C transmission is determined to be the 10-bit addressing mode; if the data received by the current byte is the set 7-bit device address, the addressing mode of the I2C transmission is determined to be the 7-bit addressing mode; If the addressing mode is 10-bit addressing mode, and the data bits [2:1] of the current byte received are bits [9:8] of the set 10-bit device address, the address is initially matched; If the address is preliminarily matched and the 0th bit of the data received in the current byte is 1, jump to the R_D read data state, set the signal mode to SEND, and prepare to send data; If the address is preliminarily matched and the 0th bit of the data received in the current byte is 0, jump to the DA_L device address low byte state, keep the signal mode as RECV, and continue to receive the device address low byte; If the addressing mode is 7-bit addressing mode, jump to the MA_H memory address high byte state and prepare to receive the memory address high byte; If the addressing mode is not 10-bit addressing mode or 7-bit addressing mode, jump to NS unselected state, set the signal mode to PASSIVE, and simulate and verify that the model is not addressed; When the MA_H memory address is in high byte state, the signal mode is RECV, and after waiting for the signal done, it enters the MA_L memory address low byte state and continues to receive the memory address low byte; When the MA_L memory address is in the low byte state, the signal mode is RECV, and after waiting for the signal done, it enters the W_D data writing state, and the I2C bus is ready to write data to the simulation verification model; When W_D is in the data writing state, the signal mode is RECV. After all data is written, the host sends a STOP bit. When R_D is in the data reading state, the signal mode is SEND. After all data are read out, the host sends a STOP bit. NS is in the unselected state, which lasts for one SCL cycle before jumping back to the DA_H device address high byte state; Among them, if the data response sending / receiving module detects the STOP bit sent by the host, it jumps to the NS unselected state; when the data response sending / receiving module sends a signal done, it represents that one byte transmission is completed.

2. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 1, characterized in that: The two tri-state gates of the data response sending / receiving module are externally connected to SDA and SCL of the host I2C interface IP.

3. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 2, characterized in that: Using assign statement to realize the connection of two tri-state gates; If the signal scl_oe is true, SCL is 0, otherwise, SCL is in high impedance state; Assign the value of SCL to the signal scl_in; If the signal sda_oe is true, SDA is 0, otherwise, SDA is in high impedance state; Assign the value of SDA to the signal sda_in; Among them, the signal scl_oe and the signal sda_oe are enable signals of SCL and SDA; the signal scl_in and the signal sda_in are interactive signals of the three-state gate.

4. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 3, characterized in that: The data response sending / receiving module also includes a data response sending / receiving state machine; The data response sending / receiving state machine includes: IDLE idle state, RECV_START receive start bit state, RECV_DATA receive data state, SEND_ACK send response bit state, SEND_DATA send data state, RECV_ACK receive response bit state, WAIT_STOP wait stop bit state; In the IDLE idle state, when the signal sda_in changes from high level to low level, it means that the data response sending / receiving module detects the START bit sent by the host and jumps to the RECV_START receiving start bit state; When RECV_START receives the start bit state, the data response send / receive module receives the START bit on the I2C bus, which lasts for one SCL cycle and jumps to the RECV_DATA receive data state; When in the RECV_DATA receiving data state, the data response send / receive module receives the data on the I2C bus, and the counter counts the number of received data bits. When the count reaches 7, it jumps to the SEND_ACK sending response bit state; When the SEND_ACK send response bit state, the data response send / receive module sends a response ACK or a non-response NAK to the I2C bus; if the signal mode is SEND, it jumps to the SEND_DATA send data state and sends a done signal. If the mode is PASSIVE, it jumps to the WAIT_STOP wait stop bit state and sends a done signal. When in the SEND_DATA data sending state, the data response sending / receiving module sends data to the I2C bus, and the counter counts the number of bits of the sent data. When the count reaches 7, it jumps to the RECV_ACK receiving response bit state; When RECV_ACK receives the response bit state, the data response sending / receiving module receives the response ACK or non-response NAK sent on the I2C bus; if the signal mode is SEND, it jumps to the SEND_DATA data sending state and sends a done signal. If the mode is PASSIVE, it jumps to the WAIT_STOP waiting stop bit state and sends a done signal. In the WAIT_STOP waiting stop bit state, when sda_in changes from low level to high level, it means that the data response sending / receiving module detects the STOP bit sent by the host and jumps to the IDLE idle state; Among them, if the data response sending / receiving module detects the STOP bit sent by the host, it jumps to the IDLE idle state.

5. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 4, characterized in that: If the RESTART bit sent by the host is detected in the RECV_DATA receiving data state, it jumps to the RECV_START receiving start bit state.

6. The simulation verification model with flexibly configurable addressing mode based on I2C interface IP verification according to claim 5, characterized in that: When SCL is high, SDA changes from high to low to indicate the START bit; when SCL is high, SDA changes from low to high to indicate the STOP bit; during data transmission, when SCL is high, SDA changes from high to low to indicate the RESTART bit.

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