Method for executing FFT (Fast Fourier Transform), processor, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a method for executing FFT (Fast Fourier Transform), a processor, electronic equipment and a storage medium. The method comprises the following steps: acquiring a point number N corresponding to a to-be-executed FFT operation; dividing the FFT operation into M-level operation according to the point number N; dividing each level of FFT operation into at least one group of butterfly operations according to twiddle factors corresponding to each butterfly operation unit in the FFT operation; in each level of operation, according to the first input value, the second input value and the twiddle factor of each butterfly operation unit, executing each group of butterfly operation in sequence to obtain a butterfly operation output sequence; and determining a first input value, a second input value and a twiddle factor of each butterfly operation unit in the (m + 1) th-level operation according to the butterfly operation output sequence corresponding to the mth-level operation, and continuously executing each group of butterfly operations in the (m + 1) th-level operation until the execution of the M-level operations is finished, thereby obtaining a result sequence corresponding to the FFT operation. According to the embodiment of the invention, the operation cost of FFT can be reduced, and the operation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, a processor, an electronic device and a storage medium for performing FFT. Background Art

[0002] Fast Fourier Transform (FFT) is a common algorithm in digital signal processing. There are usually two ways to implement the FFT algorithm: (1) attach a heterogeneous processor or peripheral module to the main processor to implement FFT calculation. This method is essentially custom hardware for FFT, which has low scalability and high R&D and production costs; (2) convert the FFT operation into a multiplication and accumulation process of several levels, and use the multiply accumulate (MAC) unit inside RSIC-V to perform parallel operations to calculate the target values. This design requires converting the original calculation into a multiplication and accumulation form, but there are still some independent multiplications that cannot be converted, and additional division calculations need to be introduced during the conversion process, resulting in low execution efficiency. Summary of the invention

[0003] The embodiments of the present invention provide a method, a processor, an electronic device and a storage medium for executing FFT, which can solve the problems of high implementation cost and low execution efficiency of FFT algorithm in related technologies.

[0004] In one aspect, an embodiment of the present invention discloses a method for performing FFT, the method comprising: Get the number of points N corresponding to the Fast Fourier Transform FFT operation to be performed; The FFT operation is divided into M-level operations according to the number of points N; M is the logarithm of N with 2 as the base; According to the rotation factors corresponding to the butterfly operation units in the FFT operation, each level of FFT operation is divided into at least one group of butterfly operations; the rotation factors corresponding to the same group of butterfly operation units are the same; In each level of operation, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence; According to the butterfly operation output sequence corresponding to the m-th level operation, determine the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)-th level operation, and continue to execute each group of butterfly operations in the (m+1)-th level operation until all M-level operations are completed, and obtain the result sequence corresponding to the FFT operation; wherein 0≤m≤(M-1), and m is an integer.

[0005] Optionally, in each level of operation, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence, including: In each level of operation, for each group of butterfly operations, an FFT instruction corresponding to each butterfly operation unit in the group is obtained; the FFT instruction carries the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs; In the decoding stage, according to the first input value and the level m, the second input value and the rotation factor corresponding to the butterfly operation unit are determined, and the first input value, the second input value and the rotation factor are written into registers respectively; During the execution stage, the FFT instruction is executed to perform a butterfly operation according to the first input value, the second input value and the rotation factor recorded in the register to obtain a first operation result and a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed and a butterfly operation output sequence is obtained.

[0006] Optionally, determining the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the level m includes: Determine a first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group according to the number of points N and the level m to which the butterfly operation unit belongs; Determine a second input value of the butterfly operation unit according to the first input value and the first interval; Determine, according to the number of points N and the number of stages m to which the butterfly operation unit belongs, a second spacing between two adjacent groups of butterfly operations in the m-th stage operation; The rotation factor corresponding to the butterfly operation unit is determined according to the second spacing.

[0007] Optionally, determining the rotation factor corresponding to the butterfly operation unit according to the second spacing includes: Obtaining a storage base address of a rotation factor corresponding to the FFT operation; Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second spacing; Based on the storage base address and the offset address, the rotation factor corresponding to the butterfly operation unit is read from the memory.

[0008] Optionally, in each level of operation, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence, including: In each stage of operation, for each butterfly operation unit, a first input value of the butterfly operation unit is read from a first register, and a second input value of the butterfly operation unit is read from a second register; Calculating the sum of the first input value and the second input value to obtain a first operation result corresponding to the butterfly operation unit; Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in a temporary register; Reading the rotation factor corresponding to the butterfly operation unit from the third register, and reading the intermediate result from the temporary register; A complex multiplication operation is performed on the intermediate result and the rotation factor to obtain a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are completed to obtain a butterfly operation output sequence.

[0009] Optionally, the method further comprises: In the m-th level operation, the first operation result and the second operation result corresponding to the butterfly operation unit are sorted according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level operation to obtain the butterfly operation output sequence corresponding to the m-th level operation.

[0010] On the other hand, an embodiment of the present invention discloses a processor for executing FFT, the processor comprising an instruction reading unit, a decoding unit, a general register file, an FFT execution unit, a memory access processing unit and a data storage unit; the FFT execution unit and the memory access processing unit share the general register file; The general register file stores the number of points N and the number of levels M corresponding to the Fast Fourier Transform FFT operation to be performed; The decoding unit is used to divide each level of FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit in the FFT operation; the rotation factors corresponding to the same group of butterfly operation units are the same; The FFT execution unit is used to perform each group of butterfly operations in sequence according to the first input value, the second input value and the rotation factor of each butterfly operation unit in each level of operation to obtain a butterfly operation output sequence; The decoding unit is further used to determine the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)th level operation according to the butterfly operation output sequence corresponding to the mth level operation; The FFT execution unit is further used to continue executing each group of butterfly operations in the (m+1)th level operation until all M levels of operations are completed, thereby obtaining a result sequence corresponding to the FFT operation; wherein 0≤m≤(M-1), and m is an integer.

[0011] Optionally, the instruction reading unit is used to obtain, in each level of operation, for each group of butterfly operations, an FFT instruction corresponding to each butterfly operation unit in the group; the FFT instruction carries the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs; The decoding unit is specifically used to: in the decoding stage, determine the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the level m, and write the first input value, the second input value and the rotation factor into the register respectively; The FFT execution unit is specifically used to: in the execution stage, execute the FFT instruction to perform a butterfly operation according to the first input value, the second input value and the rotation factor recorded in the register, and obtain the first operation result and the second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed and completed, and a butterfly operation output sequence is obtained.

[0012] Optionally, the decoding unit is specifically used for: Determine a first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group according to the number of points N and the level m to which the butterfly operation unit belongs; Determine a second input value of the butterfly operation unit according to the first input value and the first interval; Determine, according to the number of points N and the number of stages m to which the butterfly operation unit belongs, a second spacing between two adjacent groups of butterfly operations in the m-th stage operation; The rotation factor corresponding to the butterfly operation unit is determined according to the second spacing.

[0013] Optionally, the decoding unit is specifically used for: Obtaining a storage base address of a rotation factor corresponding to the FFT operation; Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second spacing; Based on the storage base address and the offset address, the rotation factor corresponding to the butterfly operation unit is read from the memory.

[0014] Optionally, the FFT execution unit is specifically used for: In each stage of operation, for each butterfly operation unit, a first input value of the butterfly operation unit is read from a first register, and a second input value of the butterfly operation unit is read from a second register; Calculating the sum of the first input value and the second input value to obtain a first operation result corresponding to the butterfly operation unit; Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in a temporary register; Reading the rotation factor corresponding to the butterfly operation unit from the third register, and reading the intermediate result from the temporary register; A complex multiplication operation is performed on the intermediate result and the rotation factor to obtain a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are completed to obtain a butterfly operation output sequence.

[0015] Optionally, the memory access processing unit is used to: In the m-th level operation, the first operation result and the second operation result corresponding to the butterfly operation unit are sorted according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level operation to obtain the butterfly operation output sequence corresponding to the m-th level operation.

[0016] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned method for executing FFT.

[0017] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned method for executing FFT.

[0018] The embodiments of the present invention include the following advantages: An embodiment of the present invention provides a method for executing FFT, which can split the FFT operation into M levels of operations according to the number of points N of the FFT operation, and divide each level of FFT operation into at least one group of butterfly operations. The result sequence corresponding to the FFT operation can be obtained by sequentially and cyclically executing each group of butterfly operations in each level of operation. There is no need to additionally customize the corresponding hardware module for the FFT operation, and there is no need to convert the original calculation into a multiplication-accumulation form, which reduces the operation cost of the FFT and improves the operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0020] Figure 1is a flowchart of a method for performing FFT according to an embodiment of the present invention; Figure 2 It is a data flow diagram of FFT of the present invention; Figure 3 is a schematic diagram of a butterfly operation unit of the present invention; Figure 4 is a schematic diagram of the structure of a processor of the present invention; Figure 5 It is a structural schematic diagram of an FFT execution unit of the present invention; Figure 6 It is a structural block diagram of an electronic device for performing FFT provided by an example of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0023] Method Embodiment Reference Figure 1 , shows a flowchart of a method for performing FFT according to an embodiment of the present invention, wherein the method may specifically include the following steps: Step 101, obtaining the number of points N corresponding to the Fast Fourier Transform FFT operation to be performed; Step 102: Divide the FFT operation into M-level operations according to the number of points N; M is the logarithm of N with 2 as the base; Step 103: divide each level of FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit in the FFT operation; the rotation factors corresponding to the same group of butterfly operation units are the same; Step 104: In each level of operation, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence; Step 105: Determine the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)th level operation according to the butterfly operation output sequence corresponding to the mth level operation, and continue to execute each group of butterfly operations in the (m+1)th level operation until all M levels of operations are completed, and obtain the result sequence corresponding to the FFT operation; wherein 0≤m≤(M-1), and m is an integer.

[0024] The embodiment of the present invention can be used to perform FFT operations and can be applied to processors, such as RSIC-V processors, ASIC processors, and the like.

[0025] The FFT operation is a fast algorithm of Discrete Fourier Transform (DFT), which is used to calculate the spectrum of a signal.

[0026] According to the definition of FFT, for a complex sequence x with a length of N, after performing FFT, a complex sequence X with a length of N can be obtained. The corresponding FFT calculation formula is as follows: (1) Where k represents the calculated complex number The sequence number in the complex sequence can also represent the input data x The sequence number in the complex sequence x; represents the rotation factor.

[0027] because ,but , so X(k) can be expressed as: (2) Divide k into odd and even numbers: = , r=0,1,2,……, (3) According to formula (3), X(k) can be divided into two parts: (4) (5) make , , we can get: (6) Reference Figure 2 , shows a data flow diagram of FFT. Figure 2 As shown, taking 8-point FFT (N=8) as an example, combined with the above formula (6), the smallest butterfly operation unit can be extracted as Figure 3 shown.

[0028] Therefore, no matter what the value of N is, the FFT algorithm can be simplified to: =x(n1)+x(n2) =[x(n1)-x(n2)] (7) Wherein, x(n1) represents the first input value of the butterfly operation unit, x(n2) represents the second input value of the butterfly operation unit, Represents the rotation factor corresponding to the butterfly operation unit, represents the first operation result of the butterfly operation unit, Indicates the second operation result of the butterfly operation unit. The first operation result corresponds to the first input value, and the second operation result corresponds to the second input value.

[0029] In the embodiment of the present application, the FFT operation is divided into M-level operations according to the number of points N corresponding to the FFT operation to be performed, where M is the logarithm of N with 2 as the base, that is: M= N. For example, Figure 2 Taking the 8-point FFT shown in the figure as an example, it can be divided into three levels of operation.

[0030] Next, each level of FFT operation is divided into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit in the FFT operation, wherein the rotation factors corresponding to the same group of butterfly operation units are the same.

[0031] It should be noted that the total number of butterfly operation units included in each level of operation is the same, both .by Figure 2 As an example, the 8-point FFT shown in the figure has the first-level operation ( Figure 2 The leftmost column of butterfly operations) contains a total of 4 butterfly operation units, which are used to operate on the original input data x(0) to x(7); the second level operation ( Figure 2 The middle column of butterfly operations) contains a total of 4 butterfly operation units, which are used to operate on the output results of the first level operation; the third level operation ( Figure 2The rightmost column of butterfly operations contains a total of 4 butterfly operation units, which are used to operate on the output results of the second-level operation to obtain the final result sequence X(0) to X(7).

[0032] In the embodiment of the present invention, the butterfly operation units included in each level of operation may be grouped according to the rotation factors corresponding to the butterfly operation units, and the butterfly operation units with the same rotation factors may be divided into a group of butterfly operations.

[0033] by Figure 2 As an example, the 8-point FFT shown in the figure Figure 2 It can be seen that the rotation factors corresponding to the four butterfly units in the first level operation are all different, so these four butterfly units can be divided into four groups, each group contains one butterfly unit. The rotation factors corresponding to the first butterfly unit and the third butterfly unit in the second level operation are the same, both , so the two butterfly units can be grouped together; the rotation factors corresponding to the second butterfly unit and the fourth butterfly unit are the same, both , so the two butterfly units can be grouped together, thus the four butterfly units in the second level operation are divided into two groups of butterfly operations. The rotation factors corresponding to the four butterfly units in the third level operation are the same, so the four butterfly units can be grouped together.

[0034] Furthermore, the number of butterfly operation groups included in each level of operation can be determined according to the number of FFT points N and the current operation level m.

[0035] Exemplarily, the number of butterfly operation units included in each group of butterfly operations may be: Num_of_Group= , where m is the current level of the butterfly operation, 0≤m≤(M-1). Each level of operation contains Therefore, in the mth level operation, each butterfly operation unit is divided according to the rotation factor, and the number of butterfly operation groups obtained is: .

[0036] Taking 8-point FFT as an example, it can be divided into 3 levels of operations. In the first level, m=0, including 4 ( =1) group of butterfly operations; in the second level operation, m=1, including 2 ( =2) groups of butterfly operations; in the third level operation, m=2, including 1 ( =4) group of butterfly operations.

[0037] Then, the M-level operations are executed cyclically: in each level of operation, each butterfly operation unit in each group of butterfly operations is executed in turn according to the first input value, the second input value and the rotation factor of each butterfly operation unit. After all the groups of butterfly operations in this level of operation are completed, the butterfly operation output sequence corresponding to this level of operation is obtained.

[0038] It should be noted that, in the embodiment of the present invention, the butterfly operation output sequence corresponding to the m-th level operation is the butterfly operation input sequence corresponding to the (m+1)-th level operation. Therefore, after the m-th level operation is completed, the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)-th level operation are determined according to the butterfly operation output sequence corresponding to the m-th level operation, and each group of butterfly operations in the (m+1)-th level operation is continued to be executed until all M-level operations are completed, and the result sequence corresponding to the FFT operation is obtained.

[0039] It is understandable that the number of points N, the scaling factor, and the memory access address of the data block of the FFT operation are relatively fixed, and the general registers in the general register stack can be opened for the FFT operation to store these parameters. Further, in the decoding stage, the first input value, the second input value, and the rotation factor of the current butterfly operation unit can be written into the register, and in the execution stage, the first input value, the second input value, and the rotation factor can be read from the register to perform the butterfly operation.

[0040] As an example, the FFT instruction corresponding to the butterfly operation unit may carry a first input value, a second input value, a rotation factor, and an operation code indicating a butterfly operation. In the decoding stage, the FFT instruction is parsed, and the first input value, the second input value, and the rotation factor are written into the register; in the execution stage, the FFT execution is executed to perform a butterfly operation according to the first input value, the second input value, and the rotation factor.

[0041] As another example, the second input value and rotation factor of the butterfly operation unit are related to the first input value and the level m corresponding to the current butterfly operation unit, so the FFT instruction corresponding to the butterfly operation unit can carry the first input value, the corresponding level m and the operation code indicating the butterfly operation. In the decoding stage, the FFT instruction is parsed, the second input value and the rotation factor are determined according to the first input value and the corresponding level m, and the first input value, the second input value and the rotation factor are written into the register; in the execution stage, the FFT execution is executed to perform the butterfly operation according to the first input value, the second input value and the rotation factor. Among them, the second input value can be determined according to the first input value, and the spacing between the butterfly operation unit and other adjacent butterfly operation units in the group; the rotation factor can be determined according to the spacing between groups in each level.

[0042] It should be noted that the specific operation process of performing the butterfly operation according to the first input value, the second input value and the rotation factor can refer to the above formula (7), wherein x(n1) can represent the first input value, x(n2) represents the second input value, represents the rotation factor, represents the first operation result corresponding to the butterfly operation unit, Indicates the second operation result corresponding to the butterfly operation unit.

[0043] by Figure 2 Taking the 8-point FFT shown in the figure as an example, the butterfly operation output sequence corresponding to the first-level operation is y(0) to y(7), the butterfly operation output sequence corresponding to the second-level operation is z(0) to z(7), and the butterfly operation output sequence corresponding to the third-level operation, that is, the result sequence corresponding to the FFT operation is X(0) to X(7). According to the embodiment of the present invention, the FFT operation is performed, and the operation process is as follows: In the first level of operation, four groups of butterfly operations are executed in sequence. Each group of butterfly operations contains a butterfly operation unit. The operation process of each butterfly operation unit is as follows: 1. y(0)=x(0)+x(4), y(4)=[x(0)-x(4)]

[0044] 2. y(1)=x(1)+x(5), y(5)=[x(1)-x(5)]

[0045] 3. y(2)=x(2)+x(6), y(4)=[x(2)-x(6)]

[0046] 4. y(3)=x(3)+x(7), y(4)=[x(3)-x(7)]

[0047] In the second level operation, two groups of butterfly operations are executed in sequence, each group of butterfly operations includes two butterfly operation units. The operation process of the two butterfly operation units in the first group is as follows: 1. z(0)=y(0)+y(2), z(2)=[y(0)-y(2)]

[0048] 2. z(4)=y(4)+y(6), z(6)=[y(4)-y(6)]

[0049] In the second level of operation, the operation process of the two butterfly operation units in the second group is as follows: 1. z(1)=y(1)+y(3), z(3)=[y(1)-y(3)]

[0050] 2. z(5)=y(5)+y(7), z(7)=[y(5)-y(7)]

[0051] In the third level operation, the four butterfly operation units are divided into a group of butterfly operations. The operation process of each butterfly operation unit is as follows: 1. X(0)=z(0)+z(1), X(4)=[z(0)-z(1)]

[0052] 2. X(2)=z(2)+z(3), X(6)=[z(2)-z(3)]

[0053] 3. X(1)=z(4)+z(5), X(5)=[z(4)-z(5)]

[0054] 4. X(3)=z(6)+z(7), X(7)=[z(6)-z(7)]

[0055] After the three-level operation is completed, the result sequence corresponding to the 8-point FFT can be obtained.

[0056] In an embodiment of the present invention, the FFT operation is split into M levels of operations, and each butterfly operation unit in each level of FFT operation is divided into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit. The result sequence corresponding to the FFT operation can be obtained by sequentially executing each group of butterfly operations in each level of operation in a loop. There is no need to customize the corresponding hardware module for the FFT operation, and there is no need to convert the original calculation into a multiplication-accumulation form, which reduces the operation cost of the FFT and improves the operation efficiency.

[0057] Furthermore, the FFT execution unit for performing FFT operations in the embodiment of the present invention may be tightly coupled with the processor core. Figure 4 , shows a schematic diagram of the structure of a processor provided by an embodiment of the present invention. Figure 4 As shown, the processor includes an instruction reading unit, a decoding unit, a general register file, an FFT execution unit, a memory access processing unit and a data storage unit.

[0058] Among them, the FFT execution unit and the memory access processing unit share a general register stack, and the general register stack stores the number of points N and the number of levels M corresponding to the fast Fourier transform FFT operation to be executed. The decoding unit is used to determine the first input value, the second input value and the rotation factor of each butterfly operation unit; and transmit the first input value, the second input value and the rotation factor to the register corresponding to the FFT execution unit. The FFT execution unit is used to execute each group of butterfly operations in sequence according to the first input value, the second input value and the rotation factor of each butterfly operation unit in each level of operation. The memory access processing unit is used to write the operation result corresponding to the butterfly operation unit into the data storage unit until all M levels of operations are executed, and the result sequence corresponding to the FFT operation is obtained.

[0059] Taking a RISC processor as an example, the processor may also include an ALU execution processing unit for executing ALU instructions. ALU instructions are mainly used to take two registers or one register and a sign extension technique for operation and store in a third register. It should be noted that the interaction process between the FFT execution unit and the previous and next stage units (or modules) is basically the same as the interaction process between other RSIC-V execution units, such as the ALU execution unit and the previous and next stage units.

[0060] Exemplarily, in an instruction fetch cycle (IF), the instruction fetch unit reads the FFT instruction corresponding to the butterfly operation unit to be executed from the memory. In an instruction decode / register fetch cycle (ID), the decode unit decodes the FFT instruction, determines the first input value, the second input value and the rotation factor corresponding to the butterfly operation unit, and transmits the first input value, the second input value and the rotation factor to the register corresponding to the FFT execution unit. In an execution / effective address cycle (EX), the FFT execution unit reads the first input value, the second input value and the rotation factor from the register, performs a butterfly operation, obtains the first operation result and the second operation result, and sends the first operation result and the second operation result to the memory access processing unit. In a memory access cycle (MEM), the memory access processing unit writes the first operation result and the second operation result into the memory or register. In a write-back cycle (WB), the data storage unit writes the program result (from the FFT execution unit or ALU operation or load instruction) into the register stack.

[0061] In an optional embodiment of the present invention, in each level of operation described in step 104, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence, including: Step S11, in each level of operation, for each group of butterfly operations, obtain the FFT instruction corresponding to each butterfly operation unit in the group; the FFT instruction carries the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs; Step S12: In the decoding stage, according to the first input value and the level m, determine the second input value and the rotation factor corresponding to the butterfly operation unit, and write the first input value, the second input value and the rotation factor into registers respectively; Step S13, in the execution stage, execute the FFT instruction to perform a butterfly operation according to the first input value, the second input value and the rotation factor recorded in the register, and obtain a first operation result and a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed and a butterfly operation output sequence is obtained.

[0062] The second input value and the rotation factor of the butterfly operation unit are related to the first input value and the level m corresponding to the current butterfly operation unit. Therefore, in an embodiment of the present invention, the FFT instruction corresponding to the butterfly operation unit can carry the first input value, the corresponding level m and the operation code indicating the butterfly operation. In the decoding stage, the FFT instruction is parsed, the second input value and the rotation factor are determined according to the first input value and the corresponding level m, and the first input value, the second input value and the rotation factor are written into the register; in the execution stage, the FFT execution is executed to perform the butterfly operation according to the first input value, the second input value and the rotation factor.

[0063] The second input value can be determined according to the first input value and the distance between the first input value and the second input value in each group; the rotation factor can be determined according to the distance between groups in each level.

[0064] It should be noted that, in the related art, if the instructions in the instruction set of the multiplexing system architecture are used to complete the FFT operation, the following instructions need to be executed to perform a butterfly operation: (1) Loadx(n1): load x(n1) (2) Loadx(n2): load x(n2) (3) ADD ,x(n1),x(n2): Execution =x(n1)+x(n2) SuBx21,x(n1),x(n2) :Execute x21 =x(n1)-x(n2) loadWn: load the rotation factor Wn (4) Store :storage

[0065] (5) Mul ,x21, Wn: Execute =[x(n1)-x(n2)] W (6) Store :storage

[0066] In the embodiment of the present invention, only one FFT instruction is required to complete a butterfly operation, and there is no need to execute ADD instructions, SuB instructions and Mul instructions, thereby reducing the number of instructions executed during the FFT operation and improving the FFT operation efficiency.

[0067] In addition, the embodiment of the present invention only carries the first input value and the level m to which the butterfly operation unit belongs in the FFT instruction. In the decoding stage, the second input value and the rotation factor are directly determined according to the first input value and the level m, and the second input value and the rotation factor are transmitted to the register corresponding to the FFT execution unit. In the execution stage, the FFT execution unit can directly obtain the first input value, the second input value and the rotation factor from the register without accessing the memory, thereby reducing the transmission complexity of the first input value, the second input value and the rotation factor, which is conducive to further improving the operational efficiency of the FFT.

[0068] Optionally, determining the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the level m includes: Step S21, determining a first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group according to the number of points N and the level m to which the butterfly operation unit belongs; Step S22, determining a second input value of the butterfly operation unit according to the first input value and the first interval; Step S23, determining a second spacing between two adjacent groups of butterfly operations in the mth level operation according to the number of points N and the level m to which the butterfly operation unit belongs; Step S24: determining a rotation factor corresponding to the butterfly operation unit according to the second spacing.

[0069] In the embodiment of the present invention, the spacing between the related operation units in each group of butterfly operations, that is, the first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group, can be determined according to the number of points N of the FFT and the number of levels m corresponding to the current butterfly operation unit. Exemplarily, the first spacing Interval_of_Unit = .

[0070] The interval between groups in each level, that is, the second interval between two adjacent groups of butterfly operations in the mth level operation, can also be determined according to the number of points N and the number of levels m of the FFT. For example, the second interval Interval_of_Group= .

[0071] The rotation factor is related to the second spacing. = ), where i is the imaginary unit, and the function exp(x) represents the natural exponential function, that is, the exponential function with the real number e as the base. pi is a constant representing л.

[0072] Optionally, determining the rotation factor corresponding to the butterfly operation unit according to the second spacing includes: Step S31, obtaining the storage base address of the rotation factor corresponding to the FFT operation; Step S32, determining an offset address of a rotation factor corresponding to the butterfly operation unit according to the second spacing; Step S33: based on the storage base address and the offset address, read the rotation factor corresponding to the butterfly operation unit from the memory.

[0073] In an embodiment of the present invention, the rotation factor can be stored in any area accessed by the processor core, and the FFT execution unit can read the rotation factor corresponding to the current butterfly operation unit based on the storage base address and offset address of the rotation factor. Specifically, the storage address of the current rotation factor = storage base address + offset address.

[0074] The offset address of the rotation factor can be determined according to the first input value and the second spacing of the butterfly operation unit.

[0075] For example, the offset address of the rotation factor It can be expressed as: = ) )(8) In the above formula (8), Converted to N and m: (9) Where r=0,1,2,……,( ).

[0076] Optionally, in each level of operation described in step 104, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence, including: Step S41, in each level of operation, for each butterfly operation unit, read the first input value of the butterfly operation unit from the first register, and read the second input value of the butterfly operation unit from the second register; Step S42, calculating the sum of the first input value and the second input value to obtain a first operation result corresponding to the butterfly operation unit; Step S43, calculating the difference between the first input value and the second input value to obtain an intermediate result, and recording the intermediate result in a temporary register; Step S44, reading the rotation factor corresponding to the butterfly operation unit from the third register, and reading the intermediate result from the temporary register; Step S45, performing a complex multiplication operation on the intermediate result and the rotation factor to obtain a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are completed to obtain a butterfly operation output sequence.

[0077] In an embodiment of the present invention, the first input value, the second input value and the rotation factor of the butterfly operation unit can be written into a register, and each time an operation is performed, the corresponding value is read from the register for operation. Similarly, the intermediate result of the calculation can also be temporarily stored in the register for easy reading during subsequent operations.

[0078] Reference Figure 5 , shows a schematic diagram of the structure of an FFT execution unit provided by an embodiment of the present invention. Figure 5 As shown, the FFT execution unit in the present invention may include a first register, a second register, a third register, a temporary register, an adder, a subtractor and a complex multiplication module. The first register is used to record the first input value, the second register is used to record the second input value, the third register is used to record the rotation factor, and the temporary register is used to record the intermediate result.

[0079] As an example, when the FFT execution unit executes the FFT instruction, it first reads the first input value x(n1), the second input value x(n2) and the rotation factor of the butterfly operation unit from the first register, the second register and the third register respectively. The first input value and the second input value are input into the adder for summation to obtain the first operation result. The first input value and the second input value are input into the subtractor for subtraction to obtain the intermediate result. , =x(n1)-x(n2). Then, the intermediate result With the rotation factor Input into the complex multiplication module for complex multiplication operation to obtain the second output result = .

[0080] Furthermore, the FFT execution unit sends the first output result and the second output result to the memory access processing unit. In the memory access cycle (MEM), the memory access processing unit writes the first operation result and the second operation result into the memory or register.

[0081] Optionally, the method further comprises: In the m-th level operation, the first operation result and the second operation result corresponding to the butterfly operation unit are sorted according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level operation to obtain the butterfly operation output sequence corresponding to the m-th level operation.

[0082] It should be noted that in the FFT operation, the positions of the first operation result and the second operation result of the butterfly operation unit in the result sequence are the same as the positions of the first input value and the second input value in the input data. Therefore, each time a group of butterfly operations is performed, the first operation result and the second operation result can be sorted according to the arrangement order of the first input value and the second input value of the butterfly operation unit in the input data corresponding to the m-th level operation to obtain the butterfly operation output sequence corresponding to the m-th level operation.

[0083] In summary, an embodiment of the present invention provides a method for performing FFT, which splits the FFT operation into M levels of operations according to the number of points N of the FFT operation, and divides the butterfly operation units in each level of FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit. The result sequence corresponding to the FFT operation can be obtained by sequentially cyclically executing each group of butterfly operations in each level of operation. There is no need to customize the corresponding hardware module for the FFT operation, nor is there any need to convert the original calculation into a multiplication-accumulation form, which reduces the operation cost of the FFT and improves the operation efficiency.

[0084] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0085] Device Embodiment Reference Figure 4, shows a structural block diagram of a processor for executing FFT according to the present invention, the processor comprising an instruction reading unit, a decoding unit, a general register file, an FFT execution unit, a memory access processing unit and a data storage unit; the FFT execution unit and the memory access processing unit share the general register file; The general register file stores the number of points N and the number of levels M corresponding to the Fast Fourier Transform FFT operation to be performed; The decoding unit is used to divide each level of FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit in the FFT operation; the rotation factors corresponding to the same group of butterfly operation units are the same; The FFT execution unit is used to perform each group of butterfly operations in sequence according to the first input value, the second input value and the rotation factor of each butterfly operation unit in each level of operation to obtain a butterfly operation output sequence; The decoding unit is further used to determine the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)th level operation according to the butterfly operation output sequence corresponding to the mth level operation; The FFT execution unit is further used to continue executing each group of butterfly operations in the (m+1)th level operation until all M levels of operations are completed, thereby obtaining a result sequence corresponding to the FFT operation; wherein 0≤m≤(M-1), and m is an integer.

[0086] Optionally, the instruction reading unit is used to obtain, in each level of operation, for each group of butterfly operations, an FFT instruction corresponding to each butterfly operation unit in the group; the FFT instruction carries the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs; The decoding unit is specifically used to: in the decoding stage, determine the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the level m, and write the first input value, the second input value and the rotation factor into the register respectively; The FFT execution unit is specifically used to: in the execution stage, execute the FFT instruction to perform a butterfly operation according to the first input value, the second input value and the rotation factor recorded in the register, and obtain the first operation result and the second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed and completed, and a butterfly operation output sequence is obtained.

[0087] Optionally, the decoding unit is specifically used for: Determine a first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group according to the number of points N and the level m to which the butterfly operation unit belongs; Determine a second input value of the butterfly operation unit according to the first input value and the first interval; Determine, according to the number of points N and the number of stages m to which the butterfly operation unit belongs, a second spacing between two adjacent groups of butterfly operations in the m-th stage operation; The rotation factor corresponding to the butterfly operation unit is determined according to the second spacing.

[0088] Optionally, the decoding unit is specifically used for: Obtaining a storage base address of a rotation factor corresponding to the FFT operation; Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second spacing; Based on the storage base address and the offset address, the rotation factor corresponding to the butterfly operation unit is read from the memory.

[0089] Optionally, the FFT execution unit is specifically used for: In each stage of operation, for each butterfly operation unit, a first input value of the butterfly operation unit is read from a first register, and a second input value of the butterfly operation unit is read from a second register; Calculating the sum of the first input value and the second input value to obtain a first operation result corresponding to the butterfly operation unit; Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in a temporary register; Reading the rotation factor corresponding to the butterfly operation unit from the third register, and reading the intermediate result from the temporary register; A complex multiplication operation is performed on the intermediate result and the rotation factor to obtain a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are completed to obtain a butterfly operation output sequence.

[0090] Optionally, the memory access processing unit is used to: In the m-th level operation, the first operation result and the second operation result corresponding to the butterfly operation unit are sorted according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level operation to obtain the butterfly operation output sequence corresponding to the m-th level operation.

[0091] In summary, an embodiment of the present invention provides a processor for executing FFT, which can split the FFT operation into M levels of operations according to the number of points N of the FFT operation, and divide each level of FFT operation into at least one group of butterfly operations. The result sequence corresponding to the FFT operation can be obtained by sequentially cyclically executing each group of butterfly operations in each level of operation. There is no need to additionally customize the corresponding hardware module for the FFT operation, nor is there any need to convert the original calculation into a multiplication-accumulation form, which reduces the operation cost of the FFT and improves the operation efficiency.

[0092] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0093] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0094] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0095] Reference Figure 6 , is a block diagram of an electronic device for performing FFT provided by an embodiment of the present invention. Figure 6 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the method for executing FFT in the above-mentioned embodiment.

[0096] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0097] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0098] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0099] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The method of performing FFT is shown.

[0100] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0101] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0102] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0103] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0104] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0105] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0106] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0107] The above is a detailed introduction to a method, processor, electronic device and storage medium for performing FFT provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for performing FFT, characterized in that The method comprises: Get the number of points N corresponding to the fast Fourier transform FFT operation to be performed; Dividing the FFT operation into M-level operations according to the number of points N; M is the logarithm of N with 2 as the base; According to the rotation factors corresponding to the butterfly operation units in the FFT operation, each level of FFT operation is divided into at least one group of butterfly operations; the rotation factors corresponding to the same group of butterfly operation units are the same; In each level of operation, each group of butterfly operations is performed in sequence according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence; According to the butterfly operation output sequence corresponding to the m-th level operation, determine the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)-th level operation, and continue to execute each group of butterfly operations in the (m+1)-th level operation until all M-level operations are completed, and obtain the result sequence corresponding to the FFT operation; wherein 0≤m≤(M-1), and m is an integer.

2. The method according to claim 1, characterized in that In each level of operation, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence, including: In each level of operation, for each group of butterfly operations, an FFT instruction corresponding to each butterfly operation unit in the group is obtained; the FFT instruction carries the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs; In the decoding stage, according to the first input value and the level m, the second input value and the rotation factor corresponding to the butterfly operation unit are determined, and the first input value, the second input value and the rotation factor are written into registers respectively; During the execution stage, the FFT instruction is executed to perform a butterfly operation according to the first input value, the second input value and the rotation factor recorded in the register to obtain a first operation result and a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed and a butterfly operation output sequence is obtained.

3. The method according to claim 2, characterized in that The determining, according to the first input value and the level m, the second input value and the rotation factor corresponding to the butterfly operation unit comprises: Determine a first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group according to the number of points N and the level m to which the butterfly operation unit belongs; Determine a second input value of the butterfly operation unit according to the first input value and the first interval; Determine, according to the number of points N and the number of stages m to which the butterfly operation unit belongs, a second spacing between two adjacent groups of butterfly operations in the m-th stage operation; The rotation factor corresponding to the butterfly operation unit is determined according to the second spacing.

4. The method according to claim 3, characterized in that The determining, according to the second spacing, a rotation factor corresponding to the butterfly operation unit includes: Obtaining a storage base address of a rotation factor corresponding to the FFT operation; Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second spacing; Based on the storage base address and the offset address, the rotation factor corresponding to the butterfly operation unit is read from the memory.

5. The method according to claim 1, characterized in that In each level of operation, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence, including: In each stage of operation, for each butterfly operation unit, a first input value of the butterfly operation unit is read from a first register, and a second input value of the butterfly operation unit is read from a second register; Calculating the sum of the first input value and the second input value to obtain a first operation result corresponding to the butterfly operation unit; Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in a temporary register; Reading the rotation factor corresponding to the butterfly operation unit from the third register, and reading the intermediate result from the temporary register; A complex multiplication operation is performed on the intermediate result and the rotation factor to obtain a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are completed to obtain a butterfly operation output sequence.

6. The method according to claim 2 or 5, characterized in that: The method further comprises: In the m-th level operation, the first operation result and the second operation result corresponding to the butterfly operation unit are sorted according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level operation to obtain the butterfly operation output sequence corresponding to the m-th level operation.

7. A processor for performing FFT, characterized in that The processor comprises an instruction fetch unit, a decoding unit, a general register file, an FFT execution unit, a memory access processing unit and a data storage unit; the FFT execution unit and the memory access processing unit share the general register file; The general register file stores the number of points N and the number of levels M corresponding to the Fast Fourier Transform FFT operation to be performed; The decoding unit is used to divide each level of FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit in the FFT operation; the rotation factors corresponding to the same group of butterfly operation units are the same; The FFT execution unit is used to perform each group of butterfly operations in sequence according to the first input value, the second input value and the rotation factor of each butterfly operation unit in each level of operation to obtain a butterfly operation output sequence; The decoding unit is further used to determine the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)th level operation according to the butterfly operation output sequence corresponding to the mth level operation; The FFT execution unit is further used to continue executing each group of butterfly operations in the (m+1)th level operation until all M levels of operations are completed, thereby obtaining a result sequence corresponding to the FFT operation; wherein 0≤m≤(M-1), and m is an integer.

8. The processor according to claim 7, characterized in that The instruction reading unit is used to obtain, in each level of operation, for each group of butterfly operations, the FFT instructions corresponding to each butterfly operation unit in the group; the FFT instructions carry the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs; The decoding unit is specifically used to: in the decoding stage, determine the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the level m, and write the first input value, the second input value and the rotation factor into the register respectively; The FFT execution unit is specifically used to: in the execution stage, execute the FFT instruction to perform a butterfly operation according to the first input value, the second input value and the rotation factor recorded in the register, and obtain the first operation result and the second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed and completed, and a butterfly operation output sequence is obtained.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the method for performing FFT as described in any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the method for performing FFT as claimed in any one of claims 1 to 6.

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