Multi-channel data transmission interface clock tree layout structure, use method thereof and electronic equipment

Abstract

The invention provides a multi-channel data transmission interface clock tree layout structure, a using method thereof and electronic equipment, the clock tree layout structure comprises a clock input interface, multiple groups of data transmission units and an adjustable delay circuit, and different clock delay control signals are input into the adjustable delay circuit; and a local clock signal input by the clock input interface is adjusted by the adjustable delay circuit and then is synchronously output to each data transmission channel in the plurality of groups of data transmission units. According to the multi-channel data transmission interface clock tree layout structure, the number of stages of buffers is small, the chip area is reduced, the hardware cost is reduced, and the integration degree of a chip is improved; due to the fact that the number of stages of the buffer is reduced, layout design difficulty is lowered, layout parasitism caused by multi-stage winding is avoided, and high-speed transmission of signals is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of circuit layout design, and in particular to a multi-channel data transmission interface clock tree layout structure and a use method thereof, and an electronic device. Background Art

[0002] In hardware circuits, when performing multi-channel data transmission, the input clock needs to be synchronously input into multiple data transmission channels to achieve clock synchronization. In related technologies, a multi-level buffer is used to make the clock arrive at each data transmission channel consistent, and each clock passes through the same number of buffer levels, that is, the clock signal passes through the same transmission path and the clock edge of each data transmission channel is aligned. In order to make each transmission link the same, some data links close to the clock signal must form a longer delay by winding to ensure the consistency of all paths, which not only occupies more channels, but also increases the difficulty of designing the clock tree layout, is not conducive to the transmission of high-speed signals, and increases the crosstalk between signals. Due to the increase in buffers, the area of ​​the circuit module increases, the miniaturization of the chip cannot be achieved, and the chip cost increases.

[0003] Therefore, how to provide a highly integrated multi-channel data transmission interface clock layout structure with fewer buffers is a problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a multi-channel data transmission interface clock tree layout structure to solve at least one of the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned purpose and other related purposes, the technical solution provided by this application is as follows.

[0006] In a first aspect, the present application provides a multi-channel data transmission interface clock tree layout structure, including:

[0007] A clock input interface, which receives a local clock signal;

[0008] A plurality of data transmission units, comprising a plurality of data transmission channels;

[0009] An adjustable delay circuit is arranged between the clock input interface and multiple groups of data transmission units. The control end of the adjustable delay circuit inputs a clock delay control signal. By inputting multiple different clock delay control signals, the clock delays output to each of the data transmission channels after adjustment by the adjustable delay circuit are equal.

[0010] In one embodiment of the present invention, the adjustable delay circuit includes a plurality of clock delay units, the input end of each of the clock delay units is connected to the clock input interface, and the output ends of the plurality of clock delay units are connected one-to-one with a plurality of groups of the data transmission units.

[0011] In one embodiment of the present invention, the clock tree layout structure also includes multiple buffers, the input ends of the multiple buffers are connected one-to-one with the output ends of the multiple clock delay units, and the output ends of the multiple buffers are connected one-to-one with the multiple groups of data transmission units.

[0012] In one embodiment of the present invention, the clock delay unit includes a first resistor, N transmission gates and N first capacitors, the capacitance of the i+1th first capacitor is a preset multiple of the capacitance of the i-th first capacitor, the first end of the first resistor is grounded after passing through the i-th transmission gate and the i-th first capacitor, wherein the control ends of the N transmission gates are connected to the clock delay control signal, the second end of the first capacitor is the input end of the clock delay unit, and the common end of the first resistor and the transmission gate is the output end of the clock delay unit, wherein N≥2, 1≤i≤N is a positive integer.

[0013] In one embodiment of the present invention, the clock delay unit also includes a first inverter and a second inverter, the output end of the first inverter is connected to the input end of the second inverter via the first resistor, the input end of the first inverter is the input end of the clock delay unit, and the output end of the second inverter is the output end of the clock delay unit.

[0014] In a second aspect, the present application further provides a method for using a multi-channel data transmission interface clock tree layout structure, which is applied to the multi-channel data transmission interface clock tree layout structure as described above, including:

[0015] Obtaining the clock tree layout structure;

[0016] Dividing a plurality of groups of data transmission channels in the clock tree layout structure into a plurality of groups of data transmission units;

[0017] Determine a plurality of the clock delay control signals according to a positional relationship between a clock input interface and a plurality of groups of the data transmission units in the clock tree layout structure;

[0018] The clock delay of the adjustable delay circuit is adjusted based on the multiple clock delay control signals so that the multiple data transmission channels receive the clock signal synchronously.

[0019] In one embodiment of the present invention, multiple groups of data transmission channels in the clock tree layout structure are divided into multiple groups of data transmission units, including: obtaining the total number of channels of the multiple groups of data transmission channels; and dividing the total number of channels into multiple groups of data transmission units based on preset grouping conditions.

[0020] In one embodiment of the present invention, a plurality of the clock delay control signals are determined according to the positional relationship between the clock input interface and the plurality of groups of the data transmission units in the clock tree layout structure, including: determining a plurality of corresponding clock transmission lines according to the positional relationship between the clock input interface and the plurality of groups of the data transmission units; and generating values ​​of a plurality of the clock delay control signals based on the plurality of the clock transmission lines.

[0021] In one embodiment of the present invention, before determining multiple clock delay control signals based on the positional relationship between the clock input interface and multiple groups of data transmission units in the clock tree layout structure, it also includes: determining the number of configuration bits of the clock delay control signal based on the positional relationship between the multiple groups of data transmission units and a preset adjustment step.

[0022] In a third aspect, the present application also provides an electronic device, which includes one or more multi-channel data transmission interface clock tree layout structures as described above.

[0023] The present application provides a multi-channel data transmission interface clock tree layout structure and its use method, and electronic equipment. The clock tree layout structure includes a clock input interface, multiple groups of data transmission units, and an adjustable delay circuit. By inputting different clock delay control signals to the adjustable delay circuit, the local clock signal input by the clock input interface is adjusted by the adjustable delay circuit and then synchronously output to each data transmission channel in the multiple groups of data transmission units. The multi-channel data transmission interface clock tree layout structure provided by the present application has a small number of buffer levels, which reduces the chip area, reduces the hardware cost, and improves the integration of the chip; because the number of buffer levels is reduced, the difficulty of layout design is reduced, and layout parasitism caused by multi-level winding is avoided, which facilitates high-speed transmission of signals.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0026] Figure 1 This is a block diagram of a traditional clock tree layout;

[0027] Figure 2 This is a schematic diagram of the traditional clock tree layout;

[0028] Figure 3 A block diagram of a clock tree layout structure of a multi-channel data transmission interface shown in an exemplary embodiment of the present invention;

[0029] Figure 4 A block diagram showing a multi-channel data transmission interface clock tree layout structure including a buffer according to an exemplary embodiment of the present invention;

[0030] Figure 5 A schematic diagram of the specific structure of a clock delay unit shown as an exemplary embodiment of the present invention;

[0031] Figure 6 A schematic diagram of a specific structure of a clock delay unit including an inverter is shown as an exemplary embodiment of the present invention;

[0032] Figure 7 A schematic diagram of multiple groups of data transmission units is shown as an exemplary embodiment of the present invention;

[0033] Figure 8 A schematic diagram of local clock transmission of a multi-channel data transmission interface clock tree layout structure shown as an exemplary embodiment of the present invention;

[0034] Fig. 9 The present invention is a flowchart of a method for using a clock tree layout structure of a multi-channel data transmission interface according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0036] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic manner, and thus the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0037] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0038] In electronic circuits, PAD refers to a pad on a circuit board. The specific role of each pad is defined according to its actual function. For example, PAD can represent a data transmission channel, the positive and negative poles of a power supply, the input or output of a buffer, etc.

[0039] In hardware circuits, when performing multi-channel data transmission, the input local clock signal needs to be input into each data transmission channel for clock synchronization. Figure 1 As shown, the local clock signal passes through multiple buffers to reach multiple single data transmission channels, where the transmission path of each data transmission channel is consistent, and each clock passes through the same number of buffer levels, that is, the local clock signal passes through the same transmission path, each path has the same load, and the clock signal delay received by each data transmission channel is the same, and the clock edges of multiple data transmission channels are aligned. Figure 2 As shown, the path from the local clock signal clkin to each data transmission channel PAD is the same, and it reaches a single data transmission channel PAD (clkin→0→1→2→3→PAD) after passing through 4 levels of buffering. The load of each level is the same, so that the delay from clkin to PAD is the same, and the clock edges of multiple data transmission channels are aligned.

[0040] like Figure 2 As shown, in the prior art, in order to make each clock transmission link the same, some clock transmission links close to the clock signal must form a longer delay by winding to ensure the consistency of all paths, which not only occupies more channels, but also increases the difficulty of designing the clock tree layout, is not conducive to the transmission of high-speed signals, and increases the crosstalk between signals. Because the transmission path of the clock signal becomes longer, the number of buffer levels in the clock tree is more, which increases the area of ​​the circuit module, makes it impossible to miniaturize the chip, and the chip cost is high.

[0041] like Figure 3 As shown, in an exemplary embodiment, a multi-channel data transmission interface clock tree layout structure includes:

[0042] A clock input interface, which receives a local clock signal;

[0043] A plurality of data transmission units, comprising a plurality of data transmission channels;

[0044] An adjustable delay circuit is arranged between a clock input interface and multiple groups of data transmission units. A clock delay control signal is input to the control end of the adjustable delay circuit. By inputting multiple different clock delay control signals, the clock delays output to each data transmission channel after adjustment by the adjustable delay circuit are equal.

[0045] In detail, the adjustable delay circuit includes a plurality of clock delay units, the input end of each clock delay unit is connected to the clock input interface, and the output ends of the plurality of clock delay units are connected to the plurality of groups of data transmission units in a one-to-one correspondence.

[0046] In detail, Figure 4 As shown, the clock tree layout structure also includes multiple buffers, the input ends of the multiple buffers are connected one-to-one with the output ends of the multiple clock delay units, and the output ends of the multiple buffers are connected one-to-one with the multiple groups of data transmission units. Adding buffers can adjust the load capacity of the transmission route and shape the clock signal.

[0047] In detail, the clock delay unit includes a first resistor, N transmission gates and N first capacitors, the capacitance of the i+1th first capacitor is a preset multiple of the capacitance of the i-th first capacitor, the first end of the first resistor is grounded after passing through the i-th transmission gate and the i-th first capacitor, wherein the control ends of the N transmission gates are connected to the clock delay control signal, the second end of the first capacitor is the input end of the clock delay unit, and the common end of the first resistor and the transmission gate is the output end of the clock delay unit, wherein N≥2, 1≤i≤N is a positive integer.

[0048] Specifically, Figure 5As shown, when N is 4, the clock delay unit includes a first resistor R1, 4 transmission gates and 4 first capacitors (C11, C12, C13, C14), the capacitance of the second first capacitor C12 is twice the capacitance of the first first capacitor C11, that is, the capacitance ratio of the fourth first capacitor to the first first capacitor is 8:4:2:1, the sum of the output capacitance values ​​is equal to the sum of the capacitances of each branch, the first end of the first resistor R1 is grounded after passing through the first transmission gate and the first first capacitor C11, the first end of the first resistor R1 is grounded after passing through the second transmission gate and the second The first end of the first resistor R1 is connected to the ground after passing through the third transmission gate and the third first capacitor C13, and the first end of the first resistor R1 is connected to the ground after passing through the fourth transmission gate and the fourth first capacitor C14, wherein the control ends of the four transmission gates are connected to the clock delay control signal SEL, the clock delay control signal SEL includes the value of 4 configuration bits, the control end of each transmission gate is connected to a configuration bit of the clock delay control signal SEL, and the control ends of the first transmission gate to the fourth transmission gate are connected to the first configuration bit sel of the clock delay control signal in sequence. <0> To the fourth configuration bit sel <3> The clock delay control signal is a 4-bit binary control signal, which is selected from the low bit sel according to the resistance value of the first capacitor. <0> Connect to high sel <3> The second end of the first resistor R1 is the input end of the clock delay unit, the input end of the clock delay unit is connected to the clock input interface, and the common end of the first resistor R1 and the four transmission gates is the output end of the clock delay unit. The preset multiple is not only 2 times, but can also be set according to actual conditions to achieve delay processing of the local clock signal.

[0049] In more detail, Figure 6 As shown, the clock delay unit also includes a first inverter NOT1 and a second inverter NOT2. The output end of the first inverter NOT1 is connected to the input end of the second inverter NOT2 via a first resistor R1. The input end of the first inverter NOT1 is the input end of the clock delay unit. The input end of the clock delay unit is connected to the clock input interface. The output end of the second inverter NOT2 is the output end of the clock delay unit. The addition of the front and rear two inverters is used to enhance the driving capability.

[0050] like Figure 3-8 As shown, the design principle of the multi-channel data transmission interface clock tree layout structure provided by this application is as follows:

[0051] The local clock signal is input into the adjustable delay circuit through the local clock interface, and the delay time of each group of data transmission units is adjusted by the clock delay unit in the adjustable delay circuit, so that the clock delay output to each group of data transmission channels after adjustment by the adjustable delay circuit is equal.

[0052] like Figure 7 As shown, Figure 7 It includes 42 data transmission channels, which are divided into 7 groups through pre-designed division rules. Each data transmission unit includes 6 data transmission channels. VDD and VSS represent power supply and ground respectively.

[0053] Combination Figure 7 and Figure 8 , the local clock interface is arranged at one side of the multiple groups of data transmission units, and the adjustable delay circuit is arranged between the local clock interface and the multiple groups of data transmission units, such as Figure 7 As shown, the data transmission paths of the 7 groups of data transmission units are divided into 4 different transmission paths. Therefore, the control bit number of the clock delay control signal can be set to 4 bits. The value of the clock delay control signal corresponding to each data transmission unit is determined according to the 7 groups of data transmission units and the clock input interface, as shown in FIG. Figure 8 As shown, since there is a path with the same transmission path load, the clock delay control signals corresponding to the left and right adjacent related data transmission units are the same.

[0054] like Figure 5 or Figure 6 As shown, the clock delay control signal is input into the clock delay unit. If the value of a certain clock delay unit is high, the corresponding transmission gate is turned on, and the first capacitor connected to the transmission gate is used for corresponding delay. When multiple transmission gates are turned on at the same time, the local clock signal is delayed accordingly by the values ​​of multiple first capacitors. The calculation formula for the delayed clock is: R1*C SUM , C SUM It is the sum of the first capacitances of each branch when the transmission gate is turned on.

[0055] Since the value of the i+1th first capacitor is twice that of the i-th first capacitor, the transmission delay of the local clock signal can be achieved by only adjusting the switching state of the transmission gate, so that the signal output by the adjustable delay circuit, after passing through the buffer, the clock signal delays received by each data transmission channel are equal, that is, the synchronous transmission processing of the local clock signal is achieved without the need for complicated winding.

[0056] like Fig. 9 As shown, the present application also provides a method for using a multi-channel data transmission interface clock tree layout structure, which is applied to the multi-channel data transmission interface clock tree layout structure as described above, including:

[0057] S910, obtaining a clock tree layout structure;

[0058] S920, dividing the multiple groups of data transmission channels in the clock tree layout structure into multiple groups of data transmission units;

[0059] S930, determining a plurality of clock delay control signals according to a positional relationship between a clock input interface and a plurality of groups of data transmission units in a clock tree layout structure;

[0060] S940, adjusting the clock delay of the adjustable delay circuit based on multiple clock delay control signals, so that multiple data transmission channels receive clock signals synchronously.

[0061] Specifically, dividing multiple groups of data transmission channels in the clock tree layout structure into multiple groups of data transmission units includes: obtaining the total number of channels of the multiple groups of data transmission channels; and dividing the total number of channels into multiple groups of data transmission units based on preset grouping conditions. Specifically, Figure 7 As shown, if the total number of channels of the multiple groups of data transmission channels in the clock layout structure is 42, the clock layout structure also includes a PAD of a positive power supply VDD and a negative power supply or a ground potential VSS, and the preset grouping condition is that each data transmission unit includes 6 data transmission channels, then the 42 groups of data transmission channels are divided into 7 groups of data transmission units. It should be noted that if the total number of channels is 34, and the preset grouping condition is that each data transmission unit includes 4 to 5 data transmission channels, the 34 groups of data transmission channels can be divided into 8 groups of data transmission channels.

[0062] Specifically, multiple clock delay control signals are determined according to the positional relationship between the clock input interface and the multiple groups of data transmission units in the clock tree layout structure, including: determining multiple corresponding different transmission lines according to the positional relationship between the clock input interface and the multiple groups of data transmission units; and generating multiple clock delay control signal values ​​based on the multiple transmission lines. Specifically, Figure 8 As shown, the local clock interface is set at one end of multiple groups of data transmission units. If there is no adjustable delay circuit and multiple buffers, the local clock signal is input from the local clock interface to each group of data transmission units, 7 transmission routes are determined, and the farthest transmission route is determined from the 7 transmission routes. According to the route difference between the farthest transmission route and other transmission routes, the specific values ​​of multiple delay control signals are determined according to different route differences.

[0063] In detail, before determining multiple clock delay control signals according to the positional relationship between the clock input interface and multiple groups of data transmission units in the clock tree layout structure, it also includes: determining the number of configuration bits of the clock delay control signal according to the positional relationship between the multiple groups of data transmission units and the preset adjustment step.

[0064] Specifically, Figure 7As shown, the clock tree layout structure includes 7 groups of data transmission units. Since the transmission routes of the two adjacent data transmission units on the left and right are the same, the delay time of the two adjacent data transmission units on the left and right is equal. The data transmission unit farthest from the clock input interface does not need to be delayed. According to the positional relationship between the 7 groups of data transmission units, it is determined that there are 3 routes that need to be delayed. If the delay time of the two adjacent transmission routes above and below is a preset adjustment step, 2 binary digits are required, that is, the configuration bit number of the clock delay control signal is at least two, that is, the clock delay control signal is {01, 10, 11}, which can achieve different time delays for the adjustable delay circuit. However, the accuracy of the minimum configuration bit number is low, there is a certain error, and the preset adjustment step is less than the delay time of the two adjacent transmission routes above and below. In this case, the configuration bit number of the clock delay control signal can be increased. For example, the configuration bit number of the clock control signal is set to 4 bits. Then, by adjusting the value of the 4-bit configuration bit number, different delay times of the clock control signal output can be achieved, and the accuracy of the delay time of the clock delay signal can also be improved, so as to facilitate the subsequent adjustment of the delay time.

[0065] In step S940, multiple clock delay control signals are input into the adjustable delay circuit to implement corresponding delays for different transmission routes, so that after the local clock signal is input into the clock input interface, it can reach multiple data transmission channels at the same time after being adjusted by the adjustable clock circuit, without requiring too many buffers, thereby improving the integration of the chip.

[0066] The present application also provides an electronic device, comprising one or more multi-channel data transmission interface clock tree layout structures as described above, so that the electronic device can transmit data synchronously.

[0067] The present application provides a multi-channel data transmission interface clock tree layout structure and its use method, and electronic equipment. The clock tree layout structure includes a clock input interface, multiple groups of data transmission units, and an adjustable delay circuit. By inputting different clock delay control signals to the adjustable delay circuit, the local clock signal input by the clock input interface is adjusted by the adjustable delay circuit and synchronously output to each data transmission channel in the multiple groups of data transmission units. Multiple buffers are added to the adjustable delay circuit and the multiple groups of data transmission units to improve the carrying capacity of clock transmission; the delay of multiple clock transmission paths is achieved by the capacitance value connected to the clock delay unit in the adjustable delay circuit, and the circuit structure is simple and easy to control. The multi-channel data transmission interface clock tree layout structure provided by the present application has a small number of buffer levels, which reduces the chip area, reduces the hardware cost, and improves the integration of the chip; because the number of buffer levels is reduced, the difficulty of layout design is reduced, and layout parasitism caused by multi-level winding is avoided, which facilitates high-speed transmission of signals.

[0068] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A multi-channel data transmission interface clock tree layout structure, characterized in that: include: A clock input interface, which receives a local clock signal; A plurality of data transmission units, comprising a plurality of data transmission channels; An adjustable delay circuit is arranged between the clock input interface and multiple groups of data transmission units. The control end of the adjustable delay circuit inputs a clock delay control signal. By inputting multiple different clock delay control signals, the clock delays output to each of the data transmission channels after adjustment by the adjustable delay circuit are equal.

2. The multi-channel data transmission interface clock tree layout structure according to claim 1, characterized in that: The adjustable delay circuit includes a plurality of clock delay units, the input end of each of the clock delay units is connected to the clock input interface, and the output ends of the plurality of clock delay units are connected to the plurality of groups of data transmission units in a one-to-one correspondence.

3. The multi-channel data transmission interface clock tree layout structure according to claim 2, characterized in that: The clock tree layout structure also includes multiple buffers, the input ends of the multiple buffers are connected to the output ends of the multiple clock delay units in a one-to-one correspondence, and the output ends of the multiple buffers are connected to the multiple groups of data transmission units in a one-to-one correspondence.

4. The multi-channel data transmission interface clock tree layout structure according to claim 2, characterized in that: The clock delay unit includes a first resistor, N transmission gates and N first capacitors, the capacitance of the i+1th first capacitor is a preset multiple of the capacitance of the i-th first capacitor, the first end of the first resistor is grounded after passing through the i-th transmission gate and the i-th first capacitor, wherein the control ends of the N transmission gates are connected to the clock delay control signal, the second end of the first resistor is the input end of the clock delay unit, and the common end of the first resistor and the transmission gate is the output end of the clock delay unit, wherein N≥2, 1≤i≤N is a positive integer.

5. The multi-channel data transmission interface clock tree layout structure according to claim 4, characterized in that: The clock delay unit also includes a first inverter and a second inverter. The output end of the first inverter is connected to the input end of the second inverter via the first resistor. The input end of the first inverter is the input end of the clock delay unit, and the output end of the second inverter is the output end of the clock delay unit.

6. A method for using a multi-channel data transmission interface clock tree layout structure, characterized in that: The multi-channel data transmission interface clock tree layout structure applied to any one of claims 1 to 5 comprises: Obtaining the clock tree layout structure; Dividing a plurality of groups of data transmission channels in the clock tree layout structure into a plurality of groups of data transmission units; Determine a plurality of the clock delay control signals according to a positional relationship between a clock input interface and a plurality of groups of the data transmission units in the clock tree layout structure; The clock delay of the adjustable delay circuit is adjusted based on the multiple clock delay control signals so that the multiple data transmission channels receive the clock signal synchronously.

7. The method for using the multi-channel data transmission interface clock tree layout structure according to claim 6, characterized in that: Dividing the plurality of groups of data transmission channels in the clock tree layout structure into a plurality of groups of data transmission units comprises: Obtaining the total number of channels of the plurality of groups of data transmission channels; The total number of channels is divided into a plurality of groups of data transmission units based on a preset grouping condition.

8. The method for using the multi-channel data transmission interface clock tree layout structure according to claim 6, characterized in that: Determining a plurality of the clock delay control signals according to the positional relationship between the clock input interface and the plurality of groups of the data transmission units in the clock tree layout structure includes: Determine a plurality of corresponding clock transmission lines according to a positional relationship between the clock input interface and a plurality of groups of the data transmission units; A plurality of values ​​of the clock delay control signal are generated based on a plurality of the clock transmission lines.

9. The method for using the multi-channel data transmission interface clock tree layout structure according to claim 8, characterized in that: Before determining the multiple clock delay control signals according to the positional relationship between the clock input interface and the multiple groups of data transmission units in the clock tree layout structure, it also includes: determining the number of configuration bits of the clock delay control signal according to the positional relationship between the multiple groups of data transmission units and the preset adjustment step.

10. An electronic device, characterized in that: It comprises one or more multi-channel data transmission interface clock tree layout structures as described in any one of claims 1-5.

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