MOS device layout design method, MOS device layout and MOS device
By calling multiple first layouts in the MOS device layout design and converting, the problem of reconstructing the ring or strip grid layout during design is solved, efficient conversion and efficiency improvement are achieved, and multiple layout needs are met.
Patent Information
- Application Number
- CN202411258053.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2025-01-03
AI Technical Summary
When designing MOS device layouts, the prior art requires reconstructing the ring grid layout or bar grid layout, resulting in additional time and workload and reducing work efficiency.
By calling multiple first layouts and converting them into second layouts, efficient conversion of MOS device layouts is achieved. The specific method includes reducing or increasing the area of the polysilicon layer and the active region to meet the needs of the ring gate or bar gate structure. .
It realizes efficient conversion of the two layouts, reduces workload, improves work efficiency, and meets the various layout needs during design.
Smart Images
Figure CN119250005A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of monolithic integrated circuit design, and in particular to a MOS device layout design method, a MOS device layout and a MOS device. Background Art
[0002] To design a MOS device layout, a large number of ring-gate layouts and strip-gate layouts are required. When there are only ring-gate layouts or strip-gate layouts in the layout library, if both the ring-gate layout and the strip-gate layout are needed, the strip-gate layout or the ring-gate layout needs to be rebuilt, so that extra time is needed to build the required layout when designing the MOS device layout, resulting in increased design workload and reduced work efficiency. Summary of the invention
[0003] In view of the above-mentioned shortcomings of the prior art, the present application provides a MOS device layout design method, a MOS device layout and a MOS device, which are used to solve at least one defect in the prior art.
[0004] To achieve the above-mentioned purpose and other purposes, the present application provides a MOS device layout design method, including: calling multiple first layouts; converting one or more of the multiple first layouts into a second layout; wherein the first layout and the second layout are layouts constituting a MOS device.
[0005] In one embodiment of the present invention, the first layout is a layout with a stripe-gate structure, and the second layout is a layout with a ring-gate structure.
[0006] In one embodiment of the present invention, the first layout is a layout with a ring-gate structure, and the second layout is a layout with a stripe-gate structure.
[0007] In one embodiment of the present invention, the first layout includes a first source terminal, a second source terminal, a drain terminal, a gate terminal, an active area, and a polysilicon layer. The first source terminal, the second source terminal, and the drain terminal are respectively in contact with the active area, and the drain terminal is arranged between the first source terminal and the second source terminal; the polysilicon layer is arranged on the active area and adheres to the active area, surrounds the drain terminal and is not in contact with the drain terminal, the first source terminal, and the second source terminal; there is a gap between the polysilicon layer and the active area layer, so that the polysilicon layer in contact with the active area is a strip structure.
[0008] In one embodiment of the present invention, the first layout includes a first source terminal, a second source terminal, a drain terminal, a gate terminal, an active area, and a polysilicon layer. The first source terminal, the second source terminal, and the drain terminal are respectively in contact with the active area. The drain terminal is arranged between the first source terminal and the second source terminal. The polysilicon layer is arranged on the active area and adheres to the active area and surrounds the drain terminal and does not contact the drain terminal, the first source terminal, and the second source terminal. There is no gap between the polysilicon layer and the active area layer, so that the polysilicon layer in contact with the active area is a ring structure.
[0009] In one embodiment of the present invention, when the first layout is a layout with a stripe gate structure and the second layout is a layout with a ring gate structure, the step of converting the first layout into the second layout includes at least one of the following: reducing the area of the polysilicon layer so that there is no gap between the polysilicon layer and the active area; increasing the area of the active area so that there is no gap between the polysilicon layer and the active area.
[0010] In one embodiment of the present invention, when the first layout is a layout with a ring gate structure and the second layout is a layout with a strip gate structure, the step of converting the first layout into the second layout includes at least one of the following: increasing the area of the polysilicon layer to form a gap between the polysilicon layer and the active area; reducing the area of the active area to form a gap between the polysilicon layer and the active area.
[0011] To achieve the above objectives and other objectives, the present application provides a MOS device layout formed using the design method.
[0012] To achieve the above objectives and other objectives, the present application provides a MOS device manufactured according to the MOS device layout.
[0013] Beneficial effects of this application:
[0014] The present application discloses a MOS device layout design method, comprising: calling multiple first layouts; converting one or more of the multiple first layouts into a second layout; wherein the first layout and the second layout are layouts constituting the MOS device. The present application can simultaneously meet the requirements of the two layouts by converting the already called layout when the new layout cannot be called, realizes efficient conversion of the two layouts, reduces workload, improves work efficiency, and is highly efficient.
[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0017] Figure 1 A flow chart of a MOS device layout design method according to an embodiment of the present application;
[0018] Figure 2 A structural diagram of a MOS device according to an embodiment of the present application;
[0019] Figure 3 A schematic diagram of a layout with a stripe grid structure according to an embodiment of the present application;
[0020] Figure 4 Schematic diagram of a layout with a gate-all-around structure according to an embodiment of the present application. DETAILED DESCRIPTION
[0021] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0022] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0023] Although the terms "first", "second", "A", and "B", etc. may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the following technology. The term "and / or" includes a combination of multiple related items or any of the multiple related items.
[0024] As used herein, unless the context indicates otherwise, the singular form is intended to include the plural form, and it will be understood that the term "comprising" means the presence of stated features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.
[0025] Before the detailed description, it is intended to clarify that the division of components in this specification is divided only by the main function of each component. That is, two or more components to be described below can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main function of the component, each component to be described below can also perform some or all of the functions of other components, and some of the main functions of each component can be exclusively performed by other components.
[0026] See also Figure 1 , Figure 1 This is a flow chart of a MOS device layout design method according to an embodiment of the present application. Figure 1 As shown, the MOS device layout design method includes:
[0027] Step S110, calling multiple first layouts;
[0028] Step S120, converting one or more of the plurality of first layouts into a second layout; wherein the first layout and the second layout are layouts constituting MOS devices.
[0029] The following is a detailed description of each step.
[0030] In step S110 , multiple first layouts are called.
[0031] The first layout can be any layout unit in the layout library. The integrated circuit layout can include multiple identical layouts, that is, one layout can be repeated multiple times in the integrated circuit layout. The integrated circuit layout can also include multiple completely different layouts, that is, all layouts in the integrated circuit layout are different.
[0032] Specifically, the designer can first determine the layout unit to be called according to the functional requirements of the integrated circuit layout, and then select the layout to be called from the layout library, and generate the integrated circuit layout through the selected layout. Among them, one layout can correspond to one identifier.
[0033] It should be noted that the layout library contains all layouts that may be used in the integrated circuit layout. The integrated circuit layout is generated by calling one or more layouts in the layout library, thereby reducing the time for generating the integrated circuit layout.
[0034] In the embodiment of the present application, the integrated circuit layout includes a layout for forming a MOS device, wherein the structure of the MOS device is as follows: Figure 2 shown.
[0035] In an embodiment of the present application, the first layout is a layout with a specific stripe grid structure, and the second layout is a layout with a ring grid structure. Of course, in another embodiment of the present application, the first layout is a layout with a ring grid structure, and the second layout is a layout with a stripe grid structure.
[0036] The structure of the first layout is as follows: Figure 3 As shown, the structure of the second version is as follows Figure 4 shown.
[0037] See also Figure 3 In an embodiment of the present application, the first layout includes a first source terminal, a second source terminal, a drain terminal, a gate terminal, an active area 110, and a polysilicon layer 150. The first source terminal, the second source terminal, and the drain terminal are respectively in contact with the active area, and the drain terminal is arranged between the first source terminal and the second source terminal; the polysilicon layer is arranged on the active area and adheres to the active area, surrounds the drain terminal and does not contact the drain terminal, the first source terminal, and the second source terminal; there is a gap between the polysilicon layer and the active area layer, so that the polysilicon layer in contact with the active area is a strip structure.
[0038] Specifically, Figure 3 As shown, the MOS tube finger (the number of gates) is adjusted to 2, the active area 110 (red area) of the MOS tube is connected to the metal layer 140 (blue area) through the contact hole 120 (green area), and the source terminal and the gate terminal are arranged on the metal layer. The drain terminal D is in the middle, the first source terminal S and the second source terminal S are distributed on both sides of the drain terminal D, and the gate terminal G is connected to the outside through the polysilicon layer 150 (purple area). Since there is a gap between the polysilicon layer and the active area layer, the polysilicon layer 150 between the active area 110 (the area framed by the thick black solid line in the figure) appears as a straight line.
[0039] See also Figure 2 In the embodiment of the present application, the first layout includes a first source terminal S, a second source terminal S, a drain terminal D, a gate terminal G, an active area 110, and a polysilicon layer 150. The first source terminal, the second source terminal, and the drain terminal are respectively in contact with the active area. The drain terminal is arranged between the first source terminal and the second source terminal. The polysilicon layer is arranged on the active area and adheres to the active area and surrounds the drain terminal and does not contact the drain terminal, the first source terminal, and the second source terminal. There is no gap between the polysilicon layer and the active area layer, so that the polysilicon layer in contact with the active area is a ring structure.
[0040] Specifically, Figure 4As shown, the MOS tube finger (the number of gates) is adjusted to 2, the active area 110 (red area) of the MOS tube is connected to the layer metal 140 (blue area) through the contact hole 120 (green area), and the source terminal and the gate terminal are set on the metal layer. The drain terminal D is in the middle, the first source terminal S and the second source terminal S are distributed on both sides of the drain terminal D, and the gate terminal G is connected to the outside through the polysilicon layer 150 (purple area). Since there is no gap between the polysilicon layer and the active area layer, the polysilicon layer 150 between the active area 110 (the area framed by the thick black solid line in the figure) is in the shape of a ring.
[0041] In an embodiment of the present application, when the first layout is a layout with a stripe gate structure and the second layout is a layout with a ring gate structure, the step of converting the first layout into the second layout includes at least one of the following: reducing the area of the polysilicon layer so that there is no gap between the polysilicon layer and the active area; increasing the area of the active area so that there is no gap between the polysilicon layer and the active area. By reducing the area of the polysilicon layer or increasing the area of the active area so that there is no gap between the polysilicon layer and the active area, the first layout is quickly converted into the second layout.
[0042] In an embodiment of the present application, when the first layout is a layout with a ring gate structure and the second layout is a layout with a stripe gate structure, the step of converting the first layout into the second layout includes at least one of the following: increasing the area of the polysilicon layer to form a gap between the polysilicon layer and the active area; reducing the area of the active area to form a gap between the polysilicon layer and the active area. By increasing the area of the polysilicon layer or reducing the area of the active area to form a gap between the polysilicon layer and the active area, the second layout is quickly converted into the first layout.
[0043] It should be noted that Figure 3 and Figure 4 It is only shown that the purpose of converting the stripe gate structure layout into the ring gate structure layout is achieved by increasing the area of the active area. For the case of converting the stripe gate structure layout into the ring gate structure layout by reducing the polysilicon layer, converting the ring gate structure layout into the stripe gate structure layout by reducing the area of the active area, or converting the ring gate structure layout into the stripe gate structure layout by increasing the polysilicon layer, those skilled in the art can adjust the corresponding parts based on the above-mentioned method of converting the stripe gate structure layout into the ring gate structure layout by increasing the area of the active area, so as to achieve the purpose of converting the stripe gate structure layout into the ring gate structure layout or converting the ring gate structure layout into the stripe gate structure layout.
[0044] In summary, the present application proposes a MOS device layout design method, comprising: calling multiple first layouts; converting one or more of the multiple first layouts into a second layout; wherein the first layout and the second layout are layouts constituting a MOS device. The present application can simultaneously meet the needs of two layouts by converting the already called layout when a new layout cannot be called, thereby achieving efficient conversion of the two layouts, reducing workload, improving work efficiency, and being highly efficient. The present invention is suitable for scenarios where there is only one layout structure in the layout library, but another layout structure is required during integrated circuit layout design.
[0045] The present application also provides a MOS device layout, which is formed using the MOS device layout design method of the aforementioned embodiment.
[0046] The present application also provides a MOS device, which is manufactured according to the MOS device layout of the aforementioned embodiment.
[0047] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.
Claims
1. A MOS device layout design method, characterized in that: The design method comprises: Call multiple first layouts; One or more of the plurality of first layouts are converted into a second layout; wherein the first layout and the second layout are layouts constituting MOS devices.
2. The MOS device layout design method according to claim 1, characterized in that: The first layout is a layout with a stripe grid structure, and the second layout is a layout with a ring grid structure.
3. The MOS device layout design method according to claim 1, characterized in that: The first layout is a layout with a ring-gate structure, and the second layout is a layout with a stripe-gate structure.
4. The MOS device layout design method according to claim 2, characterized in that: The first layout includes a first source terminal, a second source terminal, a drain terminal, a gate terminal, an active area, and a polysilicon layer. The first source terminal, the second source terminal, and the drain terminal are respectively in contact with the active area, and the drain terminal is arranged between the first source terminal and the second source terminal; the polysilicon layer is arranged on the active area and adheres to the active area, surrounds the drain terminal and does not contact the drain terminal, the first source terminal, and the second source terminal; there is a gap between the polysilicon layer and the active area layer, so that the polysilicon layer in contact with the active area is a strip structure.
5. The MOS device layout design method according to claim 3, characterized in that: The first layout includes a first source terminal, a second source terminal, a drain terminal, a gate terminal, an active area, and a polysilicon layer. The first source terminal, the second source terminal, and the drain terminal are respectively in contact with the active area. The drain terminal is arranged between the first source terminal and the second source terminal. The polysilicon layer is arranged on the active area and adheres to the active area and surrounds the drain terminal and does not contact the drain terminal, the first source terminal, and the second source terminal. There is no gap between the polysilicon layer and the active area layer, so that the polysilicon layer in contact with the active area is a ring structure.
6. The MOS device layout design method according to claim 4, characterized in that: When the first layout is a layout with a stripe grid structure and the second layout is a layout with a ring grid structure, the step of converting the first layout into the second layout includes at least one of the following: Reducing the area of the polysilicon layer so that there is no gap between the polysilicon layer and the active area; The area of the active region is increased so that there is no gap between the polysilicon layer and the active region.
7. The MOS device layout design method according to claim 5, characterized in that: When the first layout is a layout with a ring-gate structure and the second layout is a layout with a stripe-gate structure, the step of converting the first layout into the second layout includes at least one of the following: Increasing the area of the polysilicon layer to form a gap between the polysilicon layer and the active area; The area of the active region is reduced so that a gap is formed between the polysilicon layer and the active region.
8. A MOS device layout, characterized in that: It is formed by the design method described in any one of claims 1 to 7.
9. A MOS device, characterized in that: The MOS device layout according to claim 8 is manufactured.