Display panel driving method and display device

Abstract

The embodiment of the invention provides a display panel driving method and a display device. The driving method comprises the following steps: generating a first time sequence signal comprising a plurality of first-type pulses; wherein the time sequence of the first type of pulses is located at the tail of the time sequence of the refresh frame, the pulse width of the first type of pulses is NH, and the value range of N is larger than or equal to 8 and smaller than or equal to 12; scanning an initial signal end of a first gate drive circuit of the display panel by using the first time sequence signal; wherein the output end of the first gate drive circuit is used for providing a control signal for a compensation transistor of the pixel circuit. By shortening the pulse width of the first type of pulse in the refresh frame, the high level charging time of the initial signal end of the first gate drive circuit is shortened, and the positive charges in the parasitic capacitance and the capacitor CQ are reduced, so that the node Q can be switched from the high level to the low level in time, and the poor display phenomenon of upper and lower split screens is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel driving method and a display device. Background Art

[0002] Current display screens are prone to parasitic capacitance due to corrosion during reliability tests (high temperature and high humidity), and the presence of parasitic capacitance may lead to poor display. For example, for the first gate drive circuit (SC1) that provides control signals to the compensation TFT (Thin Film Transistor) of the pixel circuit, the circuit structure is as follows: Figure 1 As shown (parasitic capacitance can be connected in parallel across capacitor CQ), the timing of each signal can be seen in Figure 2 (In the refresh frame, the second pulse width of SC1's start signal terminal SC1_STV is 16H). When SC1_STV (SC1's start signal terminal) is at a high level and SC1_CK (SC1's clock signal terminal) is at a low level, capacitor CQ and parasitic capacitors will be charged with positive charges, and transistor T1 will be in the off state. When SC1_STV is converted to a low level, the positive charges in capacitor CQ and parasitic capacitors will be neutralized first, and then capacitor CQ will be charged with negative charges, so that node Q is converted to a low level and transistor T1 is turned on. However, if there are more positive charges in the parasitic capacitors and capacitor CQ, the voltage at node Q may not be able to turn on transistor T1, resulting in poor display of the upper and lower split screens, such as Figure 3 shown. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a display panel driving method and a display device to improve the poor display phenomenon of the upper and lower split screen. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a display panel driving method, the method comprising:

[0005] Generate a first timing signal including a plurality of first-type pulses; wherein the timing of the first-type pulses is located at the end of the refresh frame timing, and the pulse width of the first-type pulses is NH, and the value range of N is 8≤N≤12;

[0006] The first timing signal is used to scan the start signal end of the first gate driving circuit of the display panel; wherein the output end of the first gate driving circuit is used to provide a control signal to the compensation transistor of the pixel circuit.

[0007] In a possible implementation manner, the first timing signal further includes a plurality of second-type pulses;

[0008] The timing of the second type of pulse is located at the head of the refresh frame timing, and the pulse width of the second type of pulse is MH, and the value range of M is N≤M≤12;

[0009] The pulse interval width between the first type of pulses and the second type of pulses is LH, and the value range of L is 16≤L≤24.

[0010] In a possible implementation, the method further includes:

[0011] Generate a third timing signal including a plurality of third-type pulses; wherein the timing length of the third-type pulse is not less than the timing length of the holding frame, and in time sequence, the start time of the holding frame is not earlier than the start time of the third-type pulse, and the end time of the holding frame is not later than the end time of the third-type pulse;

[0012] The clock signal terminal of the second gate driving circuit of the display panel is scanned by using the third timing signal; wherein the output terminal of the second gate driving circuit is used to provide a control signal to the first reset transistor of the pixel circuit.

[0013] In a possible implementation manner, the first type of pulses, the second type of pulses, and the third type of pulses are all invalid level signals.

[0014] In a possible implementation, the method further includes:

[0015] Generate a fourth timing signal including a plurality of fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have overlapping parts in time sequence;

[0016] The fourth timing signal is used to scan the start signal terminal of the second gate driving circuit.

[0017] In a possible implementation manner, the fourth type of pulse is an invalid level signal.

[0018] In a second aspect, an embodiment of the present application provides a display device, the display device comprising a display panel and a display driver chip;

[0019] The display panel comprises a plurality of pixel rows, a first gate driving circuit connected to each pixel row, and a second gate driving circuit connected to each pixel row; each pixel row comprises a plurality of pixel circuits; each pixel circuit comprises a compensation transistor and a first reset transistor;

[0020] The display driver chip is used to: generate a first timing signal including multiple first-type pulses; wherein the timing of the first-type pulses is located at the end of the refresh frame timing, and the pulse width of the first-type pulses is NH, and the value range of N is 8≤N≤12; use the first timing signal to scan the start signal end of the first gate drive circuit of the display panel; wherein the output end of the first gate drive circuit is used to provide a control signal to the compensation transistor of the pixel circuit.

[0021] In one possible implementation,

[0022] The first timing signal also includes multiple second-type pulses; the timing of the second-type pulses is located at the head of the refresh frame timing, and the pulse width of the second-type pulses is MH, and the value range of M is N≤M≤12; the pulse interval width between the first-type pulses and the second-type pulses is LH, and the value range of L is 16≤L≤24.

[0023] In one possible implementation,

[0024] The display driver chip is also used to: generate a third timing signal including multiple third-type pulses; wherein the timing length of the third-type pulse is not less than the timing length of the holding frame, and in time sequence, the start time of the holding frame is not earlier than the start time of the third-type pulse, and the end time of the holding frame is not later than the end time of the third-type pulse; and use the third timing signal to scan the clock signal end of the second gate drive circuit of the display panel; wherein the output end of the second gate drive circuit is used to provide a control signal to the first reset transistor of the pixel circuit.

[0025] In one possible implementation,

[0026] The display driver chip is also used to: generate a fourth timing signal including multiple fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have an overlapping part in time sequence; and use the fourth timing signal to scan the start signal end of the second gate drive circuit.

[0027] Beneficial effects of the embodiments of the present application:

[0028] The embodiment of the present application provides a display panel driving method and a display device, the driving method comprising: generating a first timing signal including a plurality of first-class pulses; wherein the timing of the first-class pulses is located at the end of the refresh frame timing, and the pulse width of the first-class pulses is NH, and the value range of N is 8≤N≤12; using the first timing signal to scan the start signal end of the first gate driving circuit of the display panel; wherein the output end of the first gate driving circuit is used to provide a control signal to the compensation transistor of the pixel circuit. By shortening the pulse width of the first-class pulse in the refresh frame (compared with the second pulse width of the start signal end SC1_STV of the first gate driving circuit SC1 in the related art being 16H, the embodiment of the present application is shortened to 8H-12H), the high-level charging time of the start signal end of the first gate driving circuit is shortened, the positive charge in the parasitic capacitance and the capacitor CQ is reduced, so that the node Q can be timely converted from a high level to a low level, so as to improve the poor display phenomenon of the upper and lower split screens.

[0029] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0031] Figure 1 A schematic diagram of a structure of a first gate driving circuit in the related art;

[0032] Figure 2 It is a timing diagram of each signal in the related technology;

[0033] Figure 3 A schematic diagram of a poor display phenomenon of upper and lower split screen in the related art;

[0034] Figure 4 is a structural schematic diagram of a second gate driving circuit in the related art;

[0035] Figure 5 A schematic diagram of a poor display phenomenon of horizontal bright lines in the related art;

[0036] Figure 6 A schematic diagram of a first flow chart of a display panel driving method provided in an embodiment of the present application;

[0037] Figure 7 A schematic diagram of a structure of a pixel circuit in the related art;

[0038] Figure 8 It is a timing diagram of each signal after improvement in this application;

[0039] Fig. 9 A second flow chart of the display panel driving method provided in an embodiment of the present application;

[0040] Fig.10 A third flow chart of the display panel driving method provided in the embodiment of the present application;

[0041] Fig.11 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0043] In the reliability operation test (high temperature and high humidity) of current display screens, it is easy to have the problem of parasitic capacitance due to corrosion, and the existence of parasitic capacitance may cause poor display. For example, for the first gate drive circuit (SC1) that provides a control signal to the compensation transistor T10 of the pixel circuit, the circuit structure is as follows Figure 1 As shown (the parasitic capacitance may be connected in parallel at both ends of the second capacitor CQ), the gate drive circuit SC1 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C_ON, a second capacitor CQ, and a third capacitor CB (each transistor is a P-type transistor), and the connection relationship of each device is as follows:

[0044] The gate of the first transistor T1 is connected to the second end of the seventh transistor T7 and the first end of the second capacitor CQ respectively, the first end of the first transistor T1 is connected to the low level signal end VGL, and the second end of the first transistor T1 is connected to the output end SC1_OUT and the second end of the second capacitor CQ respectively;

[0045] The gate of the seventh transistor T7 is connected to the low level signal terminal VGL, and the first end of the seventh transistor T7 is connected to the second end of the third transistor T3 and the gate of the sixth transistor T6 respectively;

[0046] The gate of the third transistor T3 is connected to the clock signal terminal SC1_CK, and the first end of the third transistor T3 is connected to the start signal terminal SC1_STV and the gate of the fourth transistor T4 respectively;

[0047] A first end of the fourth transistor T4 is connected to the high level signal end VGH, and a second end of the fourth transistor T4 is connected to the gate of the fifth transistor T5 and the second end of the first capacitor C_ON respectively;

[0048] The first end of the fifth transistor T5 is respectively connected to the clock signal end SC1_CK and the first end of the first capacitor C_ON, and the second end of the fifth transistor T5 is respectively connected to the second end of the sixth transistor T6, the gate of the second transistor T2, and the first end of the third capacitor CB;

[0049] A first end of the second transistor T2 is connected to the output terminal SC1_OUT, and a second end of the second transistor T2 is connected to the second end of the third capacitor CB and the high level signal terminal VGH respectively;

[0050] A first terminal of the sixth transistor T6 is connected to the high level signal terminal VGH.

[0051] The timing of each signal of the gate drive circuit SC1 can be found in Figure 2 , in the refresh frame, the first pulse (high level) width of the start signal terminal SC1_STV of SC1 is 12H, the second pulse (high level) width of the start signal terminal SC1_STV of SC1 is 16H, the pulse interval (low level) width between the two pulses is 12H, 1H is a horizontal scanning cycle, 1H is equal to 2.9us (microseconds). When SC1_STV is at a high level and SC1_CK is at a low level, the third transistor T3 is in an on state, and the seventh transistor is in an on state due to the VGL low level signal, which will charge the second capacitor CQ and the parasitic capacitor with positive charges, and the first transistor T1 is in an off state. When SC1_STV is converted to a low level, it will first neutralize the positive charges in the second capacitor CQ and the parasitic capacitor, and then charge the second capacitor CQ with negative charges, so that the node Q is converted to a low level, and the first transistor T1 is turned on. However, if the high level of SC1_STV lasts for a long time, the positive charge in the parasitic capacitance and the second capacitor CQ is large, which may cause the voltage of node Q to be unable to turn on transistor T1, and SC1_OUT output is high, resulting in poor display of the upper and lower split screens, such as Figure 3 shown.

[0052] On the other hand, when the display screen is undergoing a reliability operation test, it is easy for the transistor TFT characteristics to shift. Once the transistor TFT characteristics shift, the transistor TFT that should be turned off will not actually be turned off. For example, for the second gate drive circuit (SC4) that provides a control signal to the first reset transistor T11 of the pixel circuit, the circuit structure is as follows Figure 4As shown, the gate drive circuit SC4 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a fourth capacitor C_ON', a fifth capacitor CQ', and a sixth capacitor CB' (each transistor is a P-type transistor), and the connection relationship of each device is as follows:

[0053] The gate of the fifteenth transistor T15 is respectively connected to the second end of the twenty-first transistor T21 and the first end of the fifth capacitor CQ′, the first end of the fifteenth transistor T15 is connected to the low level signal end VGL, and the second end of the fifteenth transistor T15 is respectively connected to the output end SC4_OUT and the second end of the fifth capacitor CQ′;

[0054] The gate of the twenty-first transistor T21 is connected to the low level signal terminal VGL, and the first end of the twenty-first transistor T21 is connected to the second end of the seventeenth transistor T17 and the gate of the twentieth transistor T20 respectively;

[0055] The gate of the seventeenth transistor T17 is connected to the clock signal terminal SC4_CK, and the first end of the seventeenth transistor T17 is connected to the start signal terminal SC4_STV and the gate of the eighteenth transistor T18 respectively;

[0056] A first end of the eighteenth transistor T18 is connected to the high level signal end VGH, and a second end of the eighteenth transistor T18 is connected to the gate of the nineteenth transistor T19 and the second end of the fourth capacitor C_ON′ respectively;

[0057] A first end of the nineteenth transistor T19 is respectively connected to the clock signal end SC4_CK and the first end of the fourth capacitor C_ON', and a second end of the nineteenth transistor T19 is respectively connected to the second end of the twentieth transistor T20, the gate of the sixteenth transistor T16, and the first end of the sixth capacitor CB';

[0058] A first end of the sixteenth transistor T16 is connected to the output terminal SC4_OUT, and a second end of the sixteenth transistor T16 is connected to the second end of the sixth capacitor CB' and the high level signal terminal VGH respectively;

[0059] A first terminal of the twentieth transistor T20 is connected to the high level signal terminal VGH.

[0060] The timing of each signal of the gate drive circuit SC4 can be found in Figure 2, in the refresh frame, the pulse (high level) width of the start signal terminal SC4_STV of SC4 is 16H, and SC4_STV maintains a low level in the hold frame. The eighteenth transistor T18 is turned on, and the VGH high level signal is written to the node Q1. The node Q1 voltage remains high, but the clock signal terminal SC4_CK of SC4 is still consistent with the refresh frame, maintaining the pulse signal. During the high temperature and humidity process of reliability, the transistor TFT characteristics shift, resulting in the nineteenth transistor T19 being unable to be completely turned off. The pulse signal of the clock signal terminal SC4_CK leaks to the sixth capacitor CB', and the low level accumulates over time. In addition, the characteristic shift of the sixteenth transistor T16 itself eventually causes T16 to be unable to be completely turned off. The VGH high level signal leaks through T16 to the output terminal SC4_OUT of SC4, and the low level signal output by SC4_OUT rises slowly. At a certain time node, the sixteenth transistor T16 is turned on. The above situation causes the low level signal output by SC4_OUT to be converted to a high level in advance, and the high level duration is longer, resulting in poor display of horizontal bright lines, such as Figure 5 shown.

[0061] In order to improve at least one of the above problems, an embodiment of the present application provides a display panel driving method and a display device.

[0062] The display panel driving method provided in the embodiment of the present application is described in detail below. Figure 6 , is a schematic diagram of a first flow chart of a display panel driving method provided in an embodiment of the present application, comprising the following steps:

[0063] Step S601, generating a first timing signal including a plurality of first-type pulses; wherein the timing of the first-type pulses is located at the end of the refresh frame timing, and the pulse width of the first-type pulses is NH, and the value range of N is 8≤N≤12.

[0064] It can be understood that, since each transistor in the first gate driving circuit SC1 is a P-type transistor, the first type of pulse (high level) is an invalid level signal, and the pulse interval (low level) is a valid level signal.

[0065] It can be understood that the first type of pulse is the second pulse of the start signal terminal SC1_STV of the first gate driving circuit SC1 in each refresh frame.

[0066] In the refresh frame, a new data signal Data is charged and applied to the gate of the driving transistor T9 of the pixel circuit; in the hold frame, the data signal Data of the previous frame is held and used.

[0067] The circuit structure of the pixel circuit can be seen in Figure 7 , Figure 7The 7T1C pixel circuit is used as an illustration, where 7T1C means that the pixel circuit includes 7 transistors (data writing transistor T8, driving transistor T9, compensation transistor T10, first reset transistor T11, first light emission control transistor T12, second light emission control transistor T13, second reset transistor T14, each transistor is an N-type transistor), and 1 storage capacitor (Cst), wherein VDD is the positive power signal terminal, and VSS is the negative power signal terminal.

[0068] Step S602 , using the first timing signal to scan the start signal terminal SC1_STV of the first gate driving circuit SC1 of the display panel; wherein the output terminal SC1_OUT of the first gate driving circuit SC1 is used to provide a control signal to the compensation transistor T10 of the pixel circuit.

[0069] An output terminal SC1_OUT of the first gate driving circuit SC1 is connected to the gate of the compensation transistor T10 .

[0070] In the embodiment of the present application, by shortening the pulse width of the first type of pulse in the refresh frame (compared to the second pulse width of 16H of the start signal terminal SC1_STV of SC1 in the related art, the embodiment of the present application is shortened to 8H-12H, the more it is shortened, the better the effect, but at the same time, it is necessary to consider that it does not conflict with other signals, and the effect of 8H is the best effect), the high-level charging time of the start signal terminal of the first gate drive circuit is shortened, the positive charge in the parasitic capacitance and the capacitor CQ is reduced, so that the node Q can be converted from a high level to a low level in time, and the problem that the transistor T1 cannot be turned on due to the large amount of positive charge in the parasitic capacitance and the capacitor CQ is improved, the stability of the transistor is increased, the reliability risk is reduced, and the poor display phenomenon of the upper and lower split screens is improved. Moreover, the solution adopted in the embodiment of the present application only needs to burn a new timing on the existing process, without introducing a new process, without increasing the process flow, reducing the introduction of reliability problems, and reducing the increase in costs. Compared with improvements from the perspective of the backplane manufacturing process, the timing improvement cycle is faster and the cost is lower.

[0071] In a possible implementation manner, the first timing signal further includes a plurality of second-type pulses;

[0072] The timing of the second type of pulse is located at the head of the refresh frame timing, and the pulse width of the second type of pulse is MH, and the value range of M is N≤M≤12;

[0073] The pulse interval width between the first type of pulses and the second type of pulses is LH, and the value range of L is 16≤L≤24.

[0074] It can be understood that, as mentioned above, the second type of pulse (high level) is an invalid level signal.

[0075] It can be understood that the second type of pulse is the first pulse of the start signal terminal SC1_STV of the first gate driving circuit SC1 in each refresh frame.

[0076] The pulse width of the second type of pulse can also be shortened, and the improvement effect brought by shortening the pulse width of the first type of pulse is better than the improvement effect brought by shortening the pulse width of the second type of pulse.

[0077] In summary, the improved signal timing of the first gate driving circuit SC1 can be seen in Figure 8 , it is understandable that Figure 8 In the figure, the first type of pulse is shortened to 8H, the pulse interval width between the first type of pulse and the second type of pulse is 20H, and the width of the second type of pulse is 12H.

[0078] In one possible implementation, see Fig. 9 ,based on Figure 6 The method further comprises the following steps:

[0079] Step S901, generating a third timing signal including multiple third-category pulses; wherein, the timing length of the third-category pulse is not less than the timing length of the holding frame, and in time sequence, the start time of the holding frame is not earlier than the start time of the third-category pulse, and the end time of the holding frame is not later than the end time of the third-category pulse.

[0080] It can be understood that, since each transistor in the second gate driving circuit SC4 is a P-type transistor, the third type of pulse (high level) is an invalid level signal, and the pulse interval (low level) is a valid level signal.

[0081] Step S902 , using the third timing signal to scan the clock signal terminal SC4_CK of the second gate driving circuit SC4 of the display panel; wherein the output terminal of the second gate driving circuit SC4 is used to provide a control signal to the first reset transistor T11 of the pixel circuit.

[0082] An output terminal SC4_OUT of the second gate driving circuit SC4 is connected to the gate of the first reset transistor T11 .

[0083] In the embodiment of the present application, by optimizing the timing signals of the clock signal terminal SC4_CK of the second gate drive circuit SC4 to a high level in the holding frame, the gate of the sixteenth transistor T16 is always stably maintained at a high level in the holding frame (T16 is always in the off state), thereby increasing the stability of the transistor, reducing the reliability risk, and improving the poor display phenomenon of the horizontal bright line caused by the inability to completely turn off T16. In addition, the solution adopted in the embodiment of the present application only needs to burn a new timing on the existing process, without introducing a new process, without increasing the process flow, reducing the introduction of reliability issues, and reducing the increase in costs. Compared with improving from the perspective of the backplane manufacturing process, the timing improvement cycle is faster and the cost is lower.

[0084] In a possible implementation manner, the first type of pulses, the second type of pulses, and the third type of pulses are all invalid level signals.

[0085] The specific analysis is the same as above and will not be repeated here.

[0086] In one possible implementation, see Fig.10 ,based on Fig. 9 The method further comprises the following steps:

[0087] Step S1001, generating a fourth timing signal including a plurality of fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have overlapping parts in time sequence.

[0088] Step S1002 , using the fourth timing signal to scan the start signal terminal SC4_STV of the second gate driving circuit SC4 .

[0089] It can be understood that, since each transistor in the second gate driving circuit SC4 is a P-type transistor, the fourth type of pulse (high level) is an invalid level signal.

[0090] It can be understood that the fourth type of pulse is a pulse of the start signal terminal SC4_STV of the second gate driving circuit SC4 in each refresh frame.

[0091] In summary, the improved signal timing of the second gate drive circuit SC4 can be seen in Figure 8 .

[0092] In the embodiment of the present application, in order to ensure the pulse overlap of SC1_STV and SC4_STV, the pulse width of SC4_STV in the refresh frame can be changed from the existing 16H (16H can refer to Figure 2 ) is expanded to 20H to improve the undesirable phenomena such as low grayscale and afterimage.

[0093] In a possible implementation manner, the fourth type of pulse is an invalid level signal.

[0094] The specific analysis is the same as above and will not be repeated here.

[0095] In a possible implementation manner, the method further includes the following steps: generating a fifth timing signal; and using the fifth timing signal to scan a clock signal terminal SC1_CK of the first gate driving circuit SC1.

[0096] The timing waveform of the fifth timing signal (see Figure 8 SC1_CK) is the same as the timing waveform of the clock signal terminal SC1_CK of the first gate drive circuit SC1 in the related art (see Figure 2 SC1_CK).

[0097] The present application also provides a display device 1, see Fig.11 , the display device 1 includes a display panel 11 and a display driver chip 12;

[0098] The display panel 11 includes a plurality of pixel rows 111, a first gate driving circuit SC1 connected to each pixel row 111, and a second gate driving circuit SC4 connected to each pixel row 111; each pixel row 111 includes a plurality of pixel circuits; each pixel circuit includes a compensation transistor T10 and a first reset transistor T11;

[0099] The display driver chip 12 is used to: generate a first timing signal including multiple first-type pulses; wherein the timing of the first-type pulses is located at the end of the refresh frame timing, and the pulse width of the first-type pulses is NH, and the value range of N is 8≤N≤12; use the first timing signal to scan the start signal terminal SC1_STV of the first gate drive circuit SC1 of the display panel; wherein the output terminal SC1_OUT of the first gate drive circuit SC1 is used to provide a control signal to the compensation transistor T10 of the pixel circuit.

[0100] A first gate driving circuit SC1 can be connected to a row of pixel rows 111 / multiple rows of pixel rows 111, a second gate driving circuit SC4 can be connected to a row of pixel rows 111 / multiple rows of pixel rows 111, a row of pixel rows 111 can be connected to multiple first gate driving circuits SC1, and a row of pixel rows 111 can be connected to multiple second gate driving circuits SC4, which is not specifically limited in this application. It is understandable that Fig.11 In the figure, a first gate driving circuit SC1 is connected to a row of pixel rows 111 , and a second gate driving circuit SC4 is connected to a row of pixel rows 111 .

[0101] The rest of the analysis is the same as above and will not be repeated here.

[0102] In one possible implementation,

[0103] The first timing signal also includes multiple second-type pulses; the timing of the second-type pulses is located at the head of the refresh frame timing, and the pulse width of the second-type pulses is MH, and the value range of M is N≤M≤12; the pulse interval width between the first-type pulses and the second-type pulses is LH, and the value range of L is 16≤L≤24.

[0104] The specific analysis is the same as above and will not be repeated here.

[0105] In one possible implementation, see Fig.11 ,

[0106] The display driver chip 12 is also used to: generate a third timing signal including multiple third-type pulses; wherein the timing length of the third-type pulse is not less than the timing length of the holding frame, and in time sequence, the start time of the holding frame is not earlier than the start time of the third-type pulse, and the end time of the holding frame is not later than the end time of the third-type pulse; use the third timing signal to scan the clock signal terminal SC4_CK of the second gate driver circuit SC4 of the display panel; wherein the output terminal SC4_OUT of the second gate driver circuit SC4 is used to provide a control signal to the first reset transistor T11 of the pixel circuit.

[0107] The specific analysis is the same as above and will not be repeated here.

[0108] In one possible implementation, see Fig.11 ,

[0109] The display driver chip 12 is also used to: generate a fourth timing signal including multiple fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have an overlapping part in time sequence; and use the fourth timing signal to scan the start signal terminal SC4_STV of the second gate drive circuit SC4.

[0110] The specific analysis is the same as above and will not be repeated here.

[0111] In one possible implementation, see Fig.11 ,

[0112] The display driving chip 12 is further used for: generating a fifth timing signal; and using the fifth timing signal to scan the clock signal terminal SC1_CK of the first gate driving circuit SC1 .

[0113] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0114] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0115] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A display panel driving method, characterized in that: The method comprises: Generate a first timing signal including a plurality of first-type pulses; wherein the timing of the first-type pulses is located at the end of the refresh frame timing, and the pulse width of the first-type pulses is NH, and the value range of N is 8≤N≤12; The first timing signal is used to scan the start signal end of the first gate driving circuit of the display panel; wherein the output end of the first gate driving circuit is used to provide a control signal to the compensation transistor of the pixel circuit.

2. The method according to claim 1, characterized in that The first timing signal also includes a plurality of second type pulses; The timing of the second type of pulse is located at the head of the refresh frame timing, and the pulse width of the second type of pulse is MH, and the value range of M is N≤M≤12; The pulse interval width between the first type of pulses and the second type of pulses is LH, and the value range of L is 16≤L≤24.

3. The method according to claim 2, characterized in that The method further comprises: Generate a third timing signal including a plurality of third-type pulses; wherein the timing length of the third-type pulse is not less than the timing length of the holding frame, and in time sequence, the start time of the holding frame is not earlier than the start time of the third-type pulse, and the end time of the holding frame is not later than the end time of the third-type pulse; The clock signal terminal of the second gate driving circuit of the display panel is scanned by using the third timing signal; wherein the output terminal of the second gate driving circuit is used to provide a control signal to the first reset transistor of the pixel circuit.

4. The method according to claim 3, characterized in that The first type of pulses, the second type of pulses, and the third type of pulses are all invalid level signals.

5. The method according to claim 3, characterized in that: The method further comprises: Generate a fourth timing signal including a plurality of fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have overlapping parts in time sequence; The fourth timing signal is used to scan the start signal terminal of the second gate driving circuit.

6. The method according to claim 5, characterized in that The fourth type of pulse is an invalid level signal.

7. A display device, characterized in that: The display device includes a display panel and a display driver chip; The display panel comprises a plurality of pixel rows, a first gate driving circuit connected to each pixel row, and a second gate driving circuit connected to each pixel row; each pixel row comprises a plurality of pixel circuits; each pixel circuit comprises a compensation transistor and a first reset transistor; The display driver chip is used to: generate a first timing signal including multiple first-type pulses; wherein the timing of the first-type pulses is located at the end of the refresh frame timing, and the pulse width of the first-type pulses is NH, and the value range of N is 8≤N≤12; use the first timing signal to scan the start signal end of the first gate drive circuit of the display panel; wherein the output end of the first gate drive circuit is used to provide a control signal to the compensation transistor of the pixel circuit.

8. The display device according to claim 7, characterized in that: The first timing signal also includes multiple second-type pulses; the timing of the second-type pulses is located at the head of the refresh frame timing, and the pulse width of the second-type pulses is MH, and the value range of M is N≤M≤12; the pulse interval width between the first-type pulses and the second-type pulses is LH, and the value range of L is 16≤L≤24.

9. The display device according to claim 8, characterized in that: The display driver chip is also used to: generate a third timing signal including multiple third-type pulses; wherein the timing length of the third-type pulse is not less than the timing length of the holding frame, and in time sequence, the start time of the holding frame is not earlier than the start time of the third-type pulse, and the end time of the holding frame is not later than the end time of the third-type pulse; and use the third timing signal to scan the clock signal end of the second gate drive circuit of the display panel; wherein the output end of the second gate drive circuit is used to provide a control signal to the first reset transistor of the pixel circuit.

10. The display device according to claim 9, characterized in that: The display driver chip is also used to: generate a fourth timing signal including multiple fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have an overlapping part in time sequence; and use the fourth timing signal to scan the start signal end of the second gate drive circuit.

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