Power supply circuit
By introducing thresholds in the multi-power rail design to control the conduction and shutdown of the switch tube, the problem of voltage below the rated during the power supply step-down process is solved, ensuring that the system works normally at higher voltages, and improving power supply stability.
Patent Information
- Application Number
- CN202411312976.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2025-01-03
AI Technical Summary
In the existing multi-power rail design, the power supply generates an additional voltage drop during the step-down process, resulting in the actual voltage intensity being lower than the rated voltage intensity, affecting the normal operation of the on-board electronic control unit and driver chip.
The first threshold value and the second threshold value are introduced, and by comparing the first supply voltage and the second supply voltage plus the threshold value, the conduction and shutdown of the switch tube are controlled to ensure that the circuit outputs a higher voltage and avoid additional voltage drops.
It effectively solves the problem of voltage drop due to voltage drop during power switching, ensures that the later-stage system works normally at a higher voltage, and improves power supply stability.
Smart Images
Figure CN119253974A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of dual power supply, and in particular to a power supply circuit. Background Art
[0002] With the rapid development of the automobile industry, especially the popularity of electric vehicles and hybrid vehicles, higher requirements are placed on the stability and reliability of vehicle power supply systems. During the cold start of a car, the battery voltage drops sharply in a short period of time, which often causes key components such as the on-board electronic control unit (ECU) and driver chips to fail to work normally due to insufficient power supply, thus affecting the starting performance and driving safety of the entire vehicle.
[0003] In the prior art, driver chips usually adopt a single power rail design, that is, they mainly rely on a high-voltage battery power supply (VS) to provide power for the analog circuits, digital circuits and driver circuits in the chip. However, in a cold start scenario, the VS voltage may quickly drop below 3V, which is far lower than the minimum power supply voltage (i.e., undervoltage threshold) required for most chips to work normally, causing the chip to fail and unable to effectively drive the load or perform necessary control operations.
[0004] To meet this challenge, the industry has begun to explore the use of multi-power rail design solutions to enhance the power supply stability of chips under extreme conditions. Among them, a low-voltage power supply (Vdd, usually 5V) is introduced as an auxiliary power rail to work in parallel with the high-voltage power supply (VS).
[0005] However, existing multi-power rail designs usually use control chip monitoring to switch the main power supply and the backup power supply. The control chip compares the voltage sizes of multiple power supplies and controls the output of the larger voltage. However, when the power supply actually outputs the voltage, an additional voltage drop will be generated after the voltage regulator or step-down circuit, causing the actual voltage strength to be lower than the rated voltage strength. When the power supply is switched in the control circuit, this voltage drop can easily cause a smaller voltage to be turned on and output. Summary of the invention
[0006] The object of the present invention is to provide a power supply circuit to solve the problem in the prior art that in a multi-power rail design, one of the power supplies generates an additional voltage drop during the voltage reduction process, resulting in the actual voltage strength being lower than the rated voltage strength, and when comparing the voltages between multiple power supplies, a smaller voltage is turned on and output due to the voltage drop.
[0007] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a power supply circuit, the circuit comprising: a voltage stabilizing circuit, generating a regulating voltage according to a first power supply voltage, wherein the value of the regulating voltage is less than the first power supply voltage; a first switch tube, having a first end, a second end and a control end, wherein the first end receives the regulating voltage; a second switch tube, having a first end, a second end and a control end, wherein the first end receives the second power supply voltage, and the second end is coupled to the second end of the first switch tube and outputs an internal power supply voltage; wherein when the first power supply voltage is less than the sum of the second power supply voltage and a first threshold value, the first switch tube is turned off, the second switch tube is turned on, and the internal power supply voltage is generated according to the second power supply voltage; and when the first power supply voltage is greater than the sum of the second power supply voltage and a second threshold value, the first switch tube is turned on, the second switch tube is turned off, and the internal power supply voltage is generated according to the regulating voltage, wherein the first threshold value is less than the second threshold value.
[0008] Compared with the prior art, the present invention has the following beneficial effects: introducing a first threshold value and a second threshold value, comparing the first supply voltage and the second supply voltage plus the first threshold value or the second threshold value, thereby solving the problem of voltage drop caused by the first supply voltage passing through the voltage stabilizing circuit, so as to determine and control the circuit to maintain a higher voltage output, thereby ensuring the normal operation of the subsequent system at a higher voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 A schematic diagram of the connection structure of a power supply circuit 100 according to an embodiment of the present invention is given.
[0010] Figure 2 A circuit structure diagram of a channel selection circuit 4 according to an embodiment of the present invention is given.
[0011] Figure 3 A schematic structural diagram of a first voltage divider circuit 11, a second voltage divider circuit 12 and a logic operation circuit 13 according to an embodiment of the present invention is given.
[0012] Figure 4 A schematic structural diagram of a voltage stabilizing circuit 3 according to an embodiment of the present invention is given. DETAILED DESCRIPTION
[0013] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.
[0014] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", "fourth", "fifth", "sixth", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0015] The phrases "one embodiment", "an embodiment", "an example", and "example" that appear in various places throughout the specification do not necessarily refer to the same embodiment or example. It should be understood by those skilled in the art that the various specific features, structures or parameters, steps, etc. disclosed in one or more embodiments of the present disclosure can be combined in any suitable manner.
[0016] Figure 1 A power supply circuit 100 according to an embodiment of the present invention is provided. The power supply circuit 100 includes a voltage stabilizing circuit 3, a first switch tube M1, and a second switch tube M2. The voltage stabilizing circuit 3 is coupled to a first power supply voltage Vs, and generates a regulating voltage VREG according to the first power supply voltage Vs, wherein the value of the regulating voltage VREG is less than the first power supply voltage Vs. The first switch tube M1 has a first end, a second end, and a control end, and its first end receives the regulating voltage VREG. The second switch tube M2 has a first end, a second end, and a control end, and its first end receives the second power supply voltage Vdd. The second end of the second switch tube M2 is coupled to the second end of the first switch tube M1 and outputs an internal power supply voltage VINT. Among them, when the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first threshold TH1, the first switch tube M1 is turned off, the second switch tube M2 is turned on, and the internal power supply voltage VINT is generated according to the second power supply voltage Vdd. When the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second threshold TH2, the first switch tube M1 is turned on, the second switch tube M2 is turned off, and the internal power supply voltage INT is generated according to the adjustment voltage VREG, wherein the first threshold TH1 is less than the second threshold TH2. In one embodiment, the first threshold TH1 is between 0.4V and 0.8V, and the second threshold TH2 is between 0.6 and 1.2V. In one embodiment, the range of the first power supply voltage Vs is between 40V-4V, and the range of the second power supply voltage Vdd is between 3.5V-5V. In one embodiment, the first switch tube M1 is a P-type field effect transistor, and the second switch tube M2 is a P-type field effect transistor.
[0017] continue Figure 1The power supply circuit 100 further includes a channel selection circuit 4, which is coupled to the first power supply voltage Vs and the second power supply voltage Vdd, and is used to generate a first switch control signal S1 and a second switch control signal S2 according to the first power supply voltage Vs and the second power supply voltage Vdd to control the on and off of the first switch tube M1 and the second switch tube M2 respectively. When the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second threshold TH2, the channel selection circuit 4 outputs the first switch control signal S1 to turn on the first switch tube M1, and the second end of the first switch tube M1 serves as the output end of the power supply circuit 100 to output the internal power supply voltage VINT. When the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first threshold TH1, the channel selection circuit 4 outputs the second switch control signal S2 to turn on the second switch tube M2, and the second end of the second switch tube M2 serves as the output end of the power supply circuit 100 to output the internal power supply voltage VINT.
[0018] continue Figure 1 As described above, the channel selection circuit 4 also receives an enable signal S3, which is a signal for controlling the power supply circuit 100 to be in a sleep state. When the enable signal S3 is valid, the first switch control signal S1 is controlled to turn off the first switch tube M1, and the second control signal S2 is controlled to turn off the second switch tube M2. When the enable signal S3 is invalid, the first switch control signal S1 and the second control signal S2 output by the channel selection circuit 4 are used to control the first switch tube M1 to be turned on and the second switch tube M2 to be turned off, or the second switch tube M2 to be turned on and the first switch tube M1 to be turned off.
[0019] Figure 2A circuit structure diagram of a channel selection circuit 4 in an embodiment of the present invention is given. The channel selection circuit 4 includes a first voltage divider circuit 11, a second voltage divider circuit 12 and a logic operation circuit 13. The first voltage divider circuit 11 is coupled to the first power supply voltage Vs, and generates a first voltage divider signal Vfb1 representing the first power supply voltage Vs according to the first power supply voltage Vs, wherein the ratio between the first voltage divider signal Vfb1 and the first power supply voltage Vs is a first voltage divider coefficient K1. The second voltage divider circuit 12 is coupled to the second power supply voltage Vdd, and generates a second voltage divider signal Vfb2 representing the second power supply voltage Vdd according to the second power supply voltage Vdd, wherein the ratio between the second voltage divider signal Vfb2 and the second power supply voltage Vdd is a second voltage divider coefficient K2. The logic operation circuit 13 receives the first voltage divider signal Vfb1 and the second voltage divider signal Vfb2, and generates a first switch control signal S1 and a second switch control signal S2 according to the first voltage divider signal Vfb1 and the second voltage divider signal Vfb2 to control the on and off of the first switch tube M1 and the second switch tube M2 respectively. In one embodiment, the channel selection circuit 4 also receives an enable signal S3, wherein when the enable signal S3 is valid, the first switch control signal S1 is controlled to turn off the first switch tube M1, and the second control signal S2 is controlled to turn off the second switch tube M2. When the enable signal S3 is valid, the enable signal S3 is characterized by a high-level signal state "1", and the first switch control signal S1 and the second control signal S2 output by the channel selection circuit 4 are both high-level signals "1", and the first switch tube M1 and the second switch tube M2 are turned off at the same time. In one embodiment, the first switch tube M1 and the second switch tube M2 have parasitic diodes. In this way, when the first switch tube M1 and the second switch tube M2 are both turned off, the parasitic diodes of the first switch tube M1 and the second switch tube M2 can also output a large voltage to the subsequent system, so that some functional modules in the subsequent stage with low power consumption and long-term power consumption can be stably and continuously powered, and when the chip is in sleep mode, there is still a stable internal power supply voltage. When the enable signal S3 is invalid, the enable signal S3 is characterized by a low-level signal state "0". In one embodiment, the channel selection circuit 4 outputs a first switch control signal S1 representing a low-level signal "0" to turn on the first switch tube M1 and outputs a second control signal S2 representing a high-level signal "1" to turn off the second switch tube M2. In another embodiment, the channel selection circuit 4 outputs a first switch control signal S1 representing a high-level signal "1" to turn off the first switch tube M1 and outputs a second control signal S2 representing a low-level signal "0" to turn on the second switch tube M2. Figure 3A circuit structure diagram of a first voltage divider circuit 11, a second voltage divider circuit 12 and a logic operation circuit 13 in one embodiment of the present invention is given. The first voltage divider circuit 11 includes a first voltage divider resistor Z1 and a second voltage divider resistor Z2, and the second voltage divider circuit 12 includes a third voltage divider resistor Z3 and a fourth voltage divider resistor Z4. The first end of the first voltage divider resistor Z1 is coupled to the first supply voltage Vs, the second end of the first voltage divider resistor Z1 is coupled to the first end of the second voltage divider resistor Z2, and the second end of the second voltage divider resistor Z2 is coupled to the reference ground GND. The first supply voltage Vs is divided by the first voltage divider resistor Z1 and the second voltage divider resistor Z2 to form a first voltage divider signal Vfb1. The first end of the third voltage divider resistor Z3 is coupled to the second supply voltage Vdd, the second end of the third voltage divider resistor Z3 is coupled to the first end of the fourth voltage divider resistor Z4, and the second end of the fourth voltage divider resistor Z4 is coupled to the reference ground GND. The second voltage V2 is divided by the third voltage divider resistor Z3 and the fourth voltage divider resistor Z4 to form a second voltage divider signal Vfb2. Vfb1=K1×Vs,Vfb2=K2×Vdd,where K1 is the first voltage division coefficient and K2 is the second voltage division coefficient. In one embodiment, the value of the first voltage division signal Vfb1 is one tenth of the value of the first power supply voltage Vs, that is, the first voltage division coefficient K1 is 0.1. In one embodiment, the first voltage division coefficient K1 is equal to the second voltage division coefficient K2. That is, the first power supply voltage Vs and the second power supply voltage Vdd are scaled in the same proportion to form the first voltage division signal Vfb1 and the second voltage division signal Vfb2. The resistance value of the first voltage division resistor Z1 is the same as the resistance value of the third voltage division resistor Z3, and the resistance value of the second voltage division resistor Z2 is the same as the resistance value of the fourth voltage division resistor Z4.
[0020] exist Figure 3 In the embodiment, the logic operation circuit 13 includes a comparator A, the first input terminal of the comparator A receives the first voltage-divided signal Vfb1, and the second input terminal of the comparator A receives the second voltage-divided signal Vfb2. In one embodiment, the comparator A is a hysteresis comparator. In one embodiment, the comparator A is configured to compare the first voltage-divided signal Vfb1 with the second voltage-divided signal Vfb2 after the first voltage-divided signal Vfb1 is offset by the rated preset value Vk and control the states of the first switch tube M1 and the second switch tube M2 according to the comparison result. In one embodiment, the first reference threshold TH1 is determined by the first voltage-divided coefficient K1, the rated preset value Vk and the hysteresis VD of the comparator A, and the hysteresis VD of the comparator A oscillates up or down by the hysteresis VD based on the rated preset value Vk. TH1 = (Vk + VD) / K1, TH2 = (Vk - VD) / K1. In one embodiment, the rated preset value Vk is 70mv, the hysteresis of the comparator A is 10mV, the first threshold TH1 is 0.8V, and the second threshold TH2 is 0.6V.
[0021] When the first power supply voltage Vs is stepped down by the voltage stabilizing circuit 3 to form the regulating voltage VREG, the voltage is further reduced in the voltage stabilizing circuit 3 due to the circuit voltage drop, so that when the first voltage-dividing signal Vfb1 and the second voltage-dividing signal Vfb2 are compared, there is a "blind spot" in the above-mentioned voltage drop interval, and the first switch tube M1 and the second switch tube M2 cannot be switched in time. In this way, the first voltage-dividing signal Vfb1 is offset by the comparator A to overcome the voltage "blind spot", so that the circuit can respond quickly during voltage conversion and ensure that a higher voltage is always output. For example, the second power supply voltage Vdd is 5V. The first threshold TH1 is 0.6V, and the second threshold TH2 is 0.8V. The sum of the second power supply voltage Vdd and the first threshold TH1 is 5.6V, and the sum of the second power supply voltage Vdd and the second threshold TH2 is 5.8V. If the first power supply voltage Vs is 6V, the adjustment voltage VREG is 5.2V, and the adjustment voltage VREG is greater than the second power supply voltage Vdd, then the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second threshold TH2, the first switch tube M1 is turned on, and the output internal power supply voltage VINT is 5.2V. When the first power supply voltage Vs is reduced to 5.5V, the adjustment voltage VREG is 4.7V, at this time, the adjustment voltage VREG is less than the second power supply voltage Vdd, the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first threshold TH1, the first switch tube M1 is turned off, the second switch tube M2 is turned on, and the output internal power supply voltage VINT is 5V.
[0022] exist Figure 3 In the embodiment, the logic operation circuit 13 further includes a first NAND gate 41, a first OR gate 43, a second resistor R2, an inverter F, a second NAND gate 42, a second OR gate 44 and a third resistor R3. The first NAND gate 41, the first OR gate 43, the second NAND gate 42 and the second OR gate 44 all have a first input terminal, a second input terminal and an output terminal. The first input terminal of the first NAND gate 41 is coupled to the output terminal of the comparator A. The first input terminal of the first OR gate 43 receives the enable signal S3, and the second input terminal is coupled to the output terminal of the first NAND gate 41. The input terminal of the second resistor R2 is coupled to the output terminal of the first OR gate 43, and the output terminal of the second resistor R2 is coupled to the control terminal of the first switch tube M1. The input terminal of the inverter F is coupled to the output terminal of the comparator A. The first input terminal of the second NAND gate 42 is coupled to the output terminal of the inverter F, and the second input terminal is coupled to the output terminal of the second resistor R2. The first input terminal of the second OR gate 44 receives the enable signal S3, and the second input terminal is coupled to the output terminal of the second NAND gate 42. An input end of the third resistor R3 is coupled to the output end of the second OR gate 44 , an output end of the third resistor R3 is coupled to the control end of the second switch tube M2 , and an output end of the third resistor R3 is also coupled to the second input end of the first NAND gate 41 .
[0023] for Figure 3The explanation is that when both inputs of the OR gate are "0", the output is "0". When both inputs of the NAND gate are "1", the output is "0".
[0024] exist Figure 3 In one embodiment, when the enable signal S3 is valid, the enable signal S3 is a high-level signal "1", and the first OR gate 43 and the second OR gate 44 receive the signal "1", then the outputs of the first OR gate 43 and the second OR gate 44 are always high-level signals "1", keeping the first switch tube M1 and the second switch tube M2 turned off.
[0025] exist Figure 3 In one embodiment, when the enable signal S3 is invalid, the enable signal S3 is a low-level signal "0". If the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second threshold value VTH2, the output end of the comparator A outputs a "1" signal, the first input end of the first NAND gate 41 receives the "1" signal, the second input end of the first NAND gate 41 receives the "1" signal, and the first NAND gate 41 outputs a "0" signal. The two input ends of the first OR gate 43 are respectively a "0" signal and a "0" signal, that is, the output "0" signal turns on the first switch tube M1. The first input end of the second NAND gate 42 receives a "0" signal, the second input end of the second NAND gate 42 receives a "1" signal, and the second NAND gate 42 outputs a "1" signal. The two input ends of the second OR gate 44 are respectively a "1" signal and a "0" signal, that is, the output "1" signal turns off the second switch tube M2. If the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first threshold TH1, the output end of the comparator A outputs a "0" signal, the first input end of the first NAND gate 41 receives a "0" signal, the second input end of the first NAND gate 41 receives a "1" signal, and the first NAND gate 41 outputs a "1" signal. The two input ends of the first OR gate 43 are a "1" signal and a "0" signal, respectively, that is, the output "1" signal turns off the first switch tube M1. The first input end of the second NAND gate 42 receives a "1" signal, the second input end of the second NAND gate 42 receives a "1" signal, and the second NAND gate 42 outputs a "0" signal. The two input ends of the second OR gate 44 are a "0" signal and a "0" signal, respectively, that is, the output "0" signal turns on the second switch tube M2.
[0026] Figure 4A schematic diagram of the structure of a voltage stabilizing circuit 3 according to an embodiment of the present invention is given. The voltage stabilizing circuit 3 includes a first resistor R1, a first Zener diode D1, a fifth switch tube K5 and a second Zener diode D2. The first end of the first resistor R1 is coupled to the first power supply voltage Vs. The first end of the first Zener diode D1 is coupled to the second end of the first resistor R1, and the second end of the first Zener diode D1 is coupled to the reference ground GND. The fifth switch tube K5 has a first end, a second end and a control end, wherein the first end is coupled to the first power supply voltage Vs, the control end is coupled between the first resistor R1 and the first Zener diode D1, and the second end outputs the regulation voltage VREG. The first end of the second Zener diode D2 is coupled to the second end of the fifth switch tube K5, and the second end of the second Zener diode D2 is coupled to the reference ground GND. In this way, the first resistor R1, the first Zener diode D1, the fifth switch tube K5 and the second Zener diode D2 form a source follower, and the second end of the fifth switch tube K5 outputs the regulation voltage VREG after the first power supply voltage Vs is stepped down. In one embodiment, the fifth switch tube K5 is an N-type field effect transistor. In one embodiment, the fifth switch tube K5 has a parasitic diode.
[0027] The power supply circuit of an embodiment of the present invention can compare the values of the first power supply voltage Vs and the second power supply voltage Vdd. When the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first threshold TH1, the first switch tube M1 is controlled to be turned off and the second switch tube M2 is turned on. When the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second threshold TH2, the first switch tube M1 is turned on and the second switch tube M2 is turned off. In this way, a voltage related to the first power supply voltage Vs or a voltage related to the second power supply voltage Vdd is output, so that the circuit can maintain a higher voltage output in real time, thereby ensuring the normal operation of the subsequent system at a higher voltage.
[0028] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
[0029] The above-mentioned specific embodiments are only used to illustrate the present invention in an exemplary manner. These embodiments are not completely exhaustive and are not intended to limit the scope of the present invention. It is possible to change and modify the disclosed embodiments, and other feasible optional embodiments and equivalent changes to the elements in the embodiments can be understood by those of ordinary skill in the art. Other changes and modifications to the embodiments disclosed by the present invention do not exceed the spirit of the present invention and the scope of protection defined by the claims.
[0030] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.
Claims
1. A power supply circuit, comprising: A voltage stabilizing circuit, generating a regulating voltage according to the first supply voltage, wherein a value of the regulating voltage is smaller than the first supply voltage; A first switch tube has a first end, a second end and a control end, and the first end receives a regulation voltage; A second switch tube has a first end, a second end and a control end, wherein the first end receives the second power supply voltage, and the second end is coupled to the second end of the first switch tube and outputs the internal power supply voltage; When the first supply voltage is less than the sum of the second supply voltage and the first threshold, the first switch tube is turned off, the second switch tube is turned on, and the internal supply voltage is generated according to the second supply voltage; when the first supply voltage is greater than the sum of the second supply voltage and the second threshold, the first switch tube is turned on, the second switch tube is turned off, and the internal supply voltage is generated according to the adjustment voltage, wherein the first threshold is less than the second threshold.
2. The power supply circuit according to claim 1, wherein the first threshold value is between 0.4V and 0.8V, and the second threshold value is between 0.6 and 1.2V.
3. The power supply circuit according to claim 1, wherein the first switch tube is a P-type field effect transistor.
4. The power supply circuit according to claim 1, further comprising a channel selection circuit, which generates a first switch control signal and a second switch control signal according to the first power supply voltage and the second power supply voltage to control the on and off of the first switch tube and the second switch tube respectively.
5. The power supply circuit according to claim 4, wherein the channel selection circuit comprises: A first voltage-dividing circuit generates a first voltage-dividing signal representing the first power supply voltage according to the first power supply voltage, wherein a ratio between the first voltage-dividing signal and the first power supply voltage is a first voltage-dividing coefficient; A second voltage-dividing circuit generates a second voltage-dividing signal representing the second power supply voltage according to the second power supply voltage, wherein a proportional relationship between the second voltage-dividing signal and the second power supply voltage is a second voltage-dividing coefficient; The logic operation circuit receives the first voltage division signal and the second voltage division signal, and generates the first switch control signal and the second switch control signal according to the first voltage division signal and the second voltage division signal to control the conduction and disconnection of the first switch tube and the second switch tube respectively. 6 . The power supply circuit according to claim 4 , wherein the channel selection circuit further receives an enable signal, wherein when the enable signal is valid, the first switch control signal turns off the first switch tube, and controls the second control signal to turn off the second switch tube.
7. The power supply circuit according to claim 4, wherein the channel selection circuit comprises: A first voltage-dividing circuit generates a first voltage-dividing signal representing the first power supply voltage according to the first power supply voltage, wherein a ratio between the first voltage-dividing signal and the first power supply voltage is a first voltage-dividing coefficient; A second voltage-dividing circuit generates a second voltage-dividing signal representing the second power supply voltage according to the second power supply voltage, wherein a proportional relationship between the second voltage-dividing signal and the second power supply voltage is a second voltage-dividing coefficient; as well as The logic operation circuit receives a first voltage division signal, a second voltage division signal and an enable signal, wherein when the enable signal is valid, the first switch control signal controls the first switch tube to be turned off, and the second switch control signal controls the second switch tube to be turned off.
8. The power supply circuit according to claim 5 or 7, wherein the logic operation circuit comprises: The hysteresis comparator receives the first voltage-divided signal, the second voltage-divided signal and the rated preset value, and generates the first switch control signal and the second switch control signal according to the first voltage-divided signal, the second voltage-divided signal and the rated preset value.
9. The power supply circuit according to claim 8, wherein the first threshold value is related to the first voltage division coefficient, a hysteresis voltage of the comparator and a rated preset value.
10. The power supply circuit according to claim 5 or 7, wherein the first voltage division coefficient is equal to the second voltage division coefficient.