Higher harmonic suppression structure, radio frequency power amplifier and method

Abstract

The invention provides a higher harmonic suppression structure, a radio frequency power amplifier and a method, and belongs to the technical field of signal transmission equipment.The higher harmonic suppression structure comprises a first inductor, a second inductor, a first capacitor and a second capacitor, the first end of the first inductor is used for being connected to the output end of the radio frequency power amplifier in parallel, and the second end of the second inductor is used for being connected to the output end of the radio frequency power amplifier in parallel; the second end of the first inductor is connected with the first end of the first capacitor, the second end of the first capacitor is grounded, the first end of the second capacitor is used for being connected to the output end of the radio frequency power amplifier in parallel, the second end of the second capacitor is connected with the first end of the second inductor and is grounded, and the first inductor is connected with the second capacitor in parallel. The first capacitor and the second inductor are connected in parallel, parameters of the first inductor, the second inductor, the first capacitor and the second capacitor are configured to have high impedance characteristics for higher harmonic signals, and a low-impedance path is provided in a loop to guide the higher harmonic signals to the ground.

Description

Technical Field

[0001] The present invention relates to the technical field of signal transmission equipment, and in particular to a high-order harmonic suppression structure, a radio frequency power amplifier and a method. Background Art

[0002] The RF front-end chip is a core component of the wireless communication system. It is located between the antenna and the transceiver and is responsible for optimizing the transmission and reception of RF signals. It includes key components such as power amplifiers (PA), low noise amplifiers (LNA), filters, duplexers, and switches to ensure that the signal is properly amplified, clearly received, and interference is reduced during transmission. The RF power amplifier is a key component in the RF front end, which is used to amplify the power of the RF signal to a level suitable for transmission. It increases the power of the signal to ensure that the signal can be effectively transmitted through the antenna and cover a wider range.

[0003] In the existing RF power amplifier design, the main large signal performance that is valued is output power and power added efficiency (PAE), where the power added efficiency is calculated by subtracting the output power from the input power and dividing it by the DC power consumption. How to ensure that the power added efficiency is high enough while the output power is gradually increasing is an issue worthy of attention. If the output power is too large and the power added efficiency is too low, the design may be burned out. Similarly, in the framework of RF power amplifiers, the most important way to improve the power added efficiency of power amplifiers is harmonic suppression. By suppressing high-frequency harmonics, power loss can be effectively reduced.

[0004] Common harmonic suppression methods such as harmonic filters, negative feedback technology and harmonic trap technology each have their own advantages and disadvantages. Harmonic filters are large in size, high in cost, and may introduce losses; negative feedback technology leads to reduced gain, affecting overall performance; harmonic trap technology can only target specific harmonic frequencies and has a greater impact on matching circuits, and may even cause power amplifier oscillations, resulting in system failure. Summary of the invention

[0005] In view of the above problems, in a first aspect, an embodiment of the present invention provides a high-order harmonic suppression structure, which includes: a first inductor, a second inductor, a first capacitor and a second capacitor, wherein the first end of the first inductor is used to be connected in parallel to the output end of the radio frequency power amplifier, the second end of the first inductor is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, the first end of the second capacitor is used to be connected in parallel to the output end of the radio frequency power amplifier, the second end of the second capacitor is connected to the first end of the second inductor, and is connected to the ground with the second end of the second inductor, the first inductor and the second capacitor are connected in parallel, the first capacitor and the second inductor are connected in parallel, and the parameters of the four elements of the first inductor, the second inductor, the first capacitor and the second capacitor are configured to have high impedance characteristics for high-order harmonic signals, and provide a low impedance path in the loop to guide the high-order harmonic signals to the ground.

[0006] The second aspect of the present application also provides a radio frequency power amplifier, which includes a high-order harmonic suppression structure as described in the above aspect, and the radio frequency power amplifier also includes: an input matching network, a stabilization network, a transistor, an output matching network and a bias circuit, the input matching network is connected to the gate of the transistor through the stabilization network, the input matching network is used to match the source impedance to the optimal input impedance of the transistor, the output matching network is connected to the drain of the transistor, the output matching network is used to match the load impedance to the optimal output impedance of the transistor, the bias network is connected to the gate and drain of the transistor, the bias network is used to provide a constant gate voltage and drain voltage for the transistor, and the high-order harmonic suppression structure is connected to the output matching network.

[0007] According to one embodiment of the present invention, the input matching network includes: a capacitor C0, a capacitor C1, a capacitor C2, a capacitor C3, an inductor L0, an inductor L1, an inductor L2 and an inductor L3, wherein the capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 are connected in series in sequence, a starting end of the series combination of the capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 is connected to the signal input end, an end of the series combination of the capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 is connected to the stabilizing network, a first end of the capacitor C1 is connected between the inductor L0 and the inductor L1, a second end of the capacitor C1 is grounded, a first end of the capacitor C2 is connected between the inductor L1 and the inductor L2, a second end of the capacitor C2 is grounded, a first end of the capacitor C3 is connected between the inductor L2 and the inductor L3, and a second end of the capacitor C3 is grounded.

[0008] According to one embodiment of the present invention, the stabilization network includes a capacitor C5 and a resistor R2, the capacitor C5 and the resistor R2 are connected in parallel, and the input matching network and the gate of the transistor are respectively connected to a common node of the parallel combination of the capacitor C5 and the resistor R2.

[0009] According to one embodiment of the present invention, the output matching network includes an inductor L6, an inductor L7, an inductor L8, a capacitor C7, a capacitor C8 and a capacitor C9, wherein the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 are connected in series in sequence, a starting section of the series combination of the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 is connected to the drain of the transistor, an end of the series combination of the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 is connected to the load end, a first end of the capacitor C7 is connected between the inductor L6 and the inductor L7, a second end of the capacitor C7 is grounded, a first end of the capacitor C8 is connected between the inductor L7 and the inductor L8, and a second end of the capacitor C8 is grounded.

[0010] According to an embodiment of the present invention, the first end of the first inductor and the first end of the second capacitor are both connected to the second end of the capacitor C8.

[0011] According to one embodiment of the present invention, the bias circuit includes a gate bias circuit and a drain bias circuit, the gate bias circuit is connected to the gate of the transistor, and the gate bias circuit is used to provide a bias voltage for the gate of the transistor; the drain bias circuit is connected to the drain of the transistor, and the drain bias circuit is used to provide a bias voltage for the drain of the transistor.

[0012] According to one embodiment of the present invention, the gate bias circuit includes a resistor R0, a capacitor C4, a resistor R1 and an inductor L4, the resistor R0, the resistor R1 and the inductor L4 are connected in series in sequence, the first end of the capacitor C4 is connected between the resistor R0 and the resistor R1, the second end of the capacitor C4 is grounded, the starting end of the series combination of the resistor R0, the resistor R1 and the inductor L4 is used to input the gate voltage, and the end of the series combination of the resistor R0, the resistor R1 and the inductor L4 is connected to the gate of the transistor.

[0013] According to one embodiment of the present invention, the drain bias circuit includes a resistor R3, a capacitor C6, a resistor R4 and an inductor L5, the resistor R3, the resistor R4 and the inductor L5 are connected in series in sequence, the first end of the capacitor C6 is connected between the resistor R3 and the resistor R4, the second end of the capacitor C6 is grounded, the starting end of the series combination of the resistor R3, the resistor R4 and the inductor L5 is used to input a gate voltage, and the end of the series combination of the resistor R3, the resistor R4 and the inductor L5 is connected to the drain of the transistor.

[0014] The third aspect of the present application further provides a method for suppressing high-order harmonics, which is applied to the high-order harmonic suppression structure as described in the first aspect above, and the method comprises:

[0015] The high-order harmonic suppression structure is connected to the output end of the radio frequency power amplifier, and the parameters of the four elements, namely the first inductor, the second inductor, the first capacitor and the second capacitor, are adjusted so that the high-order harmonic suppression structure has a high impedance characteristic for the high-order harmonic signal, thereby preventing the high-order harmonic signal from passing through, and providing a low-impedance path in the loop to guide the high-order harmonic signal to the ground.

[0016] The above one or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:

[0017] The present invention proposes a high-order harmonic suppression structure, which cleverly integrates two inductors and two capacitors to work together to optimize and protect the output of the radio frequency power amplifier, significantly improving its output power and efficiency within a specific operating frequency band. In specific applications, the high-order harmonic suppression structure does not require any adjustment or modification to the original matching circuit. It only needs to be connected in parallel to the appropriate position after the output end of the radio frequency power amplifier, so as to give full play to its suppression effect on high-order harmonic signals while retaining the basic performance of the circuit. This direct and easy-to-integrate solution not only simplifies the harmonic suppression process, but also ensures the improvement of the working efficiency of the radio frequency power amplifier at the center frequency and its surrounding frequency bands. With the help of this optimized structure, the stability of the original matching circuit can be maintained, and at the same time, the associated high-order harmonic noise is effectively reduced, ultimately achieving significantly enhanced output power and power added efficiency while maintaining the original characteristics of the circuit.

[0018] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 is a schematic diagram of a circuit module of a radio frequency power amplifier in an embodiment of the present invention;

[0021] Figure 2 Schematic diagram of the circuit principle of the radio frequency power amplifier in an embodiment of the present invention;

[0022] Figure 3 A comparison diagram of the output power (Pout) of a conventional RF power amplifier and the RF power amplifier provided in the present application;

[0023] Figure 4 A comparison chart of the power added efficiency (PAE) of a conventional RF power amplifier and the RF power amplifier provided in the present application;

[0024] Figure 5 A comparison diagram of input return loss (S11) of a conventional RF power amplifier and the RF power amplifier provided in the present application;

[0025] Figure 6 A comparison diagram of the output return loss (S12) of a conventional RF power amplifier and the RF power amplifier provided in the present application;

[0026] Figure 7 This is a comparison chart of the small signal gain (S21) of a traditional RF power amplifier and the RF power amplifier provided in this application.

[0027] Explanation of the reference numerals: 100, high-order harmonic suppression structure; 200, input matching network; 300, stabilization network; 400, transistor; 500, output matching network; 600, bias circuit. DETAILED DESCRIPTION

[0028] The overall idea of ​​the technical solution provided by the present invention is as follows:

[0029] See also Figure 2The high-order harmonic suppression structure 100 includes: a first inductor L9, a second inductor L10, a first capacitor C11 and a second capacitor C10, wherein the first end of the first inductor L9 is used to be connected in parallel to the output end of the RF power amplifier, the second end of the first inductor L9 is connected to the first end of the first capacitor C11, the second end of the first capacitor C11 is grounded, the first end of the second capacitor C10 is used to be connected in parallel to the output end of the RF power amplifier, the second end of the second capacitor C10 is connected to the first end of the second inductor L10, and the second end of the second inductor L10 is grounded, the first inductor L9 and the second capacitor C10 are connected in parallel, the first capacitor C11 and the second inductor L10 are connected in parallel, and the parameters of the four elements of the first inductor L9, the second inductor L10, the first capacitor C11 and the second capacitor C10 are configured to have a high impedance characteristic for high-order harmonic signals, and provide a low impedance path in the loop to guide the high-order harmonic signals to the ground.

[0030] Specifically, by calculating the values ​​of the first inductor L9, the second inductor L10, the first capacitor C11 and the second capacitor C10, a resonant circuit can be created to form a high impedance at specific harmonic frequencies, thereby suppressing signals of these frequencies. For example, at the second harmonic frequency and the third harmonic frequency, the parallel combination of the inductor L9 and the capacitor C10 may present a high impedance, thereby suppressing the passage of these second harmonic frequencies and the third harmonic frequencies. Similarly, the parallel combination of the capacitor C11 and the inductor L10 may present a high impedance at a specific harmonic frequency, suppressing the harmonic signal. The series combination of the inductor L9 and the capacitor C11 can form a low impedance path to guide the harmonic signal to flow to the ground. The series combination of the capacitor C10 and the inductor L10 also forms a low impedance path to guide the harmonic signal to flow to the ground. When high-order harmonic signals (such as the second or third harmonic) reach the high-order harmonic suppression structure 100, since the inductor and the capacitor present high impedance characteristics at these frequencies, they are blocked from passing through the path from the transistor output to the load. On the contrary, these signals will flow to the ground through the low impedance path of the inductor and the capacitor, thereby being effectively suppressed and eliminated.

[0031] Furthermore, the high-order harmonic suppression structure 100 cleverly integrates two inductors and two capacitors to work together to optimize and protect the output of the RF power amplifier, significantly improving its output power and efficiency within a specific operating frequency band. In specific applications, the high-order harmonic suppression structure does not require any adjustment or modification to the original matching circuit. It only needs to be connected in parallel to the appropriate position after the output end of the RF power amplifier, so as to give full play to its suppression effect on high-order harmonic signals while retaining the basic performance of the circuit. This direct and easy-to-integrate solution not only simplifies the harmonic suppression process, but also ensures the improvement of the working efficiency of the RF power amplifier at the center frequency and its surrounding frequency bands. With the help of this optimized structure, the stability of the original matching circuit can be maintained, and at the same time, the associated high-order harmonic noise is effectively reduced, ultimately achieving significantly enhanced output power and power added efficiency while maintaining the original characteristics of the circuit.

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] See also Figure 1The present invention also provides a radio frequency power amplifier, which includes the high-order harmonic control structure as described above, and also includes: an input matching network 200, a stabilizing network 300, a transistor 400, an output matching network 500 and a bias circuit 600, wherein the input matching network 200 is connected to the gate of the transistor 400 through the stabilizing network 300, the input matching network 200 is used to match the source impedance to the optimal input impedance of the transistor 400, the stabilizing network 300 can achieve frequency compensation to ensure that the radio frequency power amplifier remains stable within the entire working frequency band, the output matching network 500 is connected to the drain of the transistor 400, and the output matching network 500 is used to match the load impedance to the transistor 4 00, through the input matching network 200 and the output matching network 500, the transistor 400 can achieve maximum power transmission and maintain excellent power added efficiency. The bias network is connected to the gate and drain of the transistor 400. The bias network is used to provide constant gate voltage and drain voltage for the transistor 400, and also provides a certain stability to ensure stable, efficient and safe operation of the RF power amplifier. The high-order harmonic suppression structure 100 is connected to the output matching network 500. The high-order harmonic suppression structure 100 can directly suppress high-order harmonics such as second harmonics and third harmonics without affecting basic matching, thereby improving the output power and power added efficiency within the working frequency band.

[0034] See also Figure 3 and Figure 4 , Figure 3 : is a comparison chart of the output power (Pout, Poweroutput) of a conventional RF power amplifier and the RF power amplifier provided in this application, Figure 4 The figure is a comparison of the power added efficiency (PAE) of a conventional RF power amplifier and the RF power amplifier provided by the present application. Among them, the conventional RF power amplifier is a structure without a high-order harmonic suppression structure 100 at the output end, which corresponds to the conventional type in the figure; the RF power amplifier provided by the present application is a structure with a high-order harmonic suppression structure 100, which corresponds to the innovative type in the figure; it can be seen that at the center frequency of 10GHz, after the high-order harmonic suppression structure 100 suppresses the second harmonic and the third harmonic, the output power and power added efficiency of the RF power amplifier are significantly improved, which means that the effect of the high-order harmonic suppression structure 100 is very significant, and has the advantages of improving power and efficiency.

[0035] See also Figure 5 and Figure 6 , Figure 5 is a comparison diagram of the input return loss (S11) of a conventional RF power amplifier and the RF power amplifier provided in this application, Figure 6 The output return loss (S12) comparison diagram of the conventional RF power amplifier and the RF power amplifier provided by the present application shows that the addition of the high-order harmonic suppression structure 100 does not have a significant impact on the original input matching network and output matching network, especially after the addition of the high-order harmonic suppression structure 100, the output matching circuit S22 is completely overlapped, which means that the impact of the high-order harmonic suppression structure 100 on the output matching network can be ignored. It can be seen that the high-order harmonic suppression structure 100 has the advantages of being easy to use, strong stability, and having little impact on the original matching network.

[0036] See also Figure 7 , Figure 7 This is a comparison chart of the small signal gain (S21) of a traditional RF power amplifier and the RF power amplifier provided in the present application. It can be seen that at the second harmonic 2f0 (20GHz) and the third harmonic 3f0 (30GHz) of the center frequency f0 (10GHz), the small signal gain is significantly suppressed, thereby reflecting the harmonic suppression effect of the high-order harmonic suppression structure 100.

[0037] See also Figure 2 The input matching network 200 includes: a capacitor C0, a capacitor C1, a capacitor C2, a capacitor C3, an inductor L0, an inductor L1, an inductor L2 and an inductor L3. The capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 are connected in series in sequence. The starting end of the series combination of the capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 is connected to the signal input end, and the end of the series combination of the capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 is connected to the stabilization network 300. The first end of the capacitor C1 is connected between the inductor L0 and the inductor L1, and the second end of the capacitor C1 is grounded. The first end of the capacitor C2 is connected between the inductor L1 and the inductor L2, and the second end of the capacitor C2 is grounded. The first end of the capacitor C3 is connected between the inductor L2 and the inductor L3, and the second end of the capacitor C3 is grounded. Specifically, capacitor C0, inductor L0, inductor L1, inductor L2, and inductor L3 are connected in series in sequence to form a continuous signal path. By adjusting the values ​​of the capacitor and inductor of the signal path, a specific impedance characteristic can be designed to match the input or output impedance of the RF amplifier and optimize the signal transmission efficiency. Capacitors C1, C2, and C3 connected in parallel on the path help filter out noise or interference of specific frequencies and improve signal quality.

[0038] See also Figure 2The stabilizing network 300 includes a capacitor C5 and a resistor R2, the capacitor C5 and the resistor R2 are connected in parallel, and the gate of the input matching network 200 and the transistor M1 are respectively connected to the common connection point of the parallel combination of the capacitor C5 and the resistor R2. Specifically, the capacitor C5 and the resistor R2 are connected in parallel to form a parallel RC network, which provides a frequency-dependent impedance and helps to suppress oscillations that may be generated by the amplifier. The capacitor C5 presents a low impedance at high frequencies, which helps to transmit signals; while the resistor R2 provides a stable impedance, which helps to consume energy, thereby reducing the possibility of oscillations.

[0039] See also Figure 2 The output matching network 500 includes an inductor L6, an inductor L7, an inductor L8, a capacitor C7, a capacitor C8 and a capacitor C9, wherein the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 are connected in series in sequence, the starting section of the series combination of the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 is connected to the drain of the transistor 400, the end of the series combination of the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 is connected to the load end, the first end of the capacitor C7 is connected between the inductor L6 and the inductor L7, the second end of the capacitor C7 is grounded, the first end of the capacitor C8 is connected between the inductor L7 and the inductor L8, and the second end of the capacitor C8 is grounded. Specifically, inductor L6, inductor L7, inductor L8, capacitor C7 and capacitor C9 are connected in series in sequence to form a continuous signal path. By adjusting the values ​​of the inductance and capacitance on the signal path, impedance matching between the transistor drain and the load can be achieved, thereby optimizing the signal transmission efficiency. Capacitor C7 and capacitor C8 connected in parallel on the signal path help filter out noise or interference of a specific frequency and improve signal quality.

[0040] See also Figure 2 The first end of the first inductor L9 and the first end of the second capacitor C10 are both connected to the second end of the capacitor C8, and the signal flows from the second end of the capacitor C8 into the first end of the first inductor L9 and the first end of the second capacitor C10.

[0041] The bias circuit 600 includes a gate bias circuit and a drain bias circuit. The gate bias circuit is connected to the gate of the transistor 400 and is used to provide a bias voltage for the gate of the transistor 400; the drain bias circuit is connected to the drain of the transistor 400 and is used to provide a bias voltage for the drain of the transistor 400. Specifically, the main function of the gate bias circuit is to provide a stable bias voltage for the gate of the transistor 100. This bias voltage determines the static operating point of the transistor 100, that is, the DC operating state of the transistor 100 when there is no input signal. By accurately controlling the gate voltage, it can be ensured that the transistor 100 operates in the desired amplification area, while reducing crossover distortion and improving the linearity of the amplifier. The drain bias circuit provides a bias voltage for the drain of the transistor 100, which helps to set the DC operating point of the drain of the transistor 100. The drain bias usually works together with the gate bias to ensure the linearity and efficiency of the transistor 100 when amplifying the signal.

[0042] See also Figure 2 The gate bias circuit 600 includes a resistor R0, a capacitor C4, a resistor R1 and an inductor L4, wherein the resistor R0, the resistor R1 and the inductor L4 are connected in series in sequence, the first end of the capacitor C4 is connected between the resistor R0 and the resistor R1, the second end of the capacitor C4 is grounded, the starting end of the series combination of the resistor R0, the resistor R1 and the inductor L4 is used to input the gate voltage, and the end of the series combination of the resistor R0, the resistor R1 and the inductor L4 is connected to the gate of the transistor 400. Specifically, the resistor R0, the resistor R1 and the inductor L4 are connected in series in sequence to form a continuous signal path for inputting the gate voltage. Through the series combination of the resistor R0, the resistor R1 and the inductor L4, a stable DC bias voltage can be provided for the gate of the transistor 400. The capacitor C4 is connected in parallel with the resistor R0 and the resistor R1 and is grounded, which helps to filter out high-frequency noise in the input voltage and ensure that the gate of the transistor M1 obtains a clean bias voltage.

[0043] See also Figure 2The drain bias circuit 600 includes a resistor R3, a capacitor C6, a resistor R4 and an inductor L5. The resistor R3, the resistor R4 and the inductor L5 are connected in series in sequence. The first end of the capacitor C6 is connected between the resistor R3 and the resistor R4, and the second end of the capacitor C6 is grounded. The starting end of the series combination of the resistor R3, the resistor R4 and the inductor L5 is used to input the gate voltage. The end of the series combination of the resistor R3, the resistor R4 and the inductor L5 is connected to the drain of the transistor 400. The resistor R3, the resistor R4 and the inductor L5 are connected in series in sequence to form a continuous signal path for inputting the drain voltage. Through the series combination of the resistor R3, the resistor R4 and the inductor L5, a stable DC bias voltage can be provided for the drain of the transistor 400. The capacitor C6 is connected in parallel with the resistor R3 and the resistor R4 and is grounded, which helps to filter out high-frequency noise in the input voltage and ensure that the transistor drain obtains a clean bias voltage.

[0044] The present invention also provides a method for suppressing high-order harmonics, which is applied to the high-order harmonic suppression structure 100 as described in the above embodiment, and specifically comprises the following steps:

[0045] The high-order harmonic suppression structure 100 is connected to the output end of the radio frequency power amplifier, and the parameters of the four elements of the first inductor, the second inductor, the first capacitor and the second capacitor are adjusted so that the high-order harmonic suppression structure 100 has a high impedance characteristic for high-order harmonic signals, thereby preventing high-order harmonic signals from passing through, and providing a low-impedance path in the loop to guide the high-order harmonic signals to the ground.

[0046] Specifically, the high-order harmonic suppression structure 100 is connected to the output end of the RF power amplifier. This step ensures that the high-order harmonic suppression structure 100 can directly act on the signal output by the amplifier, and adjusts the parameters of the four components of the first inductor, the second inductor, the first capacitor and the second capacitor. This includes selecting appropriate inductor and capacitor values ​​to ensure that the suppression structure presents high impedance characteristics to high-order harmonic signals, forming a low-impedance path in the loop, and guiding the high-order harmonic signals to the ground. This step ensures that even if the high-order harmonic signals are blocked by the high-order harmonic suppression structure, they will not accumulate in the circuit or interfere with other parts, but will be effectively shunted to the ground.

[0047] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0048] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A high-order harmonic suppression structure, characterized in that: include: A first inductor, a second inductor, a first capacitor and a second capacitor, wherein the first end of the first inductor is used to be connected in parallel to the output end of the radio frequency power amplifier, the second end of the first inductor is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, the first end of the second capacitor is used to be connected in parallel to the output end of the radio frequency power amplifier, the second end of the second capacitor is connected to the first end of the second inductor, and the second end of the second inductor is grounded, the first inductor and the second capacitor are connected in parallel, the first capacitor is connected in parallel to the second inductor, and the parameters of the four elements of the first inductor, the second inductor, the first capacitor and the second capacitor are configured to have high impedance characteristics for high-order harmonic signals, and provide a low-impedance path in the loop to guide the high-order harmonic signals to the ground.

2. A radio frequency power amplifier, characterized in that: It includes a high-order harmonic suppression structure as described in claim 1, and also includes: an input matching network, a stabilization network, a transistor, an output matching network and a bias circuit, wherein the input matching network is connected to the gate of the transistor through the stabilization network, the input matching network is used to match the source impedance to the optimal input impedance of the transistor, the output matching network is connected to the drain of the transistor, the output matching network is used to match the load impedance to the optimal output impedance of the transistor, the bias network is connected to the gate and drain of the transistor, the bias network is used to provide constant gate voltage and drain voltage for the transistor, and the high-order harmonic suppression structure is connected to the output matching network.

3. A radio frequency power amplifier according to claim 2, characterized in that: The input matching network includes: a capacitor C0, a capacitor C1, a capacitor C2, a capacitor C3, an inductor L0, an inductor L1, an inductor L2 and an inductor L3, wherein the capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 are connected in series in sequence, a starting end of the series combination of the capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 is connected to the signal input end, an end of the series combination of the capacitor C0, the inductor L0, the inductor L1, the inductor L2 and the inductor L3 is connected to the stabilizing network, a first end of the capacitor C1 is connected between the inductor L0 and the inductor L1, a second end of the capacitor C1 is grounded, a first end of the capacitor C2 is connected between the inductor L1 and the inductor L2, a second end of the capacitor C2 is grounded, a first end of the capacitor C3 is connected between the inductor L2 and the inductor L3, and a second end of the capacitor C3 is grounded.

4. The radio frequency power amplifier according to claim 2, characterized in that: The stabilizing network includes a capacitor C5 and a resistor R2, the capacitor C5 and the resistor R2 are connected in parallel, and the input matching network and the gate of the transistor are respectively connected to a common node of the parallel combination of the capacitor C5 and the resistor R2.

5. The radio frequency power amplifier according to claim 2, characterized in that: The output matching network includes an inductor L6, an inductor L7, an inductor L8, a capacitor C7, a capacitor C8 and a capacitor C9, wherein the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 are connected in series in sequence, a starting section of the series combination of the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 is connected to the drain of the transistor, an end of the series combination of the inductor L6, the inductor L7, the inductor L8, the capacitor C7 and the capacitor C9 is connected to the load end, a first end of the capacitor C7 is connected between the inductor L6 and the inductor L7, a second end of the capacitor C7 is grounded, a first end of the capacitor C8 is connected between the inductor L7 and the inductor L8, and a second end of the capacitor C8 is grounded.

6. The radio frequency power amplifier according to claim 5, characterized in that: The first end of the first inductor and the first end of the second capacitor are both connected to the second end of the capacitor C8.

7. The radio frequency power amplifier according to claim 2, characterized in that: The bias circuit includes a gate bias circuit and a drain bias circuit, wherein the gate bias circuit is connected to the gate of the transistor and is used to provide a bias voltage for the gate of the transistor; the drain bias circuit is connected to the drain of the transistor and is used to provide a bias voltage for the drain of the transistor.

8. The radio frequency power amplifier according to claim 7, characterized in that: The gate bias circuit includes a resistor R0, a capacitor C4, a resistor R1 and an inductor L4, wherein the resistor R0, the resistor R1 and the inductor L4 are connected in series in sequence, a first end of the capacitor C4 is connected between the resistor R0 and the resistor R1, a second end of the capacitor C4 is grounded, a starting end of the series combination of the resistor R0, the resistor R1 and the inductor L4 is used to input a gate voltage, and an end of the series combination of the resistor R0, the resistor R1 and the inductor L4 is connected to the gate of the transistor.

9. The radio frequency power amplifier according to claim 8, characterized in that: The drain bias circuit includes a resistor R3, a capacitor C6, a resistor R4 and an inductor L5, wherein the resistor R3, the resistor R4 and the inductor L5 are connected in series in sequence, a first end of the capacitor C6 is connected between the resistor R3 and the resistor R4, a second end of the capacitor C6 is grounded, a starting end of the series combination of the resistor R3, the resistor R4 and the inductor L5 is used to input a gate voltage, and an end of the series combination of the resistor R3, the resistor R4 and the inductor L5 is connected to the drain of the transistor.

10. A method for suppressing high-order harmonics, characterized in that: The method is applied to the high-order harmonic suppression structure according to claim 1, and the method comprises: The high-order harmonic suppression structure is connected to the output end of the radio frequency power amplifier, and the parameters of the four elements, namely the first inductor, the second inductor, the first capacitor and the second capacitor, are adjusted so that the high-order harmonic suppression structure has a high impedance characteristic for the high-order harmonic signal, thereby preventing the high-order harmonic signal from passing through, and providing a low-impedance path in the loop to guide the high-order harmonic signal to the ground.

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