Decision feedback equalization circuit
By using periodic switches and capacitors in the judgment feedback equalization circuit, charge superposition operation is performed based on the judgment results of the first N clock cycles, the problems of large circuit area and high design difficulty in the prior art are solved, and more efficient and accurate Verification feedback operation.
Patent Information
- Application Number
- CN202411345973.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-09-18
- Filing Date
- 2024-09-25
- Publication Date
- 2025-01-03
AI Technical Summary
The existing judgment feedback equalization circuit requires a bias circuit to determine the initial level of the AC coupling capacitor, which causes the circuit to occupy a large area and is difficult to design, and the judgment result may be incorrect due to the uncertainty of the voltage on the capacitor.
By introducing periodic switches and capacitors into the judgment feedback equalization circuit, charge superposition operation is performed based on the judgment results of the first N clock cycles when the switch is turned off, the use of the bias circuit is avoided and the voltage certainty of the capacitor is ensured.
The area of the judgment feedback equalization circuit is effectively reduced, the circuit design difficulty is reduced, and the speed and accuracy of the judgment feedback operation is improved, avoiding operation errors caused by uncertain capacitance voltage.
Smart Images
Figure CN119254581A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a decision feedback equalization circuit. Background Art
[0002] During the data transmission and reception process of high-speed links, due to channel loss and reflection, ISI (Inter Symbol Interference) is prone to occur at the receiving end, such as data edge tailing. As the transmission rate increases, ISI becomes more serious. The receiving end usually uses DFE (Decision Feedback Equalizer) circuit to solve the ISI problem.
[0003] The DFE circuit can feed back the decision result of the current symbol to the signal receiving end, and superimpose the decision result with the subsequent symbol signal to offset or partially offset the subsequent impact of the current symbol. When superimposing the decision result with the subsequent symbol signal, it can be implemented in a variety of ways such as current superposition, voltage superposition or charge superposition. Among them, the charge superposition method can theoretically achieve high-speed DFE addition and subtraction operations because the charge sharing between capacitors is completed instantly. Figure 1 As shown, in the charge superposition method, the signal is generally coupled to the input node of the sampler (slicer) in the DFE circuit through the AC coupling capacitor, but this requires a bias circuit to be set at the input node of the slicer. Otherwise, the initial voltage at one end of the AC coupling capacitor C0 connected to the slicer is uncertain, which may lead to an erroneous decision result of the slicer.
[0004] However, such a bias circuit not only occupies a large area, but also has great design difficulty, because the output current of the bias circuit needs to be much larger than the leakage current, but also needs to be small so as not to affect the DFE calculation. Due to these problems of the bias circuit, the DFE circuit also occupies a large area and has great design difficulty. Summary of the invention
[0005] In view of this, an embodiment of the present invention provides a decision feedback equalization circuit, which can effectively reduce the area of the decision feedback equalization circuit and greatly reduce the difficulty of circuit design.
[0006] In a first aspect, an embodiment of the present invention provides a decision feedback equalization circuit, comprising: a first switch, a first capacitor and a decision feedback module; the first switch, one end of which is connected to a signal input end and the other end of which is connected to the first capacitor, is constructed to be periodically turned on or off, so as to transmit a target signal input from the signal input end to the first capacitor when it is turned on; the first capacitor, one end of which is connected to the first switch and the other end of which is grounded, is constructed to receive the target signal when the first switch is turned on, or to provide the target signal to the decision feedback module when the first switch is turned off; the decision feedback module, whose input end is connected to the first capacitor, is constructed to perform a decision feedback equalization operation based on the charge superposition of the target signal and the feedback signal when the first switch is turned off, to obtain a decision result corresponding to the target signal, wherein the feedback signal is generated based on the decision results of the signals of the previous to the previous N clock cycles of the target signal, where N is a positive integer.
[0007] In one embodiment, the decision feedback module includes: a decision submodule and a feedback submodule; the decision submodule, whose input end is respectively connected to the first capacitor and the output end of the feedback submodule, and whose output end is connected to the input end of the feedback submodule, is constructed to, when the first switch is disconnected, perform charge superposition on the target signal and the feedback signal provided by the feedback submodule to obtain a superposition signal, and make a decision on the superposition signal to obtain a decision result corresponding to the target signal; the feedback submodule is constructed to determine the feedback signal according to the decision result of the signal of the previous to the previous N clock cycles of the target signal made in advance by the decision submodule, and provide the feedback signal to the input end of the decision submodule.
[0008] In one embodiment, the feedback submodule includes: a delay queue and a first feedback unit; the delay queue includes N delay units, each of which is connected in series to the output end of the decision submodule in sequence, wherein each of the delay units is constructed to delay the decision result input to the delay unit by 1 clock cycle, and then output the delayed decision result as a decision delay result to the first feedback unit; and / or, each of the delay units is constructed to delay the inverted result of the decision result input to the delay unit by 1 clock cycle, and then output the inverted and delayed decision result as a decision delay result to the first feedback unit; the first feedback unit, whose output end is connected to the input end of the decision submodule, is constructed to determine a corresponding feedback sub-signal for each received decision delay result, and transmit each feedback sub-signal to the input end of the decision submodule respectively, and the feedback signal is equal to the superposition sum of each feedback sub-signal.
[0009] In one implementation, the feedback submodule further includes a bridge unit, the output end of the first feedback unit is connected to the input end of the decision submodule through the bridge unit, and the bridge unit includes a capacitive element.
[0010] In one embodiment, the capacitance value of the capacitive element is between 10 femtofarads and 500 femtofarads.
[0011] In one embodiment, the number of the first switch, the first capacitor and the first feedback unit are each two; the number of the decision submodule and the delay queue are each one; each delay unit in the delay queue is used to input the decision delay result corresponding to the delayed decision result into one of the first feedback units, and input the decision delay result corresponding to the inverted and delayed decision result into another first feedback unit; the decision submodule includes two input terminals, and the two input terminals include a positive input terminal and an inverting input terminal; the positive input terminal is connected to the output terminal of one of the first switches, a first capacitor and a first feedback unit, and the inverting input terminal is connected to the output terminal of another first switch, another first capacitor and another first feedback unit.
[0012] In one embodiment, the number of the decision submodules and the number of the delay queues are both 2. M Each of the decision submodules has two input terminals, and the two input terminals include a positive input terminal and a negative input terminal; the number of the first switch, the first capacitor and the first feedback unit is 2 M+1 Each input end of each decision submodule is connected to a first switch and a first capacitor; each first feedback unit performs signal feedback between the output end of each delay queue and the input end of each decision submodule, so that the decision feedback equalization circuit realizes 1 / 2 M The sampling rate is directly fed back, where M is a non-negative integer.
[0013] In one embodiment, the number of the decision submodules is 2 M+R The number of the first switches and the first capacitors are both 2 M+R+1 Each of the decision submodules has two input terminals, the two input terminals include a positive input terminal and a negative input terminal; each input terminal of each of the decision submodules is connected to a first switch and a first capacitor; the number and connection mode of the first feedback units and the delay queues enable the decision feedback equalization circuit to achieve 1 / 2 M The sampling rate R is a pre-judgment feedback, where M is a non-negative integer and R is a non-negative integer less than or equal to N.
[0014] In one embodiment, the first feedback unit includes N feedback channels formed based on a capacitor array, each of the feedback channels corresponds one-to-one to each of the feedback sub-signals; each of the feedback channels has a feedback coefficient; each of the feedback coefficients is related to the capacitance ratio of the corresponding feedback channel, and the capacitance ratio is equal to the ratio of the channel capacitance value of the feedback channel to the total capacitance value of the capacitor array.
[0015] In one embodiment, the feedback submodule also includes one or more second feedback units; each of the second feedback units is used to replace one of the feedback channels, and provide a feedback sub-signal corresponding to the decision delay result to the input end of the decision submodule according to the decision delay result corresponding to the replaced feedback channel.
[0016] In one embodiment, the second feedback unit is specifically used to replace one of the feedback channels, and according to the decision delay result corresponding to the replaced feedback channel, provides the first voltage or the second voltage as the feedback sub-signal corresponding to the decision delay result to the input end of the decision sub-module, wherein the first voltage is equal to the sum of a preset reference voltage and a target feedback voltage, the second voltage is equal to the difference between the preset reference voltage and the target feedback voltage, and the target feedback voltage is the product of the decision delay result corresponding to the replaced feedback channel and the feedback coefficient of the feedback channel.
[0017] In one implementation, the control clock of the decision submodule triggers the decision submodule to operate within a preset time range after the first switch is switched to an off state and before it is switched to an on state again.
[0018] In one embodiment, the decision feedback module also includes a second switch and a second capacitor; one end of the second switch is connected to the first capacitor, and the other end is connected to the second capacitor; one end of the second capacitor is connected to the second switch and the input end of the decision submodule, and the other end is grounded; the control clock of the first switch has the same frequency as the control clock of the second switch and has a phase difference of 180 degrees, and the control clock that triggers the operation of the decision submodule is the same as the control clock of the first switch.
[0019] In one implementation, the decision feedback module further includes a voltage follower element; one end of the second switch is connected to the first capacitor through the voltage follower element.
[0020] In one implementation, the decision feedback module is implemented based on at least one of the following methods: a full-rate direct feedback structure, a full-rate pre-judgment structure, a half-rate direct feedback structure, and a half-rate pre-judgment structure.
[0021] In the decision feedback equalization circuit provided by an embodiment of the present invention, the first switch can be periodically turned on or off, so as to transmit the target signal input from the signal input end to the first capacitor when it is turned on, and the first capacitor can receive the target signal when the first switch is turned on, or provide the target signal to the decision feedback module when the first switch is turned off. The decision feedback module can perform a decision feedback equalization operation based on the charge superposition of the target signal and the feedback signal when the first switch is turned off to obtain a decision result corresponding to the target signal. In this way, on the one hand, since the feedback signal is generated based on the judgment results of the signals of the previous to the previous N clock cycles of the target signal, after the target signal and the feedback signal are superimposed, the interference of the signal that is N clock cycles ahead of the target signal in timing to the target signal can be offset; on the other hand, since one end of the first capacitor is grounded and the other end is connected to the target signal, that is, the voltages of the two plates of the first capacitor are both certain, the first capacitor in the embodiment of the present invention will not cause errors in the operation of the decision feedback module due to the uncertainty of the voltage on the AC coupling capacitor like the AC coupling capacitor in the prior art. Therefore, the decision feedback equalization circuit provided in the embodiment of the present invention does not need to set a bias circuit at the input end of the decision feedback module, so it can effectively reduce the area of the decision feedback equalization circuit and greatly reduce the difficulty of circuit design. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 A schematic diagram of a structure of a decision feedback equalization circuit in the prior art;
[0024] Figure 2 A schematic diagram of a structure of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0025] Figure 3 Another structural schematic diagram of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0026] Figure 4 A schematic diagram of another structure of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0027] Figure 5 A schematic diagram of another structure of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0028] Figure 6A schematic diagram of yet another structure of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0029] Figure 7 Another structural schematic diagram of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0030] Figure 8 A schematic diagram of the structure of a second feedback unit in a decision feedback equalization circuit provided in an embodiment of the present invention;
[0031] Fig. 9 Still another structural schematic diagram of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0032] Fig.10 A schematic diagram of a full-rate feedback decision feedback equalization circuit in an embodiment of the present invention;
[0033] Fig.11 A schematic diagram of a structure of a half-rate predictive decision feedback equalization circuit in an embodiment of the present invention;
[0034] Fig.12 A schematic diagram of a timing relationship between a control clock of a first switch and a control clock of a decision submodule in an embodiment of the present invention;
[0035] Fig.13 A schematic diagram of a partial structure of a decision feedback module in an embodiment of the present invention;
[0036] Fig.14 is another partial structural diagram of a decision feedback module in an embodiment of the present invention;
[0037] Fig.15 A detailed structural diagram of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0038] Fig.16 for Fig.15 The equivalent circuit diagram of the two working stages of the corresponding decision feedback equalization circuit;
[0039] Fig.17 A signal eye diagram of a decision feedback equalization circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0040] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0041] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0042] In order to enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial technical effects of the embodiments of the present invention, specific embodiments are described in detail below.
[0043] The embodiments of the present invention provide a decision feedback equalization circuit, which can effectively reduce the area of the decision feedback equalization circuit and greatly reduce the difficulty of circuit design.
[0044] like Figure 2 As shown, the decision feedback equalization circuit provided by the embodiment of the present invention may include:
[0045] A first switch 1, a first capacitor 2 and a decision feedback module 3;
[0046] A first switch 1, one end of which is connected to the signal input terminal In, and the other end of which is connected to the first capacitor 2, and is configured to be periodically turned on or off, so as to transmit the target signal Vin input from the signal input terminal In to the first capacitor 2 when turned on;
[0047] A first capacitor 2, one end of which is connected to the first switch 1 and the other end of which is grounded, and is configured to receive the target signal Vin when the first switch 1 is turned on, or to provide the target signal Vin to the decision feedback module 3 when the first switch 1 is turned off;
[0048] The decision feedback module 3, whose input end is connected to the first capacitor 2, is constructed to perform a decision feedback equalization operation based on the charge superposition of the target signal Vin and the feedback signal VF when the first switch 1 is disconnected, so as to obtain a decision result D corresponding to the target signal Vin, wherein the feedback signal VF is generated based on the decision results D-1 to DN of the signals of the previous to the previous N clock cycles of the target signal Vin, where N is a positive integer.
[0049] In the decision feedback equalization circuit provided by an embodiment of the present invention, the first switch 1 can be periodically turned on or off, so as to transmit the target signal Vin input from the signal input terminal In to the first capacitor 2 when it is turned on. The first capacitor 2 can receive the target signal Vin when the first switch 1 is turned on, or provide the target signal Vin to the decision feedback module 3 when the first switch 1 is turned off. The decision feedback module 3 can perform a decision feedback equalization operation based on the charge superposition of the target signal Vin and the feedback signal VF when the first switch 1 is turned off, so as to obtain a decision result D corresponding to the target signal Vin. In this way, on the one hand, since the feedback signal VF is generated based on the decision results D-1 to DN of the signals of the previous to the previous N clock cycles of the target signal Vin, after the target signal Vin is superimposed on the feedback signal VF, the interference of the signal that is N clock cycles ahead of the target signal Vin in timing to the target signal Vin can be offset; on the other hand, since one end of the first capacitor 2 is grounded and the other end is connected to the target signal Vin, that is, the voltages of the two plates of the first capacitor 2 are both certain, the first capacitor 2 in the embodiment of the present invention will not cause the operation of the decision feedback module 3 to go wrong due to the uncertainty of the voltage on the AC coupling capacitor like the AC coupling capacitor in the prior art. Therefore, the decision feedback equalization circuit provided in the embodiment of the present invention does not need to set a bias circuit at the input end of the decision feedback module 3, so it can effectively reduce the area of the decision feedback equalization circuit and greatly reduce the difficulty of circuit design.
[0050] Furthermore, the decision feedback equalization circuit provided in the embodiment of the present invention can periodically charge the first capacitor 2 through the first switch 1, and transmit the target signal Vin to the first capacitor 2. After the first switch 1 is disconnected, the first capacitor 2 can maintain the received target signal Vin and provide the target signal Vin to the input end of the decision feedback module 3. Compared with the prior art in which the input signal is transmitted to the input end of the decision feedback module 3 through the AC coupling capacitor, in the decision feedback equalization circuit provided in the embodiment of the present invention, the target signal Vin does not need to be coupled through the AC coupling capacitor, and therefore will not be divided by the AC coupling capacitor, so that the target signal Vin can be transmitted to the input end of the decision feedback module 3 with a larger amplitude and more effectively. Since the speed and accuracy of the decision feedback equalization operation are positively correlated with the amplitude of the target signal Vin received by the decision feedback module 3, the speed and accuracy of the decision feedback operation can be effectively improved.
[0051] In the embodiment of the present invention, the signal input terminal In can be used to connect to a signal source or a reference source as required. When the signal input terminal In is connected to a signal source, the target signal Vin can be a digital signal composed of a series of 0, 1 or high and low levels, wherein each level can have its own corresponding voltage value; when the signal input terminal is connected to a reference source, the target signal Vin can be a fixed level signal.
[0052] From the timing point of view, the target signal Vin may refer to the signal currently inputted by the signal input terminal In, and the feedback signal VF is a signal generated based on the decision results D-1 to DN of the signals of the previous to the previous N clock cycles of the target signal Vin, so the decision results D-1 to DN may also be voltage signals. The feedback signal VF may be used to be superimposed with the target signal Vin (for example, to perform charge superposition) so as to offset the interference of these N signals on the target signal Vin (for example, the interference caused by the edge tailing of these N signals). Among them, the signal of the previous clock cycle of the target signal Vin is adjacent to the target signal Vin, and the interference caused to the target signal Vin is relatively large, so the influence weight of the decision result D-1 on the feedback signal VF may be relatively large, while the signal of the previous N clock cycles of the target signal Vin is far away from the target signal Vin, and the interference caused to the target signal Vin is relatively small, so the influence weight of the decision result DN on the feedback signal VF may be relatively small.
[0053] In specific implementation, Figure 3 As shown, in one embodiment of the present invention, the decision feedback module 3 may include: a decision submodule 31 and a feedback submodule 32; the decision submodule 31, whose input end is respectively connected to the output end of the first capacitor 2 and the feedback submodule 32, and whose output end is connected to the input end of the feedback submodule 32, the decision submodule 31 can be constructed to, when the first switch 1 is disconnected, perform charge superposition on the target signal Vin and the feedback signal VF provided by the feedback submodule 32 to obtain a superposition signal VA, and make a decision on the superposition signal VA to obtain a decision result D corresponding to the target signal Vin; the feedback submodule 32 can be constructed to determine the feedback signal VF according to the decision results D-1 to DN of the signals of the previous to the previous N clock cycles of the target signal Vin made in advance by the decision submodule 31, and provide the feedback signal VF to the input end of the decision submodule 31.
[0054] like Figure 4As shown, in one embodiment of the present invention, the feedback submodule 32 may include a delay queue 321 and a first feedback unit 322; wherein the delay queue 321 includes N delay units, each of which may be sequentially connected in series to the output end of the decision submodule 31, wherein each delay unit is constructed to delay the decision result input to the delay unit by 1 clock cycle, and then output the delayed decision result as a decision delay result to the first feedback unit 322; and / or, wherein each delay unit may be constructed to delay the inverted result of the decision result input to the delay unit by 1 clock cycle, and then output the inverted and delayed decision result as a decision delay result to the first feedback unit 322.
[0055] It can be understood that since the delay units are connected in series with each other, from the direction from near to far from the output end of the decision submodule 31, the decision delay result output by each delay unit is delayed by one clock cycle based on the decision delay result output by the previous delay unit. Therefore, at the same time, the decision delay result output by each delay unit is actually the decision result D-1 to DN corresponding to the signal of N clock cycles, among which the decision delay result output by the delay unit closest to the decision submodule 31 is the decision result D-1 corresponding to the signal of the previous clock cycle of the target signal, and the decision delay result output by the delay unit farthest from the decision submodule 31 is the decision result DN corresponding to the signal of the previous N clock cycles of the target signal.
[0056] The first feedback unit 322, whose output end can be connected to the input end of the decision submodule 31, is constructed to determine the corresponding feedback sub-signal Vf(i) for each received decision delay result, i=1, 2...N, and transmit each feedback sub-signal Vf(i) to the input end of the decision submodule 31 respectively, wherein the feedback signal VF is equal to the superposition sum of each feedback sub-signal Vf(i).
[0057] In a specific implementation, the first feedback unit 322 may include N feedback channels formed based on a capacitor array, each of the feedback channels corresponds to each of the feedback sub-signals one by one; each feedback channel may have a feedback coefficient; wherein each feedback coefficient is related to the capacitance ratio of the feedback channel corresponding to the feedback coefficient, and the capacitance ratio is equal to the ratio of the channel capacitance value of the feedback channel to the total capacitance value of the capacitor array. The feedback sub-signal Vf(i) of each feedback channel may be equal to the product of the feedback coefficient of the feedback channel and the decision delay result corresponding to the feedback channel. For example, Figure 5As shown, in one embodiment of the present invention, the input end of the judgment submodule 31 can be connected to a capacitor array, and the capacitor array can be composed of multiple feedback capacitors of different sizes. TAP1, TAP2...TAPN correspond to a feedback channel respectively, and each feedback channel corresponds to a plurality of feedback capacitors that can be selectively connected. By changing the feedback capacitor connected to the circuit (i.e., changing the channel capacitance value of the feedback channel), the feedback coefficient of the capacitor array can be adjusted. In one example, the channel capacitances corresponding to the feedback channels tap1~tapN are Ctap1, Ctap2,..., CtapN, respectively, and the remaining capacitors are grounded, then the sum of all feedback capacitors in the capacitor array (including the capacitors connected to the circuit and the capacitors grounded) is the total capacitance value Ctot of the capacitor array. In one embodiment of the present invention, the feedback coefficient corresponding to TAP1 is the largest, the feedback coefficient corresponding to TAP2 is the second largest, and so on. Based on this, in one example, when the capacitor array allocates capacitance, the capacitance reserved for TAP1 can be the largest, the value is the largest, TAP2 is the second largest, and gradually decreases, and the last few TAPs can reserve the same capacitance. The capacitor array may be decoded and selected in a variety of ways, such as binary decoding or thermometer decoding, which is not limited in the embodiments of the present invention.
[0058] Furthermore, in addition to the first feedback unit 322, the feedback submodule 32 may also include other circuit elements. Figure 6 As shown, in one example, the feedback submodule 32 may further include a bridge unit 323, and the output end of the first feedback unit 322 may be connected to the input end of the decision submodule 31 through the bridge unit 323, wherein the bridge unit 323 may include a capacitor element. In one embodiment, the capacitance value of the capacitor element may be between 10 femtofarads and 500 femtofarads. In this way, in the case of a large capacitance of the total capacitance value Ctot of the capacitor array in the first feedback unit 322, by connecting the bridge unit 323 in series with the capacitor array, the capacitance after the series connection may be made much smaller than the total capacitance value Ctot of the capacitor array, so that the equivalent capacitance seen from the signal input end In and the equivalent capacitance seen from the signal feedback end may be greatly reduced, thereby greatly accelerating the setup time of the input signal and the feedback signal, effectively improving the speed of the decision load balancing circuit, and also greatly reducing the power consumption loss caused by the charging and discharging of the capacitor.
[0059] In the above-mentioned embodiment, the decision feedback equalization circuit mainly implements feedback through the first feedback unit 322, but the embodiment of the present invention is not limited thereto, and in other embodiments of the present invention, signal feedback may also be implemented in other ways. For example, Figure 7 As shown, in one embodiment of the present invention, the feedback submodule 32 may further include one or more second feedback units 324; wherein each second feedback unit 324 may be used to replace one of the feedback channels (eg Figure 7 In the example, the feedback channel TAP1 is used to replace the feedback channel TAP1), and according to the decision delay result corresponding to the replaced feedback channel, a feedback sub-signal corresponding to the decision delay result is provided to the input end of the decision sub-module 31.
[0060] Specifically, in one embodiment of the present invention, the second feedback unit 324 can be used to replace one of the feedback channels, and according to the decision delay result corresponding to the replaced feedback channel, the first voltage V1 or the second voltage V2 is provided as the feedback sub-signal corresponding to the decision delay result to the input end of the decision submodule 31, wherein the first voltage V1 is equal to the sum of the preset reference voltage Vref and the target feedback voltage, the second voltage is equal to the difference between the preset reference voltage Vref and the target feedback voltage, and the target feedback voltage is the product of the decision delay result corresponding to the replaced feedback channel and the feedback coefficient of the feedback channel. For example, in one example, the target feedback voltage can be the product of the decision delay result Vtap1 (ie, D-1) and the feedback coefficient of the feedback channel TAP1. In another example, the target feedback voltage can be the product of the decision delay result Vtap2 (ie, D-2) and the feedback coefficient of the feedback channel TAP2. After the feedback channel is replaced by the second feedback unit 324, the capacitor corresponding to the feedback channel is no longer needed, so the circuit area can be effectively saved. In one example, the preset reference voltage Vref may be equal to an average value (ie, a common mode component) of the input target signal Vin.
[0061] For example, in one embodiment of the present invention, Figure 8 As shown, the second feedback unit 324 may include a data selection element MUX, which can be used to select one from the first voltage V1 and the second voltage V2 as a feedback sub-signal corresponding to the decision delay result according to the decision delay result corresponding to the replaced feedback channel and provide it to the input end of the decision sub-module 31.
[0062] In the embodiment of the present invention, the number and connection mode of the first switch 1, the first capacitor 2, the decision submodule 31, the delay queue 321 and the first feedback unit 322 are various and can be adjusted as needed.
[0063] Specifically, in one embodiment of the present invention, Fig. 9As shown, in the decision feedback equalization circuit, the number of the first switch 1, the first capacitor 2 and the first feedback unit 322 can all be two; the number of the decision submodule 31 and the delay queue 321 are both one; each delay unit in the delay queue 321 is used to input the decision delay result corresponding to the delayed decision result into one of the first feedback units 322, and input the decision delay result corresponding to the inverted result after inversion and delay into another first feedback unit 322; the decision submodule 31 includes two input terminals, and the two input terminals include a positive input terminal and an inverting input terminal; the positive input terminal is connected to the output terminal of one of the first switches 1, one first capacitor 2 and one first feedback unit 322, and the inverting input terminal is connected to the output terminal of another first switch 1, another first capacitor 2 and another first feedback unit 322.
[0064] In this way, for each input terminal of the decision submodule 31, the target signal Vin input by the first switch 1 and the first capacitor 2 and the feedback signal VF fed by the first feedback unit 322 can be superimposed here to form a superimposed signal, and the decision submodule 31 can obtain the decision result D corresponding to the target signal Vin by comparing the superimposed signal of the positive input terminal with the superimposed signal of the negative input terminal. Optionally, the decision result D can be a high level signal or a low level signal. For example, in one example, if the signal at the positive input terminal is greater than the signal at the negative input terminal, the decision result D can be a high level (or logic "1"), and if the signal at the positive input terminal is less than the signal at the negative input terminal, the decision result D can be a low level (or logic "0"). Exemplarily, the voltage corresponding to the high level can be, for example, the power supply voltage, and the voltage corresponding to the low level can be, for example, 0.
[0065] Fig. 9 In the illustrated embodiment, the decision feedback equalization operation is full-rate direct feedback (i.e., the rate of the driving clock of the decision feedback module (i.e., the sampling rate) is equal to the data rate of the signal input end), but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, other feedback modes may also exist. For example, in some embodiments of the present invention, the rate of the decision feedback equalization operation may be reduced, i.e., the frequency of the driving clock of the decision feedback module may be reduced (i.e., the sampling rate may be reduced) so that the timing of the circuit may converge more easily. In other embodiments of the present invention, a predictive structural feedback may also be used, thereby effectively improving the feedback speed.
[0066] For example, in one example, the number of decision submodules 31 and delay queues 321 are both 2. M Each decision submodule 31 has two input terminals, the two input terminals include a positive input terminal and a negative input terminal; the number of the first switch 1, the first capacitor 2 and the first feedback unit 322 are all 2 M+1Each input end of each decision submodule 31 is connected to a first switch 1 and a first capacitor 2; each first feedback unit 322 performs signal feedback between the output end of each delay queue 321 and the input end of each decision submodule 31, so that the decision feedback equalization circuit realizes 1 / 2 M Sampling rate direct feedback, where M is a non-negative integer. For example, when M is 0, the decision feedback equalization circuit is a full-rate direct feedback mode, and when M=1, the decision feedback equalization circuit is a half-rate direct feedback mode. 1 / 2 M The sampling rate direct feedback structure can be implemented in various existing ways, which will not be described here.
[0067] In another example, the number of decision submodules 31 is 2 M+R The number of first switches 1 and first capacitors 2 are both 2 M+R+1 Each decision submodule 31 has two input terminals, the two input terminals include a positive input terminal and a negative input terminal; each input terminal of each decision submodule 31 is connected to a first switch 1 and a first capacitor 2; the number and connection mode of the first feedback unit 322 and the delay queue 321 enable the decision feedback equalization circuit to achieve 1 / 2 M Sampling rate R-bit prejudgment feedback, where M is a non-negative integer and R is a non-negative integer less than or equal to N. For example, when M is 0 and R is 0, the corresponding decision feedback equalization circuit is a full-rate 0-bit prejudgment feedback mode (i.e., full-rate direct feedback mode). When M=1 and R=1, the corresponding decision feedback equalization circuit is a half-rate 1-bit prejudgment feedback. R represents the number of decision delay results using prejudgment feedback among the N decision delay results corresponding to the delay queue. 1 / 2 M The sampling rate R-bit pre-judgment feedback structure can be implemented in various existing ways, which will not be described here.
[0068] Based on this, in one embodiment of the present invention, the decision feedback module 3 can be implemented based on at least one of the following methods: full-rate direct feedback structure, full-rate prediction structure, half-rate direct feedback structure, and half-rate prediction structure.
[0069] Exemplarily, a circuit schematic diagram of a full-rate direct feedback decision feedback equalization circuit can be as follows: Fig.10 A circuit schematic diagram of a half-rate predictive decision feedback equalization circuit can be shown as follows. Fig.11 As shown. Wherein, slicer is a sampler, V1 is a first voltage, and V2 is a second voltage. Cin is a first capacitor 1, Cu is a capacitor unit, and each capacitor in the capacitor array can be an integer multiple of a capacitor unit. Cdum is a redundant capacitor.
[0070] It should be noted that, in the embodiment of the present invention, for the decision feedback equalization circuit including the positive phase input terminal and the negative phase input terminal, the way in which the signal source is connected to the signal input terminal may be different depending on the type of the signal source. For example, in one example, the signal source is a differential signal, then the two first switches 1 connected to the positive phase input terminal and the negative phase input terminal of the decision submodule 31, and their respective corresponding signal input terminals can be respectively connected to a signal component in the differential signal. In another example, the signal source is a single-ended signal, then the first switch 1 connected to one input terminal (e.g., the positive phase input terminal) of the decision submodule 31, and its corresponding signal input terminal In can be connected to the signal source, and the first switch 1 connected to the other input terminal (e.g., the negative phase input terminal) of the decision submodule 31, and its corresponding signal input terminal In can be connected to the reference source.
[0071] Regardless of the feedback structure used to implement the decision feedback equalization circuit, the decision feedback equalization circuit provided by the embodiment of the present invention can include two working stages, namely, a sampling stage and a DFE calculation stage. In the sampling stage, the first switch 1 is turned on, and the target signal Vin is input to the first capacitor 2 to implement sampling of the target signal Vin; in the DFE calculation stage, the first switch 1 is turned off, and the decision feedback module 3 can perform DFE calculations based on the target signal Vin and the feedback signal VF. Specifically, in the DFE calculation stage, after the feedback submodule 32 stabilizes the feedback signal, the decision submodule 31 can perform comparison operations and output comparison results. However, since the comparison of the decision submodule 31 requires a certain holding time, the valid signal (such as the rising edge) of the control clock of the decision submodule 31 must be both after the dfe is stabilized and before the next sampling edge of the first switch 1. Its timing can be as follows Fig.12 As shown, clk represents the control clock of the first switch, and clk_s represents the control clock of the decision submodule 31. clkb represents the inverted clock of the clk clock, which has a phase difference of 180 degrees with the clk clock, so it is not in Fig.12 Based on this, in one embodiment of the present invention, the control clock clk_s of the decision submodule 31 can trigger the decision submodule 31 to work within a preset time range after the first switch 1 is switched to the off state and before it is switched to the on state again.
[0072] Furthermore, in another embodiment of the present invention, the control timing of the decision submodule 31 may be optimized. Specifically, Fig.13As shown, in one embodiment, the decision feedback module 3 may also include a second switch 33 and a second capacitor 34; one end of the second switch 33 is connected to the first capacitor 2, and the other end is connected to the second capacitor 34; one end of the second capacitor 34 is connected to the second switch 33 and the input end of the decision submodule 31, and the other end is grounded; the control clock of the first switch 1 has the same frequency as the control clock of the second switch 33 and has a phase difference of 180 degrees, and the control clock of the decision submodule 31 is the same as the control clock of the first switch 1.
[0073] In this embodiment, the control clock of the first switch 1 and the control clock of the second switch 33 have the same frequency and a phase difference of 180 degrees. When the first switch 1 is turned on, the second switch 33 is turned off, and the target signal Vin is input to the first capacitor 2 through the first switch 1. When the first switch 1 is turned off, the second switch 33 is turned on, and the target signal Vin is transmitted from the first capacitor 2 to the second capacitor 34 through the second switch 33. When the first switch 1 is turned on again, the second switch 33 is turned off, and the target signal Vin is input to the input end of the decision submodule 31 from the second capacitor 34. Since the control clock that triggers the decision submodule 31 to work is the same as the control clock of the first switch 1, the decision submodule 31 is also triggered to work at this time. In this way, there is no need to set a control clock clk_s separately for the decision submodule 31, and the decision submodule 31 and the first switch 1 can share the same clock, so the circuit structure and timing can be more optimized.
[0074] Furthermore, if Fig.14 As shown, in another embodiment of the present invention, the decision feedback module 3 may further include a voltage follower element 35; one end of the second switch 33 may be connected to the first capacitor 2 through the voltage follower element 35. The voltage follower element 35 may be, for example, a unit gain amplifier, etc., whose output voltage may be equal to the input voltage and may change with the change of the input voltage. In this way, a voltage follower element 35 is added between the first capacitor 2 and the second switch 33 as an active isolation, thereby reducing or avoiding the mutual influence between the two-stage switches and capacitors.
[0075] The decision feedback equalization circuit provided by the embodiment of the present invention is described in detail below through a specific embodiment. The decision feedback equalization circuit provided by the embodiment of the present invention can be as follows Fig.15 The circuit is divided into two working stages: sampling stage and DFE calculation stage. The equivalent circuit diagram of the sampling stage and DFE calculation stage can be shown as Fig.16 The sampling phase and the DFE calculation phase are described below.
[0076] 1. Sampling stage. In this stage, clk=1, the sampling switch is turned on, and the DFE feedback capacitor is equivalent to grounding. At this time, the expression of Vslicer is:
[0077] (1)
[0078] 2. DFE calculation stage. In this stage, clk=0, the sampling switch is disconnected, and the Vslicer voltage is equal to the superimposed voltage VA, which is determined by the input signal Vin plus the capacitor charge and then shared VF (that is, determined by the sampling result plus the result of the DFE calculation), see formula (2). Because the delay of the logic gate will cause the voltage change of nodes such as Tap2 / 3...N to be later than the disconnection of the sampling switch, there is no need to worry about the capacitor charge backfeeding back to the Vin terminal.
[0079] (2)
[0080] Where, Ctot = Cu + 2Cu + … + 2 k Cu + Cu + 2Cu + … + 2 p Cu + … + Cu + 2Cu+ … + 2 q Cu + Cdum (3)
[0081] Where p, q, and k are all non-negative integers. Dividing both ends of formula (2) by Vin can obtain the multiple relationship between Vslicer and Vin. Assuming that the ratio of the power supply voltage to the amplitude of the input signal Vin is a, and Vtap1, Vtap2, ..., VtapN are all equal to the power supply voltage, we can further obtain the ratio of the feedback signal corresponding to the feedback channel TAP1 to the input signal, that is, the feedback coefficient corresponding to TAP1 for:
[0082] (4)
[0083] Feedback coefficient corresponding to TAP2 for:
[0084] (5)
[0085] Feedback coefficient corresponding to TAPN for:
[0086] (6)
[0087] In each coefficient expression, a, the first capacitor Cin, the bridge capacitor Cc, the parasitic capacitor Cp, and the total capacitance value Ctot of the capacitor array can all be determined by design, so the DFE feedback coefficient can be adjusted by changing the values of Ctap1~CtapN. In one embodiment of the present invention, the values of Ctap1~CtapN can be set and changed by training or adaptive means.
[0088] In an embodiment of the present invention, the first capacitor Cin and the bridge capacitor Cc are both relatively small, much smaller than the total capacitance value Ctot of the capacitor array. Furthermore, since the first capacitor Cin and the bridge capacitor Cc are both relatively small, they can be compared with the parasitic capacitor Cp at the slicer input end. Therefore, considering the influence of the parasitic capacitor Cp at the slicer input end on the input signal coupling amplitude, the first capacitor Cin and the bridge capacitor Cc can be greater than the parasitic capacitor Cp at the input end. Exemplarily, the values of the first capacitor Cin and the bridge capacitor Cc can be tens of femtofarads to hundreds of femtofarads, for example, between 10 femtofarads and 500 femtofarads.
[0089] The capacitance seen from the circuit input terminal In is: the bridge capacitor Cc is connected in series with the total capacitance Ctot of the capacitor array, and then connected in parallel with the parasitic capacitance Cp and the first capacitor Cin. Since the bridge capacitor Cc is small and the total capacitance Ctot of the capacitor array is large, the total capacitance Ctot of the capacitor array can be ignored after the total capacitance Ctot of the capacitor array is connected in series with the bridge capacitor Cc, and the series capacitance is approximately equal to the bridge capacitor Cc. Therefore, the capacitance seen from the circuit input terminal In can be simplified as: the bridge capacitor Cc is connected in parallel with the parasitic capacitance Cp and the first capacitor Cin. Similarly, the equivalent capacitance seen from the DFE feedback terminal can be simplified as the first capacitor Cin is connected in parallel with the parasitic capacitance Cp and then connected in series with the bridge capacitor Cc. Since the capacitance values of the first capacitor Cin, the parasitic capacitance Cp, and the bridge capacitor Cc can all be small values, the equivalent capacitance is small whether viewed from the input terminal or the feedback terminal, so the speed and power consumption of the circuit can be effectively optimized.
[0090] Fig.17 The eye diagram effect obtained after adopting this solution is shown. The 4-tapDFE (i.e. N=4) circuit was used in the simulation trial of this solution. Fig.17 The upper part is the signal eye diagram before DFE, that is, the input signal eye diagram of the circuit of this solution. Fig.17 The lower part is the eye diagram after DFE (after 4-tap DFE), that is, the eye diagram of the slicer input node of this solution. This solution is divided into two stages: sampling and DFE calculation. In the sampling stage, the Vslicer signal is equal to the Vin signal. The sampling stage of the Vslicer eye diagram is the same as the Vin signal eye diagram. Figure 1 However, in the DFE calculation stage, Vslicer keeps adding DFE charge and then sharing it, so the Vslicer eye diagram does not change with Vin, and because DFE eliminates the ISI effect, the eye diagram becomes significantly higher (from the original 400 mV to the current 600 mV). (It should be noted that the channel ISI used in this simulation experiment cannot be completely eliminated by 4-tap DFE alone, so the Vslicer eye diagram still has a certain eyelid thickness.)
[0091] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0092] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0093] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0094] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.
[0095] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A decision feedback equalization circuit, characterized in that: include: A first switch, a first capacitor and a decision feedback module; The first switch has one end connected to the signal input end and the other end connected to the first capacitor, and is configured to be periodically turned on or off, so as to transmit the target signal input from the signal input end to the first capacitor when turned on; The first capacitor has one end connected to the first switch and the other end grounded, and is configured to receive the target signal when the first switch is turned on, or provide the target signal to the decision feedback module when the first switch is turned off; The decision feedback module, whose input end is connected to the first capacitor, is constructed to perform a decision feedback equalization operation based on the charge superposition of the target signal and the feedback signal when the first switch is disconnected, so as to obtain a decision result corresponding to the target signal, wherein the feedback signal is generated based on the decision results of the signals of the previous to the previous N clock cycles of the target signal, where N is a positive integer.
2. The circuit according to claim 1, characterized in that The decision feedback module includes: a decision submodule and a feedback submodule; The decision submodule, whose input end is respectively connected to the first capacitor and the output end of the feedback submodule, and whose output end is connected to the input end of the feedback submodule, is configured to, when the first switch is disconnected, perform charge superposition on the target signal and the feedback signal provided by the feedback submodule to obtain a superposition signal, and make a decision on the superposition signal to obtain a decision result corresponding to the target signal; The feedback submodule is constructed to determine the feedback signal according to the decision results of the signals of the previous to N previous clock cycles of the target signal made in advance by the decision submodule, and provide the feedback signal to the input end of the decision submodule.
3. The circuit according to claim 2, characterized in that The feedback submodule includes: a delay queue and a first feedback unit; The delay queue includes N delay units, each of which is serially connected to the output end of the decision submodule in sequence, wherein each of the delay units is configured to delay the decision result input to the delay unit by 1 clock cycle, and then output the delayed decision result as a decision delay result to the first feedback unit; and / or, wherein each of the delay units is configured to delay the inverted result of the decision result input to the delay unit by 1 clock cycle, and then output the inverted and delayed decision result as a decision delay result to the first feedback unit; The first feedback unit, whose output end is connected to the input end of the decision submodule, is constructed to determine a corresponding feedback sub-signal for each received decision delay result, and transmit each feedback sub-signal to the input end of the decision submodule respectively, and the feedback signal is equal to the superposition sum of each feedback sub-signal.
4. The circuit according to claim 3, characterized in that The feedback submodule further includes a bridge unit, the output end of the first feedback unit is connected to the input end of the decision submodule through the bridge unit, and the bridge unit includes a capacitive element.
5. The circuit according to claim 4, characterized in that The capacitance value of the capacitor element is between 10 femtofarads and 500 femtofarads.
6. The circuit according to claim 3, characterized in that The number of the first switch, the first capacitor and the first feedback unit are all two; the number of the decision submodule and the delay queue are all one; each delay unit in the delay queue is used to input the decision delay result corresponding to the delayed decision result into one of the first feedback units, and input the decision delay result corresponding to the inverted and delayed decision result into another first feedback unit; The decision submodule includes two input terminals, which include a positive input terminal and an inverting input terminal; the positive input terminal is connected to the output terminal of one of the first switches, a first capacitor and a first feedback unit, and the inverting input terminal is connected to the output terminal of another first switch, another first capacitor and another first feedback unit.
7. The circuit according to claim 3, characterized in that The number of the decision submodules and the number of the delay queues are both 2 M Each of the decision submodules has two input terminals, and the two input terminals include a positive input terminal and a negative input terminal; the number of the first switch, the first capacitor and the first feedback unit is 2 M+1 Each input end of each of the decision submodules is connected to one of the first switches and one of the first capacitors; Each of the first feedback units performs signal feedback between the output end of each of the delay queues and the input end of each of the decision submodules, so that the decision feedback equalization circuit achieves 1 / 2 M The sampling rate is directly fed back, where M is a non-negative integer.
8. The circuit according to claim 3, characterized in that The number of the decision submodules is 2 M+R The number of the first switches and the first capacitors are both 2 M+R+1 Each of the decision submodules has two input terminals, and the two input terminals include a positive input terminal and a negative input terminal; each input terminal of each of the decision submodules is connected to one of the first switches and one of the first capacitors; The number and connection mode of the first feedback unit and the delay queue enable the decision feedback equalization circuit to achieve 1 / 2 M The sampling rate R is a pre-judgment feedback, where M is a non-negative integer and R is a non-negative integer less than or equal to N.
9. The circuit according to any one of claims 3 to 8, characterized in that The first feedback unit includes N feedback channels formed based on a capacitor array, each of the feedback channels corresponds one-to-one to each of the feedback sub-signals; each of the feedback channels has a feedback coefficient; each of the feedback coefficients is related to the capacitance ratio of the corresponding feedback channel, and the capacitance ratio is equal to the ratio of the channel capacitance value of the feedback channel to the total capacitance value of the capacitor array.
10. The circuit according to claim 9, characterized in that The feedback submodule also includes one or more second feedback units; each of the second feedback units is used to replace one of the feedback channels, and provide a feedback sub-signal corresponding to the decision delay result to the input end of the decision submodule according to the decision delay result corresponding to the replaced feedback channel.
11. The circuit according to claim 10, characterized in that The second feedback unit is specifically used to replace one of the feedback channels, and according to the decision delay result corresponding to the replaced feedback channel, provides the first voltage or the second voltage as the feedback sub-signal corresponding to the decision delay result to the input end of the decision sub-module, wherein the first voltage is equal to the sum of a preset reference voltage and a target feedback voltage, the second voltage is equal to the difference between the preset reference voltage and the target feedback voltage, and the target feedback voltage is the product of the decision delay result corresponding to the replaced feedback channel and the feedback coefficient of the feedback channel.
12. The circuit according to any one of claims 2 to 8, characterized in that The control clock of the decision submodule triggers the decision submodule to operate within a preset time range after the first switch is switched to the off state and before it is switched to the on state again.
13. The circuit according to any one of claims 2 to 8, characterized in that The decision feedback module also includes a second switch and a second capacitor; one end of the second switch is connected to the first capacitor, and the other end is connected to the second capacitor; one end of the second capacitor is connected to the second switch and the input end of the decision submodule, and the other end is grounded; the control clock of the first switch has the same frequency as the control clock of the second switch and has a phase difference of 180 degrees, and the control clock that triggers the operation of the decision submodule is the same as the control clock of the first switch.
14. The circuit according to claim 13, characterized in that The decision feedback module further includes a voltage follower element; one end of the second switch is connected to the first capacitor through the voltage follower element.
15. The circuit according to any one of claims 1 to 8, characterized in that The decision feedback module is implemented based on at least one of the following methods: a full-rate direct feedback structure, a full-rate pre-judgment structure, a half-rate direct feedback structure, and a half-rate pre-judgment structure.