Multi-stage flow control system for cross-chip flow lossless transmission of switch

Abstract

The invention provides a multi-stage flow control system for cross-chip flow lossless transmission of a switch. Each flow control system comprises a crossbar architecture, a first unit and a second unit, the crossbar architecture is used for sending a current slice-across data frame to the first unit through a slice-across bus; the first unit is used for carrying out address table item updating on the current slice-to-slice data frame, and selecting a corresponding sending channel and a receiving rate matched with the second unit of the adjacent flow control system under the combined action of a load balancing strategy and a rate control strategy; sending the current slice cross-slice data frame to an adjacent flow control system based on an address table item updating result; the second unit is used for acquiring adjacent cross-piece data frames, and determining a destination port number according to destination MAC addresses of the adjacent cross-piece data frames under the combined action of a load balancing strategy and a rate control strategy; and the crossbar architecture is also used for carrying out data forwarding on the adjacent cross-piece data frames according to the destination port number.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication and network switching, and in particular to a multi-level flow control system for lossless transmission of cross-chip traffic of a switch. Background Art

[0002] With the rapid development of information technology, data communication has become the infrastructure of modern society. In building an efficient data transmission network, switches play a vital role. Through internal logical processing, switches can forward data packets from one port to another to achieve data exchange between different network nodes. However, with the surge in data traffic, switches face more and more challenges in handling large-scale data transmission.

[0003] In the current data communication field, with the explosive growth of network traffic, traditional single-chip FPGA switches have gradually reached a bottleneck in processing power. In order to meet this challenge, modern switch designs tend to adopt a parallel processing architecture with multiple FPGAs. This architecture achieves an exponential increase in switching capacity by integrating multiple FPGA units, effectively expanding the data processing capabilities of the switch. However, when multi-FPGA systems achieve efficient collaborative work, cross-chip traffic transmission management becomes particularly critical. It is not only related to the throughput of the entire switching system, but also directly affects the timeliness and stability of data transmission. Therefore, the development of advanced cross-chip traffic control technology has become a core technical issue to improve the performance of multi-FPGA switches.

[0004] In existing multi-FPGA switch systems, multiple FPGA channels are independent of each other, and the channels through which traffic from different ports goes to another FPGA are fixed. This may cause data congestion and packet loss under high load conditions, affecting network performance. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a multi-level flow control system for lossless transmission of cross-chip traffic of a switch.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] The present invention provides a multi-stage flow control system for lossless transmission of cross-chip traffic of a switch, wherein a plurality of flow control systems are connected in series, and each flow control system comprises: a crossbar architecture, a first unit and a second unit;

[0008] The crossbar architecture is used to send the current slice cross-slice data frame to the first unit via the cross-slice bus;

[0009] The first unit is used to update the address table entry of the current slice cross-slice data frame, and under the joint action of the load balancing strategy and the rate control strategy, select the corresponding sending channel and the receiving rate matching the second unit of the adjacent flow control system, and send the current slice cross-slice data frame to the adjacent flow control system based on the result of the address table entry update;

[0010] The second unit is used to obtain adjacent cross-slice data frames, and under the joint action of the load balancing strategy and the rate control strategy, search the address table entry according to the destination MAC address of the adjacent cross-slice data frame to determine the destination port number;

[0011] The crossbar architecture is also used to forward data for adjacent cross-slice data frames according to the destination port number.

[0012] Optionally, the first unit includes: an output arbitration module, a transmission load balancing module, a transmission unit, an LVDS address self-learning module, and an Aurora cross-chip transmission module; the output arbitration module, the transmission load balancing module, the transmission unit, and the Aurora cross-chip transmission module are connected in sequence; a first input end of the LVDS address self-learning module is connected to the output arbitration module, and a first output end of the LVDS address self-learning module is connected to the Aurora cross-chip transmission module;

[0013] The second unit includes: Aurora cross-chip receiving module, receiving unit, receiving load balancing module, input arbitration module and LVDS address self-learning module;

[0014] The Aurora cross-chip receiving module, the receiving unit, the receiving load balancing module and the input arbitration module are connected in sequence; the second input end of the LVDS address self-learning module is connected to the Aurora cross-chip receiving module, and the second output end of the LVDS address self-learning module is connected to the input arbitration module;

[0015] The input end of the output arbitration module is connected to the output end of the crossbar architecture; the output end of the input arbitration module is connected to the input end of the crossbar architecture.

[0016] Optionally, the output arbitration module is used to parse the current cross-chip data frame to obtain parsed data information, and send the parsed data information to the LVDS address self-learning module, and send the current cross-chip data frame to the transmission load balancing module;

[0017] The LVDS address self-learning module is used to update the parsed data information as an address table entry to the lookup table, obtain an updated lookup table, and send the parsed data information to the LVDS address self-learning module of the adjacent flow control system;

[0018] The sending load balancing module is used to select the corresponding sending path according to the channel congestion situation, and send the current slice cross-slice data frame to the adjacent flow control system according to the matching sending rate through the sending unit under the corresponding sending path and the Aurora cross-slice sending module. The matching sending rate is obtained according to the data congestion situation of the second unit in the adjacent flow control system;

[0019] The Aurora cross-chip receiving module is used to receive adjacent cross-chip data frames and adjacent parsed data information, send adjacent cross-chip data frames to the receiving unit, and send adjacent parsed data information to the LVDS address self-learning module of the current chip;

[0020] The receiving unit is used to convert the formats of adjacent cross-slice data frames to obtain converted data frames, and send the converted data frames to the receiving load balancing module;

[0021] The receiving load balancing module is used to cache the converted data frames and determine whether to send the converted data frames to the input arbitration module through the back pressure signal of the crossbar architecture;

[0022] When the converted data frame is sent to the input arbitration module, the input arbitration module is used to parse the destination MAC address of the converted data frame and search and update the lookup table to determine the destination port number.

[0023] Optionally, the sending load balancing module includes: an output channel selection module, a plurality of sending buffer modules and an NFC flow control module connected in sequence;

[0024] The output channel selection module is used to store the current slice cross-slice data frame into the destination sending buffer module with the lowest congestion level among the multiple sending buffer modules according to the congestion status of the sending buffer module;

[0025] The destination sending buffer module is used to obtain a token from the NFC flow control module, and based on the token and the sending unit and Aurora cross-chip sending module under the corresponding sending path, sends the current cross-chip data frame to the adjacent flow control system at the matching sending rate.

[0026] Optionally, the NFC flow control module further includes: an NFC token bucket unit and an NFC flow control unit;

[0027] The input end of the NFC token bucket unit is connected to the output ends of the multiple sending buffer modules; the output end of the NFC token bucket unit is connected to the input end of the NFC flow control unit;

[0028] The output end of the NFC flow control unit is connected to the input end of the sending unit;

[0029] The NFC flow control unit is used to monitor the load waterline of the receiving load balancing module in the adjacent flow control system, and control the token generation rate of the NFC token bucket unit according to the load waterline;

[0030] The NFC token bucket unit is used to generate tokens according to the token generation rate, and use the tokens to control the flow rate of the sending buffer module.

[0031] Optionally, the LVDS address self-learning module includes: a lookup table module, a hash module, a learning table module and an LVDS cross-chip transmission module;

[0032] The output end of the hash module is connected to the input end of the lookup table module and the learning table module; the input end of the hash module is connected to the output arbitration module;

[0033] The input end of the learning table module is connected to the Aurora cross-chip receiving module, and the output end of the learning table module is connected to the input end of the lookup table module and the LVDS cross-chip transmission module;

[0034] The output end of the lookup table module is connected to the input arbitration module; the LVDS cross-chip transmission module is connected to the Aurora cross-chip transmission module.

[0035] Optionally, the hash module is used to convert the parsed data information into converted data information that meets the query format of the lookup table module and the learning table module; wherein the data table items inside the lookup table module and the learning table module are synchronized in real time;

[0036] The table lookup module is used to perform table lookup processing using the converted data information to obtain the destination port number;

[0037] The learning table module is used to learn the address table items of the current slice and the adjacent slice, update the learning results of the address table items to the lookup table module, and transmit the data table items of the current slice to the learning table module of the adjacent flow control system using the LVDS cross-chip transmission module; wherein the current slice is the current flow control system, and the adjacent slice is the adjacent flow control system;

[0038] The LVDS cross-chip transmission module is used to convert the data table items of the current chip into the format required by the Aurora cross-chip sending module, and send it to the LVDS address self-learning module of the adjacent flow control system based on the Aurora cross-chip sending module.

[0039] Optionally, the sending unit is provided with a plurality of sub-sending units; the Aurora cross-chip sending module is provided with a plurality of sub-Aurora cross-chip sending modules; the sub-sending units are connected to the sub-Aurora cross-chip sending modules in a one-to-one correspondence, and one sub-sending unit and one sub-Aurora cross-chip sending module constitute a sending path;

[0040] The sub-sending unit is used to convert the current slice cross-slice data frame into a data format that satisfies the sub-Aurora cross-slice sending module, and obtain the current slice cross-slice converted data frame;

[0041] The sub-Aurora cross-chip sending module is used to send the current slice cross-chip conversion data frame to the Aurora cross-chip receiving module of the adjacent flow control system.

[0042] The present invention provides a multi-level flow control system for lossless transmission of cross-chip traffic of a switch, wherein a plurality of flow control systems are connected in series, and each flow control system comprises: a crossbar architecture, a first unit and a second unit; the crossbar architecture is used to send a current-chip cross-chip data frame to the first unit via a cross-chip bus; the first unit is used to update the address table entry of the current-chip cross-chip data frame, and under the joint action of a load balancing strategy and a rate control strategy, select a corresponding sending channel and a receiving rate matching the second unit of an adjacent flow control system, and send the current-chip cross-chip data frame to the adjacent flow control system based on the result of the address table entry update; the second unit is used to obtain adjacent cross-chip data frames, and under the joint action of a load balancing strategy and a rate control strategy, search the address table entry according to the destination MAC address of the adjacent cross-chip data frame to determine the destination port number; the crossbar architecture is also used to forward data for the adjacent cross-chip data frame according to the destination port number. In the present invention, since the first unit dynamically determines the corresponding sending rate according to the receiving rate of the second unit, and uses different sending channels to send data under the action of the load balancing strategy, dynamic traffic adjustment and distribution is achieved, and the distribution efficiency of cross-chip channel loads is improved. Since the traffic distribution in the embodiment of the present invention is dynamically executed, the probability of data congestion and packet loss problems is greatly reduced, and the network performance is improved.

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of a multi-stage flow control system for lossless transmission of cross-chip traffic of a switch provided by an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of the structure of a transmission load balancing module provided in an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of a selection process of an output channel selection module provided in an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of a process of performing flow control according to a second unit of an adjacent flow control system provided in an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of the structure of an LVDS address self-learning module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0050] In order to reduce the probability of data congestion and packet loss problems and improve network performance, an embodiment of the present invention provides a multi-level flow control system for lossless transmission of cross-chip traffic of a switch. Figure 1 A schematic diagram of the structure of a multi-level flow control system for lossless transmission of cross-chip traffic of a switch provided by an embodiment of the present invention. Figure 1 As shown, a plurality of flow control systems are connected in series, and each flow control system includes: a crossbar architecture, a first unit, and a second unit;

[0051] The crossbar architecture is used to send the current slice cross-slice data frame to the first unit via the cross-slice bus;

[0052] The first unit is used to update the address table entry of the current slice cross-slice data frame, and under the joint action of the load balancing strategy and the rate control strategy, select the corresponding sending channel and the receiving rate matching the second unit of the adjacent flow control system, and send the current slice cross-slice data frame to the adjacent flow control system based on the result of the address table entry update;

[0053] The second unit is used to obtain adjacent cross-slice data frames, and under the joint action of the load balancing strategy and the rate control strategy, search the address table entry according to the destination MAC address of the adjacent cross-slice data frame to determine the destination port number;

[0054] The crossbar architecture is also used to forward data for adjacent cross-slice data frames according to the destination port number.

[0055] It should be noted that, in the embodiment of the present invention, the current slice is specifically the current flow control system, and the adjacent slice is specifically the adjacent flow control system.

[0056] An embodiment of the present invention provides a multi-level flow control system for lossless transmission of cross-chip traffic of a switch. Since the first unit dynamically determines the corresponding sending rate according to the receiving rate of the second unit, and uses different sending channels to send data under the action of the load balancing strategy, dynamic flow adjustment and distribution is achieved, and the distribution efficiency of the cross-chip channel load is improved. Since the flow distribution in the embodiment of the present invention is dynamically executed, the probability of data congestion and packet loss problems is greatly reduced, and the network performance is improved.

[0057] Optionally, the first unit includes: an output arbitration module, a transmission load balancing module, a transmission unit, an LVDS address self-learning module, and an Aurora cross-chip transmission module; the output arbitration module, the transmission load balancing module, the transmission unit, and the Aurora cross-chip transmission module are connected in sequence; a first input end of the LVDS address self-learning module is connected to the output arbitration module, and a first output end of the LVDS address self-learning module is connected to the Aurora cross-chip transmission module;

[0058] The second unit includes: Aurora cross-chip receiving module, receiving unit, receiving load balancing module, input arbitration module and LVDS address self-learning module;

[0059] The Aurora cross-chip receiving module, the receiving unit, the receiving load balancing module and the input arbitration module are connected in sequence; the second input end of the LVDS address self-learning module is connected to the Aurora cross-chip receiving module, and the second output end of the LVDS address self-learning module is connected to the input arbitration module;

[0060] The input end of the output arbitration module is connected to the output end of the crossbar architecture; the output end of the input arbitration module is connected to the input end of the crossbar architecture.

[0061] It should be noted that the output arbitration module has the same structure as the input arbitration module, the sending load balancing module has the same structure as the receiving load balancing module, the sending unit has the same structure as the receiving unit, and the Aurora cross-chip sending module has the same structure as the Aurora cross-chip receiving module. Since the structures of the above corresponding modules are the same, only the processed data is different, in the subsequent embodiments, the sending path formed by the first unit is taken as an example to describe the data transmission process.

[0062] Optionally, the output arbitration module is used to parse the current cross-chip data frame to obtain parsed data information, and send the parsed data information to the LVDS address self-learning module, and send the current cross-chip data frame to the transmission load balancing module;

[0063] The LVDS address self-learning module is used to update the parsed data information as an address table entry to the lookup table, obtain an updated lookup table, and send the parsed data information to the LVDS address self-learning module of the adjacent flow control system;

[0064] The sending load balancing module is used to select the corresponding sending path according to the channel congestion situation, and send the current slice cross-slice data frame to the adjacent flow control system according to the matching sending rate through the sending unit under the corresponding sending path and the Aurora cross-slice sending module. The matching sending rate is obtained according to the data congestion situation of the second unit in the adjacent flow control system;

[0065] The Aurora cross-chip receiving module is used to receive adjacent cross-chip data frames and adjacent parsed data information, send adjacent cross-chip data frames to the receiving unit, and send adjacent parsed data information to the LVDS address self-learning module of the current chip;

[0066] The receiving unit is used to convert the formats of adjacent cross-slice data frames to obtain converted data frames, and send the converted data frames to the receiving load balancing module;

[0067] The receiving load balancing module is used to cache the converted data frames and determine whether to send the converted data frames to the input arbitration module through the back pressure signal of the crossbar architecture;

[0068] When the converted data frame is sent to the input arbitration module, the input arbitration module is used to parse the destination MAC address of the converted data frame and search and update the lookup table to determine the destination port number.

[0069] Optionally, the sending load balancing module includes: an output channel selection module, a plurality of sending buffer modules and an NFC flow control module connected in sequence;

[0070] The output channel selection module is used to store the current slice cross-slice data frame into the destination sending buffer module with the lowest congestion level among the multiple sending buffer modules according to the congestion status of the sending buffer module;

[0071] The destination sending buffer module is used to obtain a token from the NFC flow control module, and based on the token and the sending unit and Aurora cross-chip sending module under the corresponding sending path, sends the current cross-chip data frame to the adjacent flow control system at the matching sending rate.

[0072] It should be noted that multiple sending buffer modules are connected in series. For the convenience of description, two sending buffer modules are used as an example in the embodiment of the present invention. The two sending buffer modules are: bus 1 sending buffer module (bus 1) and bus 2 sending buffer module (bus 2). Correspondingly, Figure 2 A structural diagram of a sending load balancing module provided in an embodiment of the present invention. Figure 3 A schematic diagram of the selection process of the output channel selection module provided in an embodiment of the present invention.

[0073] like Figure 3 As shown, the selection process of multiple sending buffer modules for the current slice cross-slice data frame to enter and exit the queue (enter the queue: the data frame enters the buffer module, exit the queue: the data frame comes out of the buffer module). Before the current slice cross-slice data frame selects the corresponding sending buffer module, it is first determined whether the data frame of the port corresponding to the current slice cross-slice data frame has been cached in the multiple sending buffer modules.

[0074] Case 1: If a send buffer module has already cached the data frame of this port, then determine whether the send buffer module has reached the highest watermark (no data can be stored if the highest watermark is reached). If the highest watermark has been reached, then back pressure is applied to the crossbar switching architecture (upper module) to prevent the crossbar switching architecture from outputting new data frames. If the highest watermark has not been reached, then the send buffer module is used as the destination send buffer module, and the current cross-slice data frame is queued to the destination send buffer module. The dequeueing of the data frame in the destination send buffer module requires determining whether there is a token in the token bucket. If there is a token, then after taking out a token, the data frame in the destination send buffer module is dequeued.

[0075] It can be understood that the step setting of the above situation 1 can prevent the data frames from being out of order.

[0076] Case 2: If multiple sending buffer modules do not cache the data frame of the port corresponding to the current cross-slice data frame, it is determined whether the multiple sending buffer modules have reached the highest watermark. If so, the crossbar switching architecture is back-pressured to prevent the crossbar switching architecture from outputting new data frames. If not, the current cross-slice data frame is queued to the sending buffer module with the lowest watermark, and the dequeuing process of the sending buffer module is the same as case 1.

[0077] like Figure 2 As shown, the output channel selection module compares the watermark conditions of the sending cache modules of bus 1 and bus 2, and preferentially selects the channel with the low watermark for data frame cross-slice transmission. At the same time, in order to prevent the disorder of the current slice cross-slice data frame due to load balancing, this module will first determine whether the two cache channels have cached the same MAC as the current slice cross-slice data frame before selecting the channel. If so, the channel with the same source MAC data frame will be selected regardless of the congestion situation. If the same MAC as the current slice cross-slice data frame is not cached, the channel with the lowest congestion, that is, the channel with the lowest watermark, will be selected for cross-slice transmission.

[0078] The sending buffer module uses the FIFO (First In First Out) principle to buffer the current slice cross-slice data frame. In this embodiment, the data bit width set by the FIFO can be 384 bits, the depth can be 1024 depths, the waterline can be set to five levels, and the FIFO depths corresponding to the five-level waterline are: 400 for the first level, 700 for the second level, 800 for the third level, 900 for the fourth level, and 950 for the fifth level, and at least one depth of the longest Ethernet frame is reserved.

[0079] Optionally, the NFC flow control module further includes: an NFC token bucket unit and an NFC flow control unit;

[0080] The input end of the NFC token bucket unit is connected to the output ends of the multiple sending buffer modules; the output end of the NFC token bucket unit is connected to the input end of the NFC flow control unit;

[0081] The output end of the NFC flow control unit is connected to the input end of the sending unit;

[0082] The NFC flow control unit is used to monitor the load waterline of the receiving load balancing module in the adjacent flow control system, and control the token generation rate of the NFC token bucket unit according to the load waterline;

[0083] The NFC token bucket unit is used to generate tokens according to the token generation rate, and use the tokens to control the flow rate of the sending buffer module.

[0084] The NFC traffic control unit is specifically used to receive the load waterline of the load balancing module and adjust the generation speed of tokens in the NFC token bucket unit according to the load waterline to achieve the purpose of traffic speed limiting or shutting down.

[0085] It should be noted that in the embodiment of the present invention, the current slice cross-slice data frame needs to pass through the NFC flow control module before it crosses the slice, and each frame needs to take a token from the NFC token bucket unit. When the token in the NFC token bucket unit is consumed, the current slice cross-slice data frame cannot pass and is temporarily stored in the sending cache module, so as to achieve the purpose of flow rate limiting. The generation speed of the token in the NFC token bucket unit is the highest to meet the transmission of 25Gb / s data frames. According to the 5-level waterline of the receiving cache module of the second unit, the first unit can divide the flow into 25Gb / s, 20Gb / s, 10Gb / s, 5Gb / s and 0Gb / s.

[0086] It can be understood that the above settings can avoid data congestion at the sending end, greatly avoiding the occurrence of data packet loss problems.

[0087] Further, Figure 4 A schematic diagram of a process of flow control according to a second unit of an adjacent flow control system provided by an embodiment of the present invention. Specifically, the NFC flow control unit of the current flow control system monitors the load waterline ( Figure 4 The 5-level waterline is used as an example), and the token generation rate of the NFC token bucket unit is controlled according to the load waterline to obtain an NFC flow control frame (NFC frame); the NFC token bucket unit generates tokens according to the NFC flow control frame, and uses the tokens to control the data frame sending port to send data at the corresponding flow rate.

[0088] Figure 5 Schematic diagram of the structure of the LVDS address self-learning module provided by the embodiment of the present invention. Figure 5As shown, the LVDS address self-learning module includes: a lookup table module, a hash module, a learning table module and an LVDS cross-chip transmission module;

[0089] The output end of the hash module is connected to the input end of the lookup table module and the learning table module; the input end of the hash module is connected to the output arbitration module;

[0090] The input end of the learning table module is connected to the Aurora cross-chip receiving module, and the output end of the learning table module is connected to the input end of the lookup table module and the LVDS cross-chip transmission module;

[0091] The output end of the lookup table module is connected to the input arbitration module; the LVDS cross-chip transmission module is connected to the Aurora cross-chip transmission module.

[0092] It should be noted that, in the embodiment of the present invention, the Aurora cross-chip receiving module is used to convert the data frame from the axi format to the local link format, and the Aurora cross-chip sending module is used to convert the data frame from the local link format to the axi format.

[0093] Optionally, the hash module is used to convert the parsed data information into converted data information that meets the query format of the lookup table module and the learning table module; wherein the data table items inside the lookup table module and the learning table module are synchronized in real time;

[0094] The table lookup module is used to perform table lookup processing using the converted data information to obtain the destination port number;

[0095] The learning table module is used to learn the address table items of the current slice and the adjacent slice, update the learning results of the address table items to the lookup table module, and transmit the data table items of the current slice to the learning table module of the adjacent flow control system using the LVDS cross-chip transmission module; wherein the current slice is the current flow control system, and the adjacent slice is the adjacent flow control system;

[0096] The LVDS cross-chip transmission module is used to convert the data table items of the current chip into the format required by the Aurora cross-chip sending module, and send it to the LVDS address self-learning module of the adjacent flow control system based on the Aurora cross-chip sending module.

[0097] In addition, the hash module is also used to compress the 48-bit MAC address hash into 10 bits to save space in the lookup table module.

[0098] For the learning table module, when each new data frame enters the switch, the learning table module will parse its source MAC address and establish a new address table entry with its port number as the corresponding relationship. The learning table module compares the newly learned address table entry with the already learned address table entry. If it has not been learned, a new entry will be established in the address table. If it has been learned, the duplicate entry will be discarded.

[0099] For the lookup table module, every time a new data frame enters the switch, its destination MAC address will be parsed, and the corresponding MAC address table entry and port number will be searched in the address table to obtain the destination port number.

[0100] Optionally, the sending unit is provided with a plurality of sub-sending units; the Aurora cross-chip sending module is provided with a plurality of sub-Aurora cross-chip sending modules; the sub-sending units are connected to the sub-Aurora cross-chip sending modules in a one-to-one correspondence, and one sub-sending unit and one sub-Aurora cross-chip sending module constitute a sending path;

[0101] The sub-sending unit is used to convert the current slice cross-slice data frame into a data format that satisfies the sub-Aurora cross-slice sending module, and obtain the current slice cross-slice converted data frame;

[0102] The sub-Aurora cross-chip sending module is used to send the current slice cross-chip conversion data frame to the Aurora cross-chip receiving module of the adjacent flow control system.

[0103] In summary, the present invention provides a multi-level flow control system for lossless transmission of cross-chip traffic of switches. Through the sending load balancing unit, the system can monitor the congestion status of the cross-chip channel in real time, and dynamically adjust the traffic distribution, giving priority to channels with lower congestion for data transmission, thereby improving the distribution efficiency of the cross-chip channel load. In addition, the built-in GTY high-speed interface in the Aurora cross-chip sending module can achieve a data transmission rate of up to 100Gb / s, meeting the high bandwidth requirements of modern networks. The NFC flow control unit in the sending load balancing unit sends a control signal in time to adjust the sending port state according to the congestion status of the receiving channel, effectively preventing the loss of data frames caused by insufficient processing power of the receiving end, and ensuring the integrity of data transmission. The LVDS address self-learning cross-chip unit learns the correspondence between the switch input port and the MAC address, and transmits it to another flow control system using the LVDS interface, thereby realizing cross-chip synchronization of address table entries and ensuring that data frames can be looked up and forwarded according to the correct address information.

[0104] The system design of the present invention solves the problem of disordered data frame transmission caused by load balancing, ensures the order of data frames, and improves the reliability of data transmission. Through hierarchical token bucket management, the system can flexibly adjust the flow control strategy according to different flow requirements and network conditions, and realizes more sophisticated flow management. Through the collaborative working mechanism of the multi-level flow control system, the stability and reliability of the switch in the face of complex network environments and high load conditions are improved.

[0105] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0106] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes of the above disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0107] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A multi-level flow control system for lossless transmission of cross-chip traffic of a switch, characterized in that: A plurality of flow control systems are connected in series, each of the flow control systems comprising: a crossbar architecture, a first unit and a second unit; The crossbar architecture is used to send the current slice cross-chip data frame to the first unit through the cross-chip bus; The first unit is used to update the address table entry of the current slice cross-slice data frame, and under the joint action of the load balancing strategy and the rate control strategy, select a corresponding sending channel and a receiving rate matching the second unit of the adjacent flow control system, and send the current slice cross-slice data frame to the adjacent flow control system based on the result of the address table entry update; The second unit is used to obtain adjacent cross-slice data frames, and under the joint action of the load balancing strategy and the rate control strategy, search the address table entry according to the destination MAC address of the adjacent cross-slice data frame to determine the destination port number; The crossbar architecture is also used to forward data for the adjacent cross-slice data frames according to the destination port number.

2. The multi-stage flow control system for lossless transmission of cross-chip traffic of a switch according to claim 1, characterized in that: The first unit includes: an output arbitration module, a transmission load balancing module, a transmission unit, an LVDS address self-learning module and an Aurora cross-chip transmission module; the output arbitration module, the transmission load balancing module, the transmission unit and the Aurora cross-chip transmission module are connected in sequence; the first input end of the LVDS address self-learning module is connected to the output arbitration module, and the first output end of the LVDS address self-learning module is connected to the Aurora cross-chip transmission module; The second unit includes: an Aurora cross-chip receiving module, a receiving unit, a receiving load balancing module, an input arbitration module, and an LVDS address self-learning module; The Aurora cross-chip receiving module, the receiving unit, the receiving load balancing module and the input arbitration module are connected in sequence; the second input end of the LVDS address self-learning module is connected to the Aurora cross-chip receiving module, and the second output end of the LVDS address self-learning module is connected to the input arbitration module; The input end of the output arbitration module is connected to the output end of the crossbar architecture; the output end of the input arbitration module is connected to the input end of the crossbar architecture.

3. The multi-stage flow control system for lossless transmission of cross-chip traffic of a switch according to claim 2, characterized in that: The output arbitration module is used to parse the current cross-chip data frame to obtain parsed data information, and send the parsed data information to the LVDS address self-learning module, and send the current cross-chip data frame to the transmission load balancing module; The LVDS address self-learning module is used to update the parsed data information as an address table entry to a lookup table to obtain an updated lookup table, and send the parsed data information to the LVDS address self-learning module of an adjacent flow control system; The sending load balancing module is used to select a corresponding sending path according to the channel congestion situation, and send the current slice cross-slice data frame to the adjacent flow control system according to the matching sending rate through the sending unit under the corresponding sending path and the Aurora cross-slice sending module, wherein the matching sending rate is obtained according to the data congestion situation of the second unit in the adjacent flow control system; The Aurora cross-chip receiving module is used to receive adjacent cross-chip data frames and adjacent parsed data information, send the adjacent cross-chip data frames to the receiving unit, and send the adjacent parsed data information to the LVDS address self-learning module of the current chip; The receiving unit is used for performing format conversion on the adjacent cross-slice data frames to obtain converted data frames, and sending the converted data frames to the receiving load balancing module; The receiving load balancing module is used to cache the converted data frame and determine whether to send the converted data frame to the input arbitration module through the back pressure signal of the crossbar architecture; When the converted data frame is sent to the input arbitration module, the input arbitration module is used to parse the destination MAC address of the converted data frame and search the updated lookup table to determine the destination port number.

4. The multi-stage flow control system for lossless transmission of cross-chip traffic of a switch according to claim 3, characterized in that: The transmission load balancing module includes: an output channel selection module, a plurality of transmission buffer modules and an NFC flow control module connected in sequence; The output channel selection module is used for storing the current slice inter-slice data frame into the destination sending buffer module with the lowest congestion among the multiple sending buffer modules according to the congestion condition of the sending buffer module; The destination sending buffer module is used to obtain a token from the NFC flow control module, and based on the token and the sending unit and the Aurora cross-chip sending module under the corresponding sending path, send the current slice cross-chip data frame to the adjacent flow control system at a matched sending rate.

5. The multi-stage flow control system for lossless transmission of cross-chip traffic of a switch according to claim 4, characterized in that: The NFC flow control module also includes: an NFC token bucket unit and an NFC flow control unit; The input end of the NFC token bucket unit is connected to the output end of the multiple sending buffer modules; the output end of the NFC token bucket unit is connected to the input end of the NFC flow control unit; The output end of the NFC flow control unit is connected to the input end of the sending unit; The NFC flow control unit is used to monitor the load waterline of the receiving load balancing module in the adjacent flow control system, and control the token generation rate of the NFC token bucket unit according to the load waterline; The NFC token bucket unit is used to generate tokens according to the token generation rate, and use the tokens to control the flow rate of the sending buffer module.

6. The multi-stage flow control system for lossless transmission of cross-chip traffic of a switch according to claim 3, characterized in that: The LVDS address self-learning module includes: a lookup table module, a hash module, a learning table module and an LVDS cross-chip transmission module; The output end of the hash module is connected to the input end of the lookup table module and the learning table module; the input end of the hash module is connected to the output arbitration module; The input end of the learning table module is connected to the Aurora cross-chip receiving module, and the output end of the learning table module is connected to the input end of the lookup table module and the LVDS cross-chip transmission module; The output end of the lookup table module is connected to the input arbitration module; the LVDS cross-chip transmission module is connected to the Aurora cross-chip sending module.

7. The multi-stage flow control system for lossless transmission of cross-chip traffic of a switch according to claim 6, characterized in that: The hash module is used to convert the parsed data information into converted data information that meets the query format of the lookup table module and the learning table module; wherein the internal data table items of the lookup table module and the learning table module are synchronized in real time; The table lookup module is used to perform table lookup processing using the converted data information to obtain the destination port number; The learning table module is used to learn the address table items of the current slice and the adjacent slice, update the learning results of the address table items to the lookup table module, and transmit the data table items of the current slice to the learning table module of the adjacent flow control system using the LVDS cross-chip transmission module; wherein the current slice is the current flow control system, and the adjacent slice is the adjacent flow control system; The LVDS cross-chip transmission module is used to convert the data table items of the current chip into a format that meets the requirements of the Aurora cross-chip sending module, and send the data to the adjacent flow control system based on the LVDS address self-learning module of the Aurora cross-chip sending module.

8. The multi-stage flow control system for lossless transmission of cross-chip traffic of a switch according to claim 2, characterized in that: The sending unit is provided with a plurality of sub-sending units; the Aurora cross-chip sending module is provided with a plurality of sub-Aurora cross-chip sending modules; the sub-sending units are connected to the sub-Aurora cross-chip sending modules in a one-to-one correspondence, and one sub-sending unit and one sub-Aurora cross-chip sending module constitute a sending path; The sub-slice sending unit is used to convert the current slice cross-slice data frame into a data format that meets the data format of the sub-Aurora cross-slice sending module to obtain a current slice cross-slice converted data frame; The sub-Aurora cross-slice sending module is used to send the current slice cross-slice conversion data frame to the Aurora cross-slice receiving module of the adjacent flow control system.

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