Semiconductor structure and preparation method thereof
By using an isolation structure and contact plug with a combination of conductive columns and insulating layers in the semiconductor structure, the complexity and bridging problems of metal layer wiring in DRAM are solved, electrical isolation and process simplification are achieved, and process reliability and efficiency are improved.
Patent Information
- Application Number
- CN202310763715.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-25
- Publication Date
- 2025-01-03
AI Technical Summary
In advanced dynamic random access memory (DRAM) processes, as the bit line/word line (BL/WL) size shrinks, the layout of metal layer wiring becomes complicated, resulting in increased process difficulty and bridge problems between metal layers. The prior art is difficult to effectively solve.
Using a semiconductor structure, including a substrate, a first conductive layer, an isolation structure and a contact plug, the process is simplified and crosstalk is avoided, and the combination of conductive columns and insulating layers is achieved. Electrical isolation of the first sub-conductive structure and the second sub-conductive structure.
While simplifying the process and reducing costs, crosstalk between metal layers is effectively avoided and process reliability and efficiency are improved.
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Figure CN119255594A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] In the evolution of advanced dynamic random access memory (DRAM) technology, as the size of bit lines / word lines (BL / WL) decreases, the size of the core area where the metal layer is located continues to shrink. Unlike the repeated layout of wiring and space (Line / space) in the array area, the wiring layout of the metal layer in the core area is relatively complex. The smaller and smaller size leads to increased process difficulty and easily brings about bridging problems between metal layers. Summary of the invention
[0003] In view of this, an embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same.
[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, including:
[0005] substrate;
[0006] A first conductive layer, located on the substrate, includes a first sub-conductive structure, a second sub-conductive structure, and a second conductive structure that are spaced apart from each other;
[0007] a second conductive layer, located on the first conductive layer;
[0008] an isolation structure, located between the first sub-conductive structure and the second sub-conductive structure and connected to the second conductive layer, and used for electrically isolating the first sub-conductive structure from the second sub-conductive structure;
[0009] A contact plug is located between the second conductive structure and the second conductive layer, and is used to electrically connect the second conductive structure and the second conductive layer.
[0010] In some embodiments, the top surface of the isolation structure is flush with the top surface of the contact plug, the bottom surface of the isolation structure is lower than the bottom surface of the contact plug, and the bottom surface of the isolation structure is not higher than the bottom surface of the first conductive layer.
[0011] In some embodiments, the isolation structure and the contact plug each include a conductive pillar and an insulating layer disposed around a sidewall of the conductive pillar.
[0012] In some embodiments, the semiconductor structure further comprises:
[0013] A first dielectric layer, located on the substrate, comprising a first sub-dielectric layer and a second sub-dielectric layer; wherein the first sub-dielectric layer is located on the side wall and below the first conductive layer, and the second sub-dielectric layer covers the first conductive layer and the first sub-dielectric layer;
[0014] The second dielectric layer is located on the first dielectric layer.
[0015] In some embodiments, the sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is greater than or equal to a preset value;
[0016] The isolation structure penetrates the second dielectric layer and the second sub-dielectric layer and extends into the first sub-dielectric layer;
[0017] The contact plug penetrates the second dielectric layer and the second sub-dielectric layer and contacts the second conductive structure.
[0018] In some embodiments, the sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is less than a preset value;
[0019] The semiconductor structure further includes: a third dielectric layer located on the second dielectric layer;
[0020] The isolation structure penetrates the third dielectric layer, the second dielectric layer and the second sub-dielectric layer and extends into the first sub-dielectric layer;
[0021] The contact plug penetrates the third dielectric layer, the second dielectric layer, and the second sub-dielectric layer and contacts the second conductive structure.
[0022] In some embodiments, the first dielectric layer and the second dielectric layer are made of different materials; and the second dielectric layer and the third dielectric layer are made of different materials.
[0023] In some embodiments, a size of the isolation structure in the first horizontal direction is larger than a size of the contact plug in the first horizontal direction, a size of the isolation structure in the second horizontal direction is larger than or equal to a size of the first sub-conductive structure and the second sub-conductive structure in the second horizontal direction, the first horizontal direction is an arrangement direction of the first sub-conductive structure and the second sub-conductive structure, and the second horizontal direction is an extension direction of the first sub-conductive structure and the second sub-conductive structure.
[0024] In some embodiments, the substrate includes an active region and a gate structure located on the active region, and the active region includes a first source and drain region and a second source and drain region located on opposite sides of the gate structure;
[0025] The semiconductor structure further includes: a first connecting pillar and a second connecting pillar, wherein the first connecting pillar electrically connects the first sub-conductive structure and the first source and drain region, and the second connecting pillar electrically connects the second sub-conductive structure and the second source and drain region.
[0026] According to a second aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising:
[0027] providing a substrate;
[0028] forming an initial first conductive layer on the substrate, wherein the initial first conductive layer comprises a first conductive structure and a second conductive structure which are spaced apart from each other;
[0029] forming a first trench and a second trench in the same step, wherein the first trench penetrates the first conductive structure to divide the first conductive structure into a first sub-conductive structure and a second sub-conductive structure, and the second trench is located above the second conductive structure and exposes a portion of the surface of the second conductive structure; the first sub-conductive structure, the second sub-conductive structure and the second conductive structure form a first conductive layer;
[0030] forming an isolation structure in the first trench;
[0031] forming a contact plug in the second trench;
[0032] A second conductive layer is formed on the isolation structure and the contact plug.
[0033] In some embodiments, the method further comprises:
[0034] Before forming the initial first conductive layer, forming a first sub-dielectric layer on the substrate, wherein the first sub-dielectric layer is located on the sidewall and below the initial first conductive layer;
[0035] forming a second sub-dielectric layer covering the initial first conductive layer and the first sub-dielectric layer, wherein the first sub-dielectric layer and the second sub-dielectric layer form a first dielectric layer;
[0036] A second dielectric layer is formed on the first dielectric layer.
[0037] In some embodiments, the sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is greater than or equal to a preset value;
[0038] The forming of the first trench and the second trench in the same step comprises:
[0039] Performing a first etching process, wherein the first trench penetrates the second dielectric layer and stops at the surface of the first dielectric layer, the second trench stops in the second dielectric layer, and the size of the first trench in the first horizontal direction is larger than the size of the second trench in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure and the second sub-conductive structure;
[0040] Performing a second etching process, wherein the first trench penetrates the second sub-dielectric layer and stops at the surface of the first conductive structure, the second trench stops in the second dielectric layer, and the etching selectivity ratios of the first dielectric layer and the second dielectric layer are different;
[0041] A third etching process is performed, the first trench penetrates the first conductive structure, and the second trench exposes a portion of the surface of the second conductive structure.
[0042] In some embodiments, the sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is less than a preset value;
[0043] The method further includes: forming a third dielectric layer on the second dielectric layer;
[0044] The forming of the first trench and the second trench in the same step comprises:
[0045] Performing a fourth etching process, wherein the first trench penetrates the third dielectric layer and stops at the surface of the second dielectric layer, the second trench stops in the third dielectric layer, and the size of the first trench in the first horizontal direction is larger than the size of the second trench in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure and the second sub-conductive structure;
[0046] Performing a fifth etching process, wherein the first trench penetrates the second dielectric layer and the second sub-dielectric layer and stops at the surface of the first conductive structure, the second trench penetrates the third dielectric layer and stops in the second dielectric layer, and the etching selectivity ratios of the second dielectric layer and the third dielectric layer are different;
[0047] A sixth etching process is performed, the first trench penetrates the first conductive structure, and the second trench exposes a portion of the surface of the second conductive structure.
[0048] In some embodiments, forming an isolation structure in the first trench and forming a contact plug in the second trench includes:
[0049] forming an insulating layer on sidewalls of the first trench and the second trench;
[0050] A conductive material is filled in the first trench and the second trench where the insulating layer is formed, so as to form an isolation structure in the first trench and a contact plug in the second trench.
[0051] In some embodiments, the substrate includes an active region and a gate structure located on the active region, and the active region includes a first source and drain region and a second source and drain region located on opposite sides of the gate structure;
[0052] Forming an initial first conductive layer on the substrate, comprising:
[0053] A first connecting pillar and a second connecting pillar and an initial first conductive layer located on the first connecting pillar and the second connecting pillar are formed, wherein the first connecting pillar contacts the first source and drain region, and the second connecting pillar contacts the second source and drain region.
[0054] In the disclosed embodiment, an isolation structure, a contact plug, and a first conductive layer can be formed in the same process, which simplifies the process and saves costs; at the same time, the isolation structure electrically isolates the first sub-conductive structure from the second sub-conductive structure to avoid crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS
[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0056] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;
[0057] Figure 2 A top view of a semiconductor structure provided by an embodiment of the present disclosure;
[0058] Figure 3 A schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure;
[0059] Figure 4 A flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;
[0060] Figures 5a to 7f A schematic diagram of the structure of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure.
[0061] Description of reference numerals:
[0062] Substrate, 10; active region, 11; first source and drain region, 111; second source and drain region, 112; gate structure, 12; gate insulating layer, 121; first gate conductive layer, 122; second gate conductive layer, 123; third gate conductive layer, 124; cap layer, 125; gate spacer layer, 13;
[0063] first conductive layer, 20; first conductive structure, 21; first sub-conductive structure, 211; second sub-conductive structure, 212; second conductive structure, 22; initial first conductive layer pre-layer, 200'; initial first conductive layer, 200;
[0064] second conductive layer, 30; initial second conductive layer, 300;
[0065] Isolation structure, 41; contact plug, 42; conductive pillar, 401; insulating layer, 402;
[0066] The first dielectric layer, 51; the first sub-dielectric layer, 511; the second sub-dielectric layer, 512; the second dielectric layer, 52; the third dielectric layer, 53;
[0067] A first connecting post, 61; a second connecting post, 62;
[0068] first groove, 71; second groove, 72;
[0069] A first isolation layer, 81 ; a first mask layer, 82 ; and a first pattern transfer layer, 83 . DETAILED DESCRIPTION
[0070] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0071] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0072] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0073] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.
[0074] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0075] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0076] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.
[0077] In the related art, a first conductive layer is first formed by using a self-aligned double patterning (SADP) technique, and then a dielectric layer is deposited, and then a contact plug and a second conductive layer are formed. This requires multiple processes, which increases the cost.
[0078] Based on this, the present disclosure provides a semiconductor structure. Figure 1 A schematic diagram of the structure of a semiconductor structure provided in an embodiment of the present disclosure.
[0079] See also Figure 1 , the semiconductor structure includes:
[0080] Substrate 10;
[0081] The first conductive layer 20 is located on the substrate 10 and includes a first sub-conductive structure 211, a second sub-conductive structure 212 and a second conductive structure 22 which are arranged at intervals;
[0082] A second conductive layer 30, located on the first conductive layer 20;
[0083] An isolation structure 41, located between the first sub-conductive structure 211 and the second sub-conductive structure 212 and connected to the second conductive layer 30, for electrically isolating the first sub-conductive structure 211 from the second sub-conductive structure 212;
[0084] The contact plug 42 is located between the second conductive structure 22 and the second conductive layer 30 , and is used to electrically connect the second conductive structure 22 and the second conductive layer 30 .
[0085] In the disclosed embodiment, an isolation structure, a contact plug, and a first conductive layer can be formed in the same process, which simplifies the process and saves costs; at the same time, the isolation structure electrically isolates the first sub-conductive structure from the second sub-conductive structure to avoid crosstalk.
[0086] In one embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it may also be a stacked structure, such as Si / SiGe, etc., and it may also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.
[0087] The substrate 10 includes an active region 11 and a gate structure 12 located on the active region 11. The active region 11 includes a first source-drain region 111 and a second source-drain region 112 located on opposite sides of the gate structure 12. The substrate also includes an isolation region (not shown) adjacent to the active region 11. The isolation region defines the substrate into a plurality of discrete active regions 11.
[0088] The gate structure 12 includes a gate insulating layer 121, a first gate conductive layer 122, a second gate conductive layer 123, a third gate conductive layer 124 and a capping layer 125 stacked in sequence from bottom to top, wherein the material of the gate insulating layer 121 includes but is not limited to oxide; the material of the first gate conductive layer 122 includes but is not limited to polysilicon; the material of the second gate conductive layer 123 includes but is not limited to titanium nitride; the material of the third gate conductive layer 124 includes but is not limited to metal tungsten; the material of the capping layer 125 includes but is not limited to oxide, nitride, metal oxide and oxynitride, etc.
[0089] In one embodiment, the semiconductor structure further includes a gate spacer layer 13 , and the gate spacer layer 13 covers the sidewall of the gate structure 12 to insulate and isolate the gate structure 12 from the first connection pillar 61 and the second connection pillar 62 .
[0090] See also Figure 1 The first conductive layer 20 includes a first sub-conductive structure 211 , a second sub-conductive structure 212 , and a second conductive structure 22 that are spaced apart.
[0091] The material of the first conductive layer 20 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination thereof.
[0092] In one embodiment, the semiconductor structure further includes: a first connecting pillar 61 and a second connecting pillar 62 , wherein the first connecting pillar 61 electrically connects the first sub-conductive structure 211 and the first source and drain region 111 , and the second connecting pillar 62 electrically connects the second sub-conductive structure 212 and the second source and drain region 112 .
[0093] In one embodiment, the semiconductor structure further includes: a first dielectric layer 51, located on the substrate 10, including a first sub-dielectric layer 511 and a second sub-dielectric layer 512; wherein the first sub-dielectric layer 511 is located on the side wall and below the first conductive layer 20, and the second sub-dielectric layer 512 covers the first conductive layer 20 and the first sub-dielectric layer 511; and the second dielectric layer 52 is located on the first dielectric layer 51.
[0094] Continue to see Figure 1 The second conductive layer 30 is located on the first conductive layer 20. Specifically, the second conductive layer 30 is located on the second dielectric layer 52.
[0095] The material of the second conductive layer 30 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination thereof.
[0096] Continue to see Figure 1 The isolation structure 41 is located between the first sub-conductive structure 211 and the second sub-conductive structure 212 and connected to the second conductive layer 30, and is used to electrically isolate the first sub-conductive structure 211 from the second sub-conductive structure 212; the contact plug 42 is located between the second conductive structure 22 and the second conductive layer 30, and is used to electrically connect the second conductive structure 22 to the second conductive layer 30.
[0097] In some embodiments, the bottom surface of the contact plug 42 is flush with the top surface of the second conductive structure 22 , that is, the contact plug 42 does not extend into the second conductive structure 22 .
[0098] In some other embodiments, the bottom surface of the contact plug 42 is lower than the top surface of the second conductive structure 22 and higher than the bottom surface of the second conductive structure 22 , that is, the contact plug extends into the second conductive structure 22 but does not penetrate the second conductive structure 22 .
[0099] In one embodiment, the top surface of the isolation structure 41 is flush with the top surface of the contact plug 42 , the bottom surface of the isolation structure 41 is lower than the bottom surface of the contact plug 42 , and the bottom surface of the isolation structure 41 is not higher than the bottom surface of the first conductive layer 20 .
[0100] Specifically, in some embodiments, Figure 1 As shown, the bottom surface of the isolation structure 41 is lower than the bottom surface of the first conductive layer 20; in some other embodiments, the bottom surface of the isolation structure 41 is flush with the bottom surface of the first conductive layer 20. Regardless of whether the bottom surface of the isolation structure 41 is lower than or flush with the bottom surface of the first conductive layer 20, as long as the isolation structure 41 can insulate and isolate the first sub-conductive structure 211 from the second sub-conductive structure 212, it will be sufficient.
[0101] In one embodiment, the isolation structure 41 and the contact plug 42 both include a conductive pillar 401 and an insulating layer 402 disposed around the sidewall of the conductive pillar 401 .
[0102] The insulating layer 402 in the isolation structure 41 contacts the first sub-conductive structure 211 and the second sub-conductive structure 212, and plays the role of insulation isolation. The conductive pillar 401 does not contact the first sub-conductive structure 211 and the second sub-conductive structure 212. Therefore, even if the isolation structure 41 includes the conductive pillar 401, the isolation structure 41 does not play a conductive role; the contact plug 42 does not affect the conductivity of the contact plug 42 because the bottom and top surfaces of the conductive pillar 401 are in contact with the second conductive structure 22 and the second conductive layer 30 respectively, and the insulating layer 402 is located at the side wall of the conductive pillar 401. In addition, the conductive pillar and the insulating layer constituting the isolation structure and the contact plug can be formed simultaneously in the same step, which simplifies the process steps and reduces the cost.
[0103] In some other embodiments, the isolation structure 41 may include only the insulating layer 402 , and the contact plug may include only the conductive pillar 401 .
[0104] like Figure 1 As shown, the conductive pillar 401 may include a two-layer structure, namely a first conductive pillar (not marked in the figure) and a diffusion barrier layer (not marked in the figure) located between the first conductive pillar and the insulating layer, wherein the diffusion barrier layer may also be located between the second conductive layer and the second dielectric layer. For example, the first conductive pillar is made of a metal material such as tungsten or copper, and the diffusion barrier layer is titanium nitride.
[0105] Figure 2 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure, but it needs to be explained that: Figure 2 4 is a top view after the second conductive layer, the second dielectric layer and the second sub-dielectric layer are removed, mainly to reflect the positional relationship between the isolation structure 41 and the contact plug 42 and the first conductive layer 20.
[0106] In one embodiment, if Figure 2 As shown, the size of the isolation structure 41 in the first horizontal direction is greater than the size of the contact plug 42 in the first horizontal direction, and the size of the isolation structure 41 in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure 211 and the second sub-conductive structure 212 in the second horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure 211 and the second sub-conductive structure 212, and the second horizontal direction is the extension direction of the first sub-conductive structure 211 and the second sub-conductive structure 212.
[0107] The size of the isolation structure 41 in the first horizontal direction is larger than the size of the contact plug 42 in the first horizontal direction, that is, when etching the first trench and the second trench for respectively forming the isolation structure 41 and the contact plug 42, the width of the first trench is larger than the width of the second trench. In this way, due to the etching load effect of the dielectric layer, the first trench with a larger width can be etched faster, that is, when the first trench penetrates the first conductive layer 20, the second trench stays on the surface or inside of the first conductive layer 20, and does not penetrate the first conductive layer 20.
[0108] The size of the isolation structure 41 in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure 211 and the second sub-conductive structure 212 in the second horizontal direction. In this way, the isolation structure 41 can completely isolate the first sub-conductive structure 211 and the second sub-conductive structure 212 to play an insulating and isolating role.
[0109] In some embodiments, the sum of the size of the second sub-dielectric layer 512 along the thickness direction of the substrate 10 and the size of the second dielectric layer 52 along the thickness direction of the substrate 10 is greater than or equal to a preset value;
[0110] The isolation structure 41 penetrates the second dielectric layer 52 and the second sub-dielectric layer 512 and extends into the first sub-dielectric layer 511;
[0111] The contact plug 42 penetrates the second dielectric layer 52 and the second sub-dielectric layer 512 and contacts the second conductive structure 22 .
[0112] When the sum of the size of the second sub-dielectric layer 512 along the substrate thickness direction and the size of the second dielectric layer 52 along the substrate thickness direction is greater than or equal to a preset value, the preset value is greater than one tenth of the height of the contact plug 42, for example, it can be 20nm, which means that the overall thickness of the dielectric layer is thick enough, so that there is enough margin to utilize the load effect to realize the etching of the first groove and the second groove of different depths. When the first groove with a large width etches through the second sub-dielectric layer, the second groove with a small width will not etch through the second sub-dielectric layer.
[0113] Figure 3 The schematic diagram of the structure of the semiconductor structure provided by another embodiment of the present disclosure needs to be explained as follows: Figure 3 The substrate is not shown.
[0114] In some other embodiments, such as Figure 3 As shown, the sum of the size of the second sub-dielectric layer 512 along the thickness direction of the substrate 10 and the size of the second dielectric layer 52 along the thickness direction of the substrate 10 is less than a preset value;
[0115] The semiconductor structure further includes: a third dielectric layer 53 located on the second dielectric layer 52;
[0116] The isolation structure 41 penetrates the third dielectric layer 53, the second dielectric layer 52 and the second sub-dielectric layer 512 and extends into the first sub-dielectric layer 511;
[0117] The contact plug 42 penetrates the third dielectric layer 53 , the second dielectric layer 52 and the second sub-dielectric layer 512 and contacts the second conductive structure 22 .
[0118] When the sum of the size of the second sub-dielectric layer 512 along the substrate thickness direction and the size of the second dielectric layer 52 along the substrate thickness direction is less than a preset value, it means that the sum of the thicknesses of the second sub-dielectric layer 512 and the second dielectric layer 52 is insufficient, and there is no way to utilize the load effect to achieve the etching of the first groove and the second groove of different depths. Therefore, a third dielectric layer is added to increase the overall thickness of the dielectric layer (the sum of the second sub-dielectric layer, the second dielectric layer and the third dielectric layer), thereby ensuring that there is enough margin to utilize the load effect to achieve the etching of the first groove and the second groove of different depths.
[0119] In one embodiment, the first dielectric layer 51 and the second dielectric layer 52 are made of different materials; the second dielectric layer 52 and the third dielectric layer 53 are made of different materials.
[0120] The materials between the first dielectric layer 51 and the second dielectric layer 52, and between the second dielectric layer 52 and the third dielectric layer 53 are different. In this way, it can be ensured that the etching selectivity between the first dielectric layer 51 and the second dielectric layer 52 is different, and the etching selectivity between the second dielectric layer 52 and the third dielectric layer 53 is different. Therefore, in the process of etching the first groove and the second groove, when the first groove penetrates the first conductive layer, the second groove can stay on the surface or inside the first conductive layer.
[0121] The material of the first dielectric layer 51 includes but is not limited to nitride, the material of the second dielectric layer 52 includes but is not limited to oxide, and the material of the third dielectric layer 53 includes but is not limited to nitride.
[0122] In some other embodiments, the first groove and the second groove may be formed in sequence respectively, so as to more accurately control the depth of the first groove and the second groove. For example, the first groove is first etched to form, and then a sacrificial material is filled in the first groove, and the sacrificial material is removed after the second groove is etched to form; or, the second groove is first etched to form, and then a sacrificial material is filled in the second groove, and the sacrificial material is removed after the first groove is etched to form.
[0123] The present disclosure also provides a method for preparing a semiconductor structure. Figure 4 ,like Figure 4 As shown, the method comprises the following steps:
[0124] Step 401: providing a substrate;
[0125] Step 402: forming an initial first conductive layer on a substrate, wherein the initial first conductive layer includes a first conductive structure and a second conductive structure that are spaced apart from each other;
[0126] Step 403: forming a first trench and a second trench in the same step, wherein the first trench penetrates the first conductive structure to divide the first conductive structure into a first sub-conductive structure and a second sub-conductive structure, and the second trench is located above the second conductive structure and exposes a portion of the surface of the second conductive structure; the first sub-conductive structure, the second sub-conductive structure and the second conductive structure are formed into a first conductive layer;
[0127] Step 404: forming an isolation structure in the first trench;
[0128] Step 405: forming a contact plug in the second trench;
[0129] Step 406: Form a second conductive layer on the isolation structure and the contact plug.
[0130] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail below in conjunction with specific embodiments.
[0131] Figures 5a to 7f A schematic diagram of the structure of a semiconductor structure during the preparation process provided by an embodiment of the present disclosure.
[0132] First, see Figure 5a , execute step 401 and provide a substrate 10.
[0133] In one embodiment, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it may also be a stacked structure, such as Si / SiGe, etc., and it may also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.
[0134] The substrate 10 includes an active region 11 and a gate structure 12 located on the active region 11. The active region 11 includes a first source-drain region 111 and a second source-drain region 112 located on opposite sides of the gate structure 12. The substrate 10 also includes an isolation region (not shown in the figure), which defines the substrate into a plurality of discrete active regions 11.
[0135] The gate structure 12 includes a gate insulating layer 121, a first gate conductive layer 122, a second gate conductive layer 123, a third gate conductive layer 124 and a capping layer 125 stacked in sequence from bottom to top, wherein the material of the gate insulating layer 121 includes but is not limited to oxide; the material of the first gate conductive layer 122 includes but is not limited to polysilicon; the material of the second gate conductive layer 123 includes but is not limited to titanium nitride; the material of the third gate conductive layer 124 includes but is not limited to metal tungsten; the material of the capping layer 125 includes but is not limited to oxide, nitride, metal oxide and oxynitride, etc.
[0136] In one embodiment, a gate spacer 13 is formed to cover the sidewalls of the gate structure 12 to insulate and isolate the gate structure 12 from the first connecting pillar 61 and the second connecting pillar 62 to be formed subsequently.
[0137] Next, see Figure 5a to Figure 5c , perform step 402 to form an initial first conductive layer 200 on the substrate 10, wherein the initial first conductive layer 200 includes a first conductive structure 21 and a second conductive structure 22 that are spaced apart.
[0138] In one embodiment, an initial first conductive layer 200 is formed on the substrate 10, including: forming a first connecting column 61 and a second connecting column 62 and an initial first conductive layer 200 located on the first connecting column 61 and the second connecting column 62, the first connecting column 61 contacts the first source and drain region 111, and the second connecting column 62 contacts the second source and drain region 112.
[0139] Specifically, see Figure 5a and Figure 5b The method further includes: before forming the initial first conductive layer 200, forming an initial first conductive layer pre-layer 200' on the substrate 10, and forming a first isolation layer 81, a first mask layer 82 and a first pattern transfer layer 83 on the initial first conductive layer pre-layer 200'. The first isolation layer 81, the first mask layer 82 and the first pattern transfer layer 83 can be used as masks for the subsequent formation of the initial first conductive layer 200.
[0140] In actual operation, the initial first conductive layer pre-layer 200', the first isolation layer 81, the first mask layer 82 and the first pattern transfer layer 83 can be formed using one or more thin film deposition processes; specifically, the deposition process includes but is not limited to a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a combination thereof.
[0141] The material of the first isolation layer 81 includes but is not limited to amorphous carbon (ACL), the material of the first mask layer 82 includes but is not limited to silicon oxynitride, and the material of the first pattern transfer layer 83 includes but is not limited to photoresist. The material of the initial first conductive layer pre-layer 200' includes but is not limited to tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination thereof.
[0142] See also Figure 5c The first pattern transfer layer 83 has a pattern structure. According to the pattern structure on the first pattern transfer layer 83 , the initial first conductive layer pre-layer 200 ′ is etched to form the initial first conductive layer 200 .
[0143] The initial first conductive layer 200 includes a first conductive structure 21 and a second conductive structure 22 , and the first connecting pillar 61 and the second connecting pillar 62 are connected to the first conductive structure 21 .
[0144] Next, see Figure 5d and Figures 6a to 6f ,as well as Figures 7a to 7f , execute steps 403 to 405, and form a first trench 71 and a second trench 72 in the same step, the first trench 71 penetrates the first conductive structure 21 to divide the first conductive structure 21 into a first sub-conductive structure 211 and a second sub-conductive structure 212, the second trench 72 is located above the second conductive structure 22 and exposes a portion of the surface of the second conductive structure 22; the first sub-conductive structure 211, the second sub-conductive structure 212 and the second conductive structure 22 are formed into a first conductive layer 20; an isolation structure 41 is formed in the first trench 71; and a contact plug 42 is formed in the second trench 72.
[0145] It needs to be explained that Figures 6a to 6f A schematic diagram of a semiconductor structure during the preparation process provided in one embodiment, Figures 7a to 7f A schematic diagram of a semiconductor structure during the preparation process provided by another embodiment. Figures 6a to 6f The illustrated embodiment is described in detail.
[0146] See first Figure 6a The method further includes: before forming the initial first conductive layer 200, forming a first sub-dielectric layer 511 on the substrate 10, wherein the first sub-dielectric layer 511 is located on the sidewall and below the initial first conductive layer 200;
[0147] A second sub-dielectric layer 512 is formed to cover the initial first conductive layer 200 and the first sub-dielectric layer 511 , and the first sub-dielectric layer 511 and the second sub-dielectric layer 512 are formed into the first dielectric layer 51 ;
[0148] The second dielectric layer 52 is formed on the first dielectric layer 51 .
[0149] In one embodiment, the materials of the first dielectric layer 51 and the second dielectric layer 52 are different. The material of the first dielectric layer 51 includes but is not limited to nitride, and the material of the second dielectric layer 52 includes but is not limited to oxide.
[0150] Next, see Figure 6b to Figure 6d , the sum of the size of the second sub-dielectric layer 512 along the thickness direction of the substrate 10 and the size of the second dielectric layer 52 along the thickness direction of the substrate 10 is greater than or equal to a preset value;
[0151] The first trench 71 and the second trench 72 are formed in the same step, comprising:
[0152] See also Figure 6b , performing a first etching process, the first trench 71 penetrates the second dielectric layer 52 and stops at the surface of the first dielectric layer 51, the second trench 72 stops in the second dielectric layer 52, and the size of the first trench 71 in the first horizontal direction is larger than the size of the second trench 72 in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure 211 and the second sub-conductive structure 212;
[0153] See also Figure 6c , performing a second etching process, the first trench 71 penetrates the second sub-dielectric layer 512 and stops at the surface of the first conductive structure 21, the second trench 72 stops in the second dielectric layer 52, and the etching selectivity ratios of the first dielectric layer 51 and the second dielectric layer 52 are different;
[0154] See also Figure 6d , a third etching process is performed, the first trench 71 penetrates the first conductive structure 21 , and the second trench 72 exposes a portion of the surface of the second conductive structure 22 .
[0155] In this embodiment, when the sum of the size of the second sub-dielectric layer 512 along the substrate thickness direction and the size of the second dielectric layer 52 along the substrate thickness direction is greater than or equal to a preset value, it means that the overall thickness of the dielectric layer is thick enough, so that there is enough margin to utilize the load effect to realize the etching of the first groove 71 and the second groove 72 with different depths. When the first groove 71 with a large width etches through the second sub-dielectric layer 512, the second groove 72 with a small width will not etch through the second sub-dielectric layer 512.
[0156] Furthermore, the etching selectivity of the first dielectric layer 51 and the second dielectric layer 52 is different, so that when etching the first trench 71 and the second trench 72 , when the first trench 71 etches through the first conductive structure 21 , the second trench 72 can stay on the surface or inside of the second conductive structure 22 .
[0157] Next, see Figure 6e and Figure 6f , forming an isolation structure 41 in the first trench 71 and forming a contact plug 42 in the second trench 72, including:
[0158] forming an insulating layer 402 on sidewalls of the first trench 71 and the second trench 72;
[0159] A conductive material is filled in the first trench 71 and the second trench 72 formed with the insulating layer 402 to form an isolation structure 41 in the first trench 71 and a contact plug 42 in the second trench 72 .
[0160] Specifically, the insulating layer 402 is first formed on the sidewalls of the first trench 71 and the second trench 72 , and then the conductive pillar 401 covering the insulating layer 402 is formed.
[0161] The insulating layer 402 in the isolation structure 41 is in contact with the first sub-conductive structure 211 and the second sub-conductive structure 212, and plays the role of insulation isolation. Therefore, even if the isolation structure 41 includes the conductive pillar 401, the isolation structure 41 does not play a conductive role; because the bottom and top surfaces of the contact plug 42 are respectively connected to the second conductive structure 22 and the second conductive layer 30, and the insulating layer 402 is located at the side wall, it does not affect the conductivity of the contact plug 42. In addition, the conductive pillar and the insulating layer can be formed in the isolation structure and the contact plug in the same step, which simplifies the process steps and reduces the cost.
[0162] like Figure 6f As shown, the conductive column 401 may include a two-layer structure, namely a first conductive column (not marked in the figure) and a diffusion barrier layer (not marked in the figure) located between the first conductive column and the insulating layer, wherein the diffusion barrier layer may also cover the surface of the second dielectric layer.
[0163] In this embodiment, the isolation structure 41 and the contact plug 42 both include a conductive pillar 401 and an insulating layer 402 .
[0164] In some other embodiments, in some other embodiments, the isolation structure 41 may include only the insulating layer 402 , and the contact plug 42 may include only the conductive pillar 401 .
[0165] In some embodiments, the bottom surface of the contact plug 42 is flush with the top surface of the second conductive structure 22 , that is, the contact plug 42 does not extend into the second conductive structure 22 .
[0166] In some other embodiments, the bottom surface of the contact plug 42 is lower than the top surface of the second conductive structure 22 , that is, the contact plug 42 extends into the second conductive structure 22 .
[0167] In one embodiment, the top surface of the isolation structure 41 is flush with the top surface of the contact plug 42 , the bottom surface of the isolation structure 41 is lower than the bottom surface of the contact plug 42 , and the bottom surface of the isolation structure 41 is not higher than the bottom surface of the first conductive layer 20 .
[0168] Specifically, in some embodiments, Figure 6f As shown, the bottom surface of the isolation structure 41 is lower than the bottom surface of the first conductive layer 20; in some other embodiments, the bottom surface of the isolation structure 41 is flush with the bottom surface of the first conductive layer 20. Regardless of whether the bottom surface of the isolation structure 41 is lower than or flush with the bottom surface of the first conductive layer 20, as long as the isolation structure 41 can insulate and isolate the first sub-conductive structure 211 from the second sub-conductive structure 212, it will be sufficient.
[0169] In one embodiment, if Figure 2 As shown, the size of the isolation structure 41 in the first horizontal direction is greater than the size of the contact plug 42 in the first horizontal direction, and the size of the isolation structure 41 in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure 211 and the second sub-conductive structure 212 in the second horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure 211 and the second sub-conductive structure 212, and the second horizontal direction is the extension direction of the first sub-conductive structure 211 and the second sub-conductive structure 212.
[0170] The size of the isolation structure 41 in the first horizontal direction is larger than the size of the contact plug 42 in the first horizontal direction, that is, when etching the first trench 71 and the second trench 72 for respectively forming the isolation structure 41 and the contact plug 42, the width of the first trench 71 is larger than the width of the second trench 72. In this way, due to the etching load effect of the dielectric layer, the first trench 71 with a larger width can be etched faster, that is, when the first trench penetrates the first conductive layer 20, the second trench 72 stays on the surface or inside of the first conductive layer 20 without penetrating the first conductive layer.
[0171] The size of the isolation structure 41 in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure 211 and the second sub-conductive structure 212 in the second horizontal direction. In this way, the isolation structure 41 can completely isolate the first sub-conductive structure 211 and the second sub-conductive structure 212 to play an insulating and isolating role.
[0172] Continue to see Figure 6f , while forming the conductive pillar 401 , an initial second conductive layer 300 is formed on the second dielectric layer 52 .
[0173] Next, Figures 7a to 7f The illustrated embodiment is described in detail.
[0174] The sum of the size of the second sub-dielectric layer 512 along the thickness direction of the substrate 10 and the size of the second dielectric layer 52 along the thickness direction of the substrate 10 is less than a preset value;
[0175] The method also includes:
[0176] See also Figure 7a , forming a third dielectric layer 53 on the second dielectric layer 52;
[0177] The first trench 71 and the second trench 72 are formed in the same step, comprising:
[0178] See also Figure 7b , performing a fourth etching process, the first trench 71 penetrates the third dielectric layer 53 and stops at the surface of the second dielectric layer 52, the second trench 72 stops in the third dielectric layer 53, and the size of the first trench 71 in the first horizontal direction is greater than the size of the second trench 72 in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure 211 and the second sub-conductive structure 212;
[0179] See also Figure 7c , performing a fifth etching process, the first trench 71 penetrates the second dielectric layer 52 and the second sub-dielectric layer 512 and stops at the surface of the first conductive structure 21, the second trench 72 penetrates the third dielectric layer 53 and stops in the second dielectric layer 52, and the etching selectivity ratios of the second dielectric layer 52 and the third dielectric layer 53 are different;
[0180] See also Figure 7d , a sixth etching process is performed, the first trench 71 penetrates the first conductive structure 21 , and the second trench 72 exposes a portion of the surface of the second conductive structure 22 .
[0181] When the sum of the size of the second sub-dielectric layer 512 along the substrate thickness direction and the size of the second dielectric layer 52 along the substrate thickness direction is less than a preset value, it means that the sum of the thicknesses of the second sub-dielectric layer 512 and the second dielectric layer 52 is insufficient, and there is no way to utilize the load effect to achieve the etching of the first groove and the second groove of different depths. Therefore, a third dielectric layer 53 is added to increase the overall thickness of the dielectric layer, thereby ensuring that there is enough margin to utilize the load effect to achieve the etching of the first groove and the second groove of different depths.
[0182] In one embodiment, the materials of the first dielectric layer 51 and the second dielectric layer 52 are different; the materials of the second dielectric layer 52 and the third dielectric layer 53 are different. The material of the first dielectric layer 51 includes but is not limited to nitride, the material of the second dielectric layer 52 includes but is not limited to oxide, and the material of the third dielectric layer 53 includes but is not limited to nitride.
[0183] Next, see Figure 7e and Figure 7f, forming an isolation structure 41 in the first trench 71, and forming a contact plug 42 in the second trench 72. The steps of forming the isolation structure 41 and the contact plug 42 in this embodiment are similar to those in Figure 6e and Figure 6f The same, no further description here.
[0184] Next, see Figure 5e , perform step 406 to form a second conductive layer 30 on the isolation structure 41 and the contact plug 42 .
[0185] Specifically, a mask layer may be first grown on the upper surface of the initial second conductive layer 30, and then the mask layer may be patterned to display the pattern of the second conductive layer to be etched on the mask layer, and the mask layer may be patterned by a photolithography process. The mask layer may be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer may be patterned by steps such as exposure, development, and degumming. Then, the second conductive layer 30 is etched out according to the pattern of the second conductive layer 30 to be etched.
[0186] The material of the second conductive layer 30 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination thereof.
[0187] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A first conductive layer, located on the substrate, includes a first sub-conductive structure, a second sub-conductive structure, and a second conductive structure that are spaced apart from each other; a second conductive layer, located on the first conductive layer; an isolation structure, located between the first sub-conductive structure and the second sub-conductive structure and connected to the second conductive layer, and used for electrically isolating the first sub-conductive structure from the second sub-conductive structure; A contact plug is located between the second conductive structure and the second conductive layer, and is used to electrically connect the second conductive structure and the second conductive layer.
2. The semiconductor structure according to claim 1, characterized in that: The top surface of the isolation structure is flush with the top surface of the contact plug, the bottom surface of the isolation structure is lower than the bottom surface of the contact plug, and the bottom surface of the isolation structure is not higher than the bottom surface of the first conductive layer.
3. The semiconductor structure according to claim 1, characterized in that: The isolation structure and the contact plug both include a conductive column and an insulating layer disposed around a sidewall of the conductive column.
4. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A first dielectric layer, located on the substrate, comprising a first sub-dielectric layer and a second sub-dielectric layer; wherein the first sub-dielectric layer is located on the side wall and below the first conductive layer, and the second sub-dielectric layer covers the first conductive layer and the first sub-dielectric layer; The second dielectric layer is located on the first dielectric layer.
5. The semiconductor structure according to claim 4, characterized in that: The sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is greater than or equal to a preset value; The isolation structure penetrates the second dielectric layer and the second sub-dielectric layer and extends into the first sub-dielectric layer; The contact plug penetrates the second dielectric layer and the second sub-dielectric layer and contacts the second conductive structure.
6. The semiconductor structure according to claim 4, characterized in that: The sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is smaller than a preset value; The semiconductor structure further includes: a third dielectric layer located on the second dielectric layer; The isolation structure penetrates the third dielectric layer, the second dielectric layer and the second sub-dielectric layer and extends into the first sub-dielectric layer; The contact plug penetrates the third dielectric layer, the second dielectric layer, and the second sub-dielectric layer and contacts the second conductive structure.
7. The semiconductor structure according to claim 6, characterized in that: The first dielectric layer and the second dielectric layer are made of different materials; the second dielectric layer and the third dielectric layer are made of different materials.
8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The size of the isolation structure in the first horizontal direction is greater than the size of the contact plug in the first horizontal direction, and the size of the isolation structure in the second horizontal direction is greater than or equal to the size of the first sub-conductive structure and the second sub-conductive structure in the second horizontal direction. The first horizontal direction is the arrangement direction of the first sub-conductive structure and the second sub-conductive structure, and the second horizontal direction is the extension direction of the first sub-conductive structure and the second sub-conductive structure.
9. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The substrate includes an active region and a gate structure located on the active region, wherein the active region includes a first source-drain region and a second source-drain region located on opposite sides of the gate structure; The semiconductor structure further includes: a first connecting pillar and a second connecting pillar, wherein the first connecting pillar electrically connects the first sub-conductive structure and the first source and drain region, and the second connecting pillar electrically connects the second sub-conductive structure and the second source and drain region.
10. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming an initial first conductive layer on the substrate, wherein the initial first conductive layer comprises a first conductive structure and a second conductive structure which are spaced apart from each other; forming a first trench and a second trench in the same step, wherein the first trench penetrates the first conductive structure to divide the first conductive structure into a first sub-conductive structure and a second sub-conductive structure, and the second trench is located above the second conductive structure and exposes a portion of the surface of the second conductive structure; the first sub-conductive structure, the second sub-conductive structure and the second conductive structure form a first conductive layer; forming an isolation structure in the first trench; forming a contact plug in the second trench; A second conductive layer is formed on the isolation structure and the contact plug.
11. The method according to claim 10, characterized in that The method further comprises: Before forming the initial first conductive layer, forming a first sub-dielectric layer on the substrate, wherein the first sub-dielectric layer is located on the sidewall and below the initial first conductive layer; forming a second sub-dielectric layer covering the initial first conductive layer and the first sub-dielectric layer, wherein the first sub-dielectric layer and the second sub-dielectric layer form a first dielectric layer; A second dielectric layer is formed on the first dielectric layer.
12. The method according to claim 11, characterized in that The sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is greater than or equal to a preset value; The forming of the first trench and the second trench in the same step comprises: Performing a first etching process, wherein the first trench penetrates the second dielectric layer and stops at the surface of the first dielectric layer, the second trench stops in the second dielectric layer, and the size of the first trench in the first horizontal direction is larger than the size of the second trench in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure and the second sub-conductive structure; Performing a second etching process, wherein the first trench penetrates the second sub-dielectric layer and stops at the surface of the first conductive structure, the second trench stops in the second dielectric layer, and the etching selectivity ratios of the first dielectric layer and the second dielectric layer are different; A third etching process is performed, the first trench penetrates the first conductive structure, and the second trench exposes a portion of the surface of the second conductive structure.
13. The method according to claim 11, characterized in that The sum of the size of the second sub-dielectric layer along the thickness direction of the substrate and the size of the second dielectric layer along the thickness direction of the substrate is smaller than a preset value; The method further includes: forming a third dielectric layer on the second dielectric layer; The forming of the first trench and the second trench in the same step comprises: Performing a fourth etching process, wherein the first trench penetrates the third dielectric layer and stops at the surface of the second dielectric layer, the second trench stops in the third dielectric layer, and the size of the first trench in the first horizontal direction is larger than the size of the second trench in the first horizontal direction, and the first horizontal direction is the arrangement direction of the first sub-conductive structure and the second sub-conductive structure; Performing a fifth etching process, wherein the first trench penetrates the second dielectric layer and the second sub-dielectric layer and stops at the surface of the first conductive structure, the second trench penetrates the third dielectric layer and stops in the second dielectric layer, and the etching selectivity ratios of the second dielectric layer and the third dielectric layer are different; A sixth etching process is performed, the first trench penetrates the first conductive structure, and the second trench exposes a portion of the surface of the second conductive structure.
14. The method according to claim 10, characterized in that Forming an isolation structure in the first trench and forming a contact plug in the second trench, comprising: forming an insulating layer on sidewalls of the first trench and the second trench; Conductive materials are filled in the first trench and the second trench where the insulating layer is formed, so as to form an isolation structure in the first trench and a contact plug in the second trench.
15. The method according to claim 10, characterized in that The substrate includes an active region and a gate structure located on the active region, wherein the active region includes a first source-drain region and a second source-drain region located on opposite sides of the gate structure; Forming an initial first conductive layer on the substrate, comprising: A first connecting pillar and a second connecting pillar and an initial first conductive layer located on the first connecting pillar and the second connecting pillar are formed, wherein the first connecting pillar contacts the first source and drain region, and the second connecting pillar contacts the second source and drain region.