Semiconductor device

Abstract

The semiconductor device includes: a substrate including a cell array region and a peripheral region; a bit line on the cell array region and extending in a first direction; a shield line extending from the cell array region to the peripheral region in a first direction, and arranged adjacent to the bit line in a second direction crossing the first direction; a shield contact line on the peripheral area, extending in the second direction, and connected to the shield line; a channel pattern on the bit line and extending in a direction perpendicular to the bit line; a word line extending in a second direction and located on the channel pattern; a gate insulating pattern between the channel pattern and the word line; an insulating pattern on the word line; a bonding pad connected to the channel pattern; and a data storage pattern connected to the bonding pad.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0085943 filed in the Korean Intellectual Property Office on July 3, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a shielding line and a shielding contact line. Background Art

[0003] The performance and cost of semiconductor memory devices can be improved by increasing the integration of the device. In the case of a two-dimensional semiconductor memory device or a flat area semiconductor memory device, its integration can be determined by the area occupied by the unit memory cell and can be affected by the level of fine pattern forming technology. However, since pattern miniaturization may require expensive equipment, the integration of 2D semiconductor memory devices may be limited.

[0004] In order to reduce the cost of manufacturing a semiconductor memory device, a semiconductor memory device including a vertical channel transistor in which a channel extends in a vertical direction has been proposed, which includes finely forming a pattern constituting such a semiconductor memory device. However, as the width of the fine pattern gradually decreases, parasitic capacitance may increase, and the performance of the semiconductor memory device may be degraded. Summary of the invention

[0005] An aspect of the present disclosure is to provide a semiconductor device having improved reliability and productivity.

[0006] According to an embodiment, a semiconductor device includes: a substrate, including a cell array region and a peripheral region surrounding the cell array region; a bit line, located in the cell array region and extending along a first direction; a shielding line, extending from the cell array region to the peripheral region along the first direction, and arranged adjacent to the bit line along a second direction intersecting the first direction; a shielding contact line, located in the peripheral region, extending along the second direction, and connected to the shielding line; a channel pattern, located on the bit line and extending in a direction perpendicular to the bit line; a word line, extending in the second direction, and located on the channel pattern; a gate insulation pattern, located between the channel pattern and the word line; an insulation pattern, located on the word line; a bonding pad, connected to the channel pattern; and a data storage pattern, connected to the bonding pad.

[0007] According to an embodiment, a semiconductor device includes: a substrate, including a cell array region and a peripheral region surrounding the cell array region; a plurality of bit lines, which are located in the cell array region and extend along a first direction; a plurality of shielding lines, which extend from the cell array region to the peripheral region along the first direction and are arranged alternately with the plurality of bit lines; a first shielding contact line, which extends in the peripheral region along a second direction intersecting the first direction and is connected to an end of a first shielding line among the plurality of shielding lines; a second shielding contact line, which extends in the peripheral region along the second direction and is connected to an end of a second shielding line among the plurality of shielding lines; a channel pattern, which is located on the plurality of bit lines and extends in a direction perpendicular to an upper surface of the plurality of bit lines; a word line, which extends in the second direction and is located on the channel pattern; a gate insulation pattern, which is located between the channel pattern and the word line; an insulation pattern, which is located on the word line; a bonding pad, which is connected to the channel pattern; and a data storage pattern, which is connected to the bonding pad.

[0008] According to an embodiment, a semiconductor device includes: a substrate, including a cell array region and a peripheral region surrounding the cell array region; a plurality of bit lines, located in the cell array region and extending along a first direction; a plurality of shielding lines, extending from the cell array region to the peripheral region along the first direction and arranged alternately with the plurality of bit lines; a shielding contact line, extending in a second direction intersecting the first direction in the peripheral region and connected to the plurality of shielding lines; a channel pattern, located on the plurality of bit lines and extending in a direction perpendicular to upper surfaces of the plurality of bit lines; a word line, extending in the second direction; a gate insulation pattern, located between the channel pattern and the word line; an insulation pattern, located on the word line; a bonding pad, connected to the channel pattern; a data storage pattern, connected to the bonding pad; and a conductive via, connected to a portion of the shielding contact line in the peripheral region.

[0009] According to one embodiment, by arranging shield contact lines connected to a plurality of shield lines located between bit lines in a peripheral region surrounding a cell array region, it is possible to improve a contact area between components constituting a semiconductor device and the shield contact lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a perspective view schematically showing a semiconductor memory device according to an embodiment.

[0011] Figure 2 is a top plan view schematically showing a semiconductor device according to an embodiment.

[0012] Figure 3 yes Figure 2 A partial enlarged view of area R1 in FIG.

[0013] Figure 4 It is along Figure 2A cross-sectional view taken along lines AA' and BB'.

[0014] Figure 5A and Figure 5B According to one or more embodiments, Figure 2 Cross-sectional views taken along lines CC', D-D' and EE'.

[0015] Figure 6 is a top plan view schematically showing a semiconductor device according to another embodiment.

[0016] Figure 7 According to another embodiment, Figure 6 A cross-sectional view taken along line F-F'.

[0017] Figure 8 , Fig. 9 , Fig. 10A , Fig. 10B and Fig. 10C is a top plan view schematically illustrating a semiconductor device according to one or more embodiments.

[0018] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 and Fig.25 are a top plan view and a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0019] In the following detailed description, embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. As will be appreciated by those skilled in the art, the embodiments may be modified in various different ways, all without departing from the spirit and scope of the present disclosure.

[0020] In order to clarify the present disclosure, parts that are not related to the description may be omitted, and the same elements or equivalents are denoted by the same reference numerals throughout the specification.

[0021] In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively displayed for better understanding and ease of description.

[0022] It will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, the element may be directly on the other element, or intervening elements may also be present. When an element is referred to as being "directly on" another element, there are no intervening elements. In addition, in the specification, the words "on..." or "above..." mean being located on or below an object part, and do not necessarily mean being located on the upper side of the object part based on the direction of gravity.

[0023] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” and “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0024] Furthermore, in the specification, the phrase “on a plane” means a case where a subject portion is viewed from above, and the phrase “on a cross section” means a case where a cross section taken by vertically cutting the subject portion is viewed from the side.

[0025] In the following, reference is made to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A and Figure 5B A semiconductor device according to an embodiment is described.

[0026] Figure 1 is a perspective view schematically showing a semiconductor memory device according to an embodiment. Figure 2 is a top plan view schematically showing a semiconductor device according to an embodiment. Figure 3 yes Figure 2 A partial enlarged view of area R1 in FIG. Figure 4 It is along Figure 2 A cross-sectional view taken along lines AA' and BB'. Figure 5A and Figure 5B According to one or more embodiments, Figure 2 Cross-sectional views taken along lines CC', D-D' and EE'.

[0027] Reference Figures 1 to 5B , the semiconductor device 10 according to the embodiment may include a peripheral circuit structure PS, a substrate 100, and a cell array structure CS. The peripheral circuit structure PS may be located on the substrate 100. The cell array structure CS may be located on the peripheral circuit structure PS.

[0028] The substrate 100 according to the embodiment may include a cell array region CAR and a peripheral region ER. On a plane extending along the first direction X and the second direction Y, the peripheral region ER may surround the cell array region CAR.

[0029] The peripheral region ER may include a peripheral circuit region PCR. On a plane, the peripheral circuit region PCR may be arranged separately from the cell array region CAR along the first direction X. However, the present disclosure is not limited thereto, and in some embodiments, the substrate 100 may further include other regions, and some regions may be omitted. For example, the peripheral circuit region PCR located in the peripheral region ER may be omitted.

[0030] The peripheral circuit structure PS may include a core circuit SA and a peripheral circuit PC located on the substrate 100 .

[0031] The peripheral circuit structure PS may be located between the substrate 100 and the cell array structure CS along a third direction Z, and the third direction Z may be perpendicular to the upper surface of the substrate 100. Similarly, the third direction Z may be perpendicular to a plane extending along the first direction X and the second direction Y. For example, on a plane, the core circuit SA may be located in the cell array region CAR of the substrate 100, and the peripheral circuit PC may be located in the peripheral circuit region PCR of the substrate 100. For example, the core circuit SA may be located on the cell array region CAR of the substrate 100 in the third direction Z, and the peripheral circuit PC may be located on the peripheral circuit region PCR of the substrate 100 in the third direction Z. The spatial relationship between the peripheral circuit structure PS, the cell array structure CS, and the core circuit SA and the peripheral circuit PC included in the peripheral circuit structure PS is not limited thereto, and may be changed in various ways.

[0032] The cell array structure CS may include bit lines BL, word lines WL, and memory cells MC located between the bit lines BL and the word lines WL. The memory cells MC may be two-dimensionally arranged on a plane extending along a first direction X and a second direction Y. The memory cells MC may be three-dimensionally arranged on a plane extending along the first direction X and the second direction Y.

[0033] Each memory cell MC may include a selection element TR and a data storage element DS. The selection element TR and the data storage element DS may be electrically coupled in series. The selection element TR may be connected between the data storage element DS and the word line WL. The data storage element DS may be connected to the bit line BL through the selection element TR. The selection element TR may be a field effect transistor (FET). The data storage element DS may be implemented as a capacitor, a magnetic tunnel junction pattern, or a variable resistor.

[0034] The selection element TR may include a transistor, a gate electrode, and a drain terminal / source terminal. The gate electrode of the transistor may be connected to the word line WL. The drain / source terminals of the transistor may be connected to the bit line BL and the data storage element DS, respectively.

[0035] In one embodiment, a vertical channel transistor (VCT) may be included as a selection element TR of each memory cell MC. The vertical channel transistor may refer to a structure in which a channel length extends in a third direction Z perpendicular to the upper surface of the substrate 100. In addition, a capacitor may be provided as a data storage element DS of each memory cell MC.

[0036] Specifically, the substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a semiconductor on insulator (SOI) substrate. However, the material included in the substrate 100 is not limited thereto and may be changed in various ways. Hereinafter, the substrate 100 will be described as a silicon substrate.

[0037] The peripheral circuit structure PS may include a core circuit SA, a peripheral circuit PC, a peripheral circuit insulating layer ILD, a peripheral circuit contact plug PCT, and a peripheral circuit wiring PCL. On a plane, the core circuit SA and the peripheral circuit PC may be located in a cell array region (CAR) and a peripheral circuit region PCR of the substrate 100, respectively. The peripheral circuit insulating layer ILD may cover the core circuit SA and the peripheral circuit PC.

[0038] The core circuit SA and the peripheral circuit PC may include NMOS transistors and PMOS transistors integrated on the substrate 100. The core circuit SA and the peripheral circuit PC may be electrically connected to the bit lines BL and the word lines WL through the peripheral circuit wirings PCL and the peripheral circuit contact plugs PCT.

[0039] The peripheral circuit insulating layer ILD may be located on the substrate 100. The peripheral circuit insulating layer ILD may cover the core circuit SA, the peripheral circuit PC, the peripheral circuit wirings PCL, and the peripheral circuit contact plugs PCT. The peripheral circuit insulating layer ILD may have a substantially flat upper surface.

[0040] The peripheral circuit insulating layer ILD may include a multi-layer insulating layer. For example, the peripheral circuit insulating layer ILD may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and / or a low dielectric layer. However, the peripheral circuit insulating layer ILD is not limited thereto, and the composition and material of the peripheral circuit insulating layer ILD may be changed in various ways.

[0041] The cell array structure CS may be located on the peripheral circuit insulating layer ILD. The cell array structure CS may include a plurality of bit lines BL, a plurality of shielding lines SL, a shielding contact line SCL, a first insulating layer 110, a second insulating layer 111, a third insulating layer 150, and a fourth insulating layer 160, a first insulating pattern 120 and a second insulating pattern 140, a channel pattern CP, a first word line WL1 and a second word line WL2, a gate insulating pattern Gox, a bonding pad LP, and a data storage pattern DSP.

[0042] The bit line BL may be located on the substrate 100. For example, the first insulating layer 110 may be located on the substrate 100, and the bit line BL may be located on the first insulating layer 110. The first insulating layer 110 may be located between the bit line BL and the peripheral circuit wiring PCL and between the lower conductive pad LCP and the peripheral circuit wiring PCL. The first insulating layer 110 may surround the lower contact plug LCT.

[0043] The first insulating layer 110 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer. However, the first insulating layer 110 is not limited thereto, and the material included in the first insulating layer 110 may be changed in various ways.

[0044] In one embodiment, the semiconductor device 10 may include a plurality of bit lines BL. On the cell array region CAR of the substrate 100, each of the plurality of bit lines BL may extend along the second direction Y. The plurality of bit lines BL may be separately arranged along the first direction X. Here, the first direction X and the second direction Y may be parallel to the upper surface of the substrate 100.

[0045] The bit line BL may include a conductive material. For example, the bit line BL may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. The bit line BL may be made of doped polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), niobium nitride (NbN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium nitride (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), nickel silicide (NiSi), cobalt silicide (CoSi), iridium oxide (IrOx), ruthenium oxide (RuOx), or a combination thereof, but is not limited thereto, and the material included in the bit line BL may be changed in various ways.

[0046] The bit line BL may include a single layer or multiple layers of the above materials. In some embodiments, the bit line BL may include a two-dimensional material and / or a three-dimensional material (eg, graphene of a carbon-based two-dimensional material, carbon nanotube of a three-dimensional material, or a combination thereof).

[0047] On the cell array region CAR, the first contact hole CH1 may penetrate the first insulating layer 110. On the cell array region CAR, the bit line BL may be connected to the peripheral circuit wiring PCL through the lower contact plug LCT located in the first contact hole CH1 penetrating the first insulating layer 110.

[0048] Figure 2 It is shown that the first contact hole CH1 may be located on the end of the bit line BL. The lower contact plug LCT may be located in the first contact hole CH1. The lower contact plug LCT may connect the bit line BL and the peripheral circuit wiring PCL. The positions of the first contact hole CH1 and the lower contact plug LCT for connecting the bit line BL and the peripheral circuit wiring PCL are not limited thereto and may be changed in various ways.

[0049] In addition, on the peripheral circuit region PCR, the lower conductive pad LCP may be disposed at substantially the same height as the bit line BL. The lower conductive pad LCP may be connected to the peripheral circuit wiring PCL through a lower contact plug LCT penetrating the first insulating layer 110. The lower conductive pad LCP may include the same conductive material as the bit line BL.

[0050] The second insulating layer 111 may be located on the peripheral circuit insulating layer ILD. The second insulating layer 111 may be located between the bit lines BL. The second insulating layer 111 may surround the side surfaces of the first insulating layer 110 and the bit lines BL. The upper surfaces of the bit lines BL may be exposed by the second insulating layer 111.

[0051] In one embodiment, the upper surface, the bottom surface, and the side surface of the shielding line SL may be surrounded by the second insulating layer 111. The shielding line SL may be located between the bit lines BL, and the shielding line SL may be located within the second insulating layer 111. The upper surface of the shielding line SL may be lower than the upper surface of the bit line BL. That is, the shielding line SL may be buried in the second insulating layer 111.

[0052] The second insulating layer 111 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer. However, the material included in the second insulating layer 111 is not limited thereto and may be changed in various ways.

[0053] The upper surface of the shielding line SL may be located at a height between the upper surface and the bottom surface of the bit line BL. In addition, the upper surface of the shielding line SL may be located at a higher height than the upper surface of the first insulating layer 110, and the bottom surface of the shielding line SL may be located at a height between the upper surface and the bottom surface of the first insulating layer 110. However, the spatial relationship between the shielding line SL and the bit line BL and the spatial relationship between the shielding line SL and the first insulating layer 110 are not limited thereto and may be changed in various ways.

[0054] In one embodiment, the semiconductor device 10 may include a plurality of shielding lines SL. The plurality of shielding lines SL may be located between the bit lines BL. The plurality of shielding lines SL may extend along the second direction Y. The plurality of shielding lines SL may be arranged to be spaced apart along the first direction X. The plurality of shielding lines SL and the plurality of bit lines BL may extend side by side along the second direction Y, respectively, and may be alternately arranged along the first direction X. For example, the plurality of shielding lines SL may be alternately arranged with the plurality of bit lines BL.

[0055] Furthermore, in one embodiment, the shielding line SL may be located at a central portion between the bit lines BL. That is, a separation distance from the shielding line SL to the bit line BL located on the first side of the first direction X may be substantially the same as a distance from the shielding line SL to the bit line BL located on the second side of the first direction X. However, the spatial relationship between the bit line BL and the shielding line SL is not limited thereto and may be changed in various ways.

[0056] For example, the shield line SL located between the two bit lines BL may be arranged close to one of the two bit lines BL located on both sides of the shield line SL.

[0057] In one embodiment, the length of each of the plurality of shielding lines SL along the second direction Y may be longer than the length of each of the plurality of bit lines BL along the second direction Y. That is, on a plane, unlike the plurality of bit lines BL located in the cell array region CAR, each of the plurality of shielding lines SL may extend from the cell array region CAR toward the peripheral region ER along the second direction Y. That is, the plurality of shielding lines SL may extend from the cell array region CAR along the second direction Y to reach the peripheral region ER.

[0058] In one embodiment, on a plane, a portion of each of the plurality of shielding lines SL may be located in the cell array region CAR, and the remaining portion may be located in the peripheral region ER. However, the length of the shielding lines SL and the bit lines BL along the second direction Y is not limited thereto and may be changed in various ways.

[0059] The shielding line SL may include a conductive material. For example, the shielding line SL may include a metal material (such as tungsten (W), titanium (Ti), nickel (Ni), cobalt (Co), or a combination thereof). In some embodiments, the shielding line SL may include a two-dimensional material and / or a three-dimensional material (for example, graphene of a carbon-based two-dimensional material, carbon nanotubes of a three-dimensional material, or a combination thereof).

[0060] In one embodiment, the bit line BL and the shield line SL may include different materials. For example, the bit line BL includes any one of doped polysilicon, aluminum (Al), and copper (Cu), and the shield line SL may include any one of tungsten (W), titanium (Ti), nickel (Ni), and cobalt (Co). However, the present disclosure is not limited thereto, and in some embodiments, the bit line BL and the shield line SL may include the same material.

[0061] On a plane, the shielding line SL may be located in the peripheral region ER of the substrate 100. The shielding line SL may be connected to the shielding contact line SCL extending in the first direction X. Each of the plurality of shielding lines SL may extend from the cell array region CAR of the substrate 100 toward the peripheral region ER in the second direction Y, and an end of each of the plurality of shielding lines SL located in the peripheral region ER of the substrate 100 may be connected to the shielding contact line SCL located in the peripheral region ER of the substrate 100.

[0062] On a plane, since the shielding contact line SCL may be located in the peripheral region ER of the substrate 100, the shielding contact line SCL may be spaced apart from the cell array region CAR along the second direction Y. That is, on a plane, a portion of the shielding line SL extending along the second direction Y may be located between the cell array region CAR and the shielding contact line SCL.

[0063] The plurality of shielding lines SL can reduce coupling capacitance caused by mutual interference between the bit lines BL arranged adjacent to each other. The shielding contact line SCL can be connected to a wiring for applying a voltage to the shielding line SL. A voltage can be applied from the wiring to each of the plurality of shielding lines SL connected to the shielding contact line SCL. That is, each of the plurality of shielding lines SL can be connected to a wiring or circuit for applying a voltage to each of the plurality of shielding lines SL through the shielding contact line SCL.

[0064] In one embodiment, the shielding contact line SCL may be connected to the wiring for applying a voltage to the shielding line SL through the second contact hole CH2 located on the peripheral region ER of the substrate 100. However, the position at which the shielding contact line SCL and the wiring for applying a voltage to the shielding line SL are connected and the number of contact holes are not limited thereto and may be changed in various ways.

[0065] Figure 2It is shown that the shielding contact line SCL may be located only at one side of the second direction Y of the cell array region CAR, but the position and number of the shielding contact line are not limited thereto and may be changed in various ways.

[0066] In one embodiment, the shielding wire SL and the shielding contact wire SCL may be formed as an integral unit. That is, the shielding wire SL and the shielding contact wire SCL may be formed simultaneously by the same process, thereby being integrally constructed. However, the shielding wire SL and the shielding contact wire SCL are not limited thereto, and in some embodiments, the shielding wire SL and the shielding contact wire SCL may be formed by separate processes and may be formed as separate structures.

[0067] The shielding contact line SCL may be located at substantially the same height as the shielding line SL. That is, the shielding contact line SCL may be located within the second insulating layer 111. In one embodiment, the upper surface of the shielding contact line SCL may be located at a height between the upper surface and the bottom surface of the bit line BL. In addition, the upper surface, the bottom surface, and the side surface of the shielding contact line SCL may be surrounded by the second insulating layer 111. However, the spatial relationship between the shielding contact line SCL and the shielding line SL is not limited thereto and may be changed in various ways.

[0068] In one embodiment, the shielding contact line SCL may include the same material as the material included in the shielding line SL. However, the material included in the shielding contact line SCL is not limited thereto and may be changed in various ways. For example, as described above, when the shielding line SL and the shielding contact line SCL are formed by separate processes and consist of separate structures, the shielding contact line SCL may include a material different from that of the shielding line SL.

[0069] The shielding line SL may have a first width W1 , the bit line BL may have a second width W2 , and the shielding contact line SCL may have a third width W3 .

[0070] Here, the width refers to the width along the direction perpendicular to the extension direction of each line. For example, the first width W1 of the shielding line SL and the second width W2 of the bit line BL may refer to the width along the first direction X, and the third width W3 of the shielding contact line SCL may refer to the width along the second direction Y.

[0071] In one embodiment, at least one of the first width W1, the second width W2, and the third width W3 may be different. For example, the first width W1 may be smaller than the second width W2 and the third width W3, and the second width W2 may be smaller than the third width W3. That is, the third width W3 may be the largest, and the first width W1 may be the smallest.

[0072] That is, the width of the shielding line SL may be smaller than the width of the bit line BL and the width of the shielding contact line SCL, and the width of the bit line BL may be smaller than the width of the shielding contact line SCL. However, the relationship between the width of the bit line BL, the width of the shielding line SL, and the width of the shielding contact line SCL is not limited thereto, and may be changed in various ways. For example, the first width W1 and the second width W2 may be substantially equal, and the third width W3 may be greater than the first width W1 and the second width W2.

[0073] The first insulating pattern 120 may be located on the bit line BL and the second insulating layer 111. The first insulating pattern 120 may define trenches TRC that intersect the bit line BL, extend in the first direction X, and are spaced apart from each other in the second direction Y. The first insulating pattern 120 may cover an upper surface of the lower conductive pad LCP on the peripheral circuit region PCR.

[0074] The first insulating pattern 120 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a smaller dielectric constant than silicon oxide, but is not limited thereto.

[0075] For example, the low-k material may include at least flowable oxide (FOX), torene silazene (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), FSG (fluoride silicate glass), CDO (carbon-doped silicon oxide), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material, or a combination thereof, but the present disclosure is not limited thereto and may be changed in various ways.

[0076] The channel patterns CP may be disposed on the bit lines BL. The channel patterns CP may be spaced apart from each other along the second direction Y on each bit line BL. That is, the channel patterns CP may be spaced apart from each other along the first direction X and the second direction Y intersecting each other to be arranged in a matrix form.

[0077] In addition, the channel pattern CP may not overlap with the shielding line SL located between the bit lines BL along the third direction Z perpendicular to the substrate. That is, on a plane, the channel pattern CP may not overlap with the shielding line SL. In other words, on a plane, the channel patterns CP may be arranged at intervals along the first direction X, and the shielding line SL is placed between the channel patterns CP. However, the spatial relationship between the channel pattern CP and the shielding line SL is not limited thereto, and may be changed in various ways. For example, on a plane, the channel pattern CP may overlap with at least a portion of the shielding line SL.

[0078] The channel pattern CP may include a first source / drain region and a second source / drain region. For example, a lower portion of the channel pattern CP may be used as the first source / drain region by being connected to the bit line BL, and an upper portion of the channel pattern CP may be used as the second source / drain region by being connected to the bonding pad LP, and a portion of the channel pattern CP between the first source / drain region and the second source / drain region may be used as a channel region.

[0079] In one embodiment, in cross section, the channel pattern CP may have substantially a "U" shape. Specifically, the channel pattern CP may be disposed on the sidewall of the trench TRC. The channel pattern CP may extend along the profile of the trench TRC in the first direction X. The channel pattern CP may include a plurality of portions in the trench TRC. Portions of the channel pattern CP within the same trench TRC may be arranged separately from each other along the first direction X. The channel patterns CP in different trenches TRC may be arranged separately from each other along the second direction Y. That is, the first insulating pattern 120 may be located between the channel patterns CP adjacent to each other along the second direction Y.

[0080] Each of the channel patterns CP may include a horizontal portion extending in the second direction Y and disposed on the bit line BL and vertical portions extending from ends of the horizontal portion in a third direction Z perpendicular to the substrate 100 and facing each other in the second direction Y.

[0081] The channel pattern CP may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium tin zinc oxide (ITZO), indium gallium tin oxide (IGTO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZZTO), tin oxide (SnO), hafnium indium zinc oxide (HIZO), gallium zinc tin oxide (GZTO), aluminum zinc tin oxide (AZTO), ytterbium gallium zinc oxide (YGZO), indium gallium oxide (IGO), or a combination thereof. However, the oxide semiconductor material is not limited thereto and may be changed in various ways.

[0082] In some embodiments, the channel pattern CP may include a single layer or multiple layers of the oxide semiconductor material described above. In some embodiments, the channel pattern CP may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include, for example, graphene, carbon nanotubes, or a combination thereof.

[0083] The word lines WL1 and WL2 may intersect the bit lines BL and the shield lines SL, extend in the first direction X, and be spaced apart in the second direction Y. A pair of word lines WL1 and WL2 may be located on the channel pattern CP in one trench TRC.

[0084] Specifically, each of the word lines WL1 and WL2 includes one side surface and another side surface opposite to the one side surface, and the one side surface of the word line WL1 and the one side surface of WL2 may be disposed to face each other on the channel pattern CP.

[0085] One side surface of the word line WL1 and one side surface of the word line WL2 may contact the second insulating pattern 140 , and the other side surface of the word line WL1 and the other side surface of WL2 may contact the gate insulating pattern Gox.

[0086] The word lines WL1 and WL2 may include upper and bottom surfaces facing each other in the third direction Z. The upper surfaces of the word lines WL1 and WL2 may contact the second insulating pattern 140 and may face the bonding pad LP interposed therebetween.

[0087] In one embodiment, the upper surfaces of the word lines WL1 and WL2 may be located at a higher height than the upper surface of the channel pattern CP and at a lower height than the upper surface of the first insulating pattern 120. However, the spatial relationship between the upper surfaces of the word lines WL1 and WL2, the upper surface of the channel pattern CP, and the upper surface of the first insulating pattern 120 is not limited thereto and may be changed in various ways.

[0088] Bottom surfaces of the word lines WL1 and WL2 may contact the gate insulating pattern Gox described herein and may face the bit line BL with the gate insulating pattern Gox and the channel pattern CP interposed therebetween.

[0089] The word lines WL1 and WL2 may include a conductive material, such as doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0090] As another example, word lines WL1 and WL2 may be formed of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof, but are not limited thereto, and the materials included in word lines WL1 and WL2 may be changed in various ways.

[0091] The word lines WL1 and WL2 may include a single layer or multiple layers of the above materials. In some embodiments, the word lines WL1 and WL2 may include a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0092] In one embodiment, in cross section, the gate insulating pattern Gox may have a “U” shape. For example, the gate insulating pattern Gox may be located between the channel pattern CP and the word lines WL1 and WL2. The gate insulating pattern Gox may be conformally located on a surface of the channel pattern CP within the trench TRC.

[0093] The gate insulating pattern Gox may conformally cover the surfaces of the word lines WL1 and WL2. That is, the gate insulating pattern Gox may be located between the bottom surfaces of the word lines WL1 and WL2 and the horizontal portion of the channel pattern CP, and between the other side surfaces of the word lines WL1 and WL2 and the vertical portion of the channel pattern CP, and may cover the bottom surfaces of the word lines WL1 and WL2.

[0094] In addition, the gate insulating pattern Gox may be located between the word lines WL1 and WL2 and the first insulating pattern 120 .

[0095] The upper surface of the gate insulating pattern Gox may be located at a higher height than the upper surface of the channel pattern CP and the upper surfaces of the word lines WL1 and WL2, and may be located at substantially the same height as the upper surface of the first insulating pattern 120. However, the spatial relationship between the upper surface of the channel pattern CP, the upper surfaces of the word lines WL1 and WL2, and the upper surface of the first insulating pattern 120 and the upper surface of the gate insulating pattern Gox is not limited thereto, and may be changed in various ways.

[0096] The gate insulating pattern Gox may be formed of a silicon oxide layer, a silicon oxynitride layer, a high dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof. The high dielectric layer may be made of a metal oxide or a metal oxynitride. For example, the high dielectric layer that may be used as the gate insulating layer may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto, and the material included in the gate insulating pattern Gox may be changed in various ways.

[0097] The second insulating pattern 140 may be located in the trench TRC. After forming the channel pattern CP, the gate insulating pattern Gox, and the word lines WL1 and WL2, the second insulating pattern 140 may fill the remaining trench TRC area. The second insulating pattern 140 may be located on the upper surface and the side surface of the word lines WL1 and WL2, and may extend along the second direction Y and the third direction Z. In one embodiment, in cross section, the second insulating pattern 140 may substantially have a "T" shape. However, the shape of the second insulating pattern 140 in cross section is not limited thereto, and may be modified in various ways.

[0098] In some embodiments, the gate insulating pattern Gox may be further located between the word lines WL1 and WL2 and the second insulating pattern 140. That is, the gate insulating pattern Gox may be located between the word lines WL1 and WL2 and the second insulating pattern 140, and may be conformally arranged along an upper surface and one side surface of the word line WL1 and an upper surface and one side surface of the word line WL2.

[0099] The upper surface of the second insulating pattern 140 may be located at substantially the same height as the upper surface of the first insulating pattern 120 and the upper surface of the gate insulating pattern Gox. The upper surface of the second insulating pattern 140 may be located at a higher height than the upper surface of the channel pattern CP and the upper surfaces of the word lines WL1 and WL2. However, the present disclosure is not limited thereto, and the spatial relationship between the upper surface of the first insulating pattern 120, the upper surface of the gate insulating pattern Gox, the upper surface of the channel pattern CP, and the upper surfaces of the word lines WL1 and WL2 and the upper surface of the second insulating pattern 140 may be changed in various ways.

[0100] The second insulating pattern 140 may include at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, and a low dielectric constant (low-k) material having a smaller dielectric constant than silicon oxide, however the present disclosure is not limited and the material included in the second insulating pattern 140 may be changed in various ways.

[0101] The bonding pad LP may be arranged to overlap at least a portion of the channel pattern CP along a third direction Z, and the third direction Z may be a direction perpendicular to the substrate 100 .

[0102] The semiconductor device 10 according to the embodiment may include a plurality of bonding pads LP. The plurality of bonding pads LP may be spaced apart from each other along the first direction X and the second direction Y, thereby being arranged in a matrix form. However, this is an example, and the plurality of bonding pads LP connected to the channel pattern CP may be arranged in various other shapes, such as a honeycomb shape.

[0103] In one embodiment, the bonding pad LP has a circular shape on a plane, but the present disclosure is not limited thereto, and the shape of the bonding pad LP on a plane may be changed in various ways. For example, the shape of the bonding pad LP on a plane may have various shapes (such as an ellipse, rectangle, square, diamond, or hexagon).

[0104] The bonding pad LP may be in direct contact with the channel pattern CP and connected to a vertical portion of the channel pattern CP.

[0105] A portion of the bonding pad LP may be located at a higher height than the upper surfaces of the first insulation pattern 120, the second insulation pattern 140, and the gate insulation pattern Gox, and the remaining portion may be located at a lower height than the upper surfaces of the first insulation pattern 120, the second insulation pattern 140, and the gate insulation pattern Gox.

[0106] In detail, the bonding pad LP may include a first portion extending in the second direction Y and a second portion extending in the third direction Z from the first portion.

[0107] The first portion of the landing pad LP may be located at a higher height than upper surfaces of the first insulating pattern 120 , the second insulating pattern 140 , and the gate insulating pattern Gox.

[0108] The second portion of the landing pad LP may be located at a lower height than upper surfaces of the first insulation pattern 120 , the second insulation pattern 140 , and the gate insulation pattern Gox and directly contact the upper surface of the channel pattern CP.

[0109] Figure 4 It is shown that the bottom surface of the first portion of the bonding pad LP may be located at substantially the same height as the upper surface of the first insulation pattern 120 and the upper surface of the second insulation pattern 140, however the present disclosure is not limited thereto. In some embodiments, the bottom surface of the first portion of the bonding pad LP may be located at a lower height than the upper surface of the first insulation pattern 120 and the upper surface of the second insulation pattern 140.

[0110] One side of the second portion of the landing pad LP may be in contact with the first insulating pattern 120 , and the other side of the second portion of the landing pad LP may be in contact with the gate insulating pattern Gox.

[0111] The bottom surface of the second portion of the bonding pad LP may be located at a lower height than the upper surfaces of the word lines WL1 and WL2. However, the spatial relationship between the bottom surface of the second portion of the bonding pad LP and the upper surfaces of the word lines WL1 and WL2 is not limited thereto and may be changed in various ways. For example, the bottom surface of the second portion of the bonding pad LP may be located at substantially the same height as the upper surfaces of the word lines WL1 and WL2, or at a higher height than the upper surfaces of the word lines WL1 and WL2.

[0112] The bonding pad LP may include a conductive material, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0113] As another example, the bonding pad LP may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto and may be changed in various ways.

[0114] The third insulating layer 150 may be located over the first and second insulating patterns 120 and 140 , and may fill spaces between the bonding pads LP spaced apart in the second direction Y. That is, the bonding pads LP may be separated and insulated from each other by the third insulating layer 150 .

[0115] The bottom surface of the third insulating layer 150 may be located at substantially the same height as the bottom surface of the first portion of the bonding pad LP. However, the present disclosure is not limited thereto, and in some embodiments, the bottom surface of the third insulating layer 150 may be located at a different height than the bottom surface of the first portion of the bonding pad LP.

[0116] The third insulating layer 150 may include the same material as the first insulating layer 110 and the second insulating layer 111 described herein. However, the present disclosure is not limited thereto, and the material included in the third insulating layer 150 may be changed in various ways.

[0117] The plurality of data storage patterns DSP may be respectively located on the plurality of bonding pads LP. The plurality of data storage patterns DSP may be respectively electrically connected to the channel patterns CP via the plurality of bonding pads LP.

[0118] like Figure 2 As shown in , the data storage patterns DSP may be arranged in a matrix form along the first direction X and the second direction Y. However, this is an example, and on a plane, the data storage patterns DSP connected to the bonding pads LP may have various arrangements.

[0119] In one embodiment, the data storage pattern DSP may be a capacitor and may include a lower electrode, an upper electrode, and a capacitor dielectric layer disposed between the lower electrode and the upper electrode. When the data storage pattern DSP has the above structure, the lower electrode may contact the bonding pad LP, and on a plane, the lower electrode may have various shapes (such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, or a hexagonal shape).

[0120] In contrast, the data storage pattern DSP may be a variable resistor pattern that can be switched in two resistance states by an electric pulse applied to the memory element. For example, the data storage pattern DSP may include a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, an antiferromagnetic material, or a phase change material whose crystal state changes according to the amount of current.

[0121] The fourth insulating layer 160 may be located on the third insulating layer 150. The fourth insulating layer 160 may cover the data storage pattern DSP on the cell array region CAR. That is, the fourth insulating layer 160 may cover the upper surface and the side surface of the data storage pattern DSP.

[0122] The fourth insulating layer 160 may include the same material as the third insulating layer 150. However, the present disclosure is not limited thereto, and the material included in the fourth insulating layer 160 may be changed in various ways.

[0123] The connection line CL may be located over the fourth insulating layer 160 on the peripheral region ER and the peripheral circuit region PCR of the substrate 100. The connection line CL may be a first conductive pattern.

[0124] In detail, Figure 2 , Figure 5A and Figure 5B As shown in FIG. 1 , on the peripheral region ER, the connection line CL may be connected to the shielding contact line SCL. The connection line CL may be connected to the shielding contact line SCL through the second contact hole CH2 located on the peripheral region ER. That is, the second contact hole CH2 may sequentially pass through the fourth insulating layer 160, the third insulating layer 150, and the first insulating pattern 120 to expose the upper surface of the shielding contact line SCL located in the second insulating layer 111.

[0125] In the second contact hole CH2, a first conductive via UVP1 electrically connecting the shielding contact line SCL and the connection line CL may be disposed. That is, the first conductive via UVP1 electrically connecting the shielding contact line SCL and the connection line CL may be located on the shielding contact line SCL.

[0126] The first conductive via UVP1 may include at least one metal among aluminum, copper, tungsten, molybdenum, and cobalt, but is not limited thereto and may be changed in various ways.

[0127] exist Figure 5A In the embodiment, the first conductive via UVP1 may be directly connected to the shielding contact line SCL and the connection line CL, but the connection relationship between the shielding contact line SCL and the connection line CL is not limited thereto and may be changed in various ways. Figure 5B As shown in FIG, the first conductive via UVP1 may connect the shielding contact line SCL and the connection line CL through the upper conductive pad UCP.

[0128] Specifically, the second contact hole CH2 located on the peripheral region ER of the substrate 100 may include a second lower contact hole CH2a that penetrates the first insulating pattern 120 and exposes the upper surface of the shielding contact line SCL located in the second insulating layer 111, and a second upper contact hole CH2b that penetrates the fourth insulating layer 160 and exposes the upper surface of the upper conductive pad UCP located in the third insulating layer 150.

[0129] The upper conductive pad UCP may be located on the first insulating pattern 120 and within the third insulating layer 150. The upper conductive pad UCP may include the same conductive material as the landing pad LP.

[0130] In addition, the first conductive via UVP1 may include a first lower conductive via UVP1a and a first upper conductive via UVP1b.

[0131] The first lower conductive via UVP1a may be located in the second lower contact hole CH2a and connect the shielding contact line SCL and the upper conductive pad UCP. The first upper conductive via UVP1b may be located in the second upper contact hole CH2b and connect the upper conductive pad UCP and the connection line CL.

[0132] In one embodiment, the shielding contact line SCL may be electrically connected to the connection line CL.

[0133] On the peripheral circuit region PCR of the substrate 100 , the lower conductive pad LCP may be connected to the connection line CL located on the fourth insulating layer 160 through the second conductive via UVP2 .

[0134] In detail, the third contact hole CH3 located on the peripheral circuit region PCR of the substrate 100 may include a third lower contact hole CH3a penetrating the first insulating pattern 120 and exposing the upper surface of the lower conductive pad LCP located on the first insulating layer 110, and a third upper contact hole CH3b penetrating the fourth insulating layer 160 and exposing the upper surface of the upper conductive pad UCP located in the third insulating layer 150.

[0135] In addition, the second conductive via UVP2 may include a second lower conductive via UVP2a and a second upper conductive via UVP2b.

[0136] The second lower conductive via UVP2a may be located in the third lower contact hole CH3a and connect the lower conductive pad LCP and the upper conductive pad UCP. The second upper conductive via UVP2b may be located in the third upper contact hole CH3b and connect the upper conductive pad UCP and the connection line CL. In one embodiment, the lower conductive pad LCP may be electrically connected to the connection line CL.

[0137] The second conductive via UVP2 may include the same material as the first conductive via UVP1 described above. However, the present disclosure is not limited thereto, and in some embodiments, the second conductive via UVP2 may include a material different from that of the first conductive via UVP1.

[0138] Based on the semiconductor device 10 according to the embodiment, the shield line SL may be located on the peripheral region ER of the substrate 100 and may be electrically connected to a wiring or circuit applying a voltage to the shield line SL through a shield contact line SCL connected to the shield line SL.

[0139] The shielding contact line SCL located on the peripheral region ER of the substrate 100 and connected to the shielding line SL may be formed to have a relatively wide width compared with the shielding line SL formed on the cell array region CAR of the substrate 100 .

[0140] In one embodiment, when the wiring for applying a voltage is connected to the shielding line SL and the shielding contact line SCL through the conductive via, a wide contact area of ​​the conductive via and the shielding contact line SCL may be ensured.

[0141] Therefore, in a process of forming a conductive via to electrically connect a wiring applying a voltage to the shield line SL and the shield contact line SCL, a contact area between the wirings may be prevented from being reduced due to misalignment, thereby reducing defects of the semiconductor device 10 .

[0142] Reference Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig. 10A , Fig. 10B and Fig. 10C In the following embodiments, the same reference numerals denote the same configurations as those of the previously described embodiments, and redundant descriptions may be omitted or simplified, and the differences will be mainly described.

[0143] Figure 6 is a top plan view schematically showing a semiconductor device according to another embodiment. Figure 7 According to another embodiment, Figure 6 A cross-sectional view taken along line F-F'.

[0144] Specifically, Figure 6 and Figure 7 1 is a diagram for illustrating a connection relationship between a shield contact line SCL located in a peripheral region ER of the substrate 100 on a plane and a peripheral circuit PC located in a peripheral circuit region PCR of the substrate 100 on a plane.

[0145] according to Figure 6 and Figure 7In the semiconductor device 10_1 shown in FIG. 1 , on a plane, the shielding contact line SCL located in the peripheral region ER of the substrate 100 can be electrically connected to the peripheral circuit region PCR through the connection line CL, which extends along the first direction X from the end of the shielding contact line SCL toward the peripheral circuit region PCR.

[0146] That is, the shielding contact line SCL may be connected to the connection line CL through the second contact hole CH2 on the substrate 100, and the connection line CL may be connected to one of the peripheral circuits PC through the third contact hole CH3 on the peripheral circuit region PCR.

[0147] In detail, on the peripheral region ER of the substrate 100 , the shielding contact line SCL and the connection line CL may be electrically connected through the first conductive via UVP1 located in the second contact hole CH2 described above.

[0148] On the peripheral circuit region PCR of the substrate 100 , the connection line CL may be connected to the upper conductive pad UCP through the second upper conductive via UVP2 b , and the upper conductive pad UCP may be connected to the lower conductive pad LCP through the second lower conductive via UVP2 a .

[0149] The lower conductive pad LCP may be connected to the peripheral circuit PC through the lower contact plug LCT. Here, the peripheral circuit PC may be a circuit for applying a voltage to the shielding line SL.

[0150] In one embodiment, the peripheral circuit PC can be connected to the shielding contact line SCL through the connection line CL, and a voltage is applied to the shielding line SL through the shielding contact line SCL. However, the connection relationship between the connection line CL and the peripheral circuit PC on the peripheral circuit region PCR of the substrate 100 is not limited thereto and can be changed in various ways.

[0151] For example, the third contact hole CH3 may sequentially penetrate the fourth insulating layer 160, the third insulating layer 150, the first insulating pattern 120, and the second insulating layer 111 and expose the peripheral circuit PC located in the peripheral circuit insulating layer ILD. The second conductive via UVP2 may be integrally formed and located in the third contact hole CH3.

[0152] In one embodiment, the second conductive via UVP2 may directly connect the peripheral circuit PC and the connection line CL.

[0153] Figure 7 It is shown that the shielding contact line SCL located on the peripheral region ER of the substrate 100 may be connected to the peripheral circuit PC located on the peripheral circuit region PCR through the connection line CL located on the fourth insulating layer 160 , but the present disclosure is not limited thereto.

[0154] For example, the shielding contact line SCL may be electrically connected to other conductive patterns located at a higher or lower height than the connection line CL located on the upper surface of the fourth insulating layer 160 , thereby being connected to the peripheral circuit PC located on the peripheral circuit region PCR.

[0155] also, Figure 7 It is shown that the shielding contact line SCL may be electrically connected to the connection line CL through the second contact hole CH2 located on the shielding contact line SCL, but the present disclosure is not limited thereto.

[0156] For example, the shielding contact line SCL may be electrically connected to a conductive pattern located at a lower height than the shielding contact line SCL through a contact hole located below the shielding contact line SCL.

[0157] Furthermore, in some embodiments, the shielding contact line SCL located in the peripheral region ER of the substrate 100 on a plane may be electrically connected to a circuit other than the peripheral circuit PC located in the peripheral circuit region PCR.

[0158] For example, the shielding contact line SCL may be electrically connected to a circuit located in a peripheral region ER of the substrate 100 on a plane, and a voltage may be applied to the shielding line SL through a connecting line CL other than a core circuit SA located in a cell array region CAR of the substrate 100 on a plane or a peripheral circuit PC located in the peripheral region ER on a plane.

[0159] Figures 8 to 10C Schematically illustrates a plan view of a semiconductor device according to some embodiments. Figures 8 to 10C Semiconductor devices according to some embodiments are further described.

[0160] according to Figure 8 In the embodiment shown in FIG. 1 , the second contact hole CH2 exposing the shielding contact line SCL on the peripheral region ER of the substrate 100 may be arranged to overlap a portion of the shielding contact line SCL.

[0161] Specifically, the first conductive via (in the Figure 7 The second contact hole CH2 (referred to as "UVP1") in which the shielding contact line SCL may be disposed may be arranged to overlap a portion of the shielding contact line SCL. In one embodiment, the first conductive via UVP1 located in the second contact hole CH2 may contact a portion of the upper surface of the shielding contact line SCL.

[0162] Even in the case of the semiconductor device 10_2, like the semiconductor device 10 according to the embodiment, on a plane, the shielding contact line SCL located in the peripheral region ER of the substrate 100 and connected to the shielding line SL can be formed to have a relatively wide width compared to the shielding line SL formed in the cell array region CAR of the substrate 100.

[0163] In one embodiment, since the conductive via located in the second contact hole CH2 contacts a portion of the shielding contact line SCL, the second contact hole CH2 can be formed to expose the portion of the shielding contact line SCL, and the shielding contact line SCL and the connecting line CL can be connected on the peripheral region ER of the substrate 100, which can ensure a wide contact area with the conductive via, etc.

[0164] In addition, since the second contact hole CH2 is formed to expose the portion of the shielding contact line SCL, when the conductive via located in the second contact hole CH2 contacts the portion of the shielding contact line SCL, the shielding contact line SCL and the conductive via can ensure a contact area above a certain level. In one embodiment, the spatial relationship between the fine patterns constituting the semiconductor device 10_2 can be diverse.

[0165] according to Fig. 9 In the semiconductor device 10_3 shown in FIG. 1 , the peripheral region ER of the substrate 100 may include a plurality of contact holes exposing the shielding contact lines SCL on a plane.

[0166] In detail, on the plane, Fig. 9 The semiconductor device 10_3 in the peripheral region ER of the substrate 100 may include a second contact hole CH2 located at an end of the shield contact line SCL in the first direction X and a fourth contact hole CH4 located at the other end of the shield contact line SCL in the first direction X.

[0167] Although not shown, the shielding contact line SCL and the connection wiring (refer to Figure 5A The conductive vias of the second contact hole CH2 and the fourth contact hole CH4 may be located in the second contact hole CH2 and the fourth contact hole CH4, respectively. For example, the first conductive via UVP1 may be located in the second contact hole CH2 and the fourth contact hole CH4, respectively.

[0168] That is, as described above, the first conductive vias UVP1 respectively located in the second contact hole CH2 and the fourth contact hole CH4 may electrically connect the shielding contact line SCL and the connection line CL.

[0169] In one embodiment, the first conductive via UVP1 may be electrically connected to the connection line CL, and the first conductive via UVP1 may be electrically connected to a circuit that applies a voltage to the shielding line SL.

[0170] In some embodiments, the connection forms of the first conductive via UVP1 and the connection line CL respectively located in the second contact hole CH2 and the fourth contact hole CH4 may vary.

[0171] For example, the first conductive via UVP1 located in the second contact hole CH2 may have Figure 5A The connection form of the conductive via UVP1 shown in FIG. 1 and the first conductive via UVP1 located in the fourth contact hole CH4 may have Figure 5B The connection form of the first conductive via UVP1 is shown in FIG.

[0172] Fig. 9 The second and fourth contact holes CH2 and CH4 showing the upper surface of the shielding contact line SCL exposed to connect the shielding contact line SCL and the connection line CL may be located on one side of the first direction X and the other side of the first direction X of the shielding contact line SCL, respectively, but the positions and numbers of the second and fourth contact holes CH2 and CH4 are not limited thereto.

[0173] For example, each of the second contact hole CH2 and the fourth contact hole CH4 may be located only at one end or the other end of the shielding contact line SCL in the first direction X, or only at the central portion of the shielding contact line SCL. In addition, at least one of the second contact hole CH2 and the fourth contact hole CH4 may expose at least a portion of the shielding contact line SCL.

[0174] As another example, a plurality of contact holes exposing the shielding contact line SCL other than the second contact hole CH2 and the fourth contact hole CH4 may be included.

[0175] According to the semiconductor device 10_3 , since a plurality of contact holes connecting the shield contact line SCL and the connection line CL are formed, the electrical characteristics of the semiconductor device 10_3 may be improved by reducing the resistance applied to the shield contact line SCL.

[0176] according to FIG. 10A to FIG. 10C In the semiconductor devices 10_4 , 10_5 , and 10_6 shown in FIG. 1 , a plurality of shield contact lines SCL_1 and SCL_2 may be located in the peripheral region ER of the substrate 100 on a plane.

[0177] In detail, on the plane, according to Fig. 10AThe semiconductor device 10_4 may include a first shielding contact wire SCL_1 and a second shielding contact wire SCL_2, the first shielding contact wire SCL_1 extending along the first direction X in a peripheral region ER located on one side of a cell array region CAR in the second direction Y of the substrate 100, and the second shielding contact wire SCL_2 extending along the first direction X in a peripheral region ER located on the other side of the cell array region CAR in the second direction Y. That is, the first shielding contact wire SCL_1 and the second shielding contact wire SCL_2 may be arranged apart from each other along the second direction Y, with the cell array region CAR being placed between the first shielding contact wire SCL_1 and the second shielding contact wire SCL_2.

[0178] The plurality of shielding lines SL may extend from the cell array region CAR of the substrate 100 toward the peripheral region ER along one side and the other side of the second direction Y, respectively, to be connected to the first shielding contact line SCL_1 and the second shielding contact line SCL_2, respectively. That is, each of the plurality of shielding lines SL may be connected to the first shielding contact line SCL_1 at one end in the second direction Y, and may be connected to the second shielding contact line SCL_2 at the other end in the second direction Y.

[0179] In one embodiment, the first shielding contact wire SCL_1, the second shielding contact wire SCL_2, and the plurality of shielding wires SL may be formed integrally. However, the present disclosure is not limited thereto, and the first shielding contact wire SCL_1, the second shielding contact wire SCL_2, and the plurality of shielding wires SL may be formed as separate structures by separate processes. When the first shielding contact wire SCL_1 and the second shielding contact wire SCL_2 are configured as separate structures, the first shielding contact wire SCL_1 and the second shielding contact wire SCL_2 may be located at different layers and at different heights.

[0180] The first shielding contact line SCL_1 may have a first length D1 along the first direction X, and the second shielding contact line SCL_2 may have a second length D2 along the first direction X. Fig. 10A , the first length D1 and the second length D2 are shown to be substantially the same, but the present disclosure is not limited thereto.

[0181] For example, the first length D1 and the second length D2 may be different. That is, the first length D1 and the second length D2 may be different according to the area of ​​the peripheral region ER of the substrate 100 where the first and second shielding contact wires SCL_1 and SCL_2 are located.

[0182] The first shielding contact line SCL_1 may have a third width W3 along the second direction Y, and the second shielding contact line SCL_2 may have a fourth width W4 along the second direction Y. Here, the width may refer to a width along the second direction Y. Fig. 10A, the third width W3 and the fourth width W4 are illustrated as being substantially the same, but the present disclosure is not limited thereto.

[0183] For example, the third width W3 and the fourth width W4 may be different. That is, the third width W3 and the fourth width W4 may be different according to the area of ​​the peripheral region ER of the substrate 100 where the first and second shielding contact lines SCL_1 and SCL_2 are located.

[0184] In some embodiments, the areas of the first and second shielding contact lines SCL_1 and SCL_2 on a plane may be different. For example, the first length D1 and the second length D2 may be substantially the same, and the third width W3 and the fourth width W4 may be different.

[0185] As another example, the first length D1 and the second length D2 may be different, and the third width W3 and the fourth width W4 may be substantially the same.

[0186] As another example, the first length D1 and the second length D2 may be different, and the third width W3 and the fourth width W4 may be different.

[0187] The semiconductor device 10_4 according to the embodiment may include a second contact hole CH2 and a fourth contact hole CH4, the second contact hole CH2 exposing the first shielding contact line SCL_1 to electrically connect the first shielding contact line SCL_1 and the connection wiring (refer to Figure 5A The fourth contact hole CH4 exposes the second shielding contact line SCL_2 to electrically connect the second shielding contact line SCL_2 and the connection line CL in the other side of the peripheral region ER of the substrate 100.

[0188] Fig. 10A It is shown that each of the second contact hole CH2 and the fourth contact hole CH4 may be located at the end of the first shielding contact line SCL_1 and the second shielding contact line SCL_2 in the first direction X, but the position of each of the second contact hole CH2 and the fourth contact hole CH4 is not limited thereto. Fig. 10B As shown in , the second contact hole CH2 may be located at an end of the first shielding contact line SCL_1 in the first direction X, and the fourth contact hole CH4 may be located at the other end of the second shielding contact line SCL_2 in the first direction X.

[0189] also, Fig. 10A It is shown that a contact hole may be located in each of the first and second shielding contact lines SCL_1 and SCL_2 , but the present disclosure is not limited and a plurality of contact holes may be located in each of the first and second shielding contact lines SCL_1 and SCL_2 .

[0190] As another example, at least one of the second contact hole CH2 and the fourth contact hole CH4 may expose at least a portion of the shielding contact line SCL (eg, the first shielding contact line SCL_1 and the second shielding contact line SCL_2 ).

[0191] Although not shown, conductive vias electrically connecting the shielding contact line SCL and the connection line CL may be located in the second contact hole CH2 and the fourth contact hole CH4, respectively. For example, the first conductive via UVP1 may be located in the second contact hole CH2 and the fourth contact hole CH4, respectively.

[0192] As described above, the first conductive vias UVP1 respectively located in the second contact hole CH2 and the fourth contact hole CH4 may electrically connect the shielding contact line SCL and the connection line CL.

[0193] In one embodiment, the first conductive via UVP1 may be electrically connected to the connection line CL, and the connection line CL may be electrically connected to a circuit for applying a voltage to the shielding line SL.

[0194] For example, the first conductive via UVP1 located in the second contact hole CH2 and the first conductive via UVP1 located in the fourth contact hole CH4 are connected to the same connection line CL, and the same voltage may be applied to the shielding line SL.

[0195] As another example, the first conductive via UVP1 located in the second contact hole CH2 and the first conductive via UVP1 located in the fourth contact hole CH4 may be connected to different connection lines CL and apply the same voltage to the shielding line SL.

[0196] Even in the case of the semiconductor device 10_4, the same Fig. 9 The embodiment shown in FIG. 1 has basically the same effect.

[0197] according to Fig. 10B In the semiconductor device 10_5 shown in FIG. 1 , the plurality of shielding wires SL may be connected between the first shielding contact wire SCL_1 and the second shielding contact wire SCL_2. For example, each of the plurality of shielding wires SL may be connected to the first shielding contact wire SCL_1 and the second shielding contact wire SCL_2.

[0198] according to Fig. 10C In the semiconductor device 10_6 shown in FIG. 1 , one or more first shielding wires among the plurality of shielding wires SL may be connected to the first shielding contact wire SCL_1, and one or more second shielding wires among the plurality of shielding wires SL may be connected to the second shielding contact wire SCL_2. The first shielding wire and the second shielding wire may be connected to the first shielding contact wire SCL_1 or the second shielding contact wire SCL_2. The first shielding wire and the second shielding wire may be alternately arranged along the first direction X.

[0199] That is, the plurality of shielding lines SL may include a first shielding line SL_1 and a second shielding line SL_2, the first shielding line SL_1 extending from the cell array region CAR of the substrate 100 toward the peripheral region ER along the second direction Y and connected to the first shielding contact line SCL_1, and the second shielding line SL_2 adjacent to the first shielding line SL_1 along the first direction X extending from the cell array region CAR toward the peripheral region ER along the direction opposite to the second direction Y and connected to the second shielding contact line SCL_2.

[0200] In one embodiment, the first shielding contact wire SCL_1 and the first shielding wire SL_1 may be formed integrally. The second shielding contact wire SCL_2 and the second shielding wire SL_2 may be formed as separate structures by a process separate from the first shielding contact wire SCL_1 and the first shielding wire SL_1. However, the present disclosure is not limited thereto, and the first shielding contact wire SCL_1, the first shielding wire SL_1, the second shielding contact wire SCL_2 and the second shielding wire SL_2 may be formed by the same process and may be separately constructed.

[0201] As described above, the first conductive vias (refer to Figure 5A "UVP1" in the figure) can electrically connect the shielded contact wires SCL_1 and SCL_2 to the connecting wire (refer to Figure 5A ”CL” in the figure).

[0202] In one embodiment, the first conductive via UVP1 may be electrically connected to the connection line CL, and the connection line CL may be electrically connected to a circuit for applying a voltage to the shielding line SL.

[0203] For example, the first conductive via UVP1 located in the second contact hole CH2 and the first conductive via UVP1 located in the fourth contact hole CH4 may be connected to the same connection line CL and may apply the same voltage to the first shielding line SL_1 and the second shielding line SL_2 , respectively.

[0204] As another example, the first conductive via UVP1 located in the second contact hole CH2 may be connected to the connection line CL, and the first conductive via UVP1 located in the fourth contact hole CH4 may be connected to a conductive pattern located at a higher height or a lower height than the connection line CL, and the same voltage may be applied to each of the first shielding line SL_1 and the second shielding line SL_2.

[0205] As another example, the first conductive via UVP1 located in the second contact hole CH2 can be connected to the connection line CL "connected to the peripheral circuit PC located in the peripheral circuit region PCR", the first conductive via UVP1 located in the fourth contact hole CH4 can be connected to the connection line CL "connected to the core circuit SA located in the cell array region CAR", and different voltages can be applied to each of the first shielding line SL_1 and the second shielding line SL_2.

[0206] Even in the case of the semiconductor device 10_6 according to the embodiment, the semiconductor device 10_6 can be Fig. 9 The embodiment shown in has substantially the same effect, and can improve the electrical characteristics of the semiconductor device 10_6 by making the voltage applied to each of the first shield line SL_1 and the second shield line SL_2 different according to the coupling capacitance between the bit lines BL that may be caused by mutual interference.

[0207] In the following, reference is made to Figures 11 to 25 A method for manufacturing a semiconductor device is described. Hereinafter, the same configuration as previously described is denoted by the same reference numerals, and repeated descriptions may be omitted or simplified, and differences will be mainly described. The description herein relates to a method for manufacturing a semiconductor device according to Figures 1 to 5B The semiconductor device method of the embodiment is described herein with reference to Figures 1 to 5B is further described.

[0208] Figures 11 to 25 are a top plan view and a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment.

[0209] Specifically, Fig.11 , Fig.14 , Fig.17 , Fig. 20 and Fig.23 is a plan view for explaining a method for manufacturing a semiconductor device according to an embodiment. Fig.12 , Fig.13 , Fig.15 , Fig.16 , Fig.18 , Fig.19 , Fig.21 , Fig. 22 , Fig.24 and Fig.25 Each of the cross-sectional views is cut along the cutting line of the corresponding plan view.

[0210] Reference Figures 11 to 13 , a peripheral circuit structure PS including a core circuit SA and a peripheral circuit PC may be formed on the substrate 100 .

[0211] The substrate 100 may include a cell array region CAR and a peripheral region ER surrounding the cell array region CAR on a plane extending along a first direction X and a second direction Y. The peripheral region ER may include a peripheral circuit region PCR, which is arranged separately from the cell array region CAR along the first direction X on a plane. However, the present disclosure is not limited thereto, and in some embodiments, the substrate 100 may further include other regions, and some regions may be omitted. For example, the peripheral circuit region PCR located in the peripheral region ER may be omitted.

[0212] A core circuit SA may be formed on the cell array region CAR of the substrate 100 , and a peripheral circuit PC may be formed on the peripheral circuit region PCR. The core circuit SA and the peripheral circuit PC may include NMOS transistors and PMOS transistors integrated on the substrate 100 .

[0213] A peripheral circuit insulating layer ILD covering the core circuit SA and the peripheral circuit PC may be formed on the substrate 100 .

[0214] The peripheral circuit insulating layer ILD may include a multi-layer insulating layer. For example, the peripheral circuit insulating layer ILD may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and / or a low dielectric layer. However, the present disclosure is not limited thereto, and the composition and material of the peripheral circuit insulating layer ILD may be changed in various ways.

[0215] A peripheral circuit contact plug PCT and a peripheral circuit wiring PCL may be formed in the peripheral circuit insulating layer ILD. The peripheral circuit contact plug PCT and the peripheral circuit wiring PCL may be electrically connected to the core circuit SA and the peripheral circuit PC.

[0216] A first insulating layer 110 covering the entire surface of the substrate 100 may be formed on the peripheral circuit insulating layer ILD. The first insulating layer 110 may include the same material as the peripheral circuit insulating layer ILD. However, the material included in the first insulating layer 110 is not limited thereto and may be changed in various ways.

[0217] A first contact hole CH1 penetrating the first insulating layer 110 may be formed, and a lower contact plug LCT connected to the peripheral circuit wiring PCL may be formed in the first contact hole CH1.

[0218] On the cell array region CAR of the substrate 100 , bit lines BL extending in the second direction Y and spaced apart from each other in the first direction X may be formed on the first insulating layer 110 .

[0219] The process of forming the bit line BL may include forming the bit line BL by depositing a conductive material layer on the first insulating layer 110 and patterning the conductive material layer and the first insulating layer 110 on the cell array region CAR.

[0220] In the process of forming the bit line BL, the first insulating layer 110 located on the cell array region CAR and the peripheral region ER located on one side of the second direction Y of the cell array region CAR may be patterned together.

[0221] In one embodiment, on the cell array region CAR, the bit lines BL and the first insulating layer 110 stacked in the third direction Z perpendicular to the substrate 100 may be formed, and the upper surface of the peripheral circuit insulating layer ILD between the bit lines BL on the cell array region CAR and the upper surface of the peripheral circuit insulating layer ILD on the peripheral region ER at one side of the second direction Y of the cell array region CAR may be exposed.

[0222] The conductive material layer used to form the bit line BL may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0223] Alternatively, the conductive material layer may be doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx or a combination thereof, but is not limited thereto, and the material included in the conductive material layer for forming the bit line BL may be changed in various ways.

[0224] Reference Fig.14 , Fig.15 and Fig.16 The shield line SL is located between the bit lines BL and extends in the second direction Y to reach the peripheral region ER from the cell array region CAR, and the shield contact line SCL is located in the peripheral region ER, connected to the end of the shield line SL, and extends in the first direction X.

[0225] In one embodiment, a second insulating layer 111 may be formed on the peripheral circuit insulating layer ILD. The second insulating layer 111 may be formed on the entire surface of the substrate 100. The second insulating layer 111 may fill the space between the bit lines BL on the cell array region CAR of the substrate 100. In addition, the second insulating layer 111 may also be formed on the upper surface of the bit line BL.

[0226] The second insulating layer 111 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer. However, the material included in the second insulating layer 111 is not limited thereto and may be changed in various ways.

[0227] A trench may be formed in the second insulating layer 111 by recessing the second insulating layer 111 from an upper surface toward a bottom surface. The trench may be located between the bit lines BL on the cell array region CAR and in the peripheral region ER adjacent to one side of the cell array region CAR in the second direction Y.

[0228] The trench formed in the second insulating layer 111 between the bit lines BL on the cell array region CAR may extend in the second direction Y. The trench may be spaced apart from adjacent trenches in the first direction X with the bit line BL interposed therebetween.

[0229] The trench formed in the second insulating layer 111 in the peripheral region ER adjacent to one side of the cell array region CAR in the second direction Y may extend in the first direction X.

[0230] The width of the trench formed in the second insulating layer 111 located in the peripheral region ER adjacent to one side of the cell array region CAR in the second direction Y may be greater than the width of the trench formed in the second insulating layer 111 located between the bit lines BL in the cell array region CAR.

[0231] The bottom surface of the trench formed on the second insulating layer 111 may be located at a height between the upper surface and the bottom surface of the first insulating layer 110. However, the height of the bottom surface of the trench formed on the second insulating layer 111 is not limited thereto and may be changed in various ways.

[0232] A conductive material layer for forming the shielding wires SL and the shielding contact wires SCL may be formed on the second insulating layer 111. The conductive material layer for forming the shielding wires SL and the shielding contact wires SCL may fill the grooves formed in the second insulating layer 111. In addition, a conductive material layer for forming the shielding wires SL and the shielding contact wires SCL may also be formed on the upper surface of the second insulating layer 111.

[0233] The conductive material layer may be layered using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD) techniques. However, the method of depositing the conductive material layer is not limited thereto and may be modified in various ways.

[0234] The conductive material layer used to form the shielding line SL and the shielding contact line SCL may include, for example, a metal material such as tungsten (W), titanium (Ti), nickel (Ni), cobalt (Co), or a combination thereof.

[0235] In some embodiments, the conductive material layer used to form the shielding wire SL and the shielding contact wire SCL may include a two-dimensional material and a three-dimensional material. For example, the conductive material layer used to form the shielding wire SL and the shielding contact wire SCL may include graphene as a carbon-based two-dimensional material, carbon nanotubes as a three-dimensional material, or a combination thereof. However, the conductive material layer used to form the shielding wire SL and the shielding contact wire SCL is not limited thereto and may be changed in various ways.

[0236] A portion of the conductive material layer for forming the shield line SL and the shield contact line SCL filled in the trench formed in the second insulating layer 111 may be recessed from the upper surface toward the bottom surface.

[0237] In one embodiment, an upper surface of a conductive material layer filled in a trench formed in the second insulating layer 111 for forming the shielding line SL and the shielding contact line SCL may be located at a lower height than an upper surface of the bit line BL.

[0238] Furthermore, a bottom surface of a conductive material layer for forming the shield line SL and the shield contact line SCL in the trench formed in the second insulating layer 111 may be located at a height between the upper surface and the bottom surface of the first insulating layer 110 .

[0239] A second insulating layer 111 may be formed on the shielding line SL and the shielding contact line SCL to cover upper surfaces of the shielding line SL and the shielding contact line SCL.

[0240] In one embodiment, the shielding wires SL and the shielding contact wires SCL may be buried in the second insulating layer 111. That is, upper surfaces, bottom surfaces, and side surfaces of the shielding wires SL and the shielding contact wires SCL may be surrounded by the second insulating layer 111.

[0241] A process of planarizing the second insulating layer 111 may be performed, and the upper surface of the bit line BL may be exposed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process, but is not limited thereto and may be changed in various ways.

[0242] The second insulating layer 111 on the upper surface of the bit line BL may be removed by a planarization process, and the upper surface of the bit line BL may be exposed. In addition, the upper surface of the second insulating layer 111 may be located at substantially the same height as the upper surface of the bit line BL.

[0243] In one embodiment, the shielding wire SL and the shielding contact wire SCL may be formed simultaneously in the same process step and may be formed integrally. However, the present disclosure is not limited thereto, and the shielding wire SL and the shielding contact wire SCL may be formed by separate processes, and the shielding wire SL and the shielding contact wire SCL may be made of separate structures. In addition, the method of forming the shielding wire SL and the shielding contact wire SCL in the second insulating layer 111 and the second insulating layer 111 is not limited thereto, and may be formed by various methods.

[0244] Reference Fig.17 , Fig.18 and Fig.19 , a first insulating pattern 120 defining trenches TRC extending in the first direction X on the bit lines BL and spaced apart from each other in the second direction Y may be formed.

[0245] The first insulating pattern 120 may be formed on the bit line BL and the second insulating layer 111 in the cell array region CAR of the substrate 100. Also, the first insulating pattern 120 may be formed on the second insulating layer 111 on the peripheral region ER of the substrate 100.

[0246] A trench TRC defined by the first insulating pattern 120 may be formed across the bit line BL. The trench TRC defined by the first insulating pattern 120 may expose the bit line BL and the shield line SL.

[0247] The first insulating pattern 120 may be formed of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer. However, the material included in the first insulating pattern 120 is not limited thereto and may be changed in various ways.

[0248] The channel pattern material layer may be conformally deposited on the upper and side surfaces of the first insulating pattern 120 , the upper surface of the bit line BL, and the second insulating layer 111 .

[0249] The channel pattern material layer may be deposited using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD). However, the method of depositing the channel pattern material layer is not limited thereto and may be modified in various ways.

[0250] The channel pattern material layer may include a semiconductor material, an oxide semiconductor material, or a two-dimensional semiconductor material. The channel pattern material layer may include, for example, silicon, germanium, silicon germanium, or indium gallium zinc oxide (IGZO).

[0251] By patterning the channel pattern material layer, a channel pattern CP may be formed in the cell array region CAR of the substrate 100. The channel pattern CP may be spaced apart from adjacent channel patterns disposed along the second direction Y. The channel pattern CP may be formed by patterning the channel pattern material layer.

[0252] In addition, in the third direction Z perpendicular to the substrate 100, the channel pattern CP in the trench TRC may not overlap with the shielding line SL. For example, in a plan view, a portion of the channel pattern CP in the trench TRC may be spaced apart from the shielding line SL. The portion of the channel pattern CP and the shielding line SL may be arranged at intervals along the first direction X, and in a plan view, the shielding line SL is placed between adjacent portions of the channel pattern CP. For example, the shielding line SL may overlap with a gap in the channel pattern CP, the gap being defined by a space between adjacent portions of the channel pattern CP.

[0253] The channel pattern CP may be formed along the contour of the trench TRC, and the upper surface of the channel pattern CP may be located at substantially the same height as the upper surface of the first insulating pattern 120. The channel pattern CP may be a portion of the channel pattern material layer that remains in the trench TRC during patterning of the channel pattern material layer. However, the method for forming the channel pattern CP and the arrangement of the channel pattern CP are not limited thereto and may be changed in various ways.

[0254] The process of forming the channel pattern CP may include a process of forming a sacrificial layer in the trench TRC, forming a mask pattern on the sacrificial layer to pattern the channel pattern material layer, and removing the sacrificial layer and the mask pattern.

[0255] Reference Fig. 20 , Fig.21 and Fig. 22 , a gate insulating pattern Gox and word lines WL1 and WL2 may be formed in the trench TRC.

[0256] Specifically, a gate insulation pattern material layer and a word line material layer conformally covering the first insulation pattern 120 and the channel pattern CP may be sequentially deposited.

[0257] The gate insulating pattern material layer and the word line material layer may be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD). However, the method of forming the gate insulating pattern material layer and the word line material layer is not limited thereto and may be changed in various ways.

[0258] The gate insulating pattern material layer may include silicon oxide, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0259] The word line material layer may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0260] The gate insulation pattern material layer and the word line material layer may be patterned to form a gate insulation pattern Gox and word lines WL1 and WL2 sequentially located on the channel pattern CP in the trench TRC.

[0261] The gate insulating pattern Gox and the word lines WL1 and WL2 may be a portion of each of the gate insulating pattern material layer and the word line material layer remaining in the trench TRC during etching of the gate insulating pattern material layer and the word line material layer.

[0262] The gate insulating pattern Gox may be formed on the channel pattern CP in the trench TRC. That is, the gate insulating pattern Gox may be conformally formed along the outline of the channel pattern CP located in the trench TRC.

[0263] The upper surface of the gate insulating pattern Gox may be located at substantially the same height as the upper surface of the first insulating pattern 120. Also, the gate insulating pattern Gox may be conformally formed along contours of the side surface of the first insulating pattern 120 and the upper surface of the second insulating layer 111 within the trench TRC.

[0264] By performing an anisotropic etching process on the word line material layer, a pair of word lines WL1 and WL2 may be formed in the trench TRC to be separated from each other along the second direction Y. The pair of word lines WL1 and WL2 may be formed on the gate insulating pattern Gox.

[0265] During the anisotropic etching process for the word line material layer, upper surfaces of the word lines WL1 and WL2 may be lower than upper surfaces of the first insulating pattern 120 and the gate insulating pattern Gox. In some embodiments, an etching process may be additionally performed to recess upper surfaces of the word lines WL1 and WL2.

[0266] The second insulating pattern 140 filling the trench TRC may be formed on the gate insulating pattern Gox and the word lines WL1 and WL2. That is, after forming the gate insulating pattern Gox and the word lines WL1 and WL2, the second insulating pattern 140 may be formed in the remaining trench TRC. The second insulating pattern 140 may fill the trench TRC.

[0267] The second insulating pattern 140 may be formed in the trench TRC and cover the word lines WL1 and WL2. The second insulating pattern 140 may fill the trench TRC and cover the side surfaces and upper surfaces of the word lines WL1 and WL2. The upper surface of the second insulating pattern 140 may be located at substantially the same height as the upper surface of the first insulating pattern 120 and the upper surface of the gate insulating pattern Gox.

[0268] The process of forming the second insulating pattern 140 may include a planarization process that exposes the upper surface of the first insulating pattern 120, the upper surface of the channel pattern CP, and the upper surface of the gate insulating pattern Gox. That is, the second insulating pattern 140 may be a portion of the second insulating pattern material layer that remains in the trench TRC when the planarization process is performed.

[0269] The second insulating pattern 140 may include at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, and a low dielectric constant (low-k) material having a smaller dielectric constant than silicon oxide. However, the present disclosure is not limited thereto, and the material included in the second insulating pattern 141 may be changed in various ways.

[0270] In one embodiment, a bonding pad LP connected to the channel pattern CP in the cell array region CAR may be formed.

[0271] Specifically, after depositing the bonding pad material layer, the bonding pad material layer may be patterned to form the bonding pad LP connected to the channel pattern CP.

[0272] The third insulating layer 150 may be formed, a portion between the bonding pads LP may be filled, and a planarization process may be performed. However, the order of forming the bonding pads LP and the third insulating layer 150 is not limited thereto, and in some embodiments, after forming the third insulating layer 150 and patterning the third insulating layer 150, the bonding pads LP penetrating the third insulating layer 150 may be formed.

[0273] In one embodiment, the upper surface of the channel pattern CP may be located at a lower height than the upper surfaces of the word lines WL1 and WL2. For example, an etching process may be included for recessing a portion of the channel pattern CP forming the bonding pad LP. That is, by etching a portion of the channel pattern CP from the upper surface toward the bottom surface, a groove extending along the third direction Z and defined by the first insulating pattern 120, the upper surface of the channel pattern CP, and the gate insulating pattern Gox may be formed, and the bonding pad LP may be formed in the groove.

[0274] The bonding pad LP may include an upper portion having a first width along the second direction Y and a lower portion having a second width along the second direction Y, wherein the second width is less than the first width. The upper portion of the bonding pad LP may be disposed on the second insulating pattern 140. The lower portion of the bonding pad LP may extend from the lower surface of the upper portion of the bonding pad LP. The lower portion of the bonding pad LP may extend from the upper portion of the bonding pad LP along the side surface of the upper portion of the bonding pad LP. The channel pattern CP, the lower portion of the bonding pad LP, and the upper portion of the bonding pad LP may include a coplanar surface along the third direction Z. The lower portion of the bonding pad LP may be disposed in a groove extending along the third direction Z and defined by the first insulating pattern 120, the upper surface of the channel pattern CP, and the gate insulating pattern Gox.

[0275] The bonding pad LP may include a conductive material, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0276] As another example, the bonding pad LP may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto and may be changed in various ways.

[0277] The third insulating layer 150 may include the same material as the above-described first insulating layer 110 and second insulating layer 111. However, the present disclosure is not limited thereto, and the material included in the third insulating layer 150 may be changed in various ways.

[0278] Reference Fig.23 , Fig.24 and Fig.25 , on the cell array region CAR of the substrate 100, a plurality of data storage patterns DSP respectively connected to the plurality of bonding pads LP may be formed on the bonding pads LP.

[0279] On the cell array region CAR and the peripheral region ER of the substrate 100, a fourth insulating layer 160 may be formed on the third insulating layer 150. On the cell array region CAR of the substrate 100, the fourth insulating layer 160 may be formed to cover the data storage pattern DSP.

[0280] The fourth insulating layer 160 may include the same material as the third insulating layer 150. However, the present disclosure is not limited thereto, and the material included in the fourth insulating layer 160 may be changed in various ways.

[0281] A second contact hole CH2 exposing the upper surface of the shielding contact line SCL may be formed on the peripheral region ER of the substrate 100. That is, the second contact hole CH2 penetrating the fourth insulating layer 160, the third insulating layer 150, and the first insulating pattern 120 and exposing the upper surface of the shielding contact line SCL located in the second insulating layer 111 may be formed.

[0282] The first conductive via UVP1 may be formed in the second contact hole CH2. The first conductive via UVP1 may fill the second contact hole CH2.

[0283] The first conductive via UVP1 may include at least one metal of aluminum, copper, tungsten, molybdenum, and cobalt, but is not limited thereto and may be changed in various ways.

[0284] A connection line CL including a conductive material may be formed on the fourth insulating layer 160. The connection line CL may completely cover the first conductive via UVP1 at a surface of the fourth insulating layer 160. The connection line CL may be electrically connected to the shielding contact line SCL through the first conductive via UVP1. Although not shown, the connection line CL may be electrically connected to a wiring or circuit for applying a voltage to the shielding line SL.

[0285] The process of forming the connection line CL may include forming a conductive material layer for forming the connection line CL on the fourth insulating layer 160 , and patterning the conductive material layer for forming the connection line CL.

[0286] While the present disclosure has been described in conjunction with what are presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate including a cell array region and a peripheral region surrounding the cell array region; A bit line located on the cell array region and extending along a first direction; a shield line extending from the cell array region to the peripheral region along a first direction and arranged adjacent to the bit line along a second direction crossing the first direction; a shielding contact wire, located on the peripheral region, extending in the second direction, and connected to the shielding wire; a channel pattern located on the bit line and extending in a direction perpendicular to the bit line; a word line extending along the second direction and located on the channel pattern; a gate insulating pattern, located between the channel pattern and the word line; an insulating pattern, located on the word line; a bonding pad connected to the channel pattern; as well as Data storage pattern connected to bonding pads.

2. The semiconductor device according to claim 1, wherein: The shield wire and shield contact wire are an integral unit.

3. The semiconductor device according to claim 1, wherein: The shielding line is located at a center portion between the bit line and an adjacent bit line.

4. The semiconductor device according to claim 3, wherein: The shield line overlaps the word line, and The shielding line overlaps the gap in the channel pattern.

5. The semiconductor device according to claim 1, wherein: The upper surface of the shield line and the upper surface of the shield contact line are located at a height between the upper surface and the bottom surface of the bit line, and The bottom surface of the shield line and the bottom surface of the shield contact line are located at a lower height than the surface of the bit line.

6. The semiconductor device according to claim 1, wherein: At least one of a width of the bit line, a width of the shield line, and a width of the shield contact line is different.

7. The semiconductor device according to claim 6, wherein: The width of the shield contact line is greater than the width of the shield line.

8. The semiconductor device according to claim 7, wherein: The width of the bit line is greater than the width of the shield line, and the width of the bit line is less than the width of the shield contact line.

9. The semiconductor device according to claim 1, wherein: The shield wire and the shield contact wire are at the same height, and The shield contact wire is connected to the end portion of the shield wire located on the peripheral area.

10. The semiconductor device according to claim 1, further comprising: an insulating layer covering the data storage pattern; A conductive pattern, located on the insulating layer; as well as Conductive vias connect the shielding contact wires and the conductive pattern.

11. The semiconductor device according to claim 10, further comprising: Conductive pads, located at the same height as the bonding pads, Among them, the conductive vias include: a first conductive via connecting the shielding contact line and the conductive pad; and The second conductive via connects the conductive pad and the conductive pattern.

12. The semiconductor device according to claim 10, wherein: The conductive via overlaps at least a portion of the shielding contact line.

13. The semiconductor device according to any one of claims 1 to 12, wherein: The bit lines and shield lines include different materials, and The shield wire and the shield contact wire comprise the same material.

14. A semiconductor device comprising: a substrate including a cell array region and a peripheral region surrounding the cell array region; A plurality of bit lines are located on the cell array region and extend along a first direction; a plurality of shielding lines extending from the cell array region to the peripheral region along a first direction and arranged alternately with the plurality of bit lines; a first shield contact wire extending in a second direction intersecting the first direction on the peripheral region and connected to an end of a first shield wire among the plurality of shield wires; a second shield contact wire extending in a second direction on the peripheral area and connected to an end of a second shield wire among the plurality of shield wires; a channel pattern located on the plurality of bit lines and extending in a direction perpendicular to upper surfaces of the plurality of bit lines; a word line extending along the second direction and located on the channel pattern; a gate insulating pattern, located between the channel pattern and the word line; an insulating pattern, located on the word line; a bonding pad connected to the channel pattern; as well as Data storage pattern connected to bonding pads.

15. The semiconductor device according to claim 14, further comprising: a first insulating layer covering the data storage pattern; a first conductive via penetrating the first insulating layer and connected to the first shielding contact line; as well as The second conductive via penetrates the first insulating layer and is connected to the second shielding contact line.

16. The semiconductor device according to claim 14, wherein: A first group of the plurality of shielding wires is connected to a first shielding contact wire, and A second group of the plurality of shielding wires is connected to a second shielding contact wire.

17. The semiconductor device according to claim 14, wherein: The lengths of the plurality of bit lines along the first direction are different from the lengths of the plurality of shield lines along the first direction.

18. The semiconductor device according to claim 14, further comprising: a second insulating layer disposed between the plurality of bit lines, Wherein, the plurality of shielding wires are buried in the second insulating layer.

19. A semiconductor device comprising: a substrate including a cell array region and a peripheral region surrounding the cell array region; A plurality of bit lines are located on the cell array region and extend along a first direction; a plurality of shielding lines extending from the cell array region to the peripheral region along a first direction and arranged alternately with the plurality of bit lines; a shielding contact wire extending in a second direction intersecting the first direction on the peripheral region and connected to the plurality of shielding wires; a channel pattern located on the plurality of bit lines and extending in a direction perpendicular to upper surfaces of the plurality of bit lines; A word line extending along a second direction; a gate insulating pattern, located between the channel pattern and the word line; an insulating pattern, located on the word line; a bonding pad connected to the channel pattern; a data storage pattern connected to the bonding pad; as well as A conductive via connected to a portion of the shield contact line on the peripheral area.

20. The semiconductor device according to claim 19, wherein: The lengths of the plurality of shielding lines along the first direction are longer than the lengths of the plurality of bit lines along the first direction, and The width of each of the plurality of shielding lines is smaller than the width of the shielding contact line.

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