Semiconductor package

Abstract

A semiconductor package according to an embodiment includes a circuit board including a first insulating layer without a reinforcing member, and a connection member embedded in the circuit board, the connection member being embedded in the first insulating layer of the circuit board, and the connection member including a second insulating layer containing an organic material.

Description

Technical Field

[0001] Embodiments relate to semiconductor packaging. Background Art

[0002] Higher performance electrical / electronic products are being developed, and therefore, technologies for attaching a larger number of packages to a substrate of limited size are being proposed and studied. However, general packaging is based on mounting one semiconductor device, and therefore, there are limitations in obtaining desired performance.

[0003] A general semiconductor package is a form in which a processor package in which a processor chip is arranged and a memory package in which a memory chip is attached are connected together. The semiconductor package provides the processor chip and the memory chip as one integrated package, thus having the advantages of reducing the mounting area of ​​the chip and realizing high-speed signals through a short path.

[0004] The semiconductor package as described above has advantages, and it is widely used in mobile devices and the like.

[0005] On the other hand, due to the high specifications of electronic devices such as mobile devices and the adoption of HBM (High Bandwidth Memory), the size of packages has recently increased, and therefore, semiconductor packages including an interposer are mainly used. In this case, the interposer is provided with a silicon substrate.

[0006] However, when an interposer such as a silicon substrate is applied, there are problems that the cost of manufacturing the interposer is high and the formation of through silicon vias (TSVs) is complicated.

[0007] In addition, conventionally, semiconductor packages including silicon-based interconnection bridges are provided. When the silicon-based interconnection bridge is applied, there are reliability issues due to the coefficient of thermal expansion (CTE) mismatch between the silicon material of the bridge and the organic material of the substrate, and there is a problem that power integrity characteristics deteriorate. Summary of the invention

[0008] Technical issues

[0009] The embodiment provides a semiconductor package having a novel structure.

[0010] In addition, the embodiment provides a semiconductor package that can mount a plurality of processor chips side by side.

[0011] In addition, the embodiment provides a semiconductor package that can mount a plurality of processor chips and memory chips side by side.

[0012] In addition, the embodiment provides a semiconductor package including a processor chip and passive devices embedded in a circuit board.

[0013] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by technicians in the field to which the proposed embodiments belong from the following description.

[0014] Technical Solution

[0015] A semiconductor package according to an embodiment includes a circuit board and a connecting member embedded in the circuit board, wherein the circuit board includes a first insulating layer without a reinforcing member, the connecting member is embedded in the first insulating layer of the circuit board, and the connecting member includes a second insulating layer including an organic material.

[0016] In addition, the first insulating layer includes a first layer, a second layer disposed on the first layer and having a cavity, and a third layer disposed on the second layer and filling the cavity, and the connection member is disposed in the cavity.

[0017] In addition, the second insulating layer of the connection member includes polyimide.

[0018] In addition, the circuit board further includes a third insulating layer disposed below the first insulating layer, and the third insulating layer includes an insulating material different from that of the first insulating layer.

[0019] In addition, the third insulating layer includes a reinforcement member.

[0020] In addition, the circuit board further includes a fourth insulating layer disposed below the third insulating layer, and the fourth insulating layer includes the same insulating material as that of the first insulating layer.

[0021] In addition, the third insulating layer has a through hole, and the semiconductor device is provided in the through hole.

[0022] In addition, the first insulating layer is provided to fill the through hole and cover the semiconductor device.

[0023] In addition, the through-hole includes a plurality of through-holes which are provided in the third insulating layer and are spaced apart from each other in a horizontal direction, and the semiconductor devices are respectively provided in the plurality of through-holes.

[0024] In addition, the plurality of through holes do not overlap with the connection member in a vertical direction.

[0025] A circuit board according to an embodiment includes a first substrate and a second substrate that is a bridge substrate embedded in the first substrate, wherein the first substrate includes a first insulating layer, a first circuit layer arranged on the first insulating layer, and a first via penetrating the first insulating layer; wherein the first insulating layer of the first substrate includes a first layer, a second layer arranged on the first layer and including a first cavity, and a third layer arranged on the second layer and filling the second substrate, and the second substrate is arranged in the first cavity, wherein the first to third layers of the insulating layer of the first substrate do not include glass fibers, and the second substrate includes an insulating layer containing an organic material.

[0026] In addition, the first to third layers of the first insulating layer of the first substrate include ABF (Ajinomoto deposited film).

[0027] In addition, the insulating layer of the second substrate includes polyimide.

[0028] Additionally, the first substrate further includes a second insulating layer of the first substrate disposed below the first layer of the first insulating layer of the first substrate, and the second insulating layer of the first substrate includes glass fiber.

[0029] In addition, the first substrate further includes a third insulating layer of the first substrate disposed below the second insulating layer of the first substrate, and the third insulating layer of the first substrate includes the same insulating material as the first insulating layer of the first substrate.

[0030] In addition, the first via holes of the first substrate include a 1-1 via hole penetrating the first layer of the first insulating layer, a 1-2 via hole penetrating the second layer of the first insulating layer, and a 1-3 via hole penetrating the third layer of the first insulating layer, and the first circuit layer of the first substrate includes a 1-1 circuit layer disposed on the first layer of the first insulating layer, a 1-2 circuit layer disposed on the second layer of the first insulating layer, and a 1-3 circuit layer disposed on the third layer of the first insulating layer.

[0031] In addition, the semiconductor package further includes a first device disposed in a second cavity penetrating the second insulating layer of the first substrate, and the second cavity and the first device are covered by the first layer of the first insulating layer of the first substrate.

[0032] In addition, the 1-1 via of the first substrate includes a first sub-via and a second sub-via, the first sub-via does not overlap with the first device in the thickness direction and does not directly contact the terminal of the first device; the second sub-via is spaced apart from the first sub-via in the horizontal direction, overlaps with the first device in the thickness direction, and is directly connected to the terminal of the first device; at least one of the thickness and width of the first sub-via is different from at least one of the thickness and width of the second sub-via.

[0033] In addition, the semiconductor package also includes a second device arranged in a third cavity of the second insulating layer penetrating the first substrate, wherein the third cavity and the second device are covered by the first layer of the first insulating layer of the first substrate, and the second cavity and the third cavity are spaced apart in a horizontal direction within the second insulating layer of the first substrate, and the first cavity does not overlap with the second cavity and the third cavity in a thickness direction.

[0034] In addition, the 1-3 via of the first substrate includes a first sub-via and a second sub-via, the first sub-via of the 1-3 via overlaps with the second substrate in the thickness direction and is directly connected to the pad layer of the second substrate; the second sub-via of the 1-3 via is spaced apart from the first sub-via of the 1-3 via in the horizontal direction and is not directly connected to the pad layer of the second substrate, and at least one of the thickness and width of the first sub-via of the 1-3 via is different from at least one of the thickness and width of the second sub-via of the 1-3 via.

[0035] In addition, the 1-1th circuit layer of the first substrate includes a pad portion overlapping the first cavity in a thickness direction and having an upper surface exposed through the first cavity, and the second substrate is attached to the pad portion through an adhesive layer provided on the pad portion.

[0036] In addition, the second substrate includes a first circuit layer, a second circuit layer and a via, the first circuit layer of the second substrate is arranged on the upper surface of the insulating layer of the second substrate, the second circuit layer of the second substrate is arranged on the lower surface of the insulating layer of the second substrate, and the via of the second substrate penetrates the insulating layer of the second substrate, wherein the slope of the side surface of the via of the second substrate is different from the slope of the side surface of the 1-1 via of the first substrate.

[0037] In addition, the first circuit layer of the second substrate includes a first metal layer and a second metal layer, the first metal layer includes at least one of nickel and chromium; and the second metal layer is disposed on the first metal layer and includes copper.

[0038] In addition, a slope of a side surface of the via hole of the second substrate is closer to a right angle than a slope of a side surface of the 1-1th via hole of the first substrate.

[0039] In addition, the second substrate includes a first protective layer that is disposed on the insulating layer of the second substrate and includes an opening that overlaps the first circuit layer of the second substrate in a thickness direction.

[0040] In addition, the second substrate further includes a second protective layer, which is arranged below the insulating layer of the second substrate and completely covers the lower surface of the second circuit layer of the second substrate, and the adhesive layer is arranged on the lower surface of the second protective layer of the second substrate.

[0041] In addition, the second substrate includes a pad layer, which is directly connected to the 1-3th via hole of the first substrate, and a position of an upper surface of the pad layer of the second substrate is different from a position of an upper surface of the 1-2 circuit layer of the first substrate.

[0042] In addition, the thickness of each of the first layer to the third layer of the first insulating layer of the first substrate has a first difference with the thickness of the second insulating layer of the first substrate, the height of the upper surface of the pad layer of the second substrate has a second difference with the height of the upper surface of the 1-2 circuit layer of the first substrate, and the second difference is smaller than the first difference.

[0043] Beneficial Effects

[0044] The circuit board of the embodiment includes a first insulating layer and a second insulating layer. The second insulating layer may include prepreg. Therefore, the embodiment can maintain the rigidity of the circuit board to improve the bending characteristics, thereby improving product reliability. In addition, the first insulating layer includes ABF. Therefore, the embodiment can reduce the size of the circuit layer and the via disposed on the first insulating layer. Specifically, the embodiment can form a circuit layer and a via of a fine pattern connected to the first processor chip and the second processor chip on the first insulating layer.

[0045] In addition, the first insulating layer includes multiple layers. In addition, the circuit layer and the via are arranged on each of the multiple layers of the first insulating layer. At this time, the embodiment allows the circuit layer and the via formed on the first insulating layer to gradually increase toward the second insulating layer. Therefore, the embodiment can minimize the signal transmission loss between the circuit layer and the via arranged on the first insulating layer and the circuit layer and the via arranged on the second insulating layer. Therefore, the embodiment can improve the communication characteristics of the circuit board.

[0046] In addition, the circuit board of the embodiment includes a bridge substrate embedded in the first insulating layer. The bridge substrate can be arranged in a first cavity formed in the second layer of the first insulating layer and covered by the third layer of the first insulating layer. In addition, the embodiment allows the pad layer included in the bridge substrate to be directly connected to the via hole penetrating the first insulating layer. Therefore, the embodiment can minimize the signal transmission distance and further minimize the signal transmission loss.

[0047] In addition, the insulating layer of the bridge substrate of the embodiment has a CTE similar to the CTE of the first insulating layer. In addition, the insulating layer of the bridge substrate of the embodiment has a flexible property. Specifically, the insulating layer of the bridge substrate may include polyimide (PI) as an organic material. Therefore, compared with a conventional bridge substrate including silicon, the embodiment can reduce the unit cost of the product.

[0048] In addition, the bridging substrate of the embodiment includes a pad layer. The pad layer is directly connected to the first via hole provided in the first insulating layer. At this time, the alignment state between the pad layer of the bridging substrate and the first via hole greatly affects the product reliability of the circuit board and the semiconductor package. At this time, in the embodiment, transparent polyimide is used as the insulating layer of the bridging substrate. Therefore, the embodiment can improve the alignment between the pad layer of the bridging substrate and the first via hole provided in the first insulating layer. Therefore, the embodiment can improve the overall product reliability.

[0049] In addition, the embodiments may stably protect the bridge substrate from stress generated during thermal deformation of the circuit board.

[0050] That is, in the conventional technology, the insulating layer of the bridge substrate contains silicon. Therefore, the conventional bridge substrate has rigid characteristics due to silicon. Therefore, the stress generated when the circuit board is thermally deformed is directly transferred to the bridge substrate. Therefore, the conventional bridge substrate has reliability problems such as cracks.

[0051] In contrast, the insulating layer of the bridge substrate of the embodiment includes polyimide. Therefore, when the circuit board is thermally deformed, the flow of the bridge substrate can be achieved together with the first insulating layer. Therefore, the embodiment can improve the physical reliability and electrical reliability of the bridge substrate.

[0052] In addition, the embodiment can easily control the thickness of the bridge substrate. For example, in the conventional case including silicon, in order to control the thickness of the bridge substrate, a polishing process of the silicon substrate must be performed, and therefore, due to the difficulty of processing characteristics, it is difficult to control the thickness of the bridge substrate to a desired thickness.

[0053] In contrast, the embodiment can easily control the entire thickness of the bridge substrate, and therefore can easily control the thickness of the bridge substrate according to the depth of the cavity formed in the first insulating layer. Therefore, the embodiment can minimize the thickness difference between the first sub-via directly contacting the bridge substrate and the sub-vias other than the first sub-via. Therefore, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a cross-sectional view showing a semiconductor package according to a comparative example.

[0055] Figure 2 is a cross-sectional view showing a circuit board according to an embodiment.

[0056] Figure 3 yes Figure 2 An enlarged cross-sectional view of a portion of the first insulating layer.

[0057] Figure 4 is a cross-sectional view showing a bridge substrate according to the first embodiment.

[0058] Figure 5 is a cross-sectional view showing a bridge substrate according to a second embodiment.

[0059] Figure 6 is a view showing a bridge substrate according to a third embodiment.

[0060] Figure 7 is a cross-sectional view showing a layer structure of a redistribution layer according to the first embodiment.

[0061] Figure 8 is a view showing a layer structure of a redistribution layer according to a second embodiment.

[0062] Fig. 9 is a cross-sectional view explaining a step between a 1-2 circuit layer and a pad layer of a bridge substrate according to the first embodiment.

[0063] Fig.10 1 is a view explaining a step between a 1-2 circuit layer and a pad layer of a bridge substrate according to the second embodiment.

[0064] Figures 11 to 25 Explained in order of process Figure 2 view of a circuit board.

[0065] Fig.26 2 is a view showing a semiconductor package according to a first embodiment.

[0066] Fig. 27 is a view showing a semiconductor package according to a second embodiment. DETAILED DESCRIPTION

[0067] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0068] However, the spirit and scope of the present disclosure are not limited to a part of the described embodiments, but may be implemented in various other forms, and one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of the present disclosure.

[0069] In addition, unless otherwise clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present disclosure may be interpreted as having the same meaning as that generally understood by a person of ordinary skill in the art to which the present disclosure belongs, and such terms as those defined in commonly used dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant art. In addition, the terms used in the embodiments of the present disclosure are used to describe the embodiments and are not intended to limit the present disclosure.

[0070] In the present specification, a singular form may also include a plural form unless specifically stated in a phrase, and when described as "at least one (or more) of A (and), B, and C", at least one of all combinations of A, B, and C may be included. In addition, when describing elements of an embodiment of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used.

[0071] These terms are only used to distinguish an element from other elements, and these terms do not limit the nature, order or sequence of the elements. In addition, when an element is described as being "connected", "coupled" or "contacting" another element, it may include not only that the element is directly "connected", "coupled" or "contacting" another element, but also that the element is "connected", "coupled" or "contacting" through other elements between the element and another element.

[0072] In addition, when describing that “on (above)” or “under (below)” is formed or arranged on each element, “on (above)” or “under (below)” may include not only two elements being directly connected to each other but also one or more other elements being formed or arranged between the two elements. In addition, when expressed as “on (above)” or “under (below)”, it may include not only an upper direction based on one element but also a lower direction.

[0073] Comparison example

[0074] Figure 1 is a cross-sectional view showing a semiconductor package according to a comparative example.

[0075] refer to Figure 1, in the control example, at least two packages are required to transmit the signal to the main board of the electronic device.

[0076] The semiconductor package included in the electronic device of the comparative example may be a combination of at least two or more packages.

[0077] The semiconductor package according to the comparative example includes a first package 10 and a second package 20 .

[0078] The first package 10 is a processor package on which a processor chip 12 is mounted. The second package 20 is a memory package on which a memory chip 23 is mounted.

[0079] The first package 10 includes a first substrate 11 on which a processor chip 12 is mounted. The first substrate 11 has a multi-layer structure, and includes one side provided with the processor chip 12 and the other side provided with first adhesive balls 16. The first package 10 has a fan-out structure, and is attached to a main board (not shown) of an electronic device using the first adhesive balls 16 provided on the other side.

[0080] The processor chip 12 is mounted on the first substrate 11. The processor chip 12 is an integrated processor chip that integrates various functions. Therefore, the size of the processor chip 12 increases in proportion to the number of functions it provides. The first substrate 11 allows the processor chip 12 to be mounted, and has the function of connecting the processor chip 12 and the main board of the electronic device.

[0081] Meanwhile, the first package 10 of the comparative example further includes a second substrate 15. The second substrate 15 is an interposer that interconnects the first package 10 and the second package 20.

[0082] That is, the semiconductor package of the comparative example basically includes an interposer such as the second substrate 15. In addition, the semiconductor package of the comparative example has a problem that the total volume increases in proportion to the thickness of the interposer. Therefore, the thickness of the electronic device in the semiconductor package of the comparative example increases, and there is a limit to thinning.

[0083] In addition, the problem of the semiconductor package of the comparative example is that since the first package 10 and the second package 20 are interconnected using the second substrate 15, the length of the signal transmission line increases. That is, in the semiconductor package of the comparative example, in order to transmit the signal of the processor chip 12 and the signal of the memory chip 23, these signals must at least pass through the second substrate 15, and therefore, the signal transmission distance between the processor chip 12 and the memory chip 23 increases corresponding to the length of the signal transmission line of the second substrate 15. Therefore, in the comparative example, there is a problem that high-speed communication between the processor chip 12 and the memory chip 23 is difficult due to the second substrate 15. In addition, the comparative example has a structure that is susceptible to noise due to the increase in the signal transmission distance by the second substrate 15, and therefore the communication performance is reduced.

[0084] Meanwhile, the first package 10 of the comparative example includes the second bonding balls 13 disposed on the first substrate 11 and the first molding layer 14 molding the second bonding balls 13 and the processor chip 12. At this time, the first molding layer 14 protects the processor chip 12 and the second bonding balls 13. Therefore, the thickness of the first molding layer 14 is determined by the height of the processor chip 12 and the second bonding balls 13. However, the comparative example further includes the second substrate 15 disposed above the first molding layer 14, and therefore, the thickness of the first molding layer 14 increases because the influence of the second substrate 15 must also be considered.

[0085] In addition, the second package 20 of the comparative example includes a third substrate 22 , a memory chip 23 disposed on the third substrate 22 , and a second mold layer 24 .

[0086] As described above, in the comparative example, at least three substrates are required to electrically connect the processor chip 12 and the memory chip 23 to each other. In addition, in the comparative example, a process for bonding at least three substrates to each other is required, and therefore, there is a problem of reduced yield due to an increase in the number and complexity of manufacturing processes. Specifically, due to the difficulty of a process for mounting different chips on one substrate, the comparative example requires at least three substrates.

[0087] In addition, in the comparative example, at least two bonding balls were required to bond at least three substrates to each other.

[0088] That is, the comparative example includes the second adhesive ball 13 for connecting the first substrate 11 and the second substrate 15 and the third adhesive ball 21 for connecting the second substrate 15 and the third substrate 22. Therefore, the semiconductor package according to the comparative example requires at least two adhesive balls to bond the plurality of substrates to each other, and has a problem that the reliability of the semiconductor package may be deteriorated due to poor connection of the adhesive balls. In addition, the comparative example has a structure in which two or more adhesive balls are provided in the thickness direction, and there is a problem that the thickness of the semiconductor package and further the thickness of the electronic device increases due to the thickness of the adhesive balls.

[0089] Specifically, the first substrate 11 has a first thickness t1 of 120 μm to 150 μm. The second thickness t2 including the first mold layer 14, the processor chip 12 and the second adhesive ball 13 is 145 μm to 160 μm. In addition, the third thickness t3 of the second substrate 15 is 90 μm to 110 μm. In addition, the fourth thickness t4 of the first adhesive ball 16 is 130 μm to 150 μm.

[0090] Therefore, the total thickness t8 of the first package 10 including the first to fourth thicknesses t1 , t2 , t3 , and t4 is 480 μm to 550 μm.

[0091] In addition, the fifth thickness t5 of the third adhesive ball 21 is 145 μm to 180 μm. In addition, the sixth thickness t6 of the third substrate 22 is 90 μm to 110 μm. In addition, the seventh thickness t7 including the memory chip 23 and the second mold layer 24 is 370 μm to 400 μm. Therefore, the total thickness t9 of the second package 20 including the fifth to seventh thicknesses t5, t6 and t7 is 610 μm to 700 μm. Therefore, the total thickness of the semiconductor package of the comparative example is more than 1100 μm.

[0092] Meanwhile, due to the recent thinning of electronic devices, the thickness of the semiconductor package needs to be 1100 μm or less. In addition, recently, one type of electronic device is mainly a foldable product, and the foldable product has the characteristics of small restrictions in the length direction but large restrictions in the thickness direction. However, since the semiconductor package of the comparative example has a structure in which a plurality of substrates are bonded to each other in the thickness direction by a plurality of adhesive balls, there is a problem that the specifications required for the electronic device are not met.

[0093] In addition, as the performance of electrical / electronic products has recently improved, technology for attaching a large number of packages to a substrate of limited size is being studied, and therefore, there is a demand for finer circuit patterns. However, in the case of the semiconductor package of the reference example, there is a limit to the miniaturization of the circuit pattern. The circuit pattern included in the semiconductor package of the reference example has a line width of at least 10 μm and a spacing of at least 10 μm. In addition, as the number of functions processed in an application processor (AP) has recently increased, it has become difficult to implement these functions on a single chip. However, in the case of the circuit pattern provided in the reference example, it is difficult to install two application processors (APs) that perform different functions on one first substrate 11.

[0094] The embodiment is directed to solving the problems of the comparative example, and provides a circuit board having a novel structure capable of mounting a plurality of application processor chips on one board, and a semiconductor package including the same.

[0095] Furthermore, the embodiments are directed to solving the problems of the comparative examples and provide a circuit board having a novel structure capable of mounting an application processor chip and a memory chip side by side, and a semiconductor package including the same.

[0096] Electronic devices

[0097] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. Various semiconductor devices can be mounted on the semiconductor package. In general, the various semiconductor devices mounted on the semiconductor package may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM) and flash memory, application processor chips such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors and microcontrollers, and logic chips such as analog-to-digital converters and application-specific ICs (ASICs).

[0098] In addition, the embodiment provides a semiconductor package which can mount at least two different types of chips on one substrate while reducing the thickness of the semiconductor package connected to a main board of an electronic device.

[0099] In this case, the electronic device may include a smart phone, a personal digital assistant, a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, a car, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0100] Example

[0101] Hereinafter, a circuit board and a semiconductor package including the same according to embodiments will be described in detail.

[0102] Figure 2 is a cross-sectional view showing a circuit board according to an embodiment, Figure 3 yes Figure 2 an enlarged cross-sectional view of a portion of the first insulating layer, Figure 4 is a cross-sectional view showing a bridge substrate according to a first embodiment, Figure 5 is a cross-sectional view showing a bridge substrate according to a second embodiment, Figure 6 is a view showing a bridge substrate according to a third embodiment, Figure 7 is a cross-sectional view showing a layer structure of a redistribution layer according to a first embodiment, Figure 8 is a view showing a layer structure of a redistribution layer according to a second embodiment.

[0103] In the following, reference will be made to Figures 2 to 8 A circuit board according to an embodiment is described.

[0104] refer to Figures 2 to 8 , the circuit board of the embodiment can be configured to mount at least two different chips.

[0105] For example, the circuit board of an embodiment may include a plurality of chip mounting areas in which at least two processor chips may be mounted.

[0106] For example, the circuit board of the embodiment may include a plurality of chip mounting areas in which one processor chip and one memory chip may be mounted.

[0107] For example, the circuit board of the embodiment may include a plurality of chip mounting areas in which at least one processor chip and at least one memory chip may be mounted.

[0108] The configuration of the circuit board of the embodiment except the bridge substrate 200 may be referred to as a “first substrate”, and the bridge substrate 200 may be referred to as a “second substrate”. Preferably, the bridge substrate 200 may be referred to as a connection member connecting a plurality of semiconductor devices, and other components except the bridge substrate may be referred to as a circuit board in which the connection member is buried.

[0109] In addition, the circuit board includes devices 300 and 400 embedded in the substrate together with the bridge substrate 200. The devices 300 and 400 may be embedded in the circuit board in multiple numbers. For example, the devices 300 and 400 may be embedded in multiple numbers while being horizontally spaced apart from each other in the circuit board.

[0110] Meanwhile, in the circuit board of the embodiment, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 121 may each be referred to as a substrate insulating layer. In addition, the first to third circuit layers provided on the first insulating layer 110, the second insulating layer 120, and the third insulating layer 121 may be referred to as substrate circuit layers. In addition, the first to third vias provided in the first insulating layer 110, the second insulating layer 120, and the third insulating layer 121 may be referred to as substrate vias. In addition, the first protective layer 151 provided on the first insulating layer 110 may be referred to as a first substrate protective layer. In addition, the second protective layer 152 provided below the third insulating layer 121 may be referred to as a second substrate protective layer.

[0111] Meanwhile, the bridge substrate further includes an insulating layer, a circuit layer, a via, and a protective layer. Therefore, in order to distinguish each component of the circuit board and the bridge board, the insulating layer included in the bridge substrate may be referred to as a bridge insulating layer. In addition, the circuit layer included in the bridge substrate may be referred to as a bridge circuit layer. In addition, the via included in the bridge substrate may be referred to as a bridge via. In addition, the protective layer included in the bridge substrate may be referred to as a bridge protective layer.

[0112] The circuit board may include multiple insulating layers.

[0113] For example, the circuit board may include a first insulating layer 110 , a second insulating layer 120 , and a third insulating layer 121 .

[0114] The first insulating layer 110 may refer to an insulating layer region in which a processor chip is installed among a plurality of insulating layers. In addition, the first insulating layer 110 may refer to an insulating layer region in which a bridge substrate 200 is provided. That is, the first insulating layer 110 may refer to an insulating layer in which a bridge substrate 200 connected between a plurality of processor chips is embedded while providing a mounting region for mounting a plurality of processor chips. The first insulating layer 110 may be formed of multiple layers. For example, the first insulating layer 110 may be formed of a first layer to a third layer 111, 112, and 113 from the lower side. However, the embodiment is not limited thereto, and the first insulating layer 110 may have a layer structure of two or fewer layers, or may have a layer structure of four or more layers.

[0115] The second insulating layer 120 may be disposed on one surface of the first insulating layer 110. The second insulating layer 120 may be disposed on a lower surface of the first insulating layer 110. The second insulating layer 120 may include an insulating material different from that of the first insulating layer 110. The second insulating layer 120 may include an insulating material having higher rigidity than the first insulating layer 110. The second insulating layer 120 may refer to an insulating layer region in which the devices 300 and 400 are embedded among the plurality of insulating layers.

[0116] The third insulating layer 121 may be disposed below the second insulating layer 120. The third insulating layer 121 may have a structure symmetrical to the first insulating layer 110 relative to the second insulating layer 120. The third insulating layer 121 may represent an insulating layer region connected to a mainboard among a plurality of insulating layers. For example, the third insulating layer 121 may represent an insulating layer region connected to an electronic device among a plurality of insulating layers. The number of layers of the third insulating layer 121 may be the same as the number of layers of the first insulating layer 110. Therefore, the third insulating layer 121 may include the first to third layers 122, 123, and 124. However, the embodiment is not limited thereto. For example, the third insulating layer 121 may have a greater number of layers than the first insulating layer 110, or may have a smaller number of layers than the first insulating layer 110.

[0117] The first insulating layer 110 may include a first insulating material. In addition, the second insulating layer 120 may include a second insulating material different from the first insulating material. The third insulating layer 121 may include a first insulating material similar to the insulating material of the first insulating layer 110 .

[0118] The second insulating layer 120 may be a core layer. Therefore, the circuit board of the embodiment may be a core substrate including a core layer. However, the embodiment is not limited thereto. For example, the second insulating layer 120 may represent an insulating layer disposed at an inner layer among a plurality of insulating layers, rather than a core layer. Therefore, the circuit board of the embodiment may be a coreless substrate.

[0119] The second insulating layer 120 may include a prepreg. The second insulating layer 120 may be a prepreg in which glass fibers are impregnated into a resin. The second insulating layer 120 may include a resin and glass fibers disposed in the resin. The glass fibers may also be referred to as reinforcing members. In addition, reinforcing members may be distinguished from compositions such as fillers. The resin may be an epoxy resin, but is not limited thereto. In the following, the second insulating layer 120 is described as a core layer.

[0120] The second insulating layer 120 may be a CCL (copper clad laminate) including a prepreg (PPG), or may include materials such as silicon, sapphire, glass, and ceramics. However, the second insulating layer 120 of the embodiment may include glass or sapphire as a transparent material. Therefore, the modulus rigidity of the second insulating layer 120 may improve the overall warpage characteristics of the circuit board. In addition, the circuit board of the embodiment includes a plurality of insulating layers. In addition, the sizes of the circuit layers or vias provided in the plurality of insulating layers may be different from each other. For example, at least one circuit layer or via may have a size for connecting to the bridge substrate 200 or the processor chip. In addition, at least one other circuit layer or via may have a size for connecting to the devices 300 and 400. In addition, at least another circuit layer or via may have a size for connecting to the motherboard. Therefore, the embodiment requires electrical connection reliability between the individual circuit layers or vias. Here, the electrical connection reliability may include alignment between the vias provided in each layer.

[0121] At this time, the second insulating layer 120 of the embodiment is formed of a transparent material such as sapphire or glass. Therefore, due to the transparent property of the second insulating layer 120, the embodiment is advantageous in adjusting the upper and lower alignment, and thus can improve the processability and product quality. For example, when forming a via hole in the second insulating layer 120, the embodiment can increase the position accuracy, can increase the alignment property during exposure and development, and can easily check whether the circuit layer disposed on the surface has defects.

[0122] The second insulating layer 120 may include a plurality of cavities. For example, the second insulating layer 120 may include a second cavity C2 and a third cavity C3. The second cavity C2 and the third cavity C3 may penetrate the second insulating layer 120. The second cavity C2 and the third cavity C3 may be spaced apart in a horizontal direction (e.g., in a length direction or a width direction) within the second insulating layer 120. The second cavity C2 and the third cavity C3 may provide a space in which the devices 300 and 400 are disposed.

[0123] For example, the second cavity C2 may provide a space for disposing the first device 300. In addition, the third cavity C3 may provide a space for disposing the second device 400. The width of the second cavity C2 may be greater than the width of the first device 300. Therefore, at least a portion of the second cavity C2 may be filled with the first insulating layer 110. For example, the second cavity C2 may include a first region where the first device 300 is disposed, and a second region other than the first region filled with the first insulating layer 110.

[0124] In addition, the width of the third cavity C3 may be greater than the width of the second device 400. Therefore, at least a portion of the third cavity C3 may be filled with the first insulating layer 110. For example, the third cavity C3 may include a third region where the second device 400 is disposed, and a fourth region filled with the first insulating layer 110 except the third region.

[0125] The second cavity C2 and the third cavity C3 may not overlap the first cavity C1 in a vertical direction (or a thickness direction). The first cavity C1 is formed in the first insulating layer 110 and provides a space in which the bridge substrate 200 is disposed.

[0126] The embodiment can improve the overall warpage characteristics of the circuit board by preventing the first cavity C1, the second cavity C2, and the third cavity C3 from overlapping in the vertical direction. In addition, the embodiment can minimize the signal interference between the bridge substrate 200 disposed in the first cavity C1 and the devices 300 and 400 disposed in the second cavity C2 and the third cavity C3. Therefore, the embodiment can improve the signal characteristics of the circuit board. That is, the embodiment can improve the electrical reliability and physical reliability of the circuit board through the cavity arrangement structure as described above.

[0127] The first insulating layer 110 is disposed on the second insulating layer 120. The first insulating layer 110 may be composed of a plurality of layers.

[0128] The first insulating layer 110 may include a first layer 111, a second layer 112, and a third layer 113. For example, the first insulating layer 110 may have a three-layer structure. However, the embodiment is not limited thereto. The first layer 111, the second layer 112, and the third layer 113 of the first insulating layer 110 may include an insulating material different from the insulating material of the second insulating layer 120. For example, the first insulating layer 110 may not include glass fiber. As an example, the first insulating layer 110 may include a photocurable resin or a photosensitive resin. For example, the first insulating layer 110 may include ABF (Ajinomoto deposited film). However, the embodiment is not limited thereto. For example, the first insulating layer 110 may include PID (photoimaging dielectric).

[0129] The first insulating layer 110 may include a first cavity C1 .

[0130] The first layer 111 of the first insulating layer 110 refers to a layer adjacent to the second insulating layer 120 and in which the first cavity C1 is not formed. In addition, the second layer 112 of the first insulating layer 110 refers to a layer in which the first cavity C1 is formed. In addition, the third layer 113 of the first insulating layer 110 refers to a layer disposed on the second layer 112 and filling the first cavity C1.

[0131] In addition, the first insulating layer 110 may have four or more layers. When the first insulating layer 110 has four or more layers, the first layer 111 may have more layers than the third layer. This can minimize the distance between the area where the chip is mounted and the area where the bridge substrate is provided. Therefore, the embodiment can minimize the signal transmission loss between the chips and maximize the use of the fine circuit pattern of the bridge substrate.

[0132] Furthermore, in an embodiment, the second layer 112 in which the first cavity C1 is formed may be composed of multiple layers. This can minimize signal transmission loss between chips connected through the bridge substrate by utilizing a finer circuit pattern of the bridge substrate and maximize the use of the fine circuit pattern of the bridge substrate.

[0133] The first insulating layer 110 allows for relatively fine circuit layers and vias to be formed compared to the second insulating layer 120. For example, when the first insulating layer 110 includes ABF, the width of the circuit layer or via formed in the first insulating layer 110 may be smaller than that of the circuit layer or via formed in the second insulating layer 120.

[0134] In addition, the number of terminals in a processor chip is increasing recently. Therefore, in an embodiment, the pitch of mounting pads for mounting a chip may be minimized, and thus the first insulating layer 110 should include an insulating material such as ABF or PID.

[0135] However, the embodiment configures the first insulating layer 110 using ABF, which has excellent processability and is advantageous in CTE matching with the insulating material forming the second insulating layer 120 .

[0136] Each of the first to third layers 111, 112, and 113 of the first insulating layer 110 may have a thickness in the range of 8 μm to 35 μm. Each of the first to third layers 111, 112, and 113 of the first insulating layer 110 may have a thickness in the range of 10 μm to 30 μm. Each of the first to third layers 111, 112, and 113 of the first insulating layer 110 may have a thickness in the range of 11 μm to 20 μm. If the thickness of each of the first to third layers 111, 112, and 113 of the first insulating layer 110 is less than 8 μm, the circuit layer formed on the first insulating layer 110 may not be stably protected. If the thickness of each of the first to third layers 111, 112, and 113 of the first insulating layer 110 exceeds 35 μm, it may be difficult to miniaturize the circuit layer or via formed in the first insulating layer 110, and further the thickness of the circuit board may increase.

[0137] The first layer 111 of the first insulating layer 110 is disposed on the second insulating layer 120. The first layer 111 of the first insulating layer 110 may fill at least a portion of the second cavity C2 and the third cavity C3 of the second insulating layer 120.

[0138] The second layer 112 of the first insulating layer 110 is disposed on the first layer 111 of the first insulating layer 110. The second layer 112 of the first insulating layer 110 may include a first cavity C1. The first cavity C1 may penetrate the second layer 112 of the first insulating layer 110. The first cavity C1 may provide a space in which the bridge substrate 200 is disposed within the first insulating layer 110. For example, the first cavity C1 may provide a space for embedding the bridge substrate 200 within the first insulating layer 110.

[0139] The width of the first cavity C1 may be greater than the width of the bridge substrate 200. At this time, the upper width and the lower width of the first cavity C1 may be different. For example, the lower width of the first cavity C1 may be smaller than the upper width of the first cavity C1. In addition, the width of the first cavity C1 described below may represent the lower width of the first cavity C1.

[0140] The width of the first cavity C1 may be 105% to 180% of the width of the bridge substrate 200. The width of the first cavity C1 may be 110% to 170% of the width of the bridge substrate 200. The width of the first cavity C1 may be 112% to 160% of the width of the bridge substrate 200. If the width of the first cavity C1 is less than 105% of the width of the bridge substrate 200, a problem that the bridge substrate 200 cannot be stably protected in the first cavity C1 may occur due to a process error in the process of forming the first cavity C1. In addition, if the width of the first cavity C1 is less than 105% of the width of the bridge substrate 200, stress may be concentrated on the edge area of ​​the inner wall of the first cavity C1 in the processing environment or the use environment of the circuit board, and a problem of stress transmission to the bridge substrate 200 may occur. If the width of the first cavity C1 is greater than 180% of the width of the bridge substrate 200, the size of the circuit board in the horizontal direction may increase.

[0141] The third layer 113 of the first insulating layer 110 may be disposed on the second layer 112 of the first insulating layer 110. The third layer 113 of the first insulating layer 110 may fill at least a portion of the first cavity C1 of the second layer 112 of the first insulating layer 110. For example, the third layer 113 of the first insulating layer 110 may be disposed on the second layer 112 of the first insulating layer 110 while surrounding a periphery of the bridge substrate 200 disposed in the first cavity C1.

[0142] The third insulating layer 121 may be disposed under the second insulating layer 120 .

[0143] The third insulating layer 121 may have a structure symmetrical to the first insulating layer 110 based on the second insulating layer 120 .

[0144] The third insulating layer 121 may include a first layer 122 , a second layer 123 , and a third layer 124 , but is not limited thereto.

[0145] Meanwhile, the thickness of each layer of the first insulating layer 110 may be smaller than the thickness of the second insulating layer 120 .

[0146] For example, the difference between the thickness of each layer of the first insulating layer 110 and the thickness of the second insulating layer 120 may be 15 μm or more, or 20 μm or 25 μm or more.

[0147] The circuit board of the embodiment includes a circuit layer. The circuit layer may be disposed on a surface of an insulating layer of the circuit board. For example, the circuit board of the embodiment may include a plurality of circuit layers disposed on surfaces of a plurality of insulating layers.

[0148] The circuit layer includes a first circuit layer disposed on the first insulating layer 110 .

[0149] For example, the first circuit layer includes a 1-1 circuit layer 131 disposed on the first layer 111 of the first insulating layer 110. In addition, the first circuit layer includes a 1-2 circuit layer 132 disposed on the second layer 112 of the first insulating layer 110. In addition, the first circuit layer includes a 1-3 circuit layer 133 disposed on the third layer 113 of the first insulating layer 110.

[0150] In addition, the circuit layer includes a second circuit layer disposed on the second insulating layer 120 .

[0151] For example, the second circuit layer includes a 2-1 circuit layer 134 disposed on the upper surface of the second insulating layer 120. In addition, the second circuit layer includes a 2-2 circuit layer 135 disposed on the lower surface of the second insulating layer 120.

[0152] In addition, the circuit layer includes a third circuit layer disposed on the third insulating layer 121 .

[0153] For example, the third circuit layer includes a 3-1st circuit layer 136 disposed on the first layer 122 of the third insulating layer 121. In addition, the third circuit layer includes a 3-2nd circuit layer 137 disposed on the second layer 123 of the third insulating layer 121. In addition, the third circuit layer includes a 3-3rd circuit layer 138 disposed on the third layer 124 of the third insulating layer 121.

[0154] Meanwhile, the first circuit layer includes a pad portion 131a overlapping the first cavity C1 in the vertical direction. The pad portion 131a may be in direct contact with the inner wall of the first cavity C1. For example, the pad portion 131a may have an upper surface exposed through the first cavity C1. The pad portion 131a may be a part of the 1-1st circuit layer 131 of the first circuit layer. That is, the pad portion 131a may represent a circuit layer in the 1-1st circuit layer 131 that overlaps the first cavity C1 in the vertical direction.

[0155] The pad portion 131a may be greater than the width of the first cavity C1. Therefore, the pad portion 131a may be divided into a plurality of regions.

[0156] For example, the pad portion 131a may include a first portion 131a1 that does not overlap with the first cavity C1 in the thickness direction (specifically, does not overlap with the lower region of the first cavity in the thickness direction). The upper surface of the first portion 131a1 of the pad portion 131a may not be exposed by the first cavity C1. Preferably, the first portion 131a1 of the pad portion 131a may be covered by the second layer 112 of the first insulating layer 110.

[0157] In addition, the pad portion 131a may include second portions 131a2 and 131a3 overlapping the first cavity C1 in the thickness direction. Upper surfaces of the second portions 131a2 and 131a3 of the pad portion 131a may be exposed through the first cavity C1.

[0158] The pad portion 131 a may function as a laser stopper in the process of forming the first cavity C1 .

[0159] In addition, the pad portion 131 a may be used as a mounting pad for providing the bridge substrate 200 .

[0160] In addition, the pad portion 131 a may function as a heat dissipation pad for transferring heat generated from the bridge substrate 200 .

[0161] Meanwhile, the second portions 131a2 and 131a3 of the pad portion 131a may be divided into a plurality of portions. The second portions 131a2 and 131a3 of the pad portion 131a may include a 2-1 portion 131a2 that does not overlap with at least one of the adhesive layer 500 and the bridge substrate 200 in the thickness direction. At this time, the 2-1 portion 131a2 is shown in the figure as vertically overlapping with the adhesive layer 500 as a whole, but is not limited thereto. Preferably, the 2-1 portion 131a2 represents a portion of the second portion that does not overlap with the bridge substrate 200 in the thickness direction. In addition, the 2-1 portion 131a2 may overlap with the adhesive layer 500 in the thickness direction, or may not overlap with the adhesive layer 500.

[0162] In addition, the second portion of the pad portion 131a includes a 2-2 portion 131a3 overlapping the adhesive layer 500 and the bridge substrate 200 in the thickness direction. That is, the 2-2 portion 131a3 of the second portion of the pad portion 131a provides a space where the bridge substrate 200 is actually disposed. In addition, the 2-1 portion 131a2 may be used as a free space during the process of inserting or placing the bridge substrate 200 in the first cavity C1.

[0163] Meanwhile, the first circuit layer, the second circuit layer, and the third circuit layer may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first circuit layer, the second circuit layer, and the third circuit layer may be formed of a paste or solder paste including at least one metal material having excellent bonding strength selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first circuit layer, the second circuit layer, and the third circuit layer may be formed of copper (Cu) having high conductivity and being relatively inexpensive.

[0164] The first circuit layer, the second circuit layer, and the third circuit layer may be manufactured using conventional manufacturing processes for printed circuit boards, such as an additive process, a subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and a detailed description thereof is omitted herein.

[0165] The first circuit layer, the second circuit layer, and the third circuit layer may have a thickness in the range of 7 μm to 20 μm. For example, the first circuit layer, the second circuit layer, and the third circuit layer may have a thickness in the range of 9 μm to 17 μm. The first circuit layer, the second circuit layer, and the third circuit layer may have a thickness in the range of 10 μm to 13 μm. If the thickness of the first circuit layer, the second circuit layer, and the third circuit layer is less than 7 μm, the resistance may increase, and thus the electrical characteristics may deteriorate. In addition, if the thickness of the first circuit layer, the second circuit layer, and the third circuit layer is less than 7 μm, the warping characteristics of the circuit board may deteriorate. In addition, if the thickness of the first circuit layer, the second circuit layer, and the third circuit layer exceeds 20 μm, it may be difficult to miniaturize the circuit layer. Therefore, the circuit integration of the circuit board may deteriorate. Therefore, the size of the circuit board may increase.

[0166] The first circuit layer, the second circuit layer, and the third circuit layer include pads and traces. The pads may include via pads connected to vias, core pads, or BGA pads on which adhesive balls (described later) connected to the mainboard of the electronic device are provided. In addition, the trace may represent a long linear wiring that transmits electrical signals while being connected to the pads. The pads (specifically, via pads) of the first circuit layer, the second circuit layer, and the third circuit layer may have a width in the range of 20 μm to 50 μm. The pads of the first circuit layer, the second circuit layer, and the third circuit layer may have a width in the range of 22 μm to 40 μm. The pads of the first circuit layer, the second circuit layer, and the third circuit layer may have a width in the range of 25 μm to 35 μm.

[0167] At the same time, the traces of the first circuit layer, the second circuit layer, and the third circuit layer may have a specific line width and a specific spacing. For example, the line width of the traces of the first circuit layer, the second circuit layer, and the third circuit layer may have a range of 6μm to 20μm. For example, the line width of the traces of the first circuit layer, the second circuit layer, and the third circuit layer may have a range of 7μm to 15μm. For example, the line width of the traces of the first circuit layer, the second circuit layer, and the third circuit layer may have a range of 8μm to 12μm. In addition, the spacing between the traces of the first circuit layer, the second circuit layer, and the third circuit layer may have a range of 6μm to 20μm. For example, the spacing between the traces of the first circuit layer, the second circuit layer, and the third circuit layer may have a range of 7μm to 15μm. For example, the spacing between the traces of the first circuit layer, the second circuit layer, and the third circuit layer may have a range of 8μm to 12μm.

[0168] Meanwhile, the first circuit layer, the second circuit layer, and the third circuit layer may have different thicknesses, widths, and intervals. For example, the first circuit layer and the third circuit layer are disposed on the first insulating layer 110 and the third insulating layer 121 as the first insulating material. In addition, the second circuit layer is disposed on the second insulating layer 120 as the second insulating material. Therefore, the thickness, width, and interval of the first circuit layer and the third circuit layer may be smaller than the thickness, width, and interval of the second circuit layer, but are not limited thereto.

[0169] For example, the thickness, width, and spacing of a first circuit layer may decrease as the distance from a second circuit layer increases.

[0170] For example, the thickness, width, and spacing of the 1st to 3rd circuit layers 133 in the first circuit layer can be minimal. This means that the 1st to 3rd circuit layers 133 are used as pads connected to the processor chip, and therefore must have specifications corresponding to the terminals of the processor chip. In addition, the 1st to 3rd circuit layers 133 need to be integrated. Therefore, the embodiment allows the thickness, width, and spacing of the 1st to 3rd circuit layers 133 in the first circuit layer to be minimal.

[0171] In addition, the thickness, width and interval of the 1-1 circuit layer 131 in the first circuit layer may be the largest. For example, the thickness, width and interval of the 1-1 circuit layer 131 may correspond to the thickness, width and interval of the second circuit layer.

[0172] In addition, the thickness, width, and spacing of the 1-2 circuit layer 132 of the first circuit layer may be smaller than the thickness, width, and spacing of the 1-1 circuit layer 131 and larger than the thickness, width, and spacing of the 1-3 circuit layer 133. Therefore, the embodiment minimizes the signal transmission loss caused by the difference in circuit layer specifications by varying the thickness, width, and spacing of each layer of the first circuit layer.

[0173] Meanwhile, the third circuit layer is connected to the main board of the electronic device. Therefore, the third circuit layer may have specifications corresponding to the specifications of the main board of the electronic device (eg, the number of pads, the intervals between pads, etc.).

[0174] Meanwhile, the circuit board of the embodiment includes a via. The via penetrates at least one insulating layer. Therefore, the via may also be referred to as a through-electrode. The via may penetrate one insulating layer. Differently, the via may penetrate at least two or more insulating layers together.

[0175] The via holes include a first via hole penetrating the first insulating layer 110 .

[0176] The first via hole includes a 1-1 via hole 141 penetrating the first layer 111 of the first insulating layer 110. The first via hole includes a 1-2 via hole 142 penetrating the second layer 112 of the first insulating layer 110. The first via hole includes a 1-3 via hole 143 penetrating the third layer 113 of the first insulating layer 110.

[0177] The via holes include a second via hole 144 penetrating the second insulating layer 120 .

[0178] In addition, the via hole includes a third via hole penetrating the third insulating layer 121 .

[0179] The third via hole includes a 3-1 via hole 145 penetrating the first layer 122 of the third insulating layer 121. The third via hole includes a 3-2 via hole 146 penetrating the second layer 123 of the third insulating layer 121. The third via hole includes a 3-3 via hole 147 penetrating the third layer 124 of the third insulating layer 121.

[0180] Each of the first to third vias may have a width in the range of 10 μm to 60 μm. Each of the first to third vias may have a width in the range of 15 μm to 50 μm. Each of the first to third vias may have a width in the range of 20 μm to 40 μm. At this time, each of the first to third vias includes a first surface and a second surface opposite to the first surface. In addition, the width of the first surface is different from the width of the second surface. At this time, the width of each of the first to third vias may represent the width of the surface having a relatively larger width among the first surface and the second surface.

[0181] At this time, the first to third vias may have different widths. In addition, for example, the second via 144 may have a greater width than the first and second vias. In addition, the second via 144 may have a cross-sectional shape different from that of the first and second vias, but is not limited thereto.

[0182] Meanwhile, the first via hole of the embodiment may include via holes having different thicknesses or widths in the same layer.

[0183] For example, the 1-1th via hole 141 may include a first sub-via hole 141 a and a second sub-via hole 141 b depending on the position.

[0184] The first sub-via hole 141 a of the 1-1th via hole 141 refers to a via hole connected to the second circuit layer 134 disposed on the upper surface of the second insulating layer 120 .

[0185] The second sub-via 141b of the 1-1st via 141 is horizontally spaced apart from the first sub-via 141a of the 1-1st via 141. The second sub-via 141b of the 1-1st via 141 is connected to the devices 300 and 400 inserted into the second insulating layer 120. For example, the second sub-via 141b of the 1-1st via 141 is connected to the terminals 310 and 410 of the devices 300 and 400.

[0186] Therefore, the first sub-via hole 141 a and the second sub-via hole 141 b of the 1-1th via hole 141 may have different widths or thicknesses.

[0187] For example, the width of the first sub-via 141a of the 1-1 via 141 may be greater than the width of the second sub-via 141b of the 1-1 via 141. That is, the second sub-via 141b of the 1-1 via 141 is connected to the terminals 310 and 410 of the devices 300 and 400, and therefore must have a width or pitch corresponding to the specifications of the terminals 310 and 410. However, the first sub-via 141a of the 1-1 via 141 is connected to the second circuit layer. In addition, the first sub-via 141a of the 1-1 via 141 may have a width corresponding to the width of the second via 144 to minimize signal transmission loss.

[0188] Meanwhile, the thickness of the first sub-via hole 141a of the 1-1 via hole 141 may correspond to the thickness of the first layer 111 of the first insulating layer 110. In addition, the thickness of the second sub-via hole 141b of the 1-1 via hole 141 may be different from the thickness of the first sub-via hole 141a of the 1-1 via hole 141. For example, the thickness of the second sub-via hole 141b of the 1-1 via hole 141 may be different from the thickness of the first layer 111 of the first insulating layer 110.

[0189] For example, the positions of the upper surfaces of the terminals 310 and 410 of the devices 300 and 400 may be different from the position of the upper surface of the second circuit layer 134 disposed on the upper surface of the second insulating layer 120. For example, the upper surfaces of the terminals 310 and 410 of the devices 300 and 400 may be positioned higher than the upper surface of the second circuit layer 134 disposed on the upper surface of the second insulating layer 120, or may be positioned lower than the upper surface of the second circuit layer 134.

[0190] Therefore, in one example, the thickness of the first sub-via 141a of the 1-1 via 141 may be greater than the thickness of the second sub-via 141b of the 1-1 via 141. In addition, in another example, the thickness of the first sub-via 141a of the 1-1 via 141 may be less than the thickness of the second sub-via 141b of the 1-1 via 141.

[0191] Meanwhile, the 1-3rd via 143 may include first to third sub-vias 143a, 143b, and 143c depending on the position. The first sub-via 143a of the 1-3rd via 143 may indicate a via that overlaps the bridge substrate 200 in a vertical direction. For example, the first sub-via 143a of the 1-3rd via 143 indicates a via that is directly connected to the bridge substrate 200.

[0192] The second sub-via 143 b of the 1 - 3 via 143 represents a via connected to a mounting pad (not shown) connected to a processor chip.

[0193] The third sub-via 143 c of the 1-3 th via 143 represents a via connected to a mounting pad (not shown) connected to a memory chip.

[0194] In addition, the first sub-via 143a of the 1-3rd via hole 143 may have a different thickness from the second sub-via 143b and the third sub-via 143c of the 1-3rd via hole 143. In addition, the first sub-via 143a of the 1-3rd via hole 143 may have a different width from the second sub-via 143b and the third sub-via 143c of the 1-3rd via hole 143.

[0195] In addition, the second sub-via 143b of the 1-3rd via 143 needs to be miniaturized for connection with a processor chip mounted on a substrate. Therefore, the second sub-via 143b of the 1-3rd via 143 may have a smaller width than the third sub-via 143c of the 1-3rd via 143.

[0196] Meanwhile, the third sub-via hole 143 c of the 1-3rd via hole 143 may have a greater width than the first sub-via hole 143 a and the second sub-via hole 143 b of the 1-3rd via hole 143 .

[0197] In addition, the first sub-via 143a of the 1-3 via 143 may have a smaller width than the second sub-via 143b of the 1-3 via 143. This may reduce the signal transmission length connecting the processing chip mounted on the substrate, thereby reducing signal loss when transmitting signals between chips.

[0198] As described above, in an embodiment, the first via hole provided in the first insulating layer 110 has different thicknesses or widths depending on its position or function. In an embodiment, signal transmission loss occurring in a circuit board connected to the processor chip, the devices 300 and 400, and the bridge substrate 200 can be minimized, and thus communication performance can be improved.

[0199] Meanwhile, the via hole may be formed by forming a through hole penetrating each insulating layer and filling the inside of the formed through hole with a conductive material.

[0200] The through hole can be formed by any of mechanical, laser and chemical processing methods. The through hole can be formed using any of the mechanical processing methods of milling, drilling and wiring. In addition, the through hole can be formed using any of the laser processing methods of UV or CO2. In addition, the through hole can be formed using a chemical processing method including a chemical reagent such as aminosilane, ketone, etc.

[0201] When forming the through-holes, the through-holes may be filled with a conductive material to form each via. The metal material forming the vias may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material filling may use any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet, and dispensing.

[0202] At the same time, the circuit board of the embodiment provides a mounting area in which at least two different types of chips are mounted. In addition, the circuit board of the embodiment provides an embedding area in which at least one passive device is embedded. The mounting area may refer to a chip placement area arranged outside the circuit board. In addition, the embedding area may refer to a chip placement area arranged inside the circuit board.

[0203] The circuit board can transmit and receive signals acquired or processed by at least two processor chips or by a processor chip and a memory chip. At this time, the connection between at least two processor chips or a processor chip and a memory chip is implemented in the bridge substrate 200 .

[0204] That is, the circuit board provides a chip mounting area in which a plurality of first and second chips of different types can be mounted. At this time, the first and second chips can be first and second processor chips that separate application processors according to functions.

[0205] For example, the circuit board of the embodiment provides a first mounting area in which a first processor chip is mounted. In addition, the circuit board of the embodiment provides a second mounting area in which a second processor chip is mounted. At this time, the first processor chip may be any one of application processor (AP) chips such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, etc. The second processor chip may be a processor chip in an application processor (AP) chip such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, etc. that is different from the first processor chip. For example, the first processor chip may be a central processing unit chip, and the second processor chip may be a graphics processor chip. That is, the circuit board of the embodiment may be a circuit board that separates the application processor by function and separates the dies of at least two processor chips separated by function.

[0206] Meanwhile, recently, as the functions required for application processors increase, separate processor chips for the respective functions and circuit boards on which these processor chips can be mounted are required. At this time, even if the application processor is divided into two processor chips for the respective functions, the number of terminals (input / output) provided on the respective processor chips is increasing. At this time, unlike the case where all functions are processed by one application processor chip in the comparative example, when the processor chip is divided into at least two, each processor chip must be electrically connected to each other to exchange signals.

[0207] At this time, when the separation distance between each processor chip is large, a fine pattern as in the embodiment may not be required. However, when the separation distance between each processor chip is large, the communication speed for mutual signal exchange may be reduced. In addition, when the separation distance between each processor chip increases, the power consumption required for communication increases. In addition, when the separation distance between each processor chip is large, the length of the trace connecting each processor chip also increases, which leads to susceptibility to noise and increases signal transmission loss.

[0208] That is, for reliability, the separation distance between processor chips must be less than 150 μm. For example, for reliability, the separation distance between processor chips must be less than 120 μm. For example, for reliability, the separation distance between processor chips should be less than 100 μm.

[0209] Therefore, in order to connect all wirings between the first processor chip and the second processor chip within the limited space as described above, it is necessary to refine the circuit pattern to a specific line width and a specific interval or less.

[0210] In addition, conventionally, there are N connection lines between the first processor chip and the second processor chip. And, if there are N connection lines, the refinement level of the circuit pattern within the above-mentioned limited space may be different from that of the embodiment.

[0211] On the other hand, the number of terminals in the first processor chip and the second processor chip is gradually increasing due to recent 5G, Internet of Things (IOT), improved image quality, improved communication speed, etc. Therefore, recently, the connection line between the first processor chip and the second processor chip may be more than 2 times (2N), more than 3 times (3N), or more than 10 times (10N) that of the connection line of the related art.

[0212] Therefore, in order to mount the first processor chip and the second processor chip on one circuit board while minimizing the separation distance therebetween and to connect the first processor chip and the second processor chip to each other within a limited space, ultra-fineness of the circuit layer in the circuit board is required.

[0213] However, there is a limit to the miniaturization of the circuit layer. Therefore, the embodiment allows the bridge substrate 200 to be disposed on the first layer of the first insulating layer 110. In addition, the embodiment allows connection between at least two chips to be mounted on the circuit board through the bridge substrate 200.

[0214] Therefore, as described above, the width or thickness of the first sub-via 143a of the 1-3rd via 143 may be different from the width or thickness of the other sub-vias of the 1-3rd via 143. This is because the thickness and width of the first sub-via 143a of the 1-3rd via 143 are determined according to the height of the bridge substrate 200 and the width of the wiring layer included in the bridge substrate 200.

[0215] For example, the height of the topmost wiring layer of the bridge substrate 200 can be positioned lower than the upper surface of the 1-2 circuit layer 132. Alternatively, the height of the topmost wiring layer of the bridge substrate 200 can be positioned higher than the upper surface of the 1-2 circuit layer 132. Therefore, the thickness of the first sub-via 143a of the 1-3 via 143 can be greater than the thickness of the other sub-vias, or can be less than the thickness of the other sub-vias. However, in an embodiment, the thickness difference between the first sub-via 143a of the 1-3 via 143 and the other sub-vias of the 1-3 via 143 is minimized. Thus, the embodiment can improve the reliability of the circuit board. In this case, the topmost wiring layer of the bridge substrate 200 can represent the circuit layer of the bridge substrate, or can represent the pad layer of the bridge substrate.

[0216] This can be achieved by structural features of the bridge substrate 200 described later.

[0217] Meanwhile, the circuit board of the embodiment includes a first protection layer 151. The first protection layer 151 may be disposed on the first insulating layer 110.

[0218] In addition, the circuit board of the embodiment includes a second protection layer 152. The second protection layer 152 may be disposed under the third insulating layer 121.

[0219] Each of the first protective layer 151 and the second protective layer 152 includes at least one opening.

[0220] Meanwhile, the bridge substrate 200 is disposed in the first cavity C1 of the first insulating layer 110. That is, the bridge substrate 200 is embedded in the first insulating layer 110. Specifically, the bridge substrate 200 may be covered by the third layer 113 of the first insulating layer 110 while being disposed in the first cavity C1 formed in the second layer 112 of the first insulating layer 110.

[0221] The bridge substrate 200 is electrically connected to the first circuit layer and the first via formed in the first insulating layer 110 .

[0222] For example, the bridge substrate 200 is connected to the 1-3rd via hole 143 penetrating the third layer 113 of the first insulating layer 110. Preferably, the bridge substrate 200 is connected to the first sub-via hole 143a of the 1-3rd via hole 143.

[0223] At this time, the first sub-via 143a of the 1-3 via 143 can be divided into multiple groups. For example, the first sub-via 143a of the 1-3 via 143 includes at least one first group of vias connected to the first processor chip. In addition, the first sub-via 143a of the 1-3 via 143 includes at least one second group of vias connected to the second processor chip. In addition, the bridge substrate 200 is connected to the first group of vias and the second group of vias of the first sub-via 143a of the 1-3 via 143. For example, the bridge substrate 200 is electrically connected between the first group of vias and the second group of vias of the first sub-via 143a. Therefore, the bridge substrate 200 is connected between the first processor chip and the second processor chip. Specifically, the first processor chip includes a plurality of first terminals. In addition, the second processor chip includes a plurality of second terminals. At this time, at least one of the plurality of first terminals must be electrically connected to at least one of the plurality of second terminals. At this time, the embodiment uses the bridge substrate 200 to electrically connect at least one of the plurality of first terminals and at least one of the plurality of second terminals.

[0224] The bridge substrate 200 can electrically connect multiple processor chips mounted on the circuit board, performing die-to-die interconnection between the dies. Multiple processor chips must be electrically connected to each other in a limited space. At this time, in order to connect multiple processor chips, a high-density connection circuit is required in a limited space. Therefore, in an embodiment, the bridge substrate 200 including a high-density circuit layer is disposed in the first cavity C1 of the first insulating layer 110. In addition, the embodiment uses the bridge substrate 200 to electrically connect multiple processor chips mounted on the circuit board.

[0225] The bridge substrate 200 may include an ultra-fine pattern.

[0226] The bridge substrate 200 includes an insulating layer 210 and a circuit layer disposed on the insulating layer 210 .

[0227] refer to Figure 6 The bridge substrate 200 may include one insulating layer, but is not limited thereto. For example, the bridge substrate 200 may include an insulating layer having a multi-layer laminate structure.

[0228] Therefore, the circuit layer of the bridge substrate 200 may include a first circuit layer 220 a disposed on an upper surface of the insulating layer 210 and a second circuit layer 220 b disposed on a lower surface of the insulating layer 210 .

[0229] In addition, the bridge substrate 200 includes a via hole 230 penetrating the insulating layer 210. The via hole 230 of the bridge substrate 200 electrically connects the first circuit layer 220a and the second circuit layer 220b of the bridge substrate 200.

[0230] In addition, the bridge substrate 200 includes a protective layer disposed on the insulating layer 210. For example, the bridge substrate 200 includes a first protective layer 240a disposed on the upper surface of the insulating layer 210. In addition, the bridge substrate 200 includes a second protective layer 240b disposed on the lower surface of the insulating layer 210. The first protective layer 240a and the second protective layer 240b may be solder resists, but are not limited thereto.

[0231] The first protective layer 240a is disposed on the upper surface of the insulating layer 210. In addition, the first protective layer 240a includes an opening that overlaps at least a portion of the upper surface of the first circuit layer 220a in the thickness direction. For example, the first protective layer 240a may include a first opening that overlaps with the first circuit layer 220a connected to the first group of vias in the first sub-via 143a in the thickness direction. In addition, the first protective layer 240a may include a second opening that overlaps with the first circuit layer 220a connected to the second group of vias in the first sub-via 143a in the thickness direction.

[0232] In addition, the first circuit layer 220 a overlapping the second opening of the first protection layer 240 a in the thickness direction may serve as a second pad layer connected to the second group of via holes in the first sub-via 143 a .

[0233] The second protective layer 240b is disposed on the lower surface of the insulating layer 210. At this time, the second protective layer 240b does not include an opening. For example, the second protective layer 240b is disposed to completely cover the side surface and the lower surface of the second circuit layer 220b of the bridge substrate 200.

[0234] At this time, the insulating layer 210 , the first circuit layer 220 a , and the second circuit layer 220 b constituting the bridge substrate 200 may be referred to as a redistribution layer (RDL).

[0235] In addition, the redistribution layer (RDL) may include a first protection layer 240 a and a second protection layer 240 b .

[0236] The insulating layer 210 of the bridge substrate 200 may include an organic material. The insulating layer 210 of the bridge substrate 200 may include an insulating material different from the first insulating layer 110, the second insulating layer 120, and the third insulating layer 121. For example, the bridge substrate 200 may include an insulating material having excellent processability and elasticity. For example, the insulating layer 210 of the bridge substrate 200 may include polyimide (PI).

[0237] In this case, the insulating layer of the bridge substrate is generally formed of a silicon material. Differently, the bridge substrate 200 of the embodiment includes polyimide (PI).

[0238] Therefore, embodiments allow the insulating layer 210 of the bridge substrate 200 to have a CTE similar to that of the first insulating layer 210 of the circuit board, thereby minimizing stress applied to the bridge substrate 200. Thus, embodiments allow the physical and electrical reliability of the bridge substrate 200 to be improved.

[0239] In addition, the embodiment may reduce the cost of the bridge substrate 200 by changing the material of the insulating layer 210 applied to the bridge substrate 200 to polyimide which is cheaper than a silicon substrate.

[0240] At this time, the alignment state between the first pad layer of the first circuit layer 220a of the bridge substrate 200 and the first group of vias of the first sub-via 143a of the 1-3 via 143 greatly affects the product reliability of the circuit board and the semiconductor package. In addition, the alignment state between the second pad layer of the first circuit layer 220a of the bridge substrate 200 and the second group of vias of the first sub-via 143a of the 1-3 via 143 greatly affects the product reliability of the circuit board and the semiconductor package. Therefore, the embodiment uses polyimide (PI) having a transparent property as the insulating layer of the bridge substrate 200. Thus, the embodiment can improve the alignment between the first pad layer and the second pad layer of the bridge substrate 200 and the first sub-via 143a of the 1-3 via 143.

[0241] In addition, embodiments may stably protect the bridge substrate 200 from stress generated during thermal deformation of the first insulating layer 110 through CTE matching. Thus, embodiments may stably achieve electrical connection between a plurality of semiconductor devices through the bridge substrate 200 and may stably operate the plurality of semiconductor devices.

[0242] That is, conventionally, the insulating layer of the bridge substrate is formed of a silicon material. At this time, silicon has a large CTE difference with the insulating layer constituting the first insulating layer 110. In addition, silicon has a rigid property. Therefore, a problem with the conventional bridge substrate is that when the first insulating layer 110 is thermally deformed, the bridge substrate including silicon does not flow together. Therefore, the conventional bridge substrate has reliability problems such as cracks during thermal deformation.

[0243] In contrast, embodiments allow the insulating layer 210 of the bridge substrate 200 to have a CTE similar to that of the first insulating layer 110 and have flexible characteristics. Therefore, embodiments allow the bridge substrate 200 to flow during thermal deformation of the first insulating layer 110, thereby solving reliability issues such as cracks of the bridge substrate 200.

[0244] In addition, the embodiment allows the insulating layer 210 to include polyimide (PI), so that the thickness of the bridge substrate 200 can be easily controlled. For example, in the conventional case including a silicon substrate, a polishing process of the silicon substrate must be performed to control the thickness of the bridge substrate. Therefore, due to the difficulty in processing in the conventional bridge substrate, it is difficult to control the thickness of the bridge substrate to a desired thickness. In addition, the conventional bridge substrate can use TSV (Through Silicon Via) to connect the pad portions set on different layers, but there is a problem that the processing difficulty of TSV is high and the manufacturing cost increases accordingly.

[0245] In contrast, the embodiment allows the insulating layer 210 of the bridge substrate 200 to include polyimide (PI), thereby easily controlling the thickness of the bridge substrate 200. In addition, the embodiment can easily control the total thickness of the bridge substrate 200 according to the depth of the first cavity C1 formed in the first insulating layer 110. Therefore, the embodiment can minimize the height difference between the first circuit layer 220a of the bridge substrate 200 and the 1-2 circuit layer 132 disposed on the second layer 112 of the first insulating layer 110. Therefore, the embodiment can improve product reliability.

[0246] In addition, the embodiment can facilitate electrical connection between pad layers disposed in different layers by including an organic material in the insulating layer 210 of the bridge substrate 200. For example, the embodiment forms a via hole penetrating the insulating layer 210 of the bridge substrate 200, and electrically connects the pad layers disposed in different layers through the via hole. Thus, the embodiment can stably supply power to the semiconductor device by using the pad layers disposed on the upper and lower sides of the bridge substrate 200, respectively.

[0247] In particular, the number of power terminals and communication terminals of semiconductor packages applied to servers and / or HPCs (high performance computers) is increasing significantly. Therefore, in the case of a conventional bridge substrate including an inorganic material, it may be difficult to stably supply power to the bridge substrate and the semiconductor device due to an insufficient number of power lines and / or a limitation in power intensity, and the semiconductor package may not be able to operate stably due to insufficient power of the bridge substrate and / or the semiconductor device.

[0248] In contrast, the embodiment can provide a bridge substrate 200 including an organic insulating layer, thereby increasing the number of power lines or increasing the power intensity. Therefore, the embodiment can achieve stable power supply to the bridge substrate 200 and / or the semiconductor device, and further can prevent the power supplied to the bridge substrate and / or the semiconductor device from decreasing through decoupling of the capacitor function.

[0249] At the same time, reference Figure 5 , the bridge substrate 200 of the second embodiment may further include a first pad layer 250a and a second pad layer 250b. In the first circuit layer 220a of the bridge substrate 200, the first pad layer 250a of the bridge substrate 200 is disposed on the first circuit layer vertically overlapping with the first opening of the first protective layer 240a. In addition, in the first circuit layer 220a of the bridge substrate 200, the second pad layer 250b of the bridge substrate 200 is disposed on the first circuit layer vertically overlapping with the second opening of the first protective layer 240a. Therefore, compared with the first embodiment, the bridge substrate of the second embodiment can further ensure the alignment between the first sub-via 143a of the 1-3 via 143 and the pad layer. At the same time, the first pad layer 250a and the second pad layer 250b can also be referred to as bumps.

[0250] At the same time, reference Figure 6 , the bridge substrate 200 of the third embodiment may have a multilayer structure. For example, the bridge substrate 200 may include a first insulating layer 210a, a second insulating layer 210b, and a third insulating layer 210c. In addition, the bridge substrate 200 may include a first circuit layer 220a disposed on the first insulating layer 210a. In addition, the bridge substrate 200 may include a second circuit layer 220b disposed between the lower surface of the first insulating layer 210a and the upper surface of the second insulating layer 210b. In addition, the bridge substrate 200 may include a third circuit layer 220c disposed between the lower surface of the second insulating layer 210b and the upper surface of the third insulating layer 210c. In addition, the bridge substrate 200 may include a fourth circuit layer 220d disposed on the lower surface of the third insulating layer 210c. In addition, the bridge substrate 200 of the third embodiment includes a first protective layer 240a disposed on the upper surface of the first insulating layer 210a. In addition, the bridge substrate 200 of the third embodiment includes a second protective layer 240b disposed on the lower surface of the third insulating layer 210c. In addition, the bridge substrate 200 of the third embodiment includes a first via hole 230a penetrating the first insulating layer 210a. In addition, the bridge substrate 200 of the third embodiment includes a second via hole 230b penetrating the second insulating layer 210b. In addition, the bridge substrate 200 of the third embodiment includes a third via hole 230c penetrating the third insulating layer 210c.

[0251] The following description will focus on the bridge substrate 200 of the first embodiment. However, the bridge substrate 200 may also have Figure 5 and Figure 6 The structure shown.

[0252] The slope of the side surface of the via hole 230 penetrating the insulating layer 210 of the bridge substrate 200 may be different from the slope of the side surface of the first via hole penetrating the first insulating layer 110 .

[0253] Preferably, the slope of the side surface of the via hole 230 penetrating the insulating layer 210 of the bridge substrate 200 may be closer to a right angle than the slope of the side surface of the first via hole penetrating the first insulating layer 110 .

[0254] Specifically, a difference between upper and lower widths of the via hole 230 penetrating the insulating layer 210 of the bridge substrate 200 of the embodiment may be smaller than a difference between upper and lower widths of the first via hole penetrating the first insulating layer 110 .

[0255] For example, the lower width of the via hole 230 penetrating the insulating layer 210 of the bridge substrate 200 may be in the range of 95% to 105% of the upper width of the via hole 230. For example, the lower width of the via hole 230 penetrating the insulating layer 210 of the bridge substrate 200 may be in the range of 96% to 104% of the upper width of the via hole 230. For example, the lower width of the via hole 230 penetrating the insulating layer 210 of the bridge substrate 200 may be in the range of 97% to 103% of the upper width of the via hole 230. Therefore, the embodiment can improve the electrical characteristics of the bridge substrate 200.

[0256] Meanwhile, the reason why the slope of the side surface of the via hole 230 of the bridge substrate 200 may be substantially close to a right angle is because the insulating layer 210 of the bridge substrate 200 includes polyimide (PI). That is, the embodiment requires that the insulating layer 210 includes polyimide (PI), and a through hole penetrating the insulating layer 210 of the bridge substrate 200 may be formed by using a UV laser. Therefore, the slope of the inner wall of the via hole 230 penetrating the insulating layer 210 relative to the upper surface or the lower surface of the insulating layer 210 may be close to a right angle.

[0257] At the same time, reference Figure 7 and Figure 8 , the first circuit layer 220 a , the second circuit layer 220 b , and the via 230 a of the bridge substrate 200 of the embodiment may have a multi-layer structure.

[0258] Specifically, the first circuit layer 220a of the bridge substrate 200 may include a first metal layer 220a1 and a second metal layer 220a2. In addition, the second circuit layer 220b of the bridge substrate 200 may also include a first metal layer 220b1 and a second metal layer 220b2 corresponding to the first circuit layer 220a. In addition, the via 230a of the bridge substrate 200 may also include a first metal layer 230a1 and a second metal layer 230a2 corresponding to the first circuit layer 220a and the second circuit layer 220b.

[0259] Hereinafter, the first metal layer 220a1 and the second metal layer 220a2 of the first circuit layer 220a will be described. The second circuit layer 220b and the first metal layers 220b1 and 230a1 and the second metal layers 220b2 and 230a2 of the via 230a may be formed to correspond to the first metal layer 220a1 and the second metal layer 220a2 of the first circuit layer 220a described below.

[0260] The first metal layer 220a1 of the first circuit layer 220a may be a metal layer formed by sputtering. The first metal layer 220a1 may be a seed layer. The first metal layer 220a1 may have a single layer structure, or may have a double layer structure.

[0261] When the first metal layer 220a1 has a single-layer structure, the first metal layer 220a1 may include only a first layer containing at least one of nickel (Ni) and chromium (Cr). In addition, when the first metal layer 220a1 has a double-layer structure, the first metal layer 220a1 may further include a second layer containing copper (Cu) on the first layer. Hereinafter, the first metal layer 220a1 will be described as including a first layer and a second layer. However, the embodiment is not limited thereto.

[0262] The first layer of the first metal layer 220a includes at least one of nickel (Ni) and chromium (Cr) formed by a sputtering process. In addition, the second layer of the first metal layer 220a may be formed by sputtering a metal including copper (Cu) on the first layer of the first metal layer 220a.

[0263] The first layer of the first metal layer 220a may have a thickness of 0.01 μm to 0.15 μm. For example, the first layer of the first metal layer 220a may have a thickness of 0.03 μm to 0.14 μm. For example, the first layer of the first metal layer 220a may have a thickness of 0.05 μm to 0.12 μm. If the first layer of the first metal layer 220a is less than 0.01 μm, the first metal layer 220a may not be used as a seed layer. In addition, if the first layer of the first metal layer 220a is less than 0.01 μm, adhesion between the first metal layer 220a and the second metal layer 220b may not be ensured.

[0264] In addition, if the thickness of the first metal layer 220a1 is greater than 0.15 μm, the line width and spacing of the first circuit layer 220a of the bridge substrate 200 increase. For example, if the thickness of the first metal layer 220a1 is greater than 0.15 μm, it may be difficult to provide the first circuit layer 220a of the bridge substrate 200 in an ultra-fine pattern.

[0265] The second layer of the first metal layer 220a1 may have a thickness of 0.1 μm to 0.35 μm. For example, the second layer of the first metal layer 220a1 may have a thickness of 0.12 μm to 0.34 μm. For example, the second layer of the first metal layer 220a1 may have a thickness of 0.15 μm to 0.33 μm.

[0266] Meanwhile, the total thickness of the first metal layer 220a1 including the first layer and the second layer may be 0.5 μm or less. Preferably, the total thickness of the first metal layer 220a1 including the first layer and the second layer may be 0.4 μm or less. More preferably, the total thickness of the first metal layer 220a1 including the first layer and the second layer may be 0.3 μm or less. If the total thickness of the first metal layer 220a1 including the first layer and the second layer exceeds 0.5 μm, it may be difficult to miniaturize the first circuit layer 220a. Specifically, the process of forming the first circuit layer 220a of the bridge substrate 200 includes a seed layer removal process for removing the first metal layer 220a1. At this time, as the thickness of the first metal layer 220a1 increases, the etching amount in the seed layer processing increases, and thus it may be difficult to refine the first circuit layer 220a of the bridge substrate 200.

[0267] The first metal layer 220 a 1 of the embodiment is formed by a sputtering process, and miniaturization of the first circuit layer 220 a of the bridge substrate 200 is possible.

[0268] The second metal layer 220a2 may be an electroplated layer formed by electroplating the first metal layer 220a1 as a seed layer. The second metal layer 220a2 may have a thickness in the range of 2 μm to 12 μm. The second metal layer 220a2 may have a thickness in the range of 3 μm to 11 μm. The second metal layer 220a2 may have a thickness in the range of 4 μm to 10 μm.

[0269] If the thickness of the second metal layer 220a2 is less than 2 μm, the second metal layer 220a2 may also be etched in the seed layer etching process, and thus, it may be difficult to normally implement the first circuit layer 220a of the bridge substrate 200. If the thickness of the second metal layer 220a2 is greater than 12 μm, it may be difficult to miniaturize the first circuit layer 220a of the bridge substrate 200.

[0270] In addition, the first metal layer 230a1 of the via 230a may be formed of a metal layer different from the first metal layer 220a1 of the first circuit layer 200a or the first metal layer 220b1 of the second circuit layer 220b. The first metal layer 230a1 of the via 230a may contain palladium (Pd), which is a metal different from the first metal layer 220a1 of the first circuit layer 220a or the first metal layer 220b1 of the second circuit layer 220b.

[0271] The total thickness of the first circuit layer 220a having the layer structure as described above may be in the range of 3 μm to 13 μm. The total thickness of the first circuit layer 220a having the layer structure as described above may be in the range of 4 μm to 12 μm. The total thickness of the first circuit layer 220a having the layer structure as described above may be in the range of 5 μm to 11 μm. If the thickness of the first circuit layer 220a is less than 5 μm, the resistance of the first circuit layer 220a increases, and the reliability associated with the first processor chip and the second processor chip may be reduced. If the thickness of the first circuit layer 220a exceeds 11 μm, it may be difficult to achieve the desired fine pattern in the bridge substrate 200.

[0272] Therefore, the first circuit layer 220a may be an ultra-fine pattern. For example, the first circuit layer 220a may have a line width of 5 μm or less. For example, the first circuit layer 220a may have a line width of 3 μm or less. For example, the first circuit layer 220a may have a line width of 2 μm or less. The first circuit layer 220a may have a spacing of 5 μm or less. The spacing may represent the spacing between the traces of the first circuit layer 220a disposed on the same layer. For example, the first circuit layer 220a may have a spacing of 3 μm or less. For example, the first circuit layer 220a may have a spacing of 2 μm or less.

[0273] Preferably, the first circuit layer 220a may have a line width of 1 μm to 5 μm. The first circuit layer 220a may have a line width of 1.2 μm to 3 μm. The first circuit layer 220a may have a line width of 1.5 μm to 2 μm. If the line width of the first circuit layer 220a is less than 1 μm, the resistance of the first circuit layer 220a increases, and thus normal communication with the processor chip may be difficult. If the line width of the first circuit layer 220a is greater than 5 μm, it may be difficult to implement the bridge substrate 200 for connection between multiple processor chips in a limited space. For example, if the line width of the first circuit layer 220a is greater than 6 μm, it may be difficult to place the bridge substrate 200 including traces for connection between multiple processor chips in the first cavity C1 formed in a limited space.

[0274] Meanwhile, the second circuit layer 220 b of the bridge substrate 200 may also include a first metal layer 220 b 1 and a second metal layer 220 b 2 having a structure corresponding to that of the first circuit layer 220 a .

[0275] In addition, the via 230 a of the bridge substrate 200 may also include a first metal layer 230 a 1 and a second metal layer 230 a 2 having structures corresponding to the first circuit layer 220 a and the second circuit layer 220 b .

[0276] Meanwhile, the second metal layer 230 a 2 of the via hole 230 a may have different structures according to embodiments.

[0277] For example, Figure 7 As shown, the second metal layer 230 a 2 of the via hole 230 a may be configured to completely fill the through hole penetrating the insulating layer 210 of the bridge substrate 200 .

[0278] As another example, Figure 8 As shown, the second metal layer 220 a 2 of the via hole 230 a may be disposed to partially fill a through hole penetrating the insulating layer 210 of the bridge substrate 200 .

[0279] Meanwhile, the circuit board of the embodiment includes an adhesive layer 500 disposed on a lower surface of the second protective layer 240b of the bridge substrate 200. The adhesive layer 500 may be disposed on the pad portion 131a exposed through the first cavity C1.

[0280] The adhesive layer 500 may provide a bonding force so that the bridge substrate 200 is stably fixed or mounted in the first cavity C1 .

[0281] Meanwhile, the circuit board of the embodiment may further include devices 300 and 400 disposed in the second cavity C2 and the third cavity C3 of the second insulating layer 120. The devices 300 and 400 may be passive devices, but are not limited thereto. For example, the circuit board of the embodiment may also have active devices embedded therein.

[0282] For example, the circuit board may include a first device 300 disposed in the second cavity C2. The first device 300 may be an integrated passive device (IPD). The first device 300 includes a terminal 310. The terminal 310 of the first device 300 may be electrically connected to the second sub-via 141b of the 1-1th via 141 penetrating the first layer 111 of the first insulating layer 110.

[0283] For example, the circuit board may include a second device 400 disposed in the third cavity C3. The second device 400 may be a multilayer ceramic capacitor (MLCC), but is not limited thereto. The second device 400 includes a terminal 410. For example, when the second device 400 is a multilayer ceramic capacitor, the terminal of the second device 400 may include a plurality of terminals 411, 412, and 413. For example, the second device 400 may be a 3-terminal MLCC.

[0284] Fig. 9 is a cross-sectional view explaining a step between a 1-2 circuit layer and a pad layer of a bridge substrate according to the first embodiment, Fig.10 1 is a view explaining a step between a 1-2 circuit layer and a pad layer of a bridge substrate according to the second embodiment.

[0285] refer to Fig. 9 , the bridge substrate 200 a in the first embodiment is disposed in the first cavity C1 of the second layer 112 of the first insulating layer 110 .

[0286] At this time, the thickness of the second layer 112 of the first insulating layer 110 corresponding to the depth of the first cavity C1 and the thickness of the bridge substrate 200 a may be difficult to accurately match.

[0287] Therefore, in the embodiment, the insulating layer 210 constituting the bridge substrate 200 a is formed of polyimide (PI), so that the thickness of the bridge substrate 200 a can be easily controlled.

[0288] Therefore, in an embodiment, the height difference H1 between the upper surface of the pad layer of the bridge substrate 200 a and the 1 - 2 nd circuit layer 132 may be minimized.

[0289] The pad layer of the bridge substrate 200a may represent the first circuit layer 220a of the bridge substrate 200a in the first embodiment. In addition, the pad layer of the bridge substrate 200 may represent the first pad layer 250a and the second pad layer 250b protruding on the first circuit layer 220a in the second embodiment.

[0290] For example, the upper surface of the pad layer of the bridge substrate 200a may be positioned lower than the upper surface of the 1-2 circuit layer 132. For example, the upper surface of the pad layer of the bridge substrate 200a may be positioned lower than the upper surface of the 1-2 circuit layer 132 by a first height H1.

[0291] At this time, in the embodiment, the first height H1 can be easily controlled compared to a conventional bridge substrate including silicon, so the first height H1 can be set to 25 μm or less. For example, in the embodiment, the first height H1 is set to 20 μm or less. For example, in the embodiment, the first height H1 is set to 15 μm or less.

[0292] Preferably, in the embodiment, the first height H1 is set to be smaller than the thickness difference between each layer of the first insulating layer 110 and the second insulating layer 120 .

[0293] At this time, due to the difference in the first height H1, a thickness difference or height difference occurs between the first sub-via 143a and the second sub-via 143b of the 1-3 via 143 penetrating the third layer 113 of the first insulating layer 110. At this time, the first sub-via 143a and the second sub-via 143b of the 1-3 via 143 are formed by filling the inside of the through hole with a metal material. At this time, if the first height H1 as described above increases, the size difference between the through hole constituting the first sub-via 143a and the through hole constituting the second sub-via 143b increases, and therefore, the plating properties of the plating layer filling the inside of the through hole may have problems. In addition, as the reliability of the plating properties decreases due to the size difference of the through hole, the position misalignment of the first sub-via 143a and the second sub-via 143b may occur. In addition, the position misalignment may become a factor in the deterioration of the electrical contact reliability between the circuit board of the embodiment and the bridge substrate 200a.

[0294] Therefore, the embodiment can easily control the thickness of the bridge substrate 200a by making the insulating layer 210 of the bridge substrate 200a include polyimide (PI). Therefore, the embodiment can minimize the first height H1, and thus can minimize the height difference or thickness difference between the first sub-via 143a of the 1-3 via 143 and the second bridge substrate 200. Therefore, the embodiment can improve the contact reliability between the circuit board and the bridge substrate 200a, and further improve the product reliability.

[0295] At the same time, reference Fig.10 , the bridge substrate 200 b in the second embodiment is disposed in the first cavity C1 of the second layer 112 of the first insulating layer 110 .

[0296] The upper surface of the pad layer of the bridge substrate 200b in the second embodiment may be positioned higher than the upper surface of the 1-2 circuit layer 132. For example, the upper surface of the pad layer of the bridge substrate 200b may be positioned higher by a second height H2 than the upper surface of the 1-2 circuit layer 132. In addition, the embodiment sets the second height H2 to 25 μm or less, 20 μm or less, or 15 μm or less.

[0297] The embodiment sets the first height H1 and the second height H2 to be smaller than the thickness difference between each layer of the first insulating layer 110 and the second insulating layer 120. Thus, the embodiment can maintain the strength of the circuit board.

[0298] For example, in Fig. 9 In the case of the first embodiment, the thickness of the substrate in the region where the bridge substrate is provided can be ensured, thereby improving the rigidity of the substrate. Fig.10 In the second embodiment, a microcircuit of the pad portion in contact with the chip mounting area can be implemented.

[0299] In addition, the embodiments can improve chip mounting performance.

[0300] For example, when the first height H1 and the second height H2 are greater than the thickness difference between each layer of the first insulating layer 110 and the second insulating layer 120, the height of the upper surface of the third layer 113 of the first insulating layer 110 may have a large difference for each region. Therefore, the height difference of the mounting pad connected to the chip increases, whereby a defect may occur during chip mounting.

[0301] In contrast, embodiments may reduce a height deviation of an upper surface of the third layer 113 of the first insulating layer 110 , thereby minimizing mounting defects during chip mounting.

[0302] The circuit board of the embodiment includes a first insulating layer and a second insulating layer. The second insulating layer may include prepreg. Therefore, the embodiment can maintain the rigidity of the circuit board to improve the bending characteristics, thereby improving product reliability. In addition, the first insulating layer includes ABF. Therefore, the embodiment can reduce the size of the circuit layer and the via disposed on the first insulating layer. Specifically, the embodiment can form a circuit layer and a via of a fine pattern connected to the first processor chip and the second processor chip on the first insulating layer.

[0303] In addition, the first insulating layer includes multiple layers. In addition, the circuit layer and the via are arranged on each of the multiple layers of the first insulating layer. At this time, the embodiment allows the circuit layer and the via formed on the first insulating layer to gradually increase toward the second insulating layer. Therefore, the embodiment can minimize the signal transmission loss between the circuit layer and the via arranged on the first insulating layer and the circuit layer and the via arranged on the second insulating layer. Therefore, the embodiment can improve the communication characteristics of the circuit board.

[0304] In addition, the circuit board of the embodiment includes a bridge substrate embedded in the first insulating layer. The bridge substrate can be arranged in a first cavity formed in the second layer of the first insulating layer and covered by the third layer of the first insulating layer. In addition, the embodiment allows the pad layer included in the bridge substrate to be directly connected to the via hole penetrating the first insulating layer. Therefore, the embodiment can minimize the signal transmission distance and further minimize the signal transmission loss.

[0305] In addition, the insulating layer of the bridge substrate of the embodiment has a CTE similar to the CTE of the first insulating layer. In addition, the insulating layer of the bridge substrate of the embodiment has a flexible property. Specifically, the insulating layer of the bridge substrate may include polyimide (PI) as an organic material. Therefore, compared with a conventional bridge substrate including silicon, the embodiment can reduce the unit cost of the product.

[0306] In addition, the bridging substrate of the embodiment includes a pad layer. The pad layer is directly connected to the first via hole provided in the first insulating layer. At this time, the alignment state between the pad layer of the bridging substrate and the first via hole greatly affects the product reliability of the circuit board and the semiconductor package. At this time, in the embodiment, transparent polyimide is used as the insulating layer of the bridging substrate. Therefore, the embodiment can improve the alignment between the pad layer of the bridging substrate and the first via hole provided on the first insulating layer. Therefore, the embodiment can improve the overall product reliability.

[0307] In addition, the embodiments may stably protect the bridge substrate from stress generated during thermal deformation of the circuit board.

[0308] That is, in the conventional technology, the insulating layer of the bridge substrate contains silicon. Therefore, the conventional bridge substrate has rigid characteristics due to silicon. Therefore, the stress generated when the circuit board is thermally deformed is directly transferred to the bridge substrate. Therefore, the conventional bridge substrate has reliability problems such as cracks.

[0309] In contrast, the insulating layer of the bridge substrate of the embodiment includes polyimide. Therefore, when the circuit board is thermally deformed, the flow of the bridge substrate can be achieved together with the first insulating layer. Therefore, the embodiment can improve the physical reliability and electrical reliability of the bridge substrate.

[0310] In addition, the embodiment can easily control the thickness of the bridge substrate. For example, in the conventional case of silicon, in order to control the thickness of the bridge substrate, a polishing process of the silicon substrate must be performed, and therefore, due to the difficulty of processing characteristics, it is difficult to control the thickness of the bridge substrate to a desired thickness.

[0311] In contrast, the embodiment can easily control the entire thickness of the bridge substrate, and therefore can easily control the thickness of the bridge substrate according to the depth of the cavity formed in the first insulating layer. Therefore, the embodiment can minimize the thickness difference between the first sub-via directly contacting the bridge substrate and the sub-vias other than the first sub-via. Therefore, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board.

[0312] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described.

[0313] Figures 11 to 25 Explained in order of process Figure 2 Diagram of a circuit board.

[0314] refer to Fig.11, the embodiment may perform a process of manufacturing an inner layer of a circuit board. To this end, the embodiment prepares a second insulating layer 120. Then, the embodiment forms a through hole penetrating the prepared second insulating layer 120. Thereafter, the embodiment forms a second via 144 filling the through hole of the second insulating layer 120. In addition, the embodiment may perform a process of forming second circuit layers 134 and 135 on the upper surface and the lower surface of the second insulating layer 120, respectively.

[0315] refer to Fig.12 , the embodiment may perform a process of forming the second cavity C2 and the third cavity C3 in the second insulating layer 120. The second cavity C2 and the third cavity C3 may respectively penetrate the upper surface and the lower surface of the second insulating layer 120. The second cavity C2 and the third cavity C3 may be formed to be spaced apart from each other in the horizontal direction within the second insulating layer 120.

[0316] refer to Fig.13 , embodiments may perform a process of disposing a carrier plate on a lower surface of the second insulating layer 120. The carrier plate may include a carrier insulating layer CB1 and a carrier adhesive layer CB2.

[0317] refer to Fig.14 , embodiments may perform a process of mounting the first device 300 in the second cavity C2 of the second insulating layer 120 using the carrier adhesive layer CB2 of the carrier plate. In addition, embodiments may perform a process of mounting the second device 400 in the third cavity C3 of the second insulating layer 120 using the carrier adhesive layer CB2 of the carrier plate.

[0318] refer to Fig.15 , the embodiment may perform a process of laminating the first layer 111 of the first insulating layer 110 on the second insulating layer 120. At this time, at least a portion of the first layer 111 of the first insulating layer 110 may be located in the second cavity C2 and the third cavity C3 of the second insulating layer 120. For example, the first layer 111 of the first insulating layer 110 may be disposed to cover the first device 300 disposed in the second cavity C2. In addition, the first layer 111 of the first insulating layer 110 may be disposed to cover the second device 400 disposed in the third cavity C3.

[0319] refer to Fig.16 , the embodiment may perform a process of removing the carrier plate disposed on the lower surface of the second insulating layer 120. As a result, the lower surface of the second insulating layer 120, the lower surface of the second circuit layer 135, the lower surface of the first device 300, and the lower surface of the second device 400 may be exposed.

[0320] refer to Fig.17 , embodiments may perform a process of laminating the first layer 122 of the third insulating layer 121 on the lower surface of the second insulating layer 120 .

[0321] refer to Fig.18 , embodiments may perform a process of forming a 1-1th via hole 141 penetrating the first layer 111 of the first insulating layer 110 and a 1-1th circuit layer 131 located on the upper surface of the first layer 111 of the first insulating layer 110 .

[0322] In addition, the embodiment may perform a process of forming the 3-1st via hole 145 penetrating the first layer 122 of the third insulating layer 121 and the 3-1st circuit layer 136 located on the lower surface of the first layer 122 of the third insulating layer 121 .

[0323] refer to Fig.19 , embodiments may perform a process of laminating the second layer 112 of the first insulating layer 110 on the first layer 111 of the first insulating layer 110. In addition, embodiments may perform a process of laminating the second layer 123 of the third insulating layer 121 under the first layer 122 of the third insulating layer 121.

[0324] refer to Fig. 20 , embodiments may perform a process of forming a 1-2 via hole 142 penetrating the second layer 112 of the first insulating layer 110 and a 1-2 circuit layer 132 located on the upper surface of the second layer 112 of the first insulating layer 110 .

[0325] In addition, the embodiment may perform a process of forming the 3-2 th via hole 146 penetrating the second layer 123 of the third insulating layer 121 and the 3-2 th circuit layer 137 located on the lower surface of the second layer 123 of the third insulating layer 121 .

[0326] At this time, when forming a through hole corresponding to the 1-2 th via hole 142 , the embodiment may perform a process of forming the first cavity C1 at a position corresponding to the pad portion 131 a of the 1-1 th circuit layer 131 .

[0327] refer to Fig.21 , embodiments may perform a process of disposing an adhesive layer 500 on the pad portion 131 a exposed through the first cavity C1 .

[0328] refer to Fig. 22 , embodiments may perform a process of attaching the bridge substrate 200 on the adhesive layer 500 .

[0329] refer to Fig.23 , the embodiment may perform a process of forming the third layer 113 of the first insulating layer 110 on the second layer 112 of the first insulating layer 110. The third layer 113 of the first insulating layer 110 may be formed by filling the first cavity C1 formed in the second layer 112 of the first insulating layer 110. Therefore, the bridge substrate 200 disposed in the first cavity C1 may be covered by the third layer 113 of the first insulating layer 110. Therefore, the bridge substrate 200 may be embedded in the first insulating layer 110.

[0330] In addition, embodiments may perform a process of forming the third layer 124 of the third insulating layer 121 under the second layer 123 of the third insulating layer 121 .

[0331] refer to Fig.24 , embodiments may perform a process of forming the 1-3 via holes 143 penetrating the third layer 113 of the first insulating layer 110 and the 1-3 circuit layers 133 located on the upper surface of the third layer 113 of the first insulating layer 110 .

[0332] In addition, embodiments may perform a process of forming a 3-3 via hole 147 penetrating the third layer 124 of the third insulating layer 121 and a 3-3 circuit layer 138 located on a lower surface of the third layer 124 of the third insulating layer 121 .

[0333] refer to Fig.25 , embodiments may perform a process of forming the first protective layer 151 on the third layer 113 of the first insulating layer 110 .

[0334] In addition, embodiments may perform a process of forming the second protective layer 152 under the third layer 124 of the third insulating layer 121 .

[0335] Fig.26 2 is a view showing a semiconductor package according to a first embodiment.

[0336] refer to Fig.26 In an embodiment, a plurality of chips may be provided mounted on Figure 2 structure on the circuit board.

[0337] To this end, the circuit board includes a first pad and a second pad. The first pad may be a portion of the 1-3 circuit layer 133 disposed on the uppermost side of the first circuit layer of the circuit board. For example, the first pad may be a circuit layer in the 1-3 circuit layer 133 that overlaps with the first opening of the first protective layer 151 in the thickness direction. In addition, the second pad may be a circuit layer in the 1-3 circuit layer 133 that overlaps with the second opening of the first protective layer 151 in the thickness direction.

[0338] In addition, the semiconductor package may include a first adhesive portion 610 disposed on the first pad of the circuit board. In addition, the semiconductor package may include a second adhesive portion 640 disposed on the second pad.

[0339] The first adhesive portion 610 and the second adhesive portion 640 may have the same shape, or alternatively, the first adhesive portion 610 and the second adhesive portion 640 may have different shapes.

[0340] For example, the first adhesive part 610 and the second adhesive part 640 may have a hexahedral shape. For example, the cross section of the first adhesive part 610 and the second adhesive part 640 may include a square shape. The cross section of the first adhesive part 610 and the second adhesive part 640 may include a rectangular or square shape. For example, the first adhesive part 610 and the second adhesive part 640 may include a spherical shape. For example, the cross section of the first adhesive part 610 and the second adhesive part 640 may include a circular shape or a semicircular shape. For example, the cross section of the first adhesive part 610 and the second adhesive part 640 may include a partially or completely circular shape. The cross-sectional shape of the first adhesive part 610 and the second adhesive part 640 may be flat on one side and curved on the other side. The first adhesive part 610 and the second adhesive part 640 may be solder balls, but are not limited thereto.

[0341] In an embodiment, the first chip 620 may be disposed on the first adhesive portion 610. The first chip 620 may be a first processor chip. For example, the first chip 620 may be an application processor (AP) chip in a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The terminal 625 of the first chip 620 may be electrically connected to the first pad through the first adhesive portion 610.

[0342] In addition, the embodiment may include a second chip 650 disposed on the second adhesive portion 640. The second chip 650 may be a second processor chip. For example, the second chip 650 may be a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and an application processor (AP) chip in a microcontroller that is different from the first chip 620. The terminal 655 of the second chip 650 may be electrically connected to the second pad through the second adhesive portion 640.

[0343] For example, the first chip 620 may be a central processing unit chip, and the second chip 650 may be a graphics processing unit chip, but is not limited thereto.

[0344] Meanwhile, the first chip 620 and the second chip 650 may be disposed on the circuit board with a first separation width. The first separation width may be 150 μm or less. For example, the first separation width may be 120 μm or less. For example, the first separation width may be 100 μm or less.

[0345] Preferably, the first separation width may have a range between 60 μm and 150 μm. Preferably, the first separation width may have a range between 70 μm and 120 μm. Preferably, the first separation width may have a range between 80 μm and 110 μm. If the first separation width is less than 60 μm, the operational reliability of the first chip 620 or the second chip 650 may have problems due to interference between the first chip 620 and the second chip 650. If the first separation width is less than 60 μm, the bridge substrate 200 may not be disposed in the region corresponding to the first cavity C1 due to the overlap of the first cavity C1 with the space corresponding to the first separation width in the thickness direction. If the first separation width is greater than 150 μm, the signal transmission loss may increase as the distance between the first chip 620 and the second chip 650 increases. If the first separation width is greater than 150 μm, the volume of the bridge substrate 200 may increase, and further, the volume of the semiconductor package may increase.

[0346] The semiconductor package may include a mold layer 630. The mold layer 630 may be provided to cover the first chip 620 and the second chip 650. For example, the mold layer 630 may be an EMC (Epoxy Mold Compound) formed to protect the mounted first chip 620 and the second chip 650, but is not limited thereto.

[0347] At this time, the mold layer 630 may have a low dielectric constant to enhance the heat dissipation characteristics. For example, the dielectric constant (Dk) of the mold layer 630 may be 0.2 to 10. For example, the dielectric constant (Dk) of the mold layer 630 may be 0.5 to 8. For example, the dielectric constant (Dk) of the mold layer 630 may be 0.8 to 5. Therefore, in an embodiment, the mold layer 630 is made to have a low dielectric constant to increase the heat dissipation characteristics of the heat generated from the first chip 620 and / or the second chip 650.

[0348] Meanwhile, the semiconductor package may include a third adhesive portion 660 disposed at the lowermost side of the circuit board The third adhesive portion 660 may be disposed at the lower surface of the 3-3 circuit layer 138 exposed through the opening of the second protective layer 152 .

[0349] Fig. 27 is a view showing a semiconductor package according to a second embodiment.

[0350] refer to Fig. 27 , compared with the semiconductor package according to the first embodiment, the semiconductor package of the second embodiment further includes a memory chip mounting portion.

[0351] Specifically, the semiconductor package includes a memory chip 670 disposed side by side with the first chip 620 or the second chip 650 and spaced apart from the first chip 620 or the second chip 650. At this time, the memory chip 670 may have a multi-layer structure separated by an adhesive layer 672. In addition, the semiconductor package may include a connection member 674 connected to the memory chip 670. The connection member 674 may be a wire, but is not limited thereto.

[0352] Meanwhile, the semiconductor package according to the third embodiment may further include a second package disposed on the semiconductor package of the first embodiment. The second package may be a memory package including a memory chip.

[0353] To this end, a memory package including an interposer may be provided on the semiconductor package of the first embodiment. Alternatively, a memory package may be directly provided on the semiconductor package of the first embodiment.

[0354] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. In addition, a person skilled in the art of the embodiment can combine or modify the features, structures, effects, etc. shown in each embodiment for other embodiments. Therefore, the contents related to such combinations and changes should be interpreted as included in the scope of the embodiments.

[0355] In the above, the embodiments have been mainly described, but this is only an example and does not limit the embodiments. It will be understood by those skilled in the art that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically shown in the embodiments can be implemented by modification. In addition, the differences related to these modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A semiconductor package, comprising: Circuit boards; as well as a connecting member, the connecting member being embedded in the circuit board, wherein the circuit board comprises a first insulating layer without a reinforcing member, Wherein, the connecting member is embedded in the first insulating layer of the circuit board, Wherein, the connecting member includes a second insulating layer containing organic material.

2. The semiconductor package according to claim 1, wherein The first insulating layer includes a first layer, a second layer disposed on the first layer and having a cavity, and a third layer disposed on the second layer and filling the cavity, Wherein, the connecting member is arranged in the cavity.

3. The semiconductor package according to claim 1, wherein: The second insulating layer of the connection member includes polyimide.

4. The semiconductor package according to claim 1, wherein: The circuit board further includes a third insulating layer disposed below the first insulating layer. The third insulating layer includes an insulating material different from that of the first insulating layer.

5. The semiconductor package according to claim 4, wherein: The third insulating layer includes a reinforcement member.

6. The semiconductor package according to claim 4, wherein: The circuit board further includes a fourth insulating layer disposed below the third insulating layer. The fourth insulating layer includes the same insulating material as the first insulating layer.

7. The semiconductor package according to claim 4, wherein: The third insulating layer has a through hole, Wherein, the semiconductor device is arranged in the through hole.

8. The semiconductor package according to claim 7, wherein: The first insulating layer is provided to fill the through hole and cover the semiconductor device.

9. The semiconductor package according to claim 7, wherein: The through holes include a plurality of through holes provided in the third insulating layer and spaced apart from each other in a horizontal direction, Wherein, the semiconductor devices are respectively arranged in the plurality of through holes.

10. The semiconductor package according to claim 9, wherein The plurality of through holes do not overlap with the connection member in a vertical direction.

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