Multi-core heterogeneous configurable redundancy execution control system and method

Abstract

The invention discloses a multi-core heterogeneous configurable redundancy execution control system and method, and relates to the field of nuclear industrial control system function safety. The system configuration interface unit carries out analysis processing according to the strategy configuration parameters to obtain the analyzed strategy configuration parameters and carries out decoding processing on the analyzed strategy configuration parameters, and the multi-core heterogeneous execution control unit determines heterogeneous execution cores for executing configuration according to the processed strategy configuration parameters and sends the heterogeneous execution cores to the system configuration interface unit. Performing logic processing to obtain a logic processing result; the redundancy voting unit performs redundancy configuration according to the processed strategy configuration parameters to obtain execution configuration redundancy; determining the type of an execution configuration voter according to the processed strategy configuration parameters, and carrying out periodic self-testing by adopting a predefined test sequence to ensure the safety; and based on the execution configuration redundancy and the execution configuration voter type, performing voting according to the logic processing result to obtain a voting strategy. According to the invention, flexible redundancy configuration can be realized, and the deployment applicability is improved.

Description

Technical Field

[0001] The present application relates to the field of functional safety of nuclear industry control systems, and in particular to a multi-core heterogeneous configurable redundant execution control system and method. Background Art

[0002] At present, the independently developed safety-level digital control systems, such as distributed control systems (DCS), mostly use CPU or field-programmable gate array (FPGA) technology. The internal actuator of CPU technology is a completely solidified processing unit, which is difficult to meet the diverse needs of the nuclear industry due to the lack of heterogeneity restrictions on its processing units.

[0003] Functional safety integrity often uses different hardware redundancy configurations in system architecture to meet different levels of functional safety integrity requirements. Once the hardware configuration is determined, the equipment cannot be changed, the flexibility is poor, and the cost of using hardware redundancy configuration is relatively high.

[0004] In recent years, some manufacturers have started to design functional safety ASICs, but they focus on redundant processing units and voting mechanisms. There are no heterogeneous processing units, and they cannot be flexibly configured according to different levels of functional safety integrity requirements. Summary of the invention

[0005] The purpose of this application is to provide a multi-core heterogeneous configurable redundant execution control system and method, which can achieve flexible redundant configuration and improve deployment applicability.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides a multi-core heterogeneous configurable redundant execution control system, the multi-core heterogeneous configurable redundant execution control system comprising: a host computer and a multi-core heterogeneous execution controller;

[0008] The multi-core heterogeneous execution controller includes: a system configuration interface unit, a multi-core heterogeneous execution control unit and a redundant voting unit;

[0009] The host computer is connected to the system configuration interface unit; the multi-core heterogeneous execution control unit is connected to the system configuration interface unit; the redundant voting unit is connected to the system configuration interface unit and the multi-core heterogeneous execution control unit respectively;

[0010] The host computer is used to obtain policy configuration parameters; the policy configuration parameters include: heterogeneous execution core type, redundancy structure and voter type;

[0011] The system configuration interface unit is used to perform parsing processing according to the policy configuration parameters to obtain parsed policy configuration parameters, and perform decoding processing on the parsed policy configuration parameters to obtain processed policy configuration parameters;

[0012] The multi-core heterogeneous execution control unit is used for:

[0013] According to the processed policy configuration parameters, a heterogeneous execution core for executing the configuration is determined based on a set execution mode;

[0014] Perform logic processing based on the heterogeneous execution cores configured for execution to obtain logic processing results;

[0015] The redundant voting unit is used for:

[0016] Based on the set redundancy structure table, redundancy configuration is performed according to the processed policy configuration parameters to obtain execution configuration redundancy;

[0017] Determine the execution configuration voter type based on the processed policy configuration parameters, and use predefined test sequences to perform periodic self-tests to ensure safety;

[0018] Based on the execution configuration redundancy and the execution configuration voter type, voting is performed according to the logic processing result to obtain a voting strategy; the voting strategy is used to control multi-core heterogeneity to perform operation and execution processing under different execution configuration redundancies.

[0019] Optionally, the system configuration interface unit includes: a communication port module, a decoder module and an output selection signal module;

[0020] The communication port module is connected to the host computer; the decoder module is connected to the communication port module; the output selection signal module is respectively connected to the decoder module, the multi-core heterogeneous execution control unit and the redundant voting unit;

[0021] The communication port module is used to receive the policy configuration parameters and parse the policy configuration parameters to obtain the parsed policy configuration parameters;

[0022] The decoder module is used to decode the parsed policy configuration parameters to obtain processed policy configuration parameters;

[0023] The output selection signal module is used to output the processed strategy configuration parameters.

[0024] Optionally, the decoder module uses 6-bit encoded data SWITCH_DATA to decode the parsed policy configuration parameters.

[0025] Optionally, the heterogeneous execution core types include: type I, type II, type III and type IV;

[0026] The design architecture adopted by the heterogeneous execution core includes:

[0027] Type I heterogeneous execution core adopts modular parallel mode; Type II heterogeneous execution core adopts expanded parallel mode; Type III heterogeneous execution core adopts modular serial mode, adopts a single computing core, and executes data serially; Type IV heterogeneous execution core adopts expanded serial mode, adopts a single computing core, and executes data serially;

[0028] The coding languages ​​used by the heterogeneous execution core include:

[0029] Type I heterogeneous execution cores are coded using Verilog HDL language; Type II heterogeneous execution cores are coded using VHDL language; Type III heterogeneous execution cores are coded using a mixture of Verilog HDL language and VHDL language; Type IV heterogeneous execution cores use a graphical approach to logic construction;

[0030] The encoding method used by the heterogeneous execution core includes:

[0031] Type I heterogeneous execution cores use sequential codes to encode state machines, Type II heterogeneous execution cores use one-hot codes to encode state machines, Type III heterogeneous execution cores use Gray codes to encode state machines, and Type IV heterogeneous execution cores use reverse codes to encode state machines.

[0032] The state machine types used by the heterogeneous execution core include:

[0033] Type I heterogeneous execution cores use a one-stage state machine; Type II heterogeneous execution cores use a two-stage state machine; Type III heterogeneous execution cores use a three-stage state machine; Type IV heterogeneous execution cores use a mixed one-stage, two-stage, and three-stage state machine;

[0034] The data verification methods used by the heterogeneous execution core include:

[0035] Type I heterogeneous execution core uses odd check to verify data; Type II heterogeneous execution core uses even check to verify data; Type III heterogeneous execution core uses sum check to verify data; Type IV heterogeneous execution core uses cyclic redundancy check CRC to verify data;

[0036] The data operation methods used by the heterogeneous execution core include:

[0037] Type I heterogeneous execution cores use forward processing to perform data operations; Type II heterogeneous execution cores use reverse processing to perform data operations; Type III heterogeneous execution cores use orthogonal coding calculations to perform data operations; Type IV heterogeneous execution cores use binary coding calculations to perform data operations.

[0038] Optionally, the type I heterogeneous execution core uses a dual-port random access memory DPRAM for data exchange; the type II heterogeneous execution core uses a first-in-first-out memory FIFO for data exchange; the type III heterogeneous execution core uses a Valid-Ready method for data exchange; and the type IV heterogeneous execution core uses a request-response method for data exchange.

[0039] Optionally, types of the redundancy structure include 1oo1 structure, 1oo1D structure, 2oo2 structure, 1oo2 structure, 1oo2D structure, 2oo3 structure, 2oo3D structure and 2oo4 structure; wherein the 1oo1D structure, 1oo2D structure and 2oo3D structure all include a self-diagnosis function module.

[0040] Optionally, based on the different types of the redundancy structure, the 1oo1 structure and the 1oo1D structure use one heterogeneous execution core; the 2oo2 structure, the 1oo2 structure and the 1oo2D structure use two heterogeneous execution cores; the 2oo3 structure and the 2oo3D structure use three heterogeneous execution cores; and the 2oo4 structure uses four heterogeneous execution cores.

[0041] Optionally, the voting machine types include a 2-out-of-4 voting machine V1 type, a 2-out-of-3 voting machine V2 type, a 2-out-of-1 voting machine V3 type, a 1-out-of-1 voting machine V4 type and a 2-out-of-2 voting machine V5 type.

[0042] In a second aspect, the present application provides a multi-core heterogeneous configurable redundancy execution control method, which is implemented by the multi-core heterogeneous configurable redundancy execution control system described above, and the multi-core heterogeneous configurable redundancy execution control method includes:

[0043] Obtaining policy configuration parameters; the policy configuration parameters include: heterogeneous execution core type, redundancy structure and voter type;

[0044] Performing parsing processing on the policy configuration parameters to obtain parsed policy configuration parameters, and performing decoding processing on the parsed policy configuration parameters to obtain processed policy configuration parameters;

[0045] According to the processed policy configuration parameters, a heterogeneous execution core for executing the configuration is determined based on a set execution mode;

[0046] Perform logic processing based on the heterogeneous execution cores configured for execution to obtain logic processing results;

[0047] Based on the set redundancy structure table, redundancy configuration is performed according to the processed policy configuration parameters to obtain execution configuration redundancy;

[0048] Determine the execution configuration voter type based on the processed policy configuration parameters, and use predefined test sequences to perform periodic self-tests to ensure safety;

[0049] Based on the execution configuration redundancy and the execution configuration voter type, voting is performed according to the logic processing result to obtain a voting strategy; the voting strategy is used to control multi-core heterogeneity to perform operation and execution processing under different execution configuration redundancies.

[0050] Optionally, the multi-core heterogeneous configurable redundancy execution control method further includes:

[0051] The voting strategy is downgraded according to the redundancy structure; the downgrade strategy includes: downgrading the four-out-of-two voter V1 type to the three-out-of-two voter V2 type, downgrading the three-out-of-two voter V2 type to the two-out-of-one voter V3 type, and downgrading the two-out-of-one voter V3 type to the one-out-of-one voter V4 type.

[0052] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0053] This application provides a multi-core heterogeneous configurable redundant execution control system and method. Aiming at the diverse requirements of different levels of execution control technology in the nuclear industry, and combining the characteristics of FPGA technology hardware reconfiguration, a multi-core heterogeneous execution control unit is designed, and multi-core heterogeneous execution control with different redundancy is flexibly configured according to the functional safety level requirements. On the basis of ensuring the diversity, security and flexibility of system execution control, the economy of system application and deployment can also be effectively improved. In this way, flexible redundant configuration can be achieved and deployment applicability can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 It is a schematic diagram of the structure of a multi-core heterogeneous configurable redundant execution control system;

[0056] Figure 2A schematic diagram of a scenario of a multi-core heterogeneous configurable redundant execution control system;

[0057] Figure 3 A schematic diagram of the design concept of FPGA-based multi-core heterogeneous configurable redundant execution control technology;

[0058] Figure 4 A schematic diagram of the structure of a multi-core heterogeneous execution controller;

[0059] Figure 5 A schematic diagram of the structure of the system configuration interface unit;

[0060] Figure 6 A simplified architecture diagram for a 1oo1 redundancy structure is shown;

[0061] Figure 7 A simplified architecture diagram for a 1oo1D redundancy structure is shown;

[0062] Figure 8 A simplified architecture diagram for a 2oo2 redundancy structure is shown;

[0063] Fig. 9 A simplified schematic diagram of a 1oo2 redundant structure is shown;

[0064] Fig.10 A simplified architecture diagram for a 1oo2D redundancy structure is shown;

[0065] Fig.11 A simplified architecture diagram for a 2oo3 redundancy structure is shown;

[0066] Fig.12 A simplified schematic diagram of a 2oo3D redundant structure is shown;

[0067] Fig.13 A simplified architecture diagram for a 2oo4 redundancy configuration;

[0068] Fig.14 A simplified schematic diagram of a redundant structure configured without redundancy;

[0069] Fig.15 This is a schematic diagram of multi-core redundant connection relationship;

[0070] Fig.16 Schematic diagram of the design of the voting machine in the redundant voting unit. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0072] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0073] The purpose of this application is to meet the nuclear industry's requirements for diversity and security of safety-grade DCS system controllers, while taking into account the optimization of cost factors. On a single FPGA chip, through physical area isolation and allocation, execution control units with different architectural characteristics can be implemented in each physical isolation area, and the diverse architecture of the execution unit and the reconfiguration of hardware redundancy can be achieved, thereby constructing an execution control technology with multi-core heterogeneity and configurable redundancy characteristics.

[0074] like Figure 1 and 2 As shown, an embodiment of the present application provides a multi-core heterogeneous configurable redundant execution control system, including: a host computer and a multi-core heterogeneous execution controller with FPGA technology as the core.

[0075] The multi-core heterogeneous execution controller includes: a system configuration interface unit, a multi-core heterogeneous execution control unit and a redundant voting unit.

[0076] The host computer is connected to the system configuration interface unit; the multi-core heterogeneous execution control unit is connected to the system configuration interface unit; and the redundant voting unit is connected to the system configuration interface unit and the multi-core heterogeneous execution control unit respectively.

[0077] The host computer is used to obtain policy configuration parameters; policy configuration parameters include: heterogeneous execution core type, redundancy structure and voter type.

[0078] The system configuration interface unit is used to perform parsing processing according to the policy configuration parameters to obtain the parsed policy configuration parameters, and to perform decoding processing on the parsed policy configuration parameters to obtain the processed policy configuration parameters.

[0079] The multi-core heterogeneous execution control unit is used to determine the heterogeneous execution core of the execution configuration based on the set execution mode according to the processed policy configuration parameters.

[0080] The multi-core heterogeneous execution control unit is further used to perform logic processing based on the heterogeneous execution cores of the execution configuration to obtain logic processing results.

[0081] The redundant voting unit is used to perform redundancy configuration based on the set redundancy structure table and the processed policy configuration parameters to obtain the execution configuration redundancy.

[0082] The redundant voting unit is used to configure the voting machine type according to the processed policy configuration parameters, determine the execution configuration voting machine type, and perform periodic self-tests using predefined test sequences to ensure safety.

[0083] The redundant voting unit is also used to vote according to the logical processing results based on the execution configuration redundancy and the execution configuration voter type to obtain a voting strategy; the voting strategy is used to control the multi-core heterogeneous operation and execution processing under different execution configuration redundancies.

[0084] In one embodiment, the system configuration interface unit includes: a communication port module, a decoder module and an output selection signal module.

[0085] The communication port module is connected to the host computer; the decoder module is connected to the communication port module; and the output selection signal module is respectively connected to the decoder module, the multi-core heterogeneous execution control unit and the redundant voting unit.

[0086] The communication port module is used to receive the policy configuration parameters, and parse the policy configuration parameters to obtain the parsed policy configuration parameters.

[0087] The decoder module is used to decode the parsed policy configuration parameters to obtain processed policy configuration parameters.

[0088] The output selection signal module is used to output the processed strategy configuration parameters.

[0089] In practical applications, the design concept of FPGA-based multi-core heterogeneous configurable redundant execution control technology, such as Figure 3 shown.

[0090] In the first step, after the system is powered on, the user defines the system policy configuration parameters in the software tool of the host computer used for system policy configuration according to the needs, including heterogeneous execution core type, redundancy structure, and voter type.

[0091] In the second step, the policy configuration parameters are transmitted to the multi-core heterogeneous execution controller based on FPGA technology through the communication interface.

[0092] Among them, the multi-core heterogeneous execution controller based on FPGA technology includes three functional units: system configuration interface unit, multi-core heterogeneous execution control unit, and redundant voting unit. Figure 4 shown.

[0093] The third step is to configure the system interface unit, which includes three parts: communication port module, decoder module and output selection signal module. Figure 5 shown.

[0094] In the fourth step, the communication port module is used to communicate with the software tool, that is, the host computer, receive the strategy configuration parameters of the software tool, that is, the host computer, and transmit the parsed data to the decoder module.

[0095] In the fifth step, the decoder module decodes the parsed policy configuration parameters to obtain the heterogeneous core type, redundancy structure and voter type that the multi-core heterogeneous execution controller needs to implement, that is, to obtain the processed policy configuration parameters.

[0096] In the sixth step, the decoder module decodes the heterogeneous core type and quantity, redundancy structure and voter type, and outputs them to the multi-core heterogeneous execution control unit and redundant voting unit through the output selection module.

[0097] In one embodiment, the decoder module uses 6-bit coded data SWITCH_DATA to decode the parsed policy configuration parameters.

[0098] Heterogeneous execution core types include: Type I, Type II, Type III, and Type IV. Voter types include 2-out-of-4 Voter V1, 2-out-of-3 Voter V2, 1-out-of-2 Voter V3, 1-out-of-1 Voter V4, and 2-out-of-2 Voter V5.

[0099] The types of redundancy structures include 1oo1 structure, 1oo1D structure, 2oo2 structure, 1oo2 structure, 1oo2D structure, 2oo3 structure, 2oo3D structure and 2oo4 structure; wherein the 1oo1D structure, 1oo2D structure and 2oo3D structure all include a self-diagnosis function module.

[0100] Based on the different types of redundancy structures, the 1oo1 structure and the 1oo1D structure use one heterogeneous execution core; the 2oo2 structure, the 1oo2 structure, and the 1oo2D structure use two heterogeneous execution cores; the 2oo3 structure and the 2oo3D structure use three heterogeneous execution cores; and the 2oo4 structure uses four heterogeneous execution cores.

[0101] Specifically, the decoder module is designed as 6-bit coded data SWITCH_DATA, which respectively represents the voter type, redundancy structure, and heterogeneous core type, as shown in Table 1.

[0102] (1) When data selection SWITCH_DATA=6'b00_0000, the heterogeneous type I core, i.e., the type I heterogeneous execution core, the heterogeneous type II core, i.e., the type II heterogeneous execution core, the heterogeneous type III core, i.e., the type III heterogeneous execution core, and the heterogeneous type IV core, i.e., the type IV heterogeneous execution core, are selected, and the voter is in pass-through mode.

[0103] (2) When the data selection SWITCH_DATA is not in the valid encoding range, the output is directly equal to the input without any execution control.

[0104] (3) When the data selection SWITCH_DATA=6'b00_0001, the heterogeneous type I core, that is, the type I heterogeneous execution core, is selected, the redundancy structure is a 1oo1 structure, and the voter type is V4, that is, a one-out-of-one voter V4 type.

[0105] (4) When the data selection SWITCH_DATA=6'b00_0010, the heterogeneous type II core, that is, the type II heterogeneous execution core, is selected, the redundancy structure is a 1oo1 structure, and the voter type is V4, that is, a one-out-of-one voter V4 type.

[0106] (5) When the data selection SWITCH_DATA=6'b00_0100, the heterogeneous type III core, that is, the type III heterogeneous execution core, is selected, the redundancy structure is a 1oo1 structure, and the voter type is V4, that is, a one-out-of-one voter V4 type.

[0107] (6) When the data selection SWITCH_DATA=6'b00_1000, a heterogeneous IV type core, namely, a IV type heterogeneous execution core, is selected, the redundancy structure is a 1oo1 structure, and the voter type is V4, namely, a one-out-of-one voter V4 type.

[0108] (7) When the data selection SWITCH_DATA=6'b01_0001, the heterogeneous type I core, that is, the type I heterogeneous execution core, is selected, the redundancy structure is a 1oo1D structure, and the voter type is V4, that is, a one-out-of-one voter V4 type.

[0109] (8) When the data selection SWITCH_DATA=6'b01_0010, a heterogeneous type II core, namely a type II heterogeneous execution core, is selected, the redundancy structure is a 1oo1D structure, and the voter type is V4, namely a one-out-of-one voter V4 type.

[0110] (9) When the data selection SWITCH_DATA=6'b01_0100, a heterogeneous type III core, namely a type III heterogeneous execution core, is selected, the redundancy structure is a 1oo1D structure, and the voter type is V4, namely a one-out-of-one voter V4 type.

[0111] (10) When the data selection SWITCH_DATA=6'b01_1000, a heterogeneous IV type core, namely, a IV type heterogeneous execution core, is selected, the redundancy structure is a 1oo1D structure, and the voter type is V4, namely, a one-out-of-one voter V4 type.

[0112] (11) When data selection SWITCH_DATA=6'b00_0011, the heterogeneous type I core, i.e., the type I heterogeneous execution core, and the heterogeneous type II core, i.e., the type II heterogeneous execution core, are selected, the redundancy structure is a 2oo2 structure, and the voter type is V5, i.e., a two-out-of-two voter V5 type.

[0113] (12) When data selection SWITCH_DATA=6'b00_0101, the heterogeneous type I core, i.e., the type I heterogeneous execution core, and the heterogeneous type III core, i.e., the type III heterogeneous execution core, are selected, the redundancy structure is a 2oo2 structure, and the voter type is V5, i.e., a two-out-of-two voter V5 type.

[0114] (13) When data selection SWITCH_DATA=6'b00_1001, the heterogeneous type I core, i.e., the type I heterogeneous execution core, and the heterogeneous type IV core, i.e., the type IV heterogeneous execution core, are selected, the redundancy structure is a 2oo2 structure, and the voter type is V5, i.e., a two-out-of-two voter V5 type.

[0115] (14) When data selection SWITCH_DATA=6'b00_0110, a heterogeneous type II core, i.e., a type II heterogeneous execution core, and a heterogeneous type III core, i.e., a type III heterogeneous execution core, are selected, a redundancy structure is selected as a 2oo2 structure, and a voter type is selected as a V5, i.e., a two-out-of-two voter V5 type.

[0116] (15) When data selection SWITCH_DATA=6'b00_1010, a heterogeneous type II core, i.e., a type II heterogeneous execution core, and a heterogeneous type IV core, i.e., a type IV heterogeneous execution core, are selected, the redundancy structure is a 2oo2 structure, and the voter type is V5, i.e., a two-out-of-two voter V5 type.

[0117] (16) When data selection SWITCH_DATA=6'b00_1100, a heterogeneous type III core, i.e., a type III heterogeneous execution core, and a heterogeneous type IV core, i.e., a type IV heterogeneous execution core, are selected, the redundancy structure is a 2oo2 structure, and the voter type is V5, i.e., a two-out-of-two voter V5 type.

[0118] (17) When data selection SWITCH_DATA=6'b10_0011, the heterogeneous type I core, i.e., the type I heterogeneous execution core, and the heterogeneous type II core, i.e., the type II heterogeneous execution core, are selected, the redundancy structure is a 1oo2 structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0119] (18) When data selection SWITCH_DATA=6'b10_0101, the heterogeneous type I core, i.e., the type I heterogeneous execution core, and the heterogeneous type III core, i.e., the type III heterogeneous execution core, are selected, the redundancy structure is a 1oo2 structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0120] (19) When data selection SWITCH_DATA=6'b10_1001, the heterogeneous type I core, i.e., the type I heterogeneous execution core, and the heterogeneous type IV core, i.e., the type IV heterogeneous execution core, are selected, the redundancy structure is a 1oo2 structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0121] (20) When data selection SWITCH_DATA=6'b10_0110, a heterogeneous type II core, i.e., a type II heterogeneous execution core, and a heterogeneous type III core, i.e., a type III heterogeneous execution core, are selected, the redundancy structure is a 1oo2 structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0122] (21) When data selection SWITCH_DATA=6'b10_1010, a heterogeneous type II core, i.e., a type II heterogeneous execution core, and a heterogeneous type IV core, i.e., a type IV heterogeneous execution core, are selected, the redundancy structure is a 1oo2 structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0123] (22) When data selection SWITCH_DATA=6'b10_1100, a heterogeneous type III core, i.e., a type III heterogeneous execution core, and a heterogeneous type IV core, i.e., a type IV heterogeneous execution core, are selected, the redundancy structure is a 1oo2 structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0124] (23) When data selection SWITCH_DATA=6'b11_0011, a heterogeneous type I core, i.e., a type I heterogeneous execution core, and a heterogeneous type II core, i.e., a type II heterogeneous execution core, are selected, the redundancy structure is a 1oo2D structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0125] (24) When data selection SWITCH_DATA=6'b11_0101, the heterogeneous type I core, i.e., the type I heterogeneous execution core, and the heterogeneous type III core, i.e., the type III heterogeneous execution core, are selected, the redundancy structure is a 1oo2D structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0126] (25) When data selection SWITCH_DATA=6'b11_1001, the heterogeneous type I core, i.e., the type I heterogeneous execution core, and the heterogeneous type IV core, i.e., the type IV heterogeneous execution core, are selected, the redundancy structure is a 1oo2D structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0127] (26) When data selection SWITCH_DATA=6'b11_0110, a heterogeneous type II core, i.e., a type II heterogeneous execution core, and a heterogeneous type III core, i.e., a type III heterogeneous execution core, are selected, the redundancy structure is a 1oo2D structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0128] (27) When data selection SWITCH_DATA=6'b11_1010, a heterogeneous type II core, i.e., a type II heterogeneous execution core, and a heterogeneous type IV core, i.e., a type IV heterogeneous execution core, are selected, the redundancy structure is a 1oo2D structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0129] (28) When data selection SWITCH_DATA=6'b11_1100, a heterogeneous type III core, i.e., a type III heterogeneous execution core, and a heterogeneous type IV core, i.e., a type IV heterogeneous execution core, are selected, the redundancy structure is a 1oo2D structure, and the voter type is V3, i.e., a two-out-of-one voter V3 type.

[0130] (29) When data selection SWITCH_DATA=6'b00_0111, the heterogeneous type I core, i.e., the type I heterogeneous execution core, the heterogeneous type II core, i.e., the type II heterogeneous execution core, and the heterogeneous type III core, i.e., the type III heterogeneous execution core, are selected, the redundancy structure is a 2oo3 structure, and the voting machine type is V2, i.e., a three-out-of-two voting machine V2 type.

[0131] (30) When data selection SWITCH_DATA=6'b00_1011, the heterogeneous type I core, i.e., the type I heterogeneous execution core, the heterogeneous type II core, i.e., the type II heterogeneous execution core, and the heterogeneous type IV core, i.e., the type IV heterogeneous execution core, are selected, the redundancy structure is a 2oo3 structure, and the voting machine type is V2, i.e., a three-out-of-two voting machine V2 type.

[0132] (31) When data selection SWITCH_DATA=6'b00_1110, a heterogeneous type II core, i.e., a type II heterogeneous execution core, a heterogeneous type III core, i.e., a type III heterogeneous execution core, and a heterogeneous type IV core, i.e., a type IV heterogeneous execution core, are selected, the redundancy structure is a 2oo3 structure, and the voting machine type is V2, i.e., a three-out-of-two voting machine V2 type.

[0133] (32) When data selection SWITCH_DATA=6'b01_0111, the heterogeneous type I core, i.e., the type I heterogeneous execution core, the heterogeneous type II core, i.e., the type II heterogeneous execution core, and the heterogeneous type III core, i.e., the type III heterogeneous execution core, are selected, the redundancy structure is a 2oo3D structure, and the voter type is V2, i.e., a three-out-of-two voter V2 type.

[0134] (33) When data selection SWITCH_DATA=6'b01_1011, the heterogeneous type I core, i.e., the type I heterogeneous execution core, the heterogeneous type II core, i.e., the type II heterogeneous execution core, and the heterogeneous type IV core, i.e., the type IV heterogeneous execution core, are selected, the redundancy structure is a 2oo3D structure, and the voter type is V2, i.e., a three-out-of-two voter V2 type.

[0135] (34) When data selection SWITCH_DATA=6'b01_1110, the heterogeneous type II core, i.e., the type II heterogeneous execution core, the heterogeneous type III core, i.e., the type III heterogeneous execution core, and the heterogeneous type IV core, i.e., the type IV heterogeneous execution core, are selected, the redundancy structure is a 2oo3D structure, and the voter type is V2, i.e., a three-out-of-two voter V2 type.

[0136] (35) When data selection SWITCH_DATA=6'b00_1111, the heterogeneous type I core, i.e., the type I heterogeneous execution core, the heterogeneous type II core, i.e., the type II heterogeneous execution core, the heterogeneous type III core, i.e., the type III heterogeneous execution core, and the heterogeneous type IV core, i.e., the type IV heterogeneous execution core, are selected, the redundancy structure is a 2oo4 structure, and the voting machine type is V1, i.e., a four-out-of-two voting machine V1 type.

[0137] Table 1 Decoder function selection table

[0138]

[0139]

[0140]

[0141] In the seventh step, the multi-core heterogeneous execution control unit obtains the policy configuration information of the output selection module, executes the configured heterogeneous execution control core, performs logic processing functions, and passes the logic processing results to the redundant voting unit.

[0142] The above-mentioned multi-core heterogeneous execution control unit is designed to fully meet the safety requirements of the nuclear industry and minimize the impact of common cause failures. It uses the unique advantages of FPGA technology to design four types of heterogeneous execution control cores (heterogeneous cores for short) in the multi-core heterogeneous execution controller, which are divided into type I, type II, type III and type IV. The four heterogeneous cores are distributed in four independent physical areas of the FPGA chip to achieve physical isolation.

[0143] (1) In terms of architectural diversity design, the heterogeneous type I core adopts a modular parallel approach, that is, all logic functions are modularly packaged, and the advantages of FPGA technology are used to perform parallel pipeline operations; the heterogeneous type II core adopts an expanded parallel approach, that is, all logic functions are flattened, and the advantages of FPGA technology are used to perform parallel pipeline operations; the heterogeneous type III core adopts a modular serial approach, that is, all logic functions are modularly packaged, a single computing core is used, and data is input serially for execution; the heterogeneous type IV core adopts an expanded serial approach, that is, all logic functions are flattened, a single computing core is used, and data is input serially for execution.

[0144] (2) In terms of clock diversity design, the heterogeneous type I core, heterogeneous type II core, heterogeneous type III core, and heterogeneous type IV core each use their own dedicated clock.

[0145] (3) In terms of coding language diversity design, the heterogeneous type I core is coded using the Verilog HDL language, the heterogeneous type II core is coded using the VHDL language, the heterogeneous type III core is coded using a mixture of the Verilog HDL language and the VHDL language, and the heterogeneous type IV core uses a graphical approach for logic construction.

[0146] (4) In terms of the design of state machine type diversity, the heterogeneous type I core adopts a one-stage state machine, the heterogeneous type II core adopts a two-stage state machine, the heterogeneous type III core adopts a three-stage state machine, and the heterogeneous type IV core adopts a state machine form that is a mixture of one-stage, two-stage, and three-stage states.

[0147] (5) In terms of the diversity of handshake mechanism design, the heterogeneous type I core uses a dual-port random access memory (DPRAM) to exchange data between functional modules, the heterogeneous type II core uses a first-in-first-out memory (FIFO) to exchange data between functional modules, the heterogeneous type III core uses a data valid signal (Valid-Ready) to exchange data between functional modules, and the heterogeneous type IV core uses a request-acknowledge method to exchange data between functional modules.

[0148] (6) In terms of data verification diversity design, the heterogeneous type I core uses odd parity to verify the integrity of data transmission, the heterogeneous type II core uses even parity to verify the integrity of data transmission, the heterogeneous type III core uses sum parity to verify the integrity of data transmission, and the heterogeneous type IV core uses cyclic redundancy check (CRC) to verify the integrity of data transmission.

[0149] (7) In terms of the design of encoding diversity, the heterogeneous type I core uses sequential code to encode the state machine, the heterogeneous type II core uses one-hot code to encode the state machine, the heterogeneous type III core uses Gray code to encode the state machine, and the heterogeneous type IV core uses reverse code to encode the state machine.

[0150] (8) In terms of data computing diversity design, the heterogeneous type I core uses a forward processing method to perform computing on the data, the heterogeneous type II core uses a reverse processing method to perform computing on the data, the heterogeneous type III core uses an orthogonal encoding method to perform computing on the data, and the heterogeneous type IV core uses a binary encoding method to perform computing on the data.

[0151] Table 2 Diversity technology table of four heterogeneous cores

[0152] Technical items Heterogeneous I-type core Heterogeneous Type II Core Heterogeneous Type III Core Heterogeneous Type IV Core Architecture Modular parallelism Expanded Parallel Modular Serial Expanded Serial clock Type I Type II Special Type III Special Type IV only Coding Language VerilogHDL VHDL mix Graphical State Machine Type One-stage Two-stage Three-stage Hybrid Handshake mechanism DPRAM FIFO Valid-Ready Request-Acknowledge Data Verification Odd Parity Even parity Sum check CRC Encoding Sequence code One-hot encoding Gray code Reverse code Data Budget Forward calculation Reverse calculation Orthogonal calculation Binary Code Computation

[0153] The common cause failure coefficient between heterogeneous cores is calculated by referring to the β coefficient method in IEC 61508 to calculate β and β D , where β is the common cause failure coefficient of undetectable dangerous failures; β D is the common cause failure coefficient of detectable dangerous failures.

[0154] In the eighth step, the redundant voting unit obtains the strategy configuration information of the selected output module, executes the configured redundancy structure and voter, votes on the logical output of the heterogeneous cores in the multi-core heterogeneous control unit, and generates the final output result, which is the voting strategy.

[0155] There are eight types of configurable redundancy structures, including 1oo1, 1oo1D, 2oo2, 1oo2, 1oo2D, 2oo3, 2oo3D, and 2oo4, of which 1oo1D, 1oo2D, and 2oo3D have self-diagnosis function modules. The configurable system redundancy structures are shown in Table 3.

[0156] Table 3 System redundancy structure table

[0157] structure illustrate Redundancy Structure block diagram 1oo1 One for one A core only See Figure 6 1oo1D One-take-one-band diagnosis Only A core and self-diagnosis See Figure 7 2oo2 Two out of two A core, B core See Figure 8 1oo2 Take One Out of Two A core and B core See Fig. 9 1oo2D Two-way diagnosis A core and self-diagnosis, B core and self-diagnosis See Fig.10 2oo3 Three out of two A core, B core, C core See Fig.11 2oo3D Three-out-of-two diagnosis A core and self-diagnosis, B core and self-diagnosis, C core and self-diagnosis See Fig.12 2oo4 Two out of four A core, B core, C core, D core See Fig.13 No redundancy No redundancy required A core, B core, C core, D core See Fig.14

[0158] (1) Different redundancy structures use different numbers of cores: 1oo1 and 1oo1D use one core; 2oo2, 1oo2, and 1oo2D use two cores; 2oo3 and 2oo3D use three cores; and 2oo4 uses four cores.

[0159] (2) When a core is selected, it is denoted as core A, and the core type can be any one of a heterogeneous type I core, a heterogeneous type II core, a heterogeneous type III core, or a heterogeneous type IV core.

[0160] (3) When two cores are selected, denoted as core A and core B, the types can be any two of heterogeneous type I cores, heterogeneous type II cores, heterogeneous type III cores, or heterogeneous type IV cores.

[0161] (4) When three cores are selected, they are denoted as core A, core B, and core C, and the types can be any three of heterogeneous type I core, heterogeneous type II core, heterogeneous type III core, or heterogeneous type IV core.

[0162] (5) When four cores are selected, they are recorded as core A, core B, core C and core D, and the types include heterogeneous type I core, heterogeneous type II core, heterogeneous type III core and heterogeneous type IV core.

[0163] (6) When there is no redundancy requirement, the system provides four independent heterogeneous execution control cores. There is no redundancy between the functions. Different functions can be run independently. They are configured as four cores, denoted as core A, core B, core C and core D. The types include heterogeneous type I core, heterogeneous type II core, heterogeneous type III core and heterogeneous type IV core.

[0164] (7) When configured as a 1oo1 redundancy structure, the redundant architecture only includes the A core, and the input signal is calculated by the A core and then output. Figure 6 shown.

[0165] (8) When configured as a 1oo1D redundancy structure, the redundant architecture includes the A core and its self-diagnosis function module. The input signal is calculated and output by the A core, and the self-diagnosis function is performed at the same time. Figure 7 shown.

[0166] (9) When configured as a 2oo2 redundancy structure, the redundant architecture includes core A, core B and their self-diagnosis function modules. The input signal is calculated by core A and core B respectively, and then voted and processed before output. At the same time, the self-diagnosis function is executed. The self-diagnosis function does not affect the voting strategy. Figure 8 shown.

[0167] (10) When configured as a 1oo2 redundancy structure, the redundant architecture includes core A, core B, and self-diagnosis function modules. The input signal is calculated by core A and core B respectively, and then voted and processed before output. The self-diagnosis function is also executed. The self-diagnosis function does not affect the voting strategy, but when one channel cannot be output normally, it can be downgraded to 1oo1. Fig. 9 shown.

[0168] (11) When configured as a 1oo2D redundancy structure, the redundant architecture includes core A and its self-diagnosis function module, core B and its self-diagnosis function module. The input signal is calculated by core A and core B respectively, and then voted and processed before output. The self-diagnosis function is executed at the same time. After diagnosing that a certain path has a fault, the self-diagnosis function downgrades the voting strategy to 1oo1D. Fig.10 shown.

[0169] (12) When configured as a 2oo3 redundancy structure, the redundant architecture includes core A, core B, core C and self-diagnosis function modules. The input signal is calculated by core A, core B and core C respectively, and then voted and processed before output. At the same time, the self-diagnosis function is executed. The self-diagnosis function does not affect the voting strategy, but when one channel cannot be output normally, it can be downgraded to 2oo2. Fig.11 shown.

[0170] (13) When configured as a 2oo3D redundancy structure, the redundant architecture includes core A and its self-diagnosis function module, core B and its self-diagnosis function module, core C and its self-diagnosis function. The input signal is calculated by core A, core B and core C respectively, and then voted and processed before output. The self-diagnosis function is executed at the same time. After diagnosing that a certain path has a fault, the self-diagnosis function downgrades the voting strategy to 2oo2. Fig.12 shown.

[0171] (14) When configured as a 2oo4 redundancy structure, the redundant architecture includes core A, core B, core C, core D and self-diagnosis function modules. The input signal is calculated by core A, core B, core C and core D respectively, and then voted and processed before output. At the same time, the self-diagnosis function is executed. The self-diagnosis function does not affect the voting strategy, but when one channel cannot be output, it can be downgraded to 2oo3. When two channels cannot be output normally, it can be downgraded to 2oo2. Fig.13 shown.

[0172] (15) When configured as a non-redundant structure, it includes core A, core B, core C, core D and self-diagnosis function module. The input signal is directly output after being calculated by core A, core B, core C and core D respectively, and the self-diagnosis function is executed at the same time. Fig.14 shown.

[0173] To meet the requirements of different levels of functional safety, the four heterogeneous cores are equipped with self-diagnosis functions, with a self-diagnosis coverage of no less than 90%. The redundancy can be flexibly configured through matrix switches and glue logic, and the diagnosis functions of each heterogeneous core can be connected to each other, and the diagnosis of other heterogeneous cores can be realized. Fig.15 When there is no need for diagnosis, the self-diagnosis configuration can be reduced to lower resource usage.

[0174] Combined chip failure rate λ and common cause failure coefficient β and β D , calculate the safe failure fraction SFF under different configurations. According to the comparison relationship between hardware fault margin, safe failure fraction and functional safety level of IEC 61058, different functional safety levels from the lowest SIL0 (safety integrity level 0) to the highest SIL4 (safety integrity level 4) can be achieved under the above flexible configurations. As shown in Table 4.

[0175] Table 4 Redundancy structure and safety integrity level comparison table

[0176] structure Hardware Failure Margin Safety Integrity Level (SIL) 1oo1 0 SIL0 1oo1D 0 SIL1 2oo2 0 SIL2 1oo2 1 SIL2 1oo2D 1 SIL3 2oo3 1 SIL3 2oo3D 1 SIL4 2oo4 2 SIL4 No redundancy 0 SIL0

[0177] The redundant voting unit is equipped with five types of voters, namely, V1 type, V2 type, V3 type, V4 type, and V5 type. The five types of voters are designed with built-in self-test function BIST, which injects corresponding predefined test sequences according to the configured voter type for periodic self-test. Fig.16 This is the design block diagram of the voting machine.

[0178] The type of voter, ie, the voting strategy, is determined by the strategy configuration parameters configured by the software tool, that is, the host computer.

[0179] The voting strategy can also be downgraded according to the redundancy structure, that is, V1 type is downgraded to V2 type, V2 type is downgraded to V3 type, and V3 type is downgraded to V4 type.

[0180] When there is no redundancy requirement, the voter is in pass-through mode, and the execution results of the four heterogeneous cores are output directly, allowing different logical functions to be executed in parallel.

[0181] The relationship between redundancy structure, voter type, voting strategy and degradation strategy is shown in Table 5.

[0182] Table 5 Correspondence table of redundancy structure, voting device type, voting strategy and degradation strategy

[0183]

[0184] The design architecture adopted by the heterogeneous execution core includes:

[0185] Type I heterogeneous execution core adopts a modular parallel approach; Type II heterogeneous execution core adopts an expanded parallel approach; Type III heterogeneous execution core adopts a modular serial approach, adopts a single computing core, and executes data serially; Type IV heterogeneous execution core adopts an expanded serial approach, adopts a single computing core, and executes data serially.

[0186] The coding languages ​​used by the heterogeneous execution core include:

[0187] Type I heterogeneous execution cores are coded using Verilog HDL language; Type II heterogeneous execution cores are coded using VHDL language; Type III heterogeneous execution cores are coded using a mixture of Verilog HDL language and VHDL language; Type IV heterogeneous execution cores use a graphical approach for logic construction.

[0188] The encoding method used by the heterogeneous execution core includes:

[0189] Type I heterogeneous execution core uses sequential code to encode the state machine, Type II heterogeneous execution core uses one-hot code to encode the state machine, Type III heterogeneous execution core uses Gray code to encode the state machine, and Type IV heterogeneous execution core uses reverse code to encode the state machine.

[0190] The state machine types used by the heterogeneous execution core include:

[0191] Type I heterogeneous execution core uses a one-stage state machine; Type II heterogeneous execution core uses a two-stage state machine; Type III heterogeneous execution core uses a three-stage state machine; Type IV heterogeneous execution core uses a mixed one-stage, two-stage, and three-stage state machine.

[0192] The data verification methods used by the heterogeneous execution core include:

[0193] Type I heterogeneous execution core uses odd parity to perform data verification; Type II heterogeneous execution core uses even parity to perform data verification; Type III heterogeneous execution core uses sum parity to perform data verification; Type IV heterogeneous execution core uses cyclic redundancy check CRC to perform data verification.

[0194] The data operation methods used by the heterogeneous execution core include:

[0195] Type I heterogeneous execution cores use forward processing to perform data operations; Type II heterogeneous execution cores use reverse processing to perform data operations; Type III heterogeneous execution cores use orthogonal coding calculations to perform data operations; Type IV heterogeneous execution cores use binary coding calculations to perform data operations.

[0196] Type I heterogeneous execution core uses dual-port random access memory DPRAM for data exchange; Type II heterogeneous execution core uses first-in-first-out memory FIFO for data exchange; Type III heterogeneous execution core uses Valid-Ready method for data exchange; Type IV heterogeneous execution core uses request-response method for data exchange.

[0197] The embodiment of the present application also provides a multi-core heterogeneous configurable redundancy execution control method, which is implemented by a multi-core heterogeneous configurable redundancy execution control system. The multi-core heterogeneous configurable redundancy execution control method includes:

[0198] Get policy configuration parameters; policy configuration parameters include: heterogeneous execution core type, redundancy structure and voter type.

[0199] Parsing is performed on the policy configuration parameters to obtain parsed policy configuration parameters, and decoding is performed on the parsed policy configuration parameters to obtain processed policy configuration parameters.

[0200] According to the processed policy configuration parameters, a heterogeneous execution core for executing the configuration is determined based on a set execution mode.

[0201] The heterogeneous execution cores based on the execution configuration perform logical processing to obtain logical processing results.

[0202] Based on the set redundancy structure table, redundancy configuration is performed according to the processed policy configuration parameters to obtain execution configuration redundancy.

[0203] According to the processed policy configuration parameters, the execution configuration voter type is determined, and a predefined test sequence is used to perform periodic self-tests to ensure safety.

[0204] Based on the execution configuration redundancy and the execution configuration voter type, voting is performed according to the logical processing results to obtain a voting strategy; the voting strategy is used to control multi-core heterogeneous operations and execution processing under different execution configuration redundancies.

[0205] The multi-core heterogeneous configurable redundancy execution control method further includes:

[0206] According to the redundancy structure, the voting strategy is downgraded; the downgraded strategies include: downgrading the four-out-of-two voter V1 type to the three-out-of-two voter V2 type, downgrading the three-out-of-two voter V2 type to the two-out-of-one voter V3 type, and downgrading the two-out-of-one voter V3 type to the one-out-of-one voter V4 type.

[0207] In order to solve the problem that the core execution controllers in the existing nuclear industry safety-level control systems lack heterogeneity, diversity and reconfigurability, this application designs multi-core heterogeneous execution units and flexibly configures safety execution controllers with different redundancy according to the functional safety level requirements. This technology can effectively improve the economy of system application and deployment while ensuring the diversity, safety and flexibility of system execution control.

[0208] Reliability: By building four heterogeneous execution control cores, the reliability is extremely high considering the diagnostic coverage and diversity requirements.

[0209] Availability: The system can be configured with different redundancy structures. The hardware failure margins of the five architectures, 1oo2, 1oo2D, 2oo3, 2oo3D and 2oo4, are all greater than 0, which means that the functional integrity of the system can be maintained when a failure occurs, and the availability is higher.

[0210] Safety: Through a variety of redundant architectures, the system can meet different levels of functional safety requirements and achieve the highest safety integrity level SIL4.

[0211] Flexibility: The system can configure the type, quantity and voter type of heterogeneous cores according to engineering application requirements, providing users with flexible security execution control strategies.

[0212] Economical: A complete multi-core heterogeneous configurable redundant execution controller is implemented on a single chip, replacing functions that originally required multiple hardware to implement, which is more economical.

[0213] Sustainability: The system is implemented through FPGA technology, making system upgrades easier and more sustainable. The original RTL-level design can be easily ported to the new FPGA chip. The new FPGA chip only requires the use of new software tools to re-synthesize and re-layout the existing code and design, providing sustainable support for the long-term operation of the nuclear industry system.

[0214] In summary, after the system is powered on, the user defines the system policy configuration parameters in the upper computer software tool used for system policy configuration according to needs. SWITCH_DATA is 6'b00111, that is, heterogeneous type I, type II, type III and type IV, the redundancy structure is 2oo4, and the voter is type V1.

[0215] The policy configuration parameters are transmitted to the multi-core heterogeneous execution controller based on FPGA technology through the communication interface; the system configuration interface unit of the multi-core heterogeneous execution controller performs reception, parsing, and decoding, and outputs them to the multi-core heterogeneous execution control unit (heterogeneous type I, type II, type III, and type IV) and the redundant voting unit through the output selection module; the multi-core heterogeneous execution control unit obtains the policy configuration information of the output selection module, executes the configured heterogeneous execution control core, realizes 4 heterogeneous cores, and the 4 cores independently perform logic processing functions, and passes the logic processing results to the redundant voting unit.

[0216] The redundant voting unit obtains the policy configuration information of the output selection module, executes the configured redundancy structure 2oo4 and voter V1 type, votes on the logical processing results of the above four heterogeneous core outputs, and generates the final output result for output.

[0217] Through the above implementation methods, this application can greatly reduce the cost of system application and deployment while ensuring the diversity, security and flexibility of system execution control, and provide an efficient and reliable solution for the functional safety of nuclear industrial control systems. Specifically, the safety-related systems and equipment that can be applied in this application include but are not limited to:

[0218] Reactor control system: Precise control of the reactor is achieved through multi-core heterogeneous execution units to ensure that the reactor operates in a safe and stable state.

[0219] Nuclear Fuel Processing System: Utilize configurable redundancy design to ensure data accuracy and reliability during nuclear fuel processing.

[0220] Radiation monitoring system: Real-time monitoring and early warning of radiation levels are achieved through multi-core heterogeneous execution units to ensure the safety of workers.

[0221] Taking the reactor control system as an example, the traditional safety control system usually relies on a fixed 2oo4 hardware architecture, which is difficult to adapt to complex and changing safety requirements. The use of FPGA-based multi-core heterogeneous configurable redundant execution control technology and the implementation of 2oo4 within the FPGA of one module can significantly improve the performance of the nuclear reactor safety control system.

[0222] In this application scenario, four heterogeneous execution control cores are deployed on the FPGA chip, and each control core is optimized for specific safety functions of the reactor. For example, the heterogeneous type I core is responsible for monitoring the reactor cooling system, the heterogeneous type II core is responsible for controlling the diversified drive system, and the heterogeneous type III and heterogeneous type IV cores are responsible for radioactive waste treatment and radiation monitoring, respectively. According to the operating status and safety level requirements of the reactor, the software configuration tool can dynamically adjust the redundancy configuration to achieve 1oo1, 2oo2 or higher level redundancy structure to ensure the safety and reliability of the system.

[0223] When the system detects a potential risk, the voter will vote on the outputs of multiple heterogeneous cores according to the configured voting strategy, and select the most reliable output result as the control instruction, so as to respond to the security incident quickly and accurately. In addition, the self-diagnosis function of each heterogeneous core can monitor its operating status in real time. Once a fault is detected, the system can automatically downgrade or switch to a spare core to ensure the continuous operation of the safety control system.

[0224] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0225] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A multi-core heterogeneous configurable redundant execution control system, characterized in that: The multi-core heterogeneous configurable redundant execution control system comprises: a host computer and a multi-core heterogeneous execution controller; The multi-core heterogeneous execution controller includes: a system configuration interface unit, a multi-core heterogeneous execution control unit and a redundant voting unit; The host computer is connected to the system configuration interface unit; the multi-core heterogeneous execution control unit is connected to the system configuration interface unit; the redundant voting unit is connected to the system configuration interface unit and the multi-core heterogeneous execution control unit respectively; The host computer is used to obtain policy configuration parameters; the policy configuration parameters include: heterogeneous execution core type, redundancy structure and voter type; The system configuration interface unit is used to perform parsing processing according to the policy configuration parameters to obtain parsed policy configuration parameters, and perform decoding processing on the parsed policy configuration parameters to obtain processed policy configuration parameters; The multi-core heterogeneous execution control unit is used for: According to the processed policy configuration parameters, a heterogeneous execution core for executing the configuration is determined based on a set execution mode; Perform logic processing based on the heterogeneous execution cores configured for execution to obtain logic processing results; The redundant voting unit is used for: Based on the set redundancy structure table, redundancy configuration is performed according to the processed policy configuration parameters to obtain execution configuration redundancy; Determine the execution configuration voter type based on the processed policy configuration parameters, and use predefined test sequences to perform periodic self-tests to ensure safety; Based on the execution configuration redundancy and the execution configuration voter type, voting is performed according to the logic processing result to obtain a voting strategy; the voting strategy is used to control multi-core heterogeneity to perform operation and execution processing under different execution configuration redundancies.

2. The multi-core heterogeneous configurable redundant execution control system according to claim 1, characterized in that: The system configuration interface unit includes: a communication port module, a decoder module and an output selection signal module; The communication port module is connected to the host computer; the decoder module is connected to the communication port module; the output selection signal module is respectively connected to the decoder module, the multi-core heterogeneous execution control unit and the redundant voting unit; The communication port module is used to receive the policy configuration parameters and parse the policy configuration parameters to obtain the parsed policy configuration parameters; The decoder module is used to decode the parsed policy configuration parameters to obtain processed policy configuration parameters; The output selection signal module is used to output the processed strategy configuration parameters.

3. The multi-core heterogeneous configurable redundant execution control system according to claim 2, characterized in that: The decoder module uses 6-bit coded data SWITCH_DATA to decode the parsed policy configuration parameters.

4. The multi-core heterogeneous configurable redundant execution control system according to claim 1, characterized in that: The heterogeneous execution core types include: type I, type II, type III and type IV; The design architecture adopted by the heterogeneous execution core includes: Type I heterogeneous execution core adopts modular parallel mode; Type II heterogeneous execution core adopts expanded parallel mode; Type III heterogeneous execution core adopts modular serial mode, adopts a single computing core, and executes data serially; Type IV heterogeneous execution core adopts expanded serial mode, adopts a single computing core, and executes data serially; The coding languages ​​used by the heterogeneous execution core include: Type I heterogeneous execution cores are coded using Verilog HDL language; Type II heterogeneous execution cores are coded using VHDL language; Type III heterogeneous execution cores are coded using a mixture of Verilog HDL language and VHDL language; Type IV heterogeneous execution cores use a graphical approach to logic construction; The encoding method used by the heterogeneous execution core includes: Type I heterogeneous execution cores use sequential codes to encode state machines, Type II heterogeneous execution cores use one-hot codes to encode state machines, Type III heterogeneous execution cores use Gray codes to encode state machines, and Type IV heterogeneous execution cores use reverse codes to encode state machines. The state machine types used by the heterogeneous execution core include: Type I heterogeneous execution cores use a one-stage state machine; Type II heterogeneous execution cores use a two-stage state machine; Type III heterogeneous execution cores use a three-stage state machine; Type IV heterogeneous execution cores use a mixed one-stage, two-stage, and three-stage state machine; The data verification methods used by the heterogeneous execution core include: Type I heterogeneous execution core uses odd check to verify data; Type II heterogeneous execution core uses even check to verify data; Type III heterogeneous execution core uses sum check to verify data; Type IV heterogeneous execution core uses cyclic redundancy check CRC to verify data; The data operation methods used by the heterogeneous execution core include: Type I heterogeneous execution cores use forward processing to perform data operations; Type II heterogeneous execution cores use reverse processing to perform data operations; Type III heterogeneous execution cores use orthogonal coding calculations to perform data operations; Type IV heterogeneous execution cores use binary coding calculations to perform data operations.

5. The multi-core heterogeneous configurable redundant execution control system according to claim 4, characterized in that: Type I heterogeneous execution core uses dual-port random access memory DPRAM for data exchange; Type II heterogeneous execution core uses first-in-first-out memory FIFO for data exchange; Type III heterogeneous execution core uses Valid-Ready method for data exchange; Type IV heterogeneous execution core uses request-response method for data exchange.

6. The multi-core heterogeneous configurable redundant execution control system according to claim 1, characterized in that: The types of the redundancy structure include 1oo1 structure, 1oo1D structure, 2oo2 structure, 1oo2 structure, 1oo2D structure, 2oo3 structure, 2oo3D structure and 2oo4 structure; wherein the 1oo1D structure, 1oo2D structure and 2oo3D structure all include a self-diagnosis function module.

7. The multi-core heterogeneous configurable redundant execution control system according to claim 6, characterized in that: Based on the different types of the redundancy structures, the 1oo1 structure and the 1oo1D structure use one heterogeneous execution core; the 2oo2 structure, the 1oo2 structure and the 1oo2D structure use two heterogeneous execution cores; the 2oo3 structure and the 2oo3D structure use three heterogeneous execution cores; and the 2oo4 structure uses four heterogeneous execution cores.

8. The multi-core heterogeneous configurable redundant execution control system according to claim 1, characterized in that: The voting machine types include a 2-out-of-4 voting machine V1 type, a 2-out-of-3 voting machine V2 type, a 2-out-of-1 voting machine V3 type, a 1-out-of-1 voting machine V4 type and a 2-out-of-2 voting machine V5 type.

9. A multi-core heterogeneous configurable redundancy execution control method, characterized in that: The multi-core heterogeneous configurable redundant execution control method is implemented by using the multi-core heterogeneous configurable redundant execution control system according to any one of claims 1 to 8, and the multi-core heterogeneous configurable redundant execution control method includes: Obtaining policy configuration parameters; the policy configuration parameters include: heterogeneous execution core type, redundancy structure and voter type; Performing parsing processing on the policy configuration parameters to obtain parsed policy configuration parameters, and performing decoding processing on the parsed policy configuration parameters to obtain processed policy configuration parameters; According to the processed policy configuration parameters, a heterogeneous execution core for executing the configuration is determined based on a set execution mode; Perform logic processing based on the heterogeneous execution cores configured for execution to obtain logic processing results; Based on the set redundancy structure table, redundancy configuration is performed according to the processed policy configuration parameters to obtain execution configuration redundancy; Determine the execution configuration voter type based on the processed policy configuration parameters, and use predefined test sequences to perform periodic self-tests to ensure safety; Based on the execution configuration redundancy and the execution configuration voter type, voting is performed according to the logic processing result to obtain a voting strategy; the voting strategy is used to control multi-core heterogeneity to perform operation and execution processing under different execution configuration redundancies.

10. The multi-core heterogeneous configurable redundancy execution control method according to claim 9, characterized in that: The multi-core heterogeneous configurable redundancy execution control method further includes: The voting strategy is downgraded according to the redundancy structure; the downgrade strategy includes: downgrading the four-out-of-two voter V1 type to the three-out-of-two voter V2 type, downgrading the three-out-of-two voter V2 type to the two-out-of-one voter V3 type, and downgrading the two-out-of-one voter V3 type to the one-out-of-one voter V4 type.

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