Data processing device and method

Abstract

The invention provides a data processing device and method which are used for performing multilayer IR decomposition on original application codes, extracting richer calculation and data flow features to obtain an initial calculation graph, performing graph transformation processing on the initial calculation graph to obtain a target calculation graph, and performing data processing on the target calculation graph. Therefore, the applications corresponding to the original application codes are operated on different systems, performance portability is achieved, and compared with a mode that transformation is achieved through manual selection of a user, the optimization effect and efficiency of the application tuning process are improved. In the device, an input module is used for acquiring an original application code; the multi-layer IR decomposition module is used for decomposing the original application code into multi-layer IR and determining an initial calculation graph according to the multi-layer IR; the transformation module is used for performing at least one image transformation processing on the initial calculation image to obtain a target calculation image; the code generation module is used for generating a target application code according to the target calculation graph; and the output module is used for outputting the target application code to the target equipment.

Description

[0001] This application is a divisional application. The application number of the original application is 202110285243.4, and the original application date is March 17, 2021. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of computers, and in particular to a data processing device and method. Background Art

[0003] Data movement is one of the main factors that lead to power consumption and application overhead in current computing systems. How to optimize data movement and maintain performance portability has always been the focus and difficulty of computing system and application design. The data-centric (DC) approach can effectively reduce system power consumption and improve application performance by focusing on data movement and computing to design systems and applications.

[0004] At present, academia and industry have carried out some research work around DC methods, and DC system design has become an important development trend in the future. In a typical DC-based implementation method, the original application code is converted into an intermediate representation (IR), and a computational graph is constructed based on the IR. The computational graph is then transformed by the user's manual selection, and then further transformed to obtain and output the optimized target application code.

[0005] However, in the above implementation, on the one hand, users need to study these graph transformation methods in depth and master their characteristics and usage methods, which will consume a lot of manpower and time; on the other hand, users need to combine application optimization experience and manually select the transformation method of the calculation graph, which results in low optimization efficiency.

[0006] Therefore, how to improve the optimization efficiency of application tuning and maintain performance portability is a technical problem that needs to be solved urgently. Summary of the invention

[0007] The embodiments of the present application provide a data processing device and method for enabling an application corresponding to an original application code to run on different systems and achieve performance portability, thereby improving the optimization effect and efficiency of the application tuning process compared to a method of achieving transformation through manual selection by a user.

[0008] The first aspect of the embodiment of the present application provides a data processing device, which is used in the process of application tuning of the original application code, so that the application corresponding to the original application code can run on different systems and achieve performance portability. Among them, the input module in the device first obtains the original application code, and the original application code is used as the input of the multi-layer IR decomposition module in the device. The original application code is decomposed into multi-layer IR in the multi-layer IR decomposition module and the initial calculation graph is determined according to the multi-layer IR; then, the transformation module in the device performs at least one graph transformation processing on the initial calculation graph, and the obtained target calculation graph is used as the input of the code generation module in the device, and the target application code is generated according to the target calculation graph in the code generation module; finally, the target application code is output to the target device through the output module in the device, so that the application corresponding to the target application code runs on the target device.

[0009] Based on the above technical solution, the original application code is decomposed by multi-layer IR, richer computing and data flow features are extracted to obtain the initial computing graph, and the initial computing graph is transformed at least once to obtain the target computing graph. That is, while the original application code is automatically optimized based on DC, the application corresponding to the original application code can run on different systems and achieve performance portability, which improves the optimization effect and efficiency of the application tuning process compared to the method of manually selecting the transformation by the user.

[0010] In a possible implementation method of the first aspect of the embodiment of the present application, the transformation module is specifically used to: perform at least one graph transformation process on the initial calculation graph to obtain a calculation graph after the graph transformation, and the calculation graph after the graph transformation includes original parameters; then, perform parameter transformation process on the original parameters in the code corresponding to the calculation graph after the graph transformation to obtain the target calculation graph.

[0011] Based on the above technical solution, the transformation module in the data processing device can transform the initial calculation graph at different granularities to obtain the target calculation graph, that is, after optimizing the transformed calculation graph with the calculation graph as the optimization granularity, the parameters contained in the transformed calculation graph are optimized with the optimization granularity to obtain the target calculation graph. Among them, the transformation module completes the automatic optimization of the initial calculation graph from two tuning granularities respectively, which can fully improve the application performance and reduce the system overhead.

[0012] In a possible implementation of the first aspect of the embodiment of the present application, the transformation module in the data processing device is specifically used to: based on the hardware information of the target device, perform parameter transformation processing on the original parameters in the code corresponding to the calculation graph after the transformation of the graph to obtain the target calculation graph.

[0013] Based on the above technical solution, in the process of optimizing the parameters contained in the transformed computational graph as the optimization granularity, the transformation module can specifically perform parameter transformation processing on the original parameters in the code corresponding to the transformed computational graph based on the hardware information of the target device to obtain the target computational graph. Among them, based on the hardware information of the target device, the original parameters are optimized to obtain the target parameters. Since the hardware information of the target device can indicate the hardware operating environment of the target device, the transformed computational graph constructed matches the hardware operating environment of the target device, further improving the optimization effect.

[0014] In a possible implementation of the first aspect of the embodiment of the present application, the multi-layer IR decomposition module in the data processing device includes a first-layer IR decomposition module, a second-layer IR decomposition module and a third-layer IR decomposition module; wherein the first-layer IR decomposition module is used to determine a first IR according to the original application code, and the first IR includes multiple operators; the second-layer IR decomposition module is used to construct a second IR according to the first IR, and the second IR includes a structured pattern corresponding to the multiple operators; the third-layer IR decomposition module is used to determine a DC primitive corresponding to the structured pattern according to the second IR, and the DC primitive is used to construct the initial calculation graph.

[0015] Based on the above technical solution, in the process of the multi-layer IR decomposition module performing IR decomposition on the original application code to obtain the initial calculation graph, the first IR containing multiple operators can be obtained through the first IR decomposition module, and the second IR containing the structured pattern corresponding to the multiple operators can be obtained through the second IR decomposition module, and then the DC primitive corresponding to the structured pattern for constructing the initial calculation graph can be obtained through the third IR decomposition module. Compared with the method of extracting a single level of IR from the original application code, the initial calculation graph obtained by performing multi-layer IR decomposition on the original application code can extract richer calculation and data flow features.

[0016] In a possible implementation of the first aspect of the embodiment of the present application, the second IR decomposition module in the data processing device is specifically used to construct the second IR based on the first IR and the hardware information of the target device.

[0017] Based on the above technical solution, the second IR decomposition module can construct the second IR based on the hardware information of the target device when performing IR decomposition on the first IR to construct a second IR containing a structured pattern corresponding to multiple operators. Among them, since the hardware information of the target device can indicate the hardware operating environment of the target device, the constructed second IR matches the hardware operating environment of the target device, further improving the optimization effect.

[0018] In a possible implementation of the first aspect of the embodiment of the present application, the transformation module in the data processing device is specifically used to: first, decompose the initial calculation graph to obtain multiple sub-graphs; then, perform at least one graph transformation process on the multiple sub-graphs according to a preset sub-graph transformation library to obtain the target calculation graph.

[0019] Based on the above technical solution, when the transformation module performs at least one graph transformation process on the initial calculation graph to obtain the target calculation graph, the initial calculation graph can be decomposed into multiple subgraphs, and the initial calculation graph can be iteratively optimized multiple times based on the fine-grained optimization granularity of the subgraph to obtain the target calculation graph. Compared with the optimization method based on the calculation graph as the optimization granularity, the optimization effect can be further improved.

[0020] In a possible implementation method of the first aspect of the embodiment of the present application, the transformation module in the data processing device is specifically used to: perform at least one graph transformation process on the multiple subgraphs according to a preset subgraph transformation library and a first parameter to obtain the target computational graph, and the first parameter includes at least one of the number of transformations, transformation duration, data movement overhead, and cache miss rate.

[0021] Based on the above technical solution, the transformation module can perform multiple iterative optimizations as indicated by the first parameter during the process of graph transformation of the subgraph, and different optimization requirements can be determined by the first parameter, that is, on-demand optimization is achieved during the process of graph transformation of the subgraph by the transformation module, thereby further improving the degree of automation of the optimization process.

[0022] In a possible implementation of the first aspect of the embodiment of the present application, the input module in the data processing device is also used to obtain sub-graph transformation update information; the device also includes: an update module, used to update the preset sub-graph transformation library according to the sub-graph transformation update information.

[0023] Based on the above technical solution, the preset sub-image transformation library used by the transformation module can be updated based on the sub-image transformation update information, that is, the sub-image transformation library can be updated according to the experience given by experts or the user-defined configuration.

[0024] In a possible implementation manner of the first aspect of the embodiment of the present application, the original application code includes at least one of a mathematical equation operator, a geometric discrete abstraction, a typical data structure, and a DC primitive.

[0025] Based on the above technical solution, the original application code may include the above multiple implementations, wherein, in order to support computing applications in a wide range of fields, facilitate users to write applications, and improve coding efficiency, a DSL interface that is highly abstract and close to mathematical expression is designed and provided by analyzing and summarizing commonly used mathematical operators and data structures in a wide range of computing fields. That is, the original application code includes at least one of: mathematical equation operators (e.g., n-order differential equations, matrix operations, LU decomposition, convolution operations, etc.), geometric discrete abstractions, typical data structures (e.g., vectors, two-dimensional matrices, n-dimensional matrices, trees, linked lists, and other data structures), DC primitives, etc. At the same time, the input module in the data processing device also supports user-defined extended domain-specific language (DSL) interfaces to improve the adaptability of the solution.

[0026] In a possible implementation manner of the first aspect of the embodiment of the present application, the operator includes at least one of operator decomposition based on mathematical equations, geometric discrete abstraction, and basic data types.

[0027] Based on the above technical solution, the operators obtained by the first IR decomposition module when performing IR decomposition on the original application code may include the above-mentioned multiple implementations, that is, the first IR decomposition module obtains relevant mathematical and data information of the application by scanning keywords and key information in the original application code to determine the first IR containing the above-mentioned multiple implementation operators.

[0028] In a possible implementation manner of the first aspect of the embodiment of the present application, the structured mode includes at least one of a Stencil mode, a Reduce mode, and a Package mode.

[0029] Based on the above technical solution, the second IR decomposition module further constructs the first IR to obtain a second IR, and the structured pattern contained in the second IR may include the above-mentioned multiple implementations, that is, the second IR decomposition module can construct a first IR containing multiple operators to obtain multiple different structured patterns.

[0030] In a possible implementation of the first aspect of the embodiment of the present application, the initial calculation graph includes at least one of data, data flow, calculation tasks, and loop mapping.

[0031] Based on the above technical solution, the third IR decomposition module determines the DC primitive corresponding to the structured pattern according to the second IR, wherein the initial computational graph constructed by the DC primitive may include data, data flow, computing tasks, loop mapping and other data-centric primitive representations, so that the initial computational graph is suitable for the DC-based application tuning solution.

[0032] The second aspect of the embodiment of the present application provides a data processing method, which can be applied to the process of application tuning of the original application code, so that the application corresponding to the original application code can run on different systems and achieve performance portability. In this method, the original application code is first obtained; then, the original application code is decomposed into multiple layers of IR, and the initial calculation graph is determined according to the multiple layers of IR; after the initial calculation graph is subjected to at least one graph transformation process to obtain the target calculation graph, the target application code is generated according to the target calculation graph; finally, the target application code is output to the target device.

[0033] Based on the above technical solution, the original application code is decomposed by multi-layer IR, richer computing and data flow features are extracted to obtain the initial computing graph, and the initial computing graph is transformed at least once to obtain the target computing graph. That is, while the original application code is automatically optimized based on DC, the application corresponding to the original application code can run on different systems and achieve performance portability, which improves the optimization effect and efficiency of the application tuning process compared to the method of manually selecting the transformation by the user.

[0034] In a possible implementation manner of the second aspect of the embodiment of the present application, the process of performing at least one graph transformation process on the initial computation graph to obtain the target computation graph may specifically include: performing at least one graph transformation process on the initial computation graph to obtain a transformed computation graph, wherein the transformed computation graph includes original parameters; performing parameter transformation process on the original parameters in the code corresponding to the transformed computation graph to obtain the target computation graph.

[0035] Based on the above technical solution, the target calculation graph is obtained by transforming the initial calculation graph at different granularities, that is, after optimizing the transformed calculation graph with the calculation graph as the optimization granularity, the parameters contained in the transformed calculation graph are optimized with the optimization granularity to obtain the target calculation graph. The automatic optimization of the initial calculation graph from two tuning granularities can fully improve application performance and reduce system overhead.

[0036] In a possible implementation of the second aspect of the embodiment of the present application, the process of performing parameter transformation processing on the original parameters in the code corresponding to the calculation graph after the graph transformation to obtain the target calculation graph may specifically include: based on the hardware information of the target device, performing parameter transformation processing on the original parameters in the code corresponding to the calculation graph after the graph transformation to obtain the target calculation graph.

[0037] Based on the above technical solution, in the process of optimizing the parameters contained in the transformed computation graph as the optimization granularity, the original parameters can be transformed in the code corresponding to the transformed computation graph based on the hardware information of the target device to obtain the target computation graph. Among them, based on the hardware information of the target device, the original parameters are optimized to obtain the target parameters. Since the hardware information of the target device can indicate the hardware operating environment of the target device, the transformed computation graph constructed matches the hardware operating environment of the target device, further improving the optimization effect.

[0038] In a possible implementation of the second aspect of the embodiment of the present application, the original application code is decomposed into multiple layers of IR, including: determining a first IR based on the original application code, the first IR including multiple operators; then, constructing a second IR based on the first IR, the second IR including structured patterns corresponding to the multiple operators; further, determining a DC primitive corresponding to the structured pattern based on the second IR, the DC primitive being used to construct the initial computation graph.

[0039] Based on the above technical solution, in the process of performing multi-layer IR decomposition on the original application code to obtain the initial calculation graph, specifically, a first IR containing multiple operators, a second IR containing structured patterns corresponding to multiple operators, and a DC primitive corresponding to the structured pattern for constructing the initial calculation graph can be obtained. Compared with the method of extracting a single-level IR from the original application code, the initial calculation graph obtained by performing multi-layer IR decomposition on the original application code can extract richer calculation and data flow features.

[0040] In a possible implementation of the second aspect of the embodiment of the present application, constructing the second IR based on the first IR includes: constructing the second IR based on the first IR and hardware information of the target device.

[0041] Based on the above technical solution, in the process of performing IR decomposition on the first IR and constructing a second IR containing a structured pattern corresponding to multiple operators, the second IR can be constructed based on the hardware information of the target device. Among them, since the hardware information of the target device can indicate the hardware operating environment of the target device, the constructed second IR matches the hardware operating environment of the target device, further improving the optimization effect.

[0042] In a possible implementation of the second aspect of the embodiment of the present application, the process of performing at least one graph transformation process on the initial computation graph to obtain a target computation graph may include: decomposing the initial computation graph to obtain multiple subgraphs, and then performing at least one graph transformation process on the multiple subgraphs according to a preset subgraph transformation library to obtain the target computation graph.

[0043] Based on the above technical solution, in the process of performing at least one graph transformation process on the initial computation graph to obtain the target computation graph, the initial computation graph can be specifically decomposed to obtain multiple subgraphs, and the initial computation graph is iteratively optimized multiple times based on the fine-grained optimization granularity of the subgraph to obtain the target computation graph. Compared with the optimization method using the computation graph as the optimization granularity, the optimization effect can be further improved.

[0044] In a possible implementation method of the second aspect of the embodiment of the present application, the multiple subgraphs are subjected to at least one graph transformation processing according to a preset subgraph transformation library to obtain the target computation graph, including: performing at least one graph transformation processing on the multiple subgraphs according to a preset subgraph transformation library and a first parameter to obtain the target computation graph, the first parameter including at least one of the number of transformations, transformation duration, data movement overhead, and cache miss rate.

[0045] Based on the above technical solution, in the process of graph transformation of the subgraph, multiple iterative optimizations can be performed as indicated by the first parameter, and different optimization requirements can be determined by the first parameter, that is, on-demand optimization is achieved in the process of graph transformation of the subgraph by the transformation module, thereby further improving the degree of automation of the optimization process.

[0046] In a possible implementation manner of the second aspect of the embodiment of the present application, the method further includes: acquiring sub-graph transformation update information; and updating the preset sub-graph transformation library according to the sub-graph transformation update information.

[0047] Based on the above technical solution, the preset sub-image transformation library used in the sub-image transformation process can be updated based on the sub-image transformation update information, that is, the sub-image transformation library can be updated based on the experience given by experts or the user-defined configuration.

[0048] In a possible implementation of the second aspect of the embodiment of the present application, the original application code includes at least one of a mathematical equation operator, a geometric discrete abstraction, a typical data structure, and a DC primitive.

[0049] Based on the above technical solution, the original application code may include the above multiple implementations, wherein, in order to support computing applications in a wide range of fields, facilitate users to write applications, and improve coding efficiency, a DSL interface that is highly abstract and close to mathematical expression is designed and provided by analyzing and summarizing commonly used mathematical operators and data structures in a wide range of computing fields. That is, the original application code includes at least one of: mathematical equation operators (e.g., n-order differential equations, matrix operations, LU decomposition, convolution operations, etc.), geometric discrete abstractions, typical data structures (e.g., vectors, two-dimensional matrices, n-dimensional matrices, trees, linked lists, and other data structures), DC primitives, etc. At the same time, the input module in the data processing device also supports user-defined extended domain-specific language (DSL) interfaces to improve the adaptability of the solution.

[0050] In a possible implementation of the second aspect of the embodiment of the present application, the operator includes at least one of operator decomposition based on mathematical equations, geometric discrete abstraction, and basic data types.

[0051] Based on the above technical solution, the operators obtained by IR decomposition of the original application code may include the above-mentioned multiple implementations, that is, by scanning the keywords and key information in the original application code to obtain the relevant mathematical and data information of the application, so as to determine the first IR containing the above-mentioned multiple implementation operators.

[0052] In a possible implementation manner of the second aspect of the embodiment of the present application, the structured mode includes at least one of the Stencil mode, the Reduce mode, and the Package mode.

[0053] Based on the above technical solution, the first IR can be further constructed to obtain a second IR, and the structured pattern contained in the second IR can include the above-mentioned multiple implementations, that is, multiple different structured patterns can be obtained by constructing the first IR containing multiple operators.

[0054] In a possible implementation manner of the second aspect of the embodiment of the present application, the first DC calculation graph includes at least one of data, data flow, calculation task, and loop mapping.

[0055] Based on the above technical solution, the DC primitive corresponding to the structured pattern can be determined according to the second IR, wherein the initial computational graph constructed by the DC primitive can include data, data flow, computing tasks, loop mapping and other data-centric primitive representations, so that the initial computational graph is suitable for the DC-based application tuning solution.

[0056] A third aspect of an embodiment of the present application provides a data processing device, including a processor, the processor is coupled to a memory, the memory is used to store computer programs or instructions, and the processor is used to execute the computer programs or instructions in the memory, so that the data processing device implements the aforementioned second aspect or any possible implementation method of the second aspect.

[0057] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the method as described in the second aspect or any possible implementation of the second aspect.

[0058] A fifth aspect of an embodiment of the present application provides a computer program product storing one or more computers. When the computer program product is executed by the processor, the processor executes the method of the above-mentioned second aspect or any possible implementation of the second aspect.

[0059] A sixth aspect of an embodiment of the present application provides a chip system, which includes at least one processor for supporting a data processing device to implement the functions involved in the above-mentioned second aspect or any possible implementation method of the second aspect.

[0060] In a possible design, the chip system may also include a memory for storing program instructions and data necessary for the data processing device. The chip system may be composed of a chip, or may include a chip and other discrete devices. Optionally, the chip system also includes an interface circuit, which provides program instructions and / or data for the at least one processor.

[0061] Among them, the technical effects brought about by the second to sixth aspects or any possible implementation methods thereof can refer to the technical effects brought about by the first aspect or different possible implementation methods of the first aspect, and will not be repeated here.

[0062] It can be seen from the above technical scheme that the embodiment of the present application has the following advantages: in the data processing device, the input module first obtains the original application code, which is used as the input of the multi-layer IR decomposition module in the device, and the original application code is decomposed into multi-layer IR in the multi-layer IR decomposition module and the initial calculation graph is determined according to the multi-layer IR; then, the transformation module in the device performs at least one graph transformation process on the initial calculation graph, and the obtained target calculation graph is used as the input of the code generation module in the device, and the target application code is generated according to the target calculation graph in the code generation module; finally, the target application code is output to the target device through the output module in the device, so that the application corresponding to the target application code runs on the target device. Among them, by performing multi-layer IR decomposition on the original application code, more abundant calculation and data flow features are extracted to obtain the initial calculation graph, and the initial calculation graph is respectively subjected to at least one graph transformation process to obtain the target calculation graph. That is, while the original application code is automatically optimized based on DC, the application corresponding to the original application code is run on different systems and performance portability is achieved, which improves the optimization effect and efficiency of the application tuning process compared to the method of manually selecting the transformation by the user. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram of a data processing method provided in an embodiment of the present application;

[0064] Figure 2 A schematic diagram of a data processing device provided in an embodiment of the present application;

[0065] Figure 3 Another schematic diagram of a data processing device provided in an embodiment of the present application;

[0066] Figure 4 Another schematic diagram of the data processing method provided in the embodiment of the present application;

[0067] Figure 5 Another schematic diagram of the data processing method provided in the embodiment of the present application;

[0068] Figure 6 Another schematic diagram of the data processing method provided in the embodiment of the present application;

[0069] Figure 7 Another schematic diagram of the data processing method provided in the embodiment of the present application;

[0070] Figure 8 Another schematic diagram of the data processing method provided in the embodiment of the present application;

[0071] Fig. 9 Another schematic diagram of a data processing device provided in an embodiment of the present application;

[0072] Fig.10 Another schematic diagram of a data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0074] First, some terms in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.

[0075] Application: A program or a set of programs developed for users.

[0076] Computation system: A computer system that executes applications.

[0077] Data-Centric (DC): focuses on methods of data transmission and computing.

[0078] Domain specific architecture (DSA): An architecture that focuses on a specific domain.

[0079] Intermediate representation (IR) is a representation between the target program code and the source code, which is independent of the hardware system and can describe the source code information.

[0080] Domain specific language (DSL): a language that abstracts operations and concepts in a specific domain.

[0081] Data Flow: Data transfer between different computing tasks in an application.

[0082] Data-Centric Computation Graph: A multi-graph structure used to represent the computational tasks and data flow processes of an application.

[0083] Graph Transformation: A process that keeps the application output unchanged but changes the application computational graph structure, for example: swapping the nesting order of a double-layer for loop.

[0084] Data movement is one of the main factors that lead to power consumption and application overhead of current computing systems. How to optimize data movement and maintain performance portability has always been the focus and difficulty of computing system and application design. The data-centric (DC) approach can effectively reduce system power consumption and improve application performance by focusing on data movement and computing to design systems and applications. At present, academia and industry have carried out certain research work around DC methods, and DC system design has become an important development trend in the future. At present, in the process of tuning the application, the program corresponding to the source language can be optimized to improve the operating efficiency of the program corresponding to the target language.

[0085] In the implementation of traditional application tuning methods, the input DSL application code is first converted, that is, the DC calculation graph is directly obtained through a single-level IR decomposition, and available sub-graph transformation methods are found. Whether there is an available graph transformation is manually determined:

[0086] If it exists, available graph transformation methods are provided for the user to select, and the computation graph is transformed using the graph transformation method according to the graph transformation method manually selected by the user;

[0087] If it does not exist, convert the current computation graph into target code and output the target code.

[0088] In this implementation method, on the one hand, users need to study these graph transformation methods in depth and master their characteristics and usage methods, which will consume a lot of manpower and time; on the other hand, users need to combine application optimization experience and manually select the transformation method of the calculation graph, which results in low optimization efficiency.

[0089] Therefore, how to achieve the optimization efficiency of the application tuning process and maintain performance portability is a technical problem that needs to be solved urgently. The core problem to be solved by this application is: DC automatic optimization for a wide range of computing fields, how the original application code can run on different systems to achieve performance portability, and how to optimize performance according to different systems to improve application performance.

[0090] To this end, the embodiment of the present application provides a data processing device and method for extracting richer computing and data flow features by performing multi-layer IR decomposition on the original application code to obtain an initial computing graph, and performing graph transformation processing and parameter transformation processing on the initial computing graph to obtain a target computing graph, so that the application corresponding to the original application code can run on different systems and achieve performance portability, which improves the optimization effect and efficiency of the application tuning process compared to the method of manually selecting the transformation by the user. The embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0091] See also Figure 1, is a schematic diagram of a data processing method provided in an embodiment of the present application, the method comprising the following steps.

[0092] S101. Obtain the original application code;

[0093] In this embodiment, when executing a compilation task, the data processing device obtains the original application code of the application to be optimized for compilation in step S101.

[0094] Specifically, the data processing device may be a server, a data center, a mobile or user device, a network component, or a part of an execution module in a server, a data center, a mobile or user device, a network component, or the like.

[0095] In addition, an implementation example of the data processing device can be achieved by Figure 2 Indicates. Figure 2 As shown, the data processing device 200 may at least include an input module 201, a multi-layer IR decomposition module 202, a transformation module 203, a code generation module 204, and an output module 205. In step S101, the original application code may be obtained by the input module 201 in the data processing device 200. Since the input module 201 may obtain the original application code based on DSL, the input module may also be expressed as a DSL interface module.

[0096] In a possible implementation, the applications to be optimized may include: high performance computing (HPC) applications, cloud computing applications, AI applications, and other applications in a wide range of computing fields. In addition, the original application code may also be represented as the DSL code of the original application, and the original application code may include at least one of a mathematical equation operator, a geometric discrete abstraction, a typical data structure, and a DC primitive.

[0097] Specifically, in order to support computing applications in a wide range of fields, facilitate users to write applications, and improve coding efficiency, this embodiment analyzes and summarizes commonly used mathematical operators and data structures in a wide range of computing fields, designs and provides a highly abstract DSL interface that is close to mathematical expression, including: mathematical equation operators (for example: n-order differential equations, matrix operations, LU decomposition, convolution operations, etc.), geometric discrete abstractions, typical data structures (for example: vectors, two-dimensional matrices, n-dimensional matrices, trees, linked lists, and other data structures), and DC primitives. At the same time, this embodiment also supports user-defined extension of the DSL interface.

[0098] Furthermore, during the execution of step S101, in addition to obtaining the original application code, the data processing device may also obtain target hardware information, which is used to indicate the hardware information of the target device on which the target application code compiled using the original application code runs. Thus, in the subsequent optimization process, the target hardware information may be combined to perform targeted optimization to improve the optimization effect.

[0099] Exemplarily, the target hardware information may include at least one of the number of central processing unit (CPU) cores, frequency, cache capacity at each level, vectorization length, memory size, GPU memory capacity, etc. of the target device.

[0100] S102. Decompose the original application code into multiple layers of IR, and determine an initial computation graph according to the multiple layers of IR.

[0101] In this embodiment, the data processing device decomposes the original application code obtained in step S101 to obtain multi-layer IRs, and determines an initial calculation graph according to the multi-layer IRs. The initial calculation graph may be a DC-based calculation graph.

[0102] Among them, step S102 can be Figure 2 The multi-layer IR decomposition module 202 in the data processing device 200 performs multi-layer IP decomposition on the original application code obtained by the input module 201 into multi-layer IR, and determines the initial calculation graph according to the multi-layer IR.

[0103] Specifically, in step S102, the data processing device can first decompose the multi-layer IR to obtain the first layer IR, and then further obtain the next layer IR based on the first layer IR, and so on, to obtain multi-layer IR; and further determine the initial calculation graph based on the multi-layer IR. Compared with the traditional application tuning method that extracts a single layer of IR, in step S102, the original application code is decomposed into multiple layers of IR to extract richer calculation and data flow features to obtain the initial calculation graph.

[0104] For example, the following description is based on the example that the number of layers of the multi-layer IR is 3. Figure 3 , Figure 2The multi-layer IR decomposition module 202 shown includes at least a first-layer IR decomposition module 2021, a second-layer IR decomposition module 2022 and a third-layer IR decomposition module 2023. The first-layer IR decomposition module 2021 is used to determine a first IR according to the original application code, and the first IR includes multiple operators; the second-layer IR decomposition module 2022 is used to construct a second IR according to the first IR, and the second IR includes a structured pattern corresponding to the multiple operators; the third-layer IR decomposition module 2023 is used to determine a DC primitive corresponding to the structured pattern according to the second IR, and the DC primitive is used to construct the initial calculation graph. Compared with the method of extracting a single-level IR in the original application code, the initial calculation graph obtained by performing multi-layer IR decomposition on the original application code can extract richer calculation and data flow features.

[0105] Figure 3 The first-layer IR decomposition module 2021 is used to determine the first IR corresponding to the original application code according to the original application code obtained in step S101, and the first IR includes multiple operators.

[0106] Specifically, the input of the first-layer IR decomposition module 2021 is the original application code (or the DSL code of the original application), and the output is the first IR containing operators such as mathematical equations and data structures. The first IR includes: operator decomposition based on mathematical equations, geometric discrete abstraction (such as the calculation method and classification of grids), basic data types, etc. The first-layer IR decomposition module 2021 can obtain relevant mathematical and data information of the application by scanning the keywords and key information in the original application DSL code to determine the first IR containing the operator. The operator determined by the first-layer IR decomposition module 2021 can come from at least one of the operator decomposition based on mathematical equations, geometric discrete abstraction, and basic data types in the original application code. Since the first IR obtained by the first-layer IR decomposition module 2021 includes operators, the first-layer IR decomposition module 2021 can also be expressed as an operator layer module.

[0107] Figure 3 The second-layer IR decomposition module 2022 shown is used to further construct a second IR based on the first IR determined by the first-layer IR decomposition module 2021, wherein the second IR includes structured patterns corresponding to multiple operators in the first IR.

[0108] Specifically, the input of the second-layer IR decomposition module 2022 is a first IR containing an operator, and the output is a second IR containing the best structured pattern corresponding to the operator in the first IR. Exemplarily, the second IR may include representations of typical structured patterns such as Stencil pattern, Reduce pattern, Package pattern, etc. The second-layer IR decomposition module 2022 can establish a correspondence between operators and structured patterns by combining expert experience, and automatically select the best structured pattern. Among them, since the second IR obtained by the second-layer IR decomposition module 2022 includes a structured pattern, the second-layer IR decomposition module 2022 can also be expressed as a structured pattern layer module.

[0109] In a possible implementation, the basis for constructing the second IR by the second-layer IR decomposition module 2022 may include the hardware information of the target device in addition to the first IR. That is, the second IR is constructed based on the first IR and the hardware information of the target device, wherein, as described in step S101, the target hardware information is used to indicate the hardware information of the target device, so that the second IR constructed by the second-layer IR decomposition module 2022 matches the hardware operating environment of the target device, thereby improving the optimization effect.

[0110] Figure 3 The third-layer IR decomposition module 2023 shown is used to determine the DC primitive corresponding to the structured pattern according to the second IR constructed by the second-layer IR decomposition module 2022, and the DC primitive is used to construct the initial calculation graph.

[0111] Specifically, the input of the third-layer IR decomposition module 2023 is the second IR containing the structured pattern, and the output is the DC primitive corresponding to the structured pattern in the second IR, and the DC primitive is used to construct the initial calculation graph. Exemplarily, the third IR may include data, data flow, calculation tasks, loop mapping and other data-centric primitive representations. The third-layer IR decomposition module 2023 further establishes a conversion library of structured patterns and DC primitives by combining expert experience, directly gives the IR representation and converts it into a DC calculation graph. It should be noted that the third-layer IR decomposition module 2023 can support user customization and supplement the IR representation provided by each level, and, unlike the traditional application tuning method, the expert experience combined with the above content may not be provided by the user. Among them, since the third IR obtained by the third-layer IR decomposition module 2023 includes a DC calculation graph, the third-layer IR decomposition module 2023 can also be represented as a DC primitive layer module.

[0112] For example, Figure 4 A schematic diagram of the hierarchical relationship from computing application to optimization implementation designed for this embodiment.

[0113] exist Figure 4In the example, the original application code input to the first-layer IR decomposition module 2021 includes multiple mathematical equations corresponding to the computing application. For example, when the computing application is computational fluid dynamics (CFD), the corresponding mathematical equations at least include the level set method (Level Set), machine learning (Machine Learning Method), etc. When the computing application is machine learning (Machine Learning), the corresponding mathematical equations at least include support vector machine classification (SVM Classification), K-means clustering algorithm (k-means clustering, or K-Means for short). The corresponding relationship between different applications and multiple mathematical equations is as follows: Figure 4 The arrows shown indicate that, obviously, the original application code can also be implemented through other applications, which is not limited here.

[0114] The operator pattern layer IR (i.e., the first IR) decomposed by the first-layer IR decomposition module 2021 includes: operator decomposition based on mathematical equations, geometric discrete abstraction (such as the calculation method and classification of grids), basic data types, etc.; the structured pattern layer IR (i.e., the second IR) decomposed by the second-layer IR decomposition module 2022 includes Figure 4 One or more of the various structural modes shown; the DC primitive layer IR (i.e., the third IR) used to construct the initial computation graph includes data, data flow (DataMovement), computation task (Computation Task), and other data-centric primitive representations. Furthermore, the hardware information of the aforementioned target device can be obtained through Figure 4 The middle optimization implementation layer indicates that the target hardware information indicates the hardware parameters of the target device, for example, indicating whether the chip used in the target device is Kunpeng, Ascend, or other chips.

[0115] In this embodiment, in step S102, it is proposed to perform multi-layer decomposition through the multi-layer IR decomposition module 202 to obtain a multi-layer computing IR, which has the separation of algorithm and optimization, can abstract richer computing and data flow features, and obtain a regular, concise, and preliminarily optimized IR. In this embodiment, the computing application is parsed into: the first IR corresponding to the operator pattern layer module, the second IR corresponding to the structured pattern layer module, and the third IR corresponding to the DC primitive layer module, and is built into the DSL design, so that by scanning and analyzing the DSL code of the original application, richer computing and data flow features can be captured for automatic optimization in subsequent steps.

[0116] S103. Perform at least one graph transformation process on the initial computation graph to obtain a target computation graph;

[0117] In this embodiment, the data processing device performs at least one graph transformation process on the initial computation graph determined in step S102 in step S103, that is, optimizes the graph transformation of the initial computation graph to obtain a target computation graph.

[0118] Among them, step S103 can be Figure 2 The transformation module 203 in the data processing device 200 performs at least one graph transformation process on the initial calculation graph determined by the multi-layer IR decomposition module 202 to obtain a target calculation graph.

[0119] In a possible implementation, in step S103, the process of performing at least one graph transformation process on the initial computation graph to obtain the target computation graph may include: decomposing the initial computation graph to obtain multiple subgraphs; performing at least one graph transformation process on the multiple subgraphs according to a preset subgraph transformation library to obtain the target computation graph. That is, the initial computation graph is optimized with the computation graph as the optimization granularity.

[0120] Optionally, in step S103, the initial calculation graph may be subjected to multiple iterative graph transformation processing in a preset subgraph transformation library to obtain a final target calculation graph. Wherein, the data processing device may automatically perform graph transformation processing on the multiple subgraphs according to the preset subgraph transformation library in step S103, and the process of obtaining the second DC calculation graph may include: performing graph transformation processing on the multiple subgraphs according to the preset subgraph transformation library and the first parameter to obtain the second DC calculation graph, and the first parameter includes at least one of the number of transformations, the transformation duration, the data movement overhead, and the cache miss rate. Wherein, in the process of graph transformation of the subgraph, multiple iterative optimizations may be performed in the subgraph transformation graph according to different optimization requirements, and the different optimization requirements may be determined by the first parameter. Optionally, the first parameter may be pre-configured in the data processing device, or may be determined by responding to the user's input operation, or may be configured by other means, which is not limited here.

[0121] In a possible implementation, for the sub-image transformation library used in step S103, the method may further include: obtaining sub-image transformation update information; and then updating the preset sub-image transformation library according to the sub-image transformation update information. That is, the sub-image transformation library may be updated based on the experience given by experts or the user-defined configuration.

[0122] In this embodiment, in order to support DC optimization, a subgraph decomposition and change library is designed in step S103, which is used to decompose the DC calculation graph into several subgraphs, provide several DC optimization methods (expressed through subgraph transformation), and support users to customize and supplement the subgraph decomposition method and subgraph transformation library. The purpose of subgraph decomposition is to divide the original calculation graph into several subgraphs, and judge whether the subgraph meets the applicability matching conditions of the subgraph transformation, that is, to find available optimization methods for the calculation graph. The subgraph change library provides several subgraph transformation methods for expressing DC optimization methods, such as: fusion, tile, local-storage, etc. In addition, in order to improve scalability and optimization effects, step S103 supports users to customize and supplement the subgraph decomposition method and subgraph transformation (DC optimization method) library.

[0123] Figure 5 An example of a DC calculation subgraph after vectorization transformation is shown, where: Figure 5 The original DC calculation subgraph shown is an example of a subgraph obtained by subgraph decomposition of the initial calculation graph. After the graph transformation processing of the subgraph transformation library, the transformed DC calculation subgraph (i.e., an example of the target calculation graph) is obtained. Figure 5 In , the DC computation subgraph input is a one-dimensional vector, and the computation operation is bitwise summation, which satisfies Vectorization. Then the transformed computation subgraph omits the cyclic mapping process. Specifically, in Figure 5 The code logic represented by the original DC calculation subgraph in is: input two one-dimensional vectors (arrays) M and N with length n, add the two vectors, and assign them to vector N. Figure 5 It can be seen that the original DC calculation subgraph adds each element of M and N one by one and assigns them to N through a layer of n loops. Since the original calculation subgraph conforms to the vectorized instructions supported by the target architecture, after determining the corresponding transformation method in the subgraph transformation library and performing vectorized transformation on it, it can be seen that the changed calculation graph omits the loop operation, but directly uses the vectorized instructions to add the data of vectors M and N at one time and copy them to N. Furthermore, the transformed calculation graph omits the n-loop process, greatly reducing the related memory access, calculation, judgment and other operations and instruction calls.

[0124] Furthermore, after the above description optimizes the initial computation graph to obtain the target computation graph in step S103 with the computation graph as the optimization granularity, since the target computation graph contains initial parameters, i.e., relevant performance parameters, the processing process can be further optimized in step S103 with the parameters as the optimization granularity. For example, please refer to Figure 3 , Figure 2The transformation module 203 shown may include a graph transformation module 2031 and a parameter transformation module 2032 .

[0125] In a possible implementation, the graph transformation module 2031 is specifically used to: perform at least one graph transformation process on the initial calculation graph to obtain a transformed calculation graph, and the transformed calculation graph includes original parameters; then, the parameter transformation module 2032 performs parameter transformation process on the original parameters in the code corresponding to the transformed calculation graph to obtain the target calculation graph. Among them, the transformation module in the data processing device can transform the initial calculation graph at different granularities to obtain the target calculation graph, that is, after optimizing the transformed calculation graph with the calculation graph as the optimization granularity, the parameters contained in the transformed calculation graph are optimized with the optimization granularity to obtain the target calculation graph. Among them, the transformation module completes the automatic optimization of the initial calculation graph from two tuning granularities respectively, which can fully improve the application performance and reduce the system overhead.

[0126] Furthermore, the process of optimizing the initial parameters in the code corresponding to the transformed computation graph to obtain the target computation graph containing the target parameters may include: optimizing the initial parameters based on the hardware information of the target device to obtain the target parameters. Since the target hardware information is used to indicate the hardware information of the target device, so that the constructed transformed computation graph matches the hardware operating environment of the target device, the optimization effect is further improved.

[0127] For example, Figure 6 The framework and process of the automatic tuning module are demonstrated. The input of the automatic tuning engine (i.e., the transformation module 203) is the DC computational graph (i.e., the initial computational graph) and the hardware information of the target computing system. The subgraph transformation library applicability matching rules can be pre-stored in the data processing device or obtained by input. The output is the target computational graph obtained by the optimized graph transformation and the optimized parameter combination.

[0128] exist Figure 6In the subgraph transformation library, the subgraph transformation applicability matching rules may include subgraph transformation of loop expansion by eliminating redundant variables, subgraph transformation of loop merging by GPU variable binding, subgraph transformation of loop exchange by FPGA loop optimization, and subgraph transformation of a multithreaded parallel programming interface (Open Multi-Processing, OpenMP) parallel processing by MPI parallel processing. The automatic tuning module (i.e., transformation module 203) completes automatic optimization from two tuning granularities respectively, firstly searches for optimized graph transformation combinations with DC calculation graph as granularity, and then fine-grainedly tunes the performance parameters exposed by the graph transformation combinations to fully improve application performance and reduce overhead. The iterative tuning process of the DC calculation graph is as follows: first, subgraph decomposition and matching are performed on the current DC calculation graph; then, a solution space is constructed according to the subgraph decomposition and matching results, and the solution is an available subgraph transformation (DC optimization method); finally, a new DC calculation graph is generated by searching, evaluating, and using the optimized subgraph transformation method, and a performance evaluation is performed based on the aforementioned first parameter for indicating the optimization requirement to complete multiple iterations. In addition, the fine-grained parameter tuning part supports users to use any parameter automatic tuning method and finally outputs the target computation graph, which includes the optimized graph transformation and the optimized parameter value combination.

[0129] S104. Generate target application code according to the target computation graph;

[0130] In this embodiment, the data processing apparatus further generates a target application code according to the target computation graph obtained after the optimization process in step S103, and the target application code is used to run in the target device.

[0131] Among them, step S104 can be Figure 2 The code generation module 204 in the data processing device 200 processes the target computation graph obtained by the transformation module 203 to generate target application code.

[0132] Optionally, in step S104, when the data processing device generates the target application code, it can also process according to the hardware information of the target device and the transformed calculation graph to obtain the target application code. Since the target hardware information is used to indicate the hardware information of the target device, the generated target application code matches the hardware operating environment of the target device, further improving the optimization effect.

[0133] S105. Output the target application code to the target device.

[0134] In this embodiment, in step S105 , the data processing apparatus outputs the target application code generated in step S104 to the target device, so that the target device runs the application corresponding to the target application code.

[0135] Among them, step S105 can be Figure 2 The output module 205 in the data processing device 200 is configured to output the target application code generated by the code generation module 204 .

[0136] Specifically, in the process of tuning the application, the input of the data processing device is: the DSL code of the original application and the target hardware information; the output is: the optimized application binary for the target system structure. The workflow in the compilation process is: first, the original application DSL code input by the user is decomposed into multi-layer calculation IR, and the DC calculation graph is obtained; then, the DC calculation graph is decomposed into several subgraphs; then, the automatic tuning engine automatically tunes the DC calculation graph according to the optimization method in the subgraph transformation library, and then fine-grainedly tunes the relevant parameters exposed by the graph transformation method to obtain the optimal graph transformation and parameter value combination; finally, the target code is generated for the optimized calculation graph, and the application binary is compiled and output.

[0137] See also Figure 7 , is a schematic diagram of a framework used by the data processing method provided in the embodiment of the present application, which is specifically a data-centric "computing-data" automatic optimization framework, which is used to optimize the input information such as business algorithms and hardware configurations to achieve the optimal performance of the computing system. Figure 7 The implementation framework shown includes the following implementation processes:

[0138] An input module (i.e., a DSL interface in the figure) 201, used to obtain original application code and hardware information;

[0139] A multi-layer IR decomposition module 202 is used to perform multi-layer computation IR decomposition on the original application code to obtain an initial computation graph represented by a DSL-Model graph;

[0140] The transformation module 203 is used to perform subgraph decomposition on the initial computation graph to obtain a computation subgraph (SubGraph), and then perform subgraph transformation based on the automatic tuning engine and the subgraph transformation library to obtain a target computation graph;

[0141] A code generation module 204 is used to generate code according to the target computation graph to obtain a target application code, wherein the target application code can obtain different codes based on different hardware, such as a target application code suitable for running on a Kunpeng chip (Code for Kunpeng), a target application code suitable for running on an Ascend chip (Code for Ascend), a target application code suitable for running on a GPU (Code for GPU), etc.;

[0142] The output module 205 is used to output the target application code to the target device, so that the target device can uniformly compile the target application code, obtain and run the optimized application binary code, and realize the original application code to run on different systems and achieve performance portability. Compared with the method of realizing transformation through manual selection by the user, the optimization effect and efficiency of the application tuning process are improved.

[0143] See also Figure 8 , which is based on the embodiments of this application Figures 4 to 7 A specific application example of the implementation process shown. Figure 8 The following workflow is included.

[0144] In the input module 201, the input is the DSL code of the application (i.e., the original application code) and the hardware information of the system. The application can be any HPC application, cloud computing application, or AI application. The hardware information includes: number of CPU cores, frequency, cache capacity at all levels, vectorization length, memory size, GPU memory capacity, etc.

[0145] In the multi-layer IR decomposition module 202, firstly, based on the key information of the DSL interface, the key information in the application DSL code is scanned and analyzed to construct the operator layer IR; then, according to the system hardware information, the correspondence between the operator and the structured pattern is selected to construct the structured pattern layer IR; thereafter, according to the correspondence between the structured pattern and the DC primitive, a DC calculation graph (i.e., the initial calculation graph) is constructed;

[0146] In the transformation module 203, the DC calculation graph and its parameters are automatically tuned, and an optimized graph transformation method and parameter combination are given;

[0147] Specifically, first decompose the current DC calculation graph to generate several calculation subgraphs; then, read the graph transformation method in the subgraph transformation library; then, according to the graph transformation method, perform applicability matching on the DC calculation subgraph, find available graph transformation methods for the DC calculation subgraph, and construct a solution space; thereafter, determine whether the current solution space is empty, that is, determine whether all DC calculation subgraphs have no available graph transformation methods?

[0148] If the current solution space is not empty, the optimal graph transformation method is searched and evaluated in the solution space, and the current DC calculation graph is transformed. When it is judged that the current calculation graph meets the optimization requirements, a fine-grained tuning process is performed. When it is judged that the current calculation graph does not meet the optimization requirements, subgraph decomposition and solution space processing are iteratively performed.

[0149] If the current solution space is empty, fine-grained tuning is performed, that is, the performance parameters exposed by the currently used graph transformation method are automatically tuned based on the target system hardware information to obtain the target computation graph;

[0150] In the code generation module 204, the target code is generated according to the target computation graph obtained by combining the graph transformation mode and parameters optimized in the transformation module 203, and the target code is compiled to generate binary;

[0151] In the output module 205, the optimized application binary is output to the target device.

[0152] It should be noted that:

[0153] (1) Figure 8 The DSL interface used in the multi-layer IR decomposition module 202, the correspondence between operators and structured patterns, the correspondence between structured patterns and DC primitives, and the subgraph transformation library used in the transformation module 203 all support user-defined supplements;

[0154] (2) The judgment condition for determining whether the optimization requirement is met in the transformation module 203 is determined by default to determine whether a specified number of iterations is met (for example, determining whether 30 iterations are met). The judgment condition supports user modification and may include but is not limited to: application execution time, data movement overhead, cache miss rate, etc.;

[0155] (3) Transformation module 203: if the current solution space is not empty, the search and evaluation methods used support user customization and replacement. For example, the solution can be evaluated by full space search and actual measurement (graph transformation method available for subgraphs);

[0156] In addition, the transformation module 203 can use an extensible framework for program autotuning (OpenTuner) to automatically tune the performance parameters, and can support users to use other parameter automatic tuning methods, such as ACCTuner for adjusting vector length and FAST for adjusting Stencil calculation.

[0157] In summary, the data processing device and method provided in the embodiments of the present application support automatic optimization of DC for applications in a wide range of computing fields, achieve application performance portability, improve application performance, reduce power consumption overhead, reduce optimization gate opening, and improve optimization efficiency. In addition, compared with traditional application tuning methods, there is no need for users to accumulate and combine optimization experience to manually complete the DC optimization process, which improves optimization efficiency; and it can realize automatic optimization of DC calculation graphs at different granularities, not just parameter tuning, and does not rely on user experience; further, it also provides a highly abstract DSL interface, which can be used in a wide range of computing fields, perform multi-layer computing IR decomposition on DSL source code, extract richer computing and data flow features, realize automatic optimization of DC, and improve optimization effect and efficiency. Among them, the innovations and benefits of each technical point are as follows:

[0158] (1) Highly abstract DSL interface close to mathematical expression:

[0159] By analyzing and summarizing the commonly used mathematical operators and data structures in a wide range of computing fields, a set of highly abstract and mathematically close DSL interfaces is designed and provided, including: mathematical equation operators (differential equations, LU decomposition, etc.), geometric discrete abstraction, typical data structures (vectors, matrices, etc.), DC primitives, etc. Compared with the prior art, the DSL interface provided by the present invention highly abstracts the calculation and data flow of applications; is close to the mathematical expression of applications, improves user coding efficiency; supports the expression of computing applications in a wide range of fields, and has a wide range of applications.

[0160] (2) Multi-layer IR decomposition:

[0161] The present invention innovatively divides the computing application IR into three levels: operator mode layer, structured mode layer, and DC layer, and is built into the DSL design. Compared with the prior art, the present invention decomposes the application into the above three levels of IR with preliminary optimization layer by layer by scanning the keyword information of the DSL code of the application, combining the conversion relationship between IRs at each level constructed by expert experience and hardware information, realizing the separation of algorithm and optimization, and capturing richer computing and data flow features, such as: computing equation operators, communication modes, computing modes, data flows, etc.

[0162] (3) DC automatic tuning engine:

[0163] The present invention first uses graph transformation as the granularity, constructs a solution space, iteratively searches, evaluates, and applies optimized graph transformation methods, automatically selects optimized subgraph transformation combinations, and then automatically fine-grainedly tunes the performance parameters exposed by graph transformation. Compared with the prior art, the present invention realizes automatic optimization of DC and automatic tuning of related parameters without relying on user experience, eliminating the process of users manually selecting graph transformations, achieving performance portability, and improving optimization efficiency. At the same time, it can be used for computing applications in a wide range of fields and has a wide range of applications.

[0164] The above describes the embodiments of the present application from the perspective of the method, and the following describes the embodiments of the present application from the perspective of the device.

[0165] See also Fig. 9 , is a schematic diagram of the hardware structure of the data processing device provided in an embodiment of the present application. Fig. 9 The data processing device 900 shown (the device 900 may be a computer device) includes a memory 901, a processor 902, a communication interface 903 and a bus 904. The memory 901, the processor 902 and the communication interface 903 are connected to each other through the bus 904.

[0166] The memory 901 may be a read only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 901 may store a program. When the program stored in the memory 901 is executed by the processor 902, the processor 902 and the communication interface 903 are used to execute the various steps of the model processing method of the embodiment of the present application.

[0167] Processor 902 can adopt a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits to execute relevant programs to implement the functions required to be performed by the units in the data processing device of the embodiment of the present application, or to execute the model processing method of the method embodiment of the present application.

[0168] The processor 902 may also be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the model processing method of the present application may be completed by an integrated logic circuit of hardware or software instructions in the processor 902. The above-mentioned processor 902 may also be a general-purpose processor, a digital signal processor (digital signal processing, DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware decoding processor, or may be executed by a combination of hardware and software modules in a decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 901, and the processor 902 reads the information in the memory 901, and combines its hardware to complete the functions required to be performed by the units included in the data processing device of the embodiment of the present application, or executes the model processing method of the method embodiment of the present application.

[0169] The communication interface 903 uses a transceiver such as, but not limited to, a transceiver to implement communication between the device 900 and other devices or a communication network. For example, training data (such as the training image in the embodiment of the present application) can be obtained through the communication interface 903.

[0170] The bus 904 may include a path for transmitting information between various components of the device 900 (eg, the memory 901 , the processor 902 , and the communication interface 903 ).

[0171] It should be noted that although Fig. 9 The device 900 shown only shows a memory, a processor, and a communication interface, but in the specific implementation process, those skilled in the art should understand that the device 900 also includes other devices necessary for normal operation. At the same time, according to specific needs, those skilled in the art should understand that the device 900 may also include hardware devices for implementing other additional functions. In addition, those skilled in the art should understand that the device 900 may also only include the devices necessary to implement the embodiments of the present application, and does not necessarily include Fig. 9 All devices shown in .

[0172] It should be noted that Fig. 9 The data processing device shown can be specifically used to implement the steps implemented by the data processing device in the aforementioned method embodiment, and achieve the corresponding technical effects of the data processing device. Fig. 9 The specific implementation methods of the data processing device shown can refer to the descriptions in the aforementioned method embodiments, which will not be described in detail here.

[0173] See also Fig.10 , is another schematic structural diagram of a data processing device provided in the present application, wherein the data processing device 1000 includes a logic circuit 1001 and an input / output interface 1002. The data processing device 1000 may be a chip or an integrated circuit.

[0174] in, Fig. 9 The communication interface 903 shown can be Fig.10 The input / output interface 1002 in the embodiment may include an input interface and an output interface. Alternatively, the communication interface may also be a transceiver circuit, which may include an input interface circuit and an output interface circuit. In addition, Fig. 9 The processor 902 shown may be Fig.10 The logic circuit 1001 in FIG.

[0175] Specifically, the input / output interface 1002 is used to obtain the original application code, and the logic circuit 1001 is used to process the original application code to obtain the target application code, and output the target application code through the input / output interface 1002 .

[0176] In one possible implementation, the logic circuit 1001 can also execute other steps executed by the aforementioned processor 902 and achieve corresponding beneficial effects, and the input and output interface 1002 can also execute other steps executed by the aforementioned communication interface 903 and achieve corresponding beneficial effects, which will not be repeated here.

[0177] In a possible implementation, the logic circuit 1001 may be a processing device, and the functions of the processing device may be partially or completely implemented by software. The functions of the processing device may be partially or completely implemented by software.

[0178] Optionally, the processing device may include a memory and a processor, wherein the memory is used to store a computer program, and the processor reads and executes the computer program stored in the memory to perform corresponding processing and / or steps in any one of the method embodiments.

[0179] Alternatively, the processing device may include only a processor. A memory for storing a computer program is located outside the processing device, and the processor is connected to the memory via a circuit / wire to read and execute the computer program stored in the memory. The memory and the processor may be integrated together, or may be physically independent of each other.

[0180] Optionally, the processing device may be one or more chips, or one or more integrated circuits. For example, the processing device may be one or more field-programmable gate arrays (FPGA), application specific integrated circuits (ASIC), system on chip (SoC), central processor unit (CPU), network processor (NP), digital signal processor (DSP), microcontroller unit (MCU), programmable logic device (PLD) or other integrated chips, or any combination of the above chips or processors.

[0181] An embodiment of the present application also provides a computer-readable storage medium storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the method as a possible implementation method of the data processing device in the aforementioned embodiment.

[0182] An embodiment of the present application also provides a computer program product (or computer program) storing one or more computers. When the computer program product is executed by the processor, the processor executes the method of the possible implementation mode of the above-mentioned data processing device.

[0183] The embodiment of the present application also provides a chip system, which includes at least one processor for supporting a terminal device to implement the functions involved in the possible implementation of the above-mentioned data processing device. Optionally, the chip system also includes an interface circuit, which provides program instructions and / or data to the at least one processor. In one possible design, the chip system may also include a memory, which is used to store the necessary program instructions and data for the terminal device. The chip system can be composed of chips, or it can include chips and other discrete devices.

[0184] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the unit is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0185] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0186] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program code.

[0187] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing device, characterized in that: include: A multi-layer intermediate representation IR decomposition module, used to decompose the original application code into multi-layer IRs and determine an initial calculation graph according to the multi-layer IRs; A transformation module, used to perform at least one graph transformation process on the initial computation graph to obtain a target computation graph; A code generation module, used to generate target application code according to the target computation graph; The output module is used to output the target application code to the target device.

2. The device according to claim 1, characterized in that The transformation module is specifically used for: Performing at least one graph transformation process on the initial computation graph to obtain a transformed computation graph, wherein the transformed computation graph includes original parameters; The original parameters are subjected to parameter transformation processing in the code corresponding to the computational graph after the graph transformation to obtain the target computational graph.

3. The device according to claim 2, characterized in that The transformation module is specifically used for: Based on the hardware information of the target device, parameter transformation processing is performed on the original parameters in the code corresponding to the calculation graph after the graph transformation to obtain the target calculation graph.

4. The device according to any one of claims 1 to 3, characterized in that The multi-layer IR decomposition module includes a first-layer IR decomposition module, a second-layer IR decomposition module and a third-layer IR decomposition module; The first-layer IR decomposition module is used to determine a first IR according to the original application code, where the first IR includes a plurality of operators; The second-layer IR decomposition module is used to construct a second IR according to the first IR, wherein the second IR includes structured patterns corresponding to the multiple operators; The third-layer IR decomposition module is used to determine the DC primitive corresponding to the structured pattern according to the second IR, and the DC primitive is used to construct the initial calculation graph.

5. The device according to claim 4, characterized in that The second IR decomposition module is specifically used for: The second IR is constructed based on the first IR and the hardware information of the target device.

6. The device according to any one of claims 1 to 5, characterized in that The transformation module is specifically used for: Decomposing the initial computation graph to obtain multiple subgraphs; Perform at least one graph transformation process on the multiple subgraphs according to a preset subgraph transformation library to obtain the target computation graph.

7. The device according to claim 6, characterized in that The transformation module is specifically used for: The target computational graph is obtained by performing graph transformation processing on the multiple subgraphs at least once according to a preset subgraph transformation library and a first parameter, wherein the first parameter includes at least one of the number of transformations, the transformation duration, the data movement overhead, and the cache miss rate.

8. The device according to claim 6 or 7, characterized in that It also includes an input module for obtaining sub-graph transformation update information; The device also includes: An updating module is used to update the preset sub-graph transformation library according to the sub-graph transformation update information.

9. The device according to any one of claims 1 to 8, characterized in that The original application code includes at least one of a mathematical equation operator, a geometric discrete abstraction, a typical data structure, and a DC primitive.

10. The device according to any one of claims 4 to 9, characterized in that The operator includes at least one of operator decomposition based on mathematical equations, geometric discrete abstraction, and basic data types.

11. The device according to any one of claims 4 to 10, characterized in that The structured mode includes at least one of a Stencil mode, a Reduce mode, and a Package mode.

12. The device according to any one of claims 4 to 11, characterized in that The initial computation graph includes at least one of data, data flow, computation tasks, and loop mapping.

13. A data processing method, characterized in that: include: Decomposing the original application code into multiple layers of IR, and determining an initial computation graph according to the multiple layers of IR; Performing at least one graph transformation process on the initial computation graph to obtain a target computation graph; Generate target application code according to the target computation graph; The target application code is output to the target device.

14. The method according to claim 13, characterized in that The performing at least one graph transformation process on the initial computation graph to obtain a target computation graph comprises: Performing at least one graph transformation process on the initial computation graph to obtain a transformed computation graph, wherein the transformed computation graph includes original parameters; The original parameters are subjected to parameter transformation processing in the code corresponding to the computational graph after the graph transformation to obtain the target computational graph.

15. The method according to claim 14, characterized in that The performing parameter transformation processing on the original parameters in the code corresponding to the calculation graph after the graph transformation to obtain the target calculation graph comprises: Based on the hardware information of the target device, parameter transformation processing is performed on the original parameters in the code corresponding to the calculation graph after the graph transformation to obtain the target calculation graph.

16. The method according to any one of claims 13 to 15, characterized in that Decomposing the original application code into multiple layers of IR includes: Determine a first IR according to the original application code, wherein the first IR includes a plurality of operators; constructing a second IR according to the first IR, wherein the second IR includes structured patterns corresponding to the plurality of operators; A DC primitive corresponding to the structured pattern is determined according to the second IR, and the DC primitive is used to construct the initial computation graph.

17. The method according to claim 16, characterized in that The step of constructing the second IR according to the first IR comprises: The second IR is constructed based on the first IR and the hardware information of the target device.

18. The method according to any one of claims 13 to 17, characterized in that The performing at least one graph transformation process on the initial computation graph to obtain a target computation graph includes: Decomposing the initial computation graph to obtain multiple subgraphs; Perform at least one graph transformation process on the multiple subgraphs according to a preset subgraph transformation library to obtain the target computation graph.

19. The method according to claim 18, characterized in that The performing at least one graph transformation process on the plurality of subgraphs according to a preset subgraph transformation library to obtain the target computation graph includes: The target computational graph is obtained by performing graph transformation processing on the multiple subgraphs at least once according to a preset subgraph transformation library and a first parameter, wherein the first parameter includes at least one of the number of transformations, the transformation duration, the data movement overhead, and the cache miss rate.

20. The method according to claim 18 or 19, characterized in that The method further comprises: Get sub-image transformation update information; The preset sub-graph transformation library is updated according to the sub-graph transformation update information.

21. A data processing device, characterized in that: The method comprises a processor, wherein the processor is coupled to a memory, the memory is used to store a computer program or an instruction, and the processor is used to execute the computer program or the instruction in the memory, so that the method according to any one of claims 13 to 20 is executed.

22. A computer storage medium, characterized in that The computer storage medium stores instructions, and when the instructions are executed on a computer, the computer is caused to perform the method according to any one of claims 13 to 20.

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