Data packet size matching method, equipment, device and storage medium

Abstract

The invention discloses a data packet size matching method, equipment and device and a storage medium, and relates to the technical field of computers. If the parameter value is a matched data packet size mark, scanning an initial data packet size corresponding to each port of the corresponding current converter under the target architecture; and performing matching processing according to the initial data packet size corresponding to each port of the current converter to obtain a final data packet size of each port of the current converter. According to the method, the initial data packet size of each port is matched with the data packet size between two ports corresponding to point-to-point communication under the current converter, so that final MPSs between the ports connected through the converter are the same, imbalance between the MPSs is eliminated, and downtime is avoided. Meanwhile, triggering of a data packet matching mechanism is adopted, a self-adaptive MPS adaptation method is achieved, and the experience feeling of customers is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data packet size matching method, equipment, device and storage medium. Background Art

[0002] The Transaction Layer Packet (TLP) of the Peripheral Component Interconnect Express (PCIE) is a data packet used to transmit data and control information between different devices in the PCIE architecture.

[0003] In the PCIE link, the maximum payload size (Max PayloadSize, MPS) of the data packet of each endpoint (port) needs to be negotiated. Its MPS determines the size of the data packet during the TLP transmission process to determine the final MPS corresponding to each endpoint. The data transmission between each endpoint needs to be connected through a converter (Switch) for link extension. At this time, since the final MPS of each port is different, the data transmission between each port will cause MPS mismatch in the converter, which will cause MPS imbalance and cause the restart operation downtime due to data transmission failure.

[0004] Therefore, how to eliminate MPS imbalance to avoid downtime is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a data packet size matching method, device, apparatus and storage medium to solve the problem of MPS mismatch in the converter caused by data transmission between various ports, thereby causing downtime caused by MPS imbalance.

[0006] In order to solve the above technical problems, the present invention provides a method for matching data packet sizes, comprising:

[0007] Obtaining a parameter value corresponding to a data packet matching mechanism; wherein the parameter value of the data packet matching mechanism represents a flag bit of a matching data packet size;

[0008] If the parameter value is a matching data packet size flag, scanning the initial data packet size corresponding to each port of the current converter corresponding to the target architecture;

[0009] Matching is performed according to the initial data packet sizes corresponding to the ports of the current converter to obtain the final data packet sizes of the ports of the current converter; wherein the final data packet sizes are the same at the ports of the current converter.

[0010] On the one hand, the process of determining the parameter value corresponding to the data packet matching mechanism includes:

[0011] Added packet matching option by booting the system's installation path;

[0012] Add the flag parameter value of the data packet size of the port and the flag parameter value of the data packet size of the converter to the data packet matching option to use the flag parameter value as the parameter value; wherein the flag parameter value of the data packet size of the port is different from the flag parameter value of the data packet size of the converter.

[0013] On the other hand, the triggering method of the packet matching mechanism includes one of the following methods:

[0014] receiving a user modification instruction, and triggering the data packet matching mechanism according to the user modification instruction;

[0015] Triggering the packet matching mechanism via a tool for configuring and downloading hardware;

[0016] The packet matching mechanism is triggered through a command line tool.

[0017] On the other hand, the process of determining the parameter value corresponding to the packet matching mechanism includes:

[0018] Create hardware management interface commands for modifying packet matching options;

[0019] Adding the flag parameter value of the data packet size of the port and the flag parameter value of the data packet size of the switch to the data packet matching option;

[0020] Receiving the hardware management interface command through the control platform to modify the data packet matching option;

[0021] The modified flag parameter value of the data packet matching option is determined by the guiding system as the parameter value.

[0022] On the other hand, matching processing is performed according to the initial data packet sizes corresponding to the ports of the current converter to obtain the final data packet sizes of the ports of the current converter, including:

[0023] Obtaining an initial data packet size corresponding to a current port and an initial data packet size corresponding to a next port of the current converter;

[0024] Determine whether the initial data packet size corresponding to the current port is the same as the initial data packet size corresponding to the next port;

[0025] If they are the same, the next port is used as the new current port, and the initial data packet size corresponding to the new next port is obtained; and the step of determining whether the initial data packet size corresponding to the current port is the same as the initial data packet size corresponding to the next port is returned;

[0026] If they are different, the smallest initial data packet size is obtained from the initial data packet size corresponding to the current port and the initial data packet size corresponding to the next port as the first data packet size, and the first data packet size is replaced with the initial data packet size corresponding to the current port and the next port respectively; and the next port is used as the new current port, and the initial data packet size corresponding to the new next port is obtained, and the step of determining whether the initial data packet size corresponding to the current port and the initial data packet size corresponding to the next port are the same is returned; until the initial data packet sizes of all ports under the current converter are compared, the matching processing of the initial data packet sizes of all ports is completed, and the final data packet size of all ports after the matching corresponding to the current converter is output.

[0027] To solve the above technical problems, the present invention also provides a method for matching data packet size based on a topological structure, wherein the topological structure includes a root complex, a switch and a port; the root complex includes a plurality of switches; a switch includes a plurality of ports;

[0028] The control root complex scans the initial data packet size corresponding to each port of the corresponding current converter when the reset is completed;

[0029] Obtaining the final data packet size corresponding to each port obtained by each converter through the steps of the data packet size matching method described above;

[0030] The final data packet size of each converter is matched to obtain the data packet size under the topology structure.

[0031] In order to solve the above technical problems, the present invention further provides a data packet size matching device, comprising:

[0032] A first acquisition module is used to acquire a parameter value corresponding to a data packet matching mechanism; wherein the parameter value of the data packet matching mechanism represents a flag bit of a matching data packet size;

[0033] A scanning module, configured to scan the initial data packet size corresponding to each port of the current converter corresponding to the target architecture if the parameter value is a matching data packet size flag;

[0034] The first matching processing module is used to perform matching processing according to the initial data packet size corresponding to each port of the current converter to obtain the final data packet size of each port of the current converter; wherein the final data packet size is the same at each port of the current converter.

[0035] To solve the above technical problems, the present invention also provides a data packet size matching device based on a topology structure, wherein the topology structure includes a root complex, a switch and a port; the root complex includes a plurality of switches; a switch includes a plurality of ports;

[0036] A control module, used for controlling the root complex to scan the initial data packet size corresponding to each port of the corresponding current converter when the reset is completed;

[0037] A second acquisition module, used to acquire the final data packet size corresponding to each port obtained by each converter through the steps of the data packet size matching method described above;

[0038] The second matching processing module is used to match the final data packet size of each converter to obtain the data packet size under the topology structure.

[0039] In order to solve the above technical problems, the present invention also provides a data packet size matching device, comprising:

[0040] Memory for storing computer programs;

[0041] A processor is used to implement the steps of the data packet size matching method described above or the data packet size matching method based on topology structure described above when executing the computer program.

[0042] In order to solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the data packet size matching method as described above or the data packet size matching method based on topology structure as described above.

[0043] The present invention provides a data packet size matching method, which obtains a parameter value corresponding to a data packet matching mechanism; wherein the parameter value of the data packet matching mechanism represents a flag bit of the matching data packet size; if the parameter value is a matching data packet size flag, the initial data packet size corresponding to each port of the current converter corresponding to the target architecture is scanned; matching processing is performed according to the initial data packet size corresponding to each port of the current converter to obtain the final data packet size of each port of the current converter; wherein the final data packet size is the same at each port of the current converter.

[0044] The beneficial effect of the present invention is that the initial data packet size of each port is combined with the current converter to match the data packet size between the two ports corresponding to the point-to-point communication, so as to achieve the same final MPS between the ports connected through the converter, eliminate the imbalance between MPSs, and avoid downtime. At the same time, the triggering of the data packet matching mechanism is adopted to realize the adaptive MPS adaptation method, thereby improving the customer experience.

[0045] Secondly, by adding parameter values ​​of packet matching options under the guidance system, the system can be automatically adapted through the flag bit to improve the automation and efficiency of matching. The triggering method of multiple packet matching mechanisms of the guidance system improves the flexibility and diversity of triggering the mechanism, and at the same time, improves the automation of the triggering method. The parameter values ​​corresponding to the packet matching mechanism are determined by the control platform to improve the flexibility and diversity of triggering the mechanism, and at the same time, improve the automation of the triggering method. The matching process adopts a cyclic iterative comparison method to improve the efficiency of screening and matching processing.

[0046] In addition, the present invention also provides a data packet size matching method based on topology structure, a data packet size matching device, a data packet size matching device based on topology structure, a data packet size matching apparatus and a medium, which have the same beneficial effects as the above-mentioned data packet size matching method. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A flow chart of a data packet size matching method provided by an embodiment of the present invention;

[0049] Figure 2 A schematic diagram of hardware interaction corresponding to the matching of a data packet size provided in an embodiment of the present invention;

[0050] Figure 3 A flowchart of another data packet size matching method provided by an embodiment of the present invention;

[0051] Figure 4 A flowchart of a method for matching data packet size based on topology structure provided by an embodiment of the present invention;

[0052] Figure 5 A structural diagram of a data packet size matching device provided by an embodiment of the present invention;

[0053] Figure 6 A structural diagram of a device for matching data packet size based on topology structure provided by an embodiment of the present invention;

[0054] Figure 7 A structural diagram of a data packet size matching device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] The core of the present invention is to provide a data packet size matching method, device, apparatus and storage medium to solve the problem of MPS mismatch in the converter caused by data transmission between various ports, thereby causing downtime due to MPS imbalance.

[0057] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0058] MPS is an important parameter in the PCI Express bus. It defines the maximum length of the data payload in the TLP message. The memory read request, memory write request, and memory read request TLP of the PCIE bus contain data payloads, and the length of these data payloads is related to the MPS, the maximum read request size (Max Read Request Size, MRRS), and the read completion boundary (Read Completion Boundary, RCB). MPS represents the maximum length of the data payload in the TLP message. The maximum value of the PCIE bus MPS is 4KB, but not all PCIE devices can send data payloads according to the maximum length. Therefore, the actual MPS used is determined by the device Function negotiation at both ends of the link. When the length of the sent data exceeds the MPS, this data will be divided into multiple TLP messages and sent. For the memory read completion TLP message, the length of the data payload cannot exceed the MPS. If it exceeds the MPS, multiple read completion messages need to be sent, and the requirements of the read completion boundary (Read Completion Boundary, RCB) must also be met.

[0059] In the PCIE device configuration space, the Device Capabilities register records the MPS supported by the PCIE device function, while the Device Control register saves the MPS set by the host. This means that by adjusting the values ​​of these registers, the MPS settings of the PCIE device can be affected and controlled, thereby affecting the efficiency and stability of data transmission. For example, by optimizing the MPS settings, the number of data segmentation can be reduced, the efficiency of large data transmission can be improved, and the integrity and correctness of data transmission can be ensured. According to the PCIE Spec, MPS is divided into six types: 128B, 256B, 512B, 1024B, 2048B, and 4096B. The larger the MPS, the higher the proportion of valid data that can be carried in the TLP.

[0060] However, the larger the MPS, the better. A larger MPS will increase the size of each data packet, which will increase the transmission load, increase the delay, increase the error rate, and even reduce the system performance. During the initialization of the PCIE link, the MPS will be set to the same value, that is, the minimum MPS parameter, according to the MPSS support of the root complex (RC), peripheral component interconnect fast channel converter (PCIE Switch), and endpoint of the PCIE architecture according to the barrel effect. In most port nodes, the MPSS parameter is no more than 512B. The size of the MPS parameter is proportional to the transmission efficiency of the PCIE link. The larger the parameter, the higher the utilization rate of the PCIE link bandwidth, and the smaller the parameter, the lower the utilization rate of the PCIE link bandwidth.

[0061] Multiple devices with different bandwidths are connected in a port node, and the MPS of each device is different. The conventional port node is determined by the minimum MPS parameter of all devices under the node. When the data is processed by the RC end, the RC will unpack the data according to the unit determined by the platform to ensure that TLP can be identified when the ports interact. The size of the MPS will affect the transmission efficiency and performance of the PCIE bus. A smaller MPS value may cause the data transmission to be divided into multiple TLPs, thereby reducing the transmission efficiency; while a larger MPS value may increase the memory and logic required for the hardware to process the data packet. In order to ensure the compatibility and stability of data transmission, such processing will also reduce performance. Therefore, the RC end selects the best decision from the perspective of stability and performance. Although the data interaction processed by the RC has solved the problem, for the interaction that does not pass through the RC end, there is no processing standard and corresponding processing, such as the built-in SW (converter), and the SW does not handle this type of problem. Therefore, when the TLP does not match, the device will receive a value that exceeds the negotiated MPS and cannot be identified. At this time, the "Malformed TLP" error or even downtime will occur.

[0062] Malformed TLP data communication error. If the Length field of the TLP sent by the RC device exceeds the MPS configuration of the endpoint device (EP), or the built-in SW or the SWs have different MPS for peer-to-peer (P2P) interaction, the EP device will consider the TLP illegal and may report a "Malformed TLP" error. This will cause data transmission failure or system instability. Communication failure: In the PCIE topology, if the MPS values ​​between different nodes are not equal and are not properly configured, communication between the RC and EP may fail.

[0063] System crash or restart: In extreme cases, an imbalance in MPS may cause a system crash or restart, especially in scenarios involving critical data transmission and processing. Device incompatibility: With the continuous upgrading of PCIE devices and systems, the support scope of MPS is also changing. If the MPS settings between new and old devices are incompatible, it may cause the device to not work properly or the overall system performance to deteriorate.

[0064] Conventional links find the link with the smallest MPS support on the two links according to the configuration, and set the affected port nodes to matching values. The transmission efficiency is low, and the customer configuration needs to be identified in advance, resulting in a poor customer experience. The data packet size matching method provided by the present invention can solve the above technical problems.

[0065] Figure 1A flow chart of a method for matching data packet sizes provided by an embodiment of the present invention, such as Figure 1 As shown, the method includes:

[0066] S11: Obtain parameter values ​​corresponding to the data packet matching mechanism;

[0067] Wherein, the parameter value of the packet matching mechanism represents the flag bit of the matching packet size;

[0068] S12: If the parameter value is a matching data packet size flag, scanning the initial data packet size corresponding to each port of the current converter corresponding to the target architecture;

[0069] S13: performing matching processing according to the initial data packet sizes corresponding to the various ports of the current converter to obtain the final data packet sizes of the various ports of the current converter;

[0070] The final data packet size is the same at each port of the current converter.

[0071] PCIE is a high-speed serial bus standard used to connect computer motherboards and external devices. It is used to connect external devices on computer motherboards. PCIE devices are hardware devices connected to the motherboard through PCIE slots. PCIE is developed based on the traditional Peripheral Component Interconnect (PCI) bus to provide higher bandwidth and performance.

[0072] The TLP (Transaction Layer Packet) in the PCIE bus transaction layer is the basic unit of data packets transmitted when the processor or other PCIE devices access the PCIE device. The transmission process of TLP starts from the transaction layer of the sending end, passes through the data link layer and the physical layer, and finally reaches the transaction layer of the receiving end.

[0073] When a device communicates through the PCIE bus, it first encapsulates the PCIE transaction request (such as memory read and write, configuration access, interrupt generation, etc.) initiated by the upper layer (such as the application layer, device driver layer, etc.) into TLP, and then sends it out through the various layers of the PCIE bus. The basic format of TLP includes one or more TLP Prefixes, TLP headers, Data Payload data payload, and TLP Digest. Among them, the TLP header is the most important symbol of TLP, which contains a series of information such as the bus transaction type and routing information of the current TLP. The length of Data Payload is variable, with a minimum of 0 and a maximum of 1024DW. TLPDigest is optional. Whether a TLP needs TLP Digest is determined by the TLP header. Data Payload is also optional. Some TLPs do not require Data Payload, such as memory read requests, configurations, and input and output (IO) write completions.

[0074] Specifically, the present invention only matches the data packet size for MPS matching in each port of the current converter. Conventional MPS matching for multiple devices corresponding to only one port causes the current converter to connect multiple ports with different MPS parameter sizes, resulting in unmatched balance.

[0075] The parameter value of the packet matching mechanism in step S11 is a flag bit that triggers the matching packet pool size. For example, when the flag bit is 1, the packet matching mechanism is triggered; when the flag bit is 0, the packet matching mechanism is not triggered. In order to achieve automatic matching, the present invention is triggered by the parameter value of the flag bit, thereby improving the automatic implementation of the matching process.

[0076] Regarding the addition of parameter values ​​of the packet matching mechanism, it can be added in the form of options through the boot system or the control platform. The boot system refers to a series of programs and processes used to load and start the operating system during the computer startup process. It is responsible for loading the operating system kernel into the memory and completing the necessary initialization work so that the system can run normally. This process usually includes multiple steps such as hardware self-test, execution of the boot loader, loading of the operating system kernel, and display of the user interface. The boot system of the present invention can be an input and output system (Basic InputOutput System, BIOS), or a unified extensible firmware interface, a boot loader, etc., which is not limited here and can be set according to actual conditions.

[0077] The initial data packet size corresponding to each port connected to the current converter. It should be noted here that the initial data packet size of each port is the data packet size formed after the data packet sizes of all devices under the respective ports have been matched.

[0078] Before step S11, the server needs to be powered on and executed as follows:

[0079] 1. Turn on the server;

[0080] 2. Initialize the PCIE bus, including setting some basic parameters of the bus, such as clock frequency, bus width, etc.;

[0081] 3. Reset the RC on the PCIE bus, including device detection, configuration, and data transmission. The RC operation will put all devices on the bus into an unconfigured state.

[0082] 4. After the RC end is reset, it starts scanning the devices on the PCIE bus. The scanning process starts from RC, discovers and scans the PCI bridge, and then scans each device step by step downward.

[0083] 5. Read the configuration space of each PCIE device to obtain the device's capabilities and configuration information, including some important configuration information of the device, such as device identifier (DID), vendor identifier (VID), device type, maximum supported payload size (MPSS), and MPS parameters.

[0084] 6. The system negotiates and determines the actual MPS value to be used based on the device capabilities at both ends of the PCIE link. This process involves communication and negotiation between multiple devices and the Root end.

[0085] 7. After negotiation, the MPS value will be determined, and the BIOS will write this value into the Device Control register of the PCIE device. This register is located in the configuration space of the PCIE device, and the corresponding Device Control MPS register is found through the Capability Pointer register for writing.

[0086] In step S12, based on the parameter value being a matching packet size flag, it is necessary to scan the output packet size corresponding to each port of the current converter under the target architecture. The scanning method here is a deep scan. The matching packet size flag in step S12 is used to trigger the current packet matching mechanism, that is, to determine that the current end node is a converter node. If it is not a converter node, the current end node will be skipped and the scanning will continue until all devices on the PCIE bus are scanned.

[0087] After the initial data packet sizes corresponding to the various ports of the current converter are scanned in step S13, matching processing is performed to obtain the final data packet sizes of the various ports of the current converter. It should be noted here that the matching processing is to achieve data packet balance of the various ports connected to the current converter for transmission. The specific matching process can be to determine the parameter values ​​that can be transmitted by each port through a specific algorithm, or to select the same data packet size for determination. The transmission data packet size of a port includes multiple ones, taking into account the transmission data packet size of each port, the same data packet size can be selected for transmission, and the smallest data packet size can be used for transmission, etc. The ultimate goal is to achieve the same final data packet size for each port of the current converter.

[0088] A data packet size matching method provided by an embodiment of the present invention obtains a parameter value corresponding to a data packet matching mechanism; wherein the parameter value of the data packet matching mechanism represents a flag bit of the matching data packet size; if the parameter value is a matching data packet size flag, the initial data packet size corresponding to each port of the current converter corresponding to the target architecture is scanned; matching processing is performed according to the initial data packet size corresponding to each port of the current converter to obtain the final data packet size of each port of the current converter; wherein the final data packet size is the same for each port of the current converter. With respect to the initial data packet size of each port, the data packet size between the two ports corresponding to the point-to-point communication is matched in combination with the current converter, so that the final MPS between the ports connected by the converter is the same, the imbalance between the MPS is eliminated, and downtime is avoided. At the same time, the triggering of the data packet matching mechanism is adopted to realize an adaptive MPS adaptation method to improve the customer experience.

[0089] In some embodiments, the parameter value of the packet matching mechanism is added, and the determination process is as follows:

[0090] Added packet matching option by booting the system's installation path;

[0091] Add the flag parameter value of the data packet size of the port and the flag parameter value of the data packet size of the converter to the data packet matching option to use the flag parameter value as the parameter value; wherein the flag parameter value of the data packet size of the port and the flag parameter value of the data packet size of the converter are different.

[0092] Specifically, the packet matching option is added through the installation path of the boot system. Here, the boot system takes BIOS as an example, and its installation path is: Advanced->Miscellaneous Configuration. A new packet matching option is added, and the optional values ​​are Disable(0) and Enable(1). The default value of this option is Disable. Disable means negotiation is performed according to the MPS of the devices at both ends and RC, and the entire port is set according to the minimum MPS for Device Control, that is, keep the default; Enable means negotiation is performed under the same SW, and negotiation is performed according to the minimum device under the SW, ensuring that the MPS under the same SW is the same.

[0093] This embodiment provides a parameter value of a data packet matching option added under the boot system, so as to realize automatic adaptation of the system through a flag bit, thereby improving the automation and efficiency of matching.

[0094] In some embodiments, the packet matching mechanism is triggered in one of the following ways:

[0095] Receive user modification instructions and trigger the data packet matching mechanism according to the user modification instructions;

[0096] Triggering the packet matching mechanism through the tools used to configure and download the hardware;

[0097] Trigger the packet matching mechanism through the command line tool.

[0098] Specifically, the system receives user modification instructions and triggers the packet matching mechanism according to the user modification instructions. The customer sets the option value according to the requirements, enters BIOS SETUP, finds Advanced->Miscellaneous Configuration->Auto Match MPS, manually modifies the option, saves and restarts to take effect.

[0099] The packet matching mechanism is triggered by tools used to configure and download hardware, such as the Station Configuration Editor (SEC tool), a tool used to configure and manage personal computers (PC) in automation systems. It can achieve centralized management and configuration of PC stations in automation systems, thereby improving system efficiency and reliability. Enter the operating system (OS) or Shell, use the SCE tool, modify the option value to 0 or 1 through mapstring AutoMatch MPS, and restart the system to take effect.

[0100] The packet matching mechanism is triggered by command line tools, such as the redfish tool, which is a management standard based on the secure Hyper Text Transfer Protocol (HTTPs) service, and implements device management using an interface (RESTful) that follows the Representational State Transfer (REST) ​​architectural style. Each HTTPs operation submits or returns a resource or result in the UTF-8 encoded, interpreted JavaScript Object Notation (JSON) format, just like a World Wide Web (Web) application returns Hyper Text Markup Language (HTML) to a browser. This technology has the advantages of reducing development complexity, being easy to implement, easy to use, and providing scalability, leaving room for design flexibility. The Redfish management interface can be used to implement common hardware management and BIOS configuration, including user management, obtaining server information, and managing module information. Redfish tools generally refer to command line tools or software used to access and operate device management interfaces that comply with the Redfish standard. These tools can perform various management tasks, such as monitoring server hardware status, configuring system settings, managing user permissions, etc., and interact with the server through the Redfish Application Programming Interface (API).

[0101] The triggering method of the multiple data packet matching mechanism of the guidance system provided in this embodiment improves the flexibility and diversity of triggering the mechanism, and at the same time, also improves the automation of the triggering method.

[0102] In some embodiments, the process of determining the parameter value corresponding to the packet matching mechanism includes:

[0103] Create hardware management interface commands for modifying packet matching options;

[0104] Add the flag parameter value of the port's packet size and the flag parameter value of the switch's packet size to the packet matching options;

[0105] Receive hardware management interface commands through the control platform to modify data packet matching options;

[0106] The flag parameter value of the modified packet matching option is determined by the boot system as the parameter value.

[0107] Specifically, develop an original equipment manufacturer (OEM) hardware management interface command, such as an Intelligent Platform Management Interface (IPMI) command, which is used to set the current value and default value of the option Auto Match MPS. After receiving the IPMI command, the BMC parses the command, modifies the current value and default value of the option Auto Match MPS according to the command requirements, saves them, and sets the flag of the option change to 1. The machine restarts, and the BIOS determines the flag information to synchronize the options.

[0108] Figure 2 A schematic diagram of hardware interaction corresponding to a data packet size matching provided by an embodiment of the present invention, such as Figure 2 As shown, the control platform and the corresponding intelligent platform management interface under the boot system are connected through the application programming interface, wherein the control platform connects the IPMI command through the communication medium to achieve the interaction before matching.

[0109] This embodiment provides a method for determining parameter values ​​corresponding to a data packet matching mechanism through a control platform, thereby improving the flexibility and diversity of triggering the mechanism and, at the same time, improving the automation of the triggering method.

[0110] In some embodiments, performing matching processing according to the initial data packet sizes corresponding to the ports of the current converter to obtain the final data packet sizes of the ports of the current converter includes:

[0111] Obtaining an initial data packet size corresponding to a current port and an initial data packet size corresponding to a next port of the current converter;

[0112] Determine whether the initial data packet size corresponding to the current port is the same as the initial data packet size corresponding to the next port;

[0113] If they are the same, the next port is used as the new current port, and the initial data packet size corresponding to the new next port is obtained; and the step of determining whether the initial data packet size corresponding to the current port is the same as the initial data packet size corresponding to the next port is returned;

[0114] If they are different, the smallest initial data packet size is obtained from the initial data packet size corresponding to the current port and the initial data packet size corresponding to the next port as the first data packet size, and the first data packet size is replaced with the initial data packet size corresponding to the current port and the next port respectively; and the next port is used as the new current port, and the initial data packet size corresponding to the new next port is obtained, and the step of determining whether the initial data packet size corresponding to the current port and the initial data packet size corresponding to the next port are the same is returned; until the initial data packet sizes of all ports under the current converter are compared, the matching processing of the initial data packet sizes of all ports is completed, and the final data packet size of all ports after the matching of the current converter is completed is output.

[0115] In this embodiment, for the initial data packet sizes of all ports of the current converter scanned in step S12, a comparison method is adopted for every two, and the initial data packet size of the current port is compared with the initial data packet size corresponding to the next port. If they are the same, it means that the initial data packet sizes of the two ports are the same, and if data is transmitted in these two ports, there will be no imbalance problem. Therefore, the next port is continued as the new current port for comparison. If the initial data packet size of the current port is different from the initial data packet size corresponding to the next port, it is necessary to obtain the smallest initial data packet size as the first data packet size from the initial data packet size corresponding to the current port and the initial data packet size corresponding to the next port according to the barrel effect, and replace the initial data packet size corresponding to the current port and the next port respectively with the first data packet size to achieve the balance of the initial data packet size of the two ports. Continue to compare the initial data packets of the next port with the two ports. If they are the same, continue to select the subsequent port for comparison. If they are different, continue to select the smallest initial data packet size as the data packet size of the three ports until the initial data packet size of all ports of the current converter is compared. The matching process of the initial data packet sizes of all ports is completed, and the final data packet size of all ports corresponding to the current converter after the matching is completed is output.

[0116] The matching process provided in this embodiment uses a cyclic iterative comparison method to improve the efficiency of the screening and matching process.

[0117] In some other embodiments, matching processing is performed according to the initial data packet sizes corresponding to the ports of the current converter to obtain the final data packet sizes of the ports of the current converter, including:

[0118] Get the initial data packet size corresponding to all ports of the current converter;

[0119] Determine whether the initial data packet sizes corresponding to all ports are the same;

[0120] If they are the same, the initial data packet sizes corresponding to all ports are taken as the final data packet sizes;

[0121] If there is a difference, the initial data packet sizes corresponding to all ports are sorted from small to large, and the smallest initial data packet size is used as the final data packet size of all ports.

[0122] The comparison method of this embodiment is different from that of the above embodiment. The above embodiment uses a cyclic iteration method for comparison. In this embodiment, the initial data packet sizes corresponding to all ports are judged to see if they are the same. If they are the same, the initial data packet sizes corresponding to all ports are used as the final data packet size. If there are differences, the initial data packet sizes corresponding to all ports are sorted from small to large, and the smallest initial data packet size is used as the final data packet size of all ports.

[0123] The comparison and matching process provided in this embodiment improves the diversity and flexibility of data matching processing. At the same time, through the data barrel effect comparison method, the matching process is made simple and clear, and the efficiency of the matching processing is improved.

[0124] Figure 3 A flowchart of another data packet size matching method provided by an embodiment of the present invention, such as Figure 3 As shown, including:

[0125] S21: server startup;

[0126] S22: Initialization of the peripheral component interconnect fast channel bus;

[0127] S23: The root complex of the peripheral component interconnect fast channel bus performs a reset operation;

[0128] S24: Scan the devices on the PICH bus, and read the configuration space of each PICH device to obtain the capability and configuration information of the device;

[0129] S25: Negotiate and determine the actual data packet size value to be used according to the device capabilities at both ends of the peripheral component interconnect fast channel link;

[0130] S26: Obtain the current value of the stored automatic packet matching option and assign the variable as a flag bit;

[0131] S27: Determine whether the flag bit is 1; if so, proceed to step S28; if not, return to step S26 to obtain;

[0132] S28: Scan each port of each converter again in a deep scanning manner;

[0133] S29: Determine whether the scan is finished; if so, proceed to step S35; if not, proceed to step S30;

[0134] S30: Determine whether the node is a node of a converter; if so, proceed to step S31, if not, return to step S28;

[0135] S31: Obtain the initial data packet size corresponding to each port and compare them in sequence;

[0136] S32: Determine whether the initial data packet sizes of the ports under the current converter node are consistent; if consistent, return to step S28; if inconsistent, proceed to step S33;

[0137] S33: modify the initial data packet sizes corresponding to all links that are inconsistent with the minimum initial data packet size; and return to step S28;

[0138] S34: After the final data packet size of each port under the current converter node is set, the peripheral component interconnect fast channel device will perform data transmission according to the negotiated final data packet size;

[0139] S35: Continue to execute subsequent operations until entering the startup phase of the operating system.

[0140] Furthermore, the present invention also provides a method for matching data packet size based on topology structure. Figure 4 A flowchart of a method for matching data packet size based on a topology structure provided by an embodiment of the present invention, wherein the topology structure includes a root complex, a switch and a port node; the root complex includes a plurality of switches; a switch includes a plurality of port nodes; Figure 4 As shown, the method includes:

[0141] S41: When the reset of the control root complex is completed, scanning the initial data packet size corresponding to each port of the corresponding current converter;

[0142] S42: Obtaining the final data packet size corresponding to each port obtained by each converter through the steps of the data packet size matching method;

[0143] S43: Matching the final data packet size of each converter to obtain the data packet size under the topology structure.

[0144] It should be noted that the root complex, converter and port node in this embodiment form a topological structure, and the root complex (RC) is usually integrated in the host. It is responsible for parsing and generating PCIE messages and can support one or more ports. RC can convert requests from the central processing unit (CPU) into different types of PCIE requests, such as configuration, memory, I / O and message requests. Port nodes are leaf roles based on the tree topology and are PCIE functional devices, such as network cards, graphics cards, etc. EPs do not have the function of forwarding data, they are the source or destination of data. The converter allows a PCIE port to be expanded into multiple ports, thereby connecting more devices. A standard Switch has an upstream port (Upstream Port) and multiple downstream ports (Downstream Ports). The upstream port is connected to the downstream port of the RC or other Switch, and the downstream port can be connected to the upstream port of the EP or other Switch. The Switch is composed of multiple virtual PCI-PCI bridges, and each port corresponds to a virtual PCI bridge. Switch is responsible for forwarding transactions between ports and must be able to forward all types of TLPs between any group of ports.

[0145] This embodiment implements the MPS matching balance of multiple converters corresponding to the multiple ports connected to the multiple converters respectively, on the premise that the MPS matching balance is implemented for the multiple ports under one converter in the above embodiments.

[0146] For an introduction to a topology-based data packet size matching method provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. The method has the same beneficial effects as the above data packet size matching method.

[0147] The above describes in detail various embodiments corresponding to the data packet size matching method. On this basis, the present invention also discloses a data packet size matching device corresponding to the above method. Figure 5 A structural diagram of a data packet size matching device provided by an embodiment of the present invention. Figure 5 As shown, the matching devices for data packet size include:

[0148] The first acquisition module 11 is used to acquire a parameter value corresponding to a data packet matching mechanism; wherein the parameter value of the data packet matching mechanism represents a flag bit of a matching data packet size;

[0149] A scanning module 12, configured to scan the initial data packet size corresponding to each port of the current converter corresponding to the target architecture if the parameter value is a matching data packet size flag;

[0150] The first matching processing module 13 is used to perform matching processing according to the initial data packet sizes corresponding to the ports of the current converter to obtain the final data packet sizes of the ports of the current converter; wherein the final data packet sizes are the same at the ports of the current converter.

[0151] On this basis, the present invention also discloses a data packet size matching device based on a topology structure corresponding to the above method, wherein the topology structure includes a root complex, a converter and a port; the root complex includes a plurality of converters; a converter includes a plurality of ports; Figure 6 A structural diagram of a device for matching data packet size based on topology structure provided by an embodiment of the present invention. Figure 6 As shown, the matching of packet size based on topology includes:

[0152] The control module 14 is used to control the root complex to scan the initial data packet size corresponding to each port of the corresponding current converter when the reset is completed;

[0153] A second acquisition module 15 is used to acquire the final data packet size corresponding to each port obtained by each converter through the steps of the above-mentioned data packet size matching method;

[0154] The second matching processing module 16 is used to match the final data packet size of each converter to obtain the data packet size under the topology structure.

[0155] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0156] For an introduction to a data packet size matching device or a data packet size matching device based on a topological structure provided by the present invention, please refer to the above-mentioned method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above-mentioned data packet size matching method or the data packet size matching method based on a topological structure.

[0157] Figure 7 A structural diagram of a data packet size matching device provided by an embodiment of the present invention, such as Figure 7 As shown, the device comprises:

[0158] A memory 21, used for storing computer programs;

[0159] The processor 22 is used to implement the steps of the above-mentioned data packet size matching method or the data packet size matching method based on the topology structure when executing the computer program.

[0160] The data packet size matching device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0161] Among them, the processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 22 may be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 22 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU; the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 22 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 22 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0162] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used to store the following computer program 211, wherein, after the computer program is loaded and executed by the processor 22, it can implement the relevant steps of the data packet size matching method disclosed in any of the aforementioned embodiments or the data packet size matching method based on the topological structure. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include but is not limited to the data involved in the data packet size matching method or the data packet size matching method based on the topological structure, etc.

[0163] In some embodiments, the data packet size matching device may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a power supply 26 , and a communication bus 27 .

[0164] Those skilled in the art can understand that Figure 7 The structure shown in the figure does not constitute a limitation on the device for matching the data packet size, and may include more or less components than those shown in the figure.

[0165] The processor 22 calls the instructions stored in the memory 21 to implement the data packet size matching method provided in any of the above embodiments or the data packet size matching method based on the topology structure.

[0166] For an introduction to a data packet size matching device provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above data packet size matching method or the data packet size matching method based on topology structure.

[0167] Furthermore, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by the processor 22, implements the steps of the above-mentioned data packet size matching method or the data packet size matching method based on topology structure.

[0168] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0169] For an introduction to a computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above data packet size matching method or the data packet size matching method based on topology structure.

[0170] Furthermore, an embodiment of the present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of a data packet size matching method or a data packet size matching method based on a topology structure.

[0171] For an introduction to a computer program product provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. It has the same beneficial effects as the above data packet size matching method or the data packet size matching method based on topology structure.

[0172] The above is a detailed introduction to a data packet size matching method, device, apparatus and storage medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

[0173] It should also be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A method for matching data packet size, characterized in that: include: Obtaining a parameter value corresponding to a data packet matching mechanism; wherein the parameter value of the data packet matching mechanism represents a flag bit of a matching data packet size; If the parameter value is a matching data packet size flag, scanning the initial data packet size corresponding to each port of the current converter corresponding to the target architecture; Matching is performed according to the initial data packet sizes corresponding to the ports of the current converter to obtain the final data packet sizes of the ports of the current converter; wherein the final data packet sizes are the same at the ports of the current converter.

2. The method for matching data packet size according to claim 1, characterized in that: The process of determining the parameter value corresponding to the packet matching mechanism includes: Added packet matching option by booting the system's installation path; Add the flag parameter value of the data packet size of the port and the flag parameter value of the data packet size of the converter to the data packet matching option to use the flag parameter value as the parameter value; wherein the flag parameter value of the data packet size of the port is different from the flag parameter value of the data packet size of the converter.

3. The method for matching data packet size according to claim 2, characterized in that: The packet matching mechanism is triggered in one of the following ways: receiving a user modification instruction, and triggering the data packet matching mechanism according to the user modification instruction; Triggering the packet matching mechanism via a tool for configuring and downloading hardware; The packet matching mechanism is triggered through a command line tool.

4. The method for matching data packet size according to claim 1, characterized in that: The process of determining the parameter value corresponding to the packet matching mechanism includes: Create hardware management interface commands for modifying packet matching options; Adding the flag parameter value of the data packet size of the port and the flag parameter value of the data packet size of the switch to the data packet matching option; Receiving the hardware management interface command through the control platform to modify the data packet matching option; The modified flag parameter value of the data packet matching option is determined by the guiding system as the parameter value.

5. The method for matching data packet size according to any one of claims 1 to 4, characterized in that: The final data packet size of each port of the current converter is obtained by performing matching processing according to the initial data packet size corresponding to each port of the current converter, including: Obtaining an initial data packet size corresponding to a current port and an initial data packet size corresponding to a next port of the current converter; Determine whether the initial data packet size corresponding to the current port is the same as the initial data packet size corresponding to the next port; If they are the same, the next port is used as the new current port, and the initial data packet size corresponding to the new next port is obtained; and the step of determining whether the initial data packet size corresponding to the current port is the same as the initial data packet size corresponding to the next port is returned; If they are different, the smallest initial data packet size is obtained from the initial data packet size corresponding to the current port and the initial data packet size corresponding to the next port as the first data packet size, and the first data packet size is replaced with the initial data packet size corresponding to the current port and the next port respectively; and the next port is used as the new current port, and the initial data packet size corresponding to the new next port is obtained, and the step of determining whether the initial data packet size corresponding to the current port and the initial data packet size corresponding to the next port are the same is returned; until the initial data packet sizes of all ports under the current converter are compared, the matching processing of the initial data packet sizes of all ports is completed, and the final data packet size of all ports after the matching corresponding to the current converter is output.

6. A method for matching data packet size based on topology structure, characterized in that: The topology structure includes a root complex, a switch and a port; the root complex includes a plurality of switches; a switch includes a plurality of ports; The control root complex scans the initial data packet size corresponding to each port of the corresponding current converter when the reset is completed; Obtaining the final data packet size corresponding to each port obtained by each converter through the steps of the data packet size matching method according to any one of claims 1 to 5; The final data packet size of each converter is matched to obtain the data packet size under the topology structure.

7. A data packet size matching device, characterized in that: include: A first acquisition module is used to acquire a parameter value corresponding to a data packet matching mechanism; wherein the parameter value of the data packet matching mechanism represents a flag bit of a matching data packet size; A scanning module, configured to scan the initial data packet size corresponding to each port of the current converter corresponding to the target architecture if the parameter value is a matching data packet size flag; The first matching processing module is used to perform matching processing according to the initial data packet size corresponding to each port of the current converter to obtain the final data packet size of each port of the current converter; wherein the final data packet size is the same at each port of the current converter.

8. A device for matching data packet size based on topology structure, characterized in that: The topology structure includes a root complex, a switch and a port; the root complex includes a plurality of switches; a switch includes a plurality of ports; A control module, used for controlling the root complex to scan the initial data packet size corresponding to each port of the corresponding current converter when the reset is completed; A second acquisition module, used to acquire the final data packet size corresponding to each port obtained by each converter through the steps of the data packet size matching method according to any one of claims 1 to 5; The second matching processing module is used to match the final data packet size of each converter to obtain the data packet size under the topology structure.

9. A data packet size matching device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data packet size matching method according to any one of claims 1 to 5 or the data packet size matching method based on topology structure according to claim 6 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the data packet size matching method according to any one of claims 1 to 5 or the data packet size matching method based on topology structure according to claim 6.

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