Display apparatus and control method

Abstract

The embodiment of the invention provides a display device and a control method, a plurality of pixel driving circuits are arranged on a display panel of the display device, a fourth transistor in each pixel driving circuit is removed, and the capability of providing a second power supply signal for a first capacitor is replaced by a conduction loop composed of a seventh transistor and a third transistor. The first capacitor can still be reset by using the second power supply signal in the pixel driving circuit, and when the first capacitor provides driving data after threshold voltage compensation for the first transistor, only the leakage current of the third transistor affects data stored in the first capacitor, so that the leakage path is reduced, and the reliability of the pixel driving circuit is improved. The influence of the leakage current on the data stored in the first capacitor is reduced, and the stability of the driving current in the driving signal generated by the first transistor based on the data stored in the first capacitor is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display technology, and more particularly to a display device and a control method. Background Art

[0002] In recent years, display panels built based on organic light-emitting diodes or microdiodes have the characteristics of being light, power-saving, and self-luminous, becoming a hot topic in the display field.

[0003] The display panel has a plurality of pixel circuits arranged in an array, and the light-emitting element in each pixel circuit is driven to emit light by a pixel driving circuit. The operation process of the pixel driving circuit in a display cycle includes a reset phase, a data writing phase, and a display driving phase. During the display driving phase, when the driving transistor in the pixel driving circuit generates a driving signal according to the threshold-compensated driving data stored in its gate, the transistor electrically connected to the gate of the driving transistor generates a leakage current, thereby affecting the stability of the current value of the driving signal generated by the driving transistor.

[0004] Therefore, how to maintain the stability of the driving current becomes the focus of research. Summary of the invention

[0005] The present application provides a display device and a control method, which are used to solve the technical problem that a pixel driving circuit is affected by leakage current and the current value of a generated driving signal is unstable.

[0006] In a first aspect, an embodiment of the present application provides a display device, including:

[0007] A display panel, wherein a power line, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits are arranged on the display panel;

[0008] Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element;

[0009] The pixel driving circuit comprises:

[0010] a seventh transistor, a first end of which is electrically connected to the power line, a control end of which is electrically connected to the gate line, and configured to obtain a first scan signal and a second power signal, to control its conduction state by the first scan signal, and to output the second power signal from its second end when it is turned on;

[0011] a sixth transistor, a first end of which is electrically connected to the second end of the seventh transistor, a control end of which is electrically connected to the gate line, a second end of which is electrically connected to the first end of the light-emitting element, and configured to obtain a second light-emitting control signal and the second power supply signal, and to control its conduction state by the second light-emitting control signal, and to output the second power supply signal from its second end when it is turned on, so as to reset the first end of the light-emitting element;

[0012] a third transistor, a first end of which is electrically connected to the second end of the seventh transistor, a control end of which is electrically connected to the gate line, and configured to obtain a second scanning signal and the second power supply signal, to control its conduction state by the second scanning signal, and to output the second power supply signal from its second end when it is turned on;

[0013] The first capacitor has a first terminal electrically connected to the second terminal of the third transistor and is configured to reset the first terminal thereof using the second power signal.

[0014] In the above technical solution, the pixel driving circuit transmits the second power supply signal to the light-emitting element through the loop composed of the seventh transistor and the sixth transistor to reset the light-emitting element and maintain the resetting function of the seventh transistor on the light-emitting element. At the same time, the second power supply signal is transmitted to the first capacitor through the loop composed of the seventh transistor and the third transistor to reset the first capacitor, thereby replacing the function of the fourth transistor in the traditional pixel driving circuit, so that when the first capacitor provides the driving data after threshold voltage compensation to the first transistor, only the leakage current of the third transistor affects the data stored in the first capacitor, thereby reducing the leakage path and reducing the influence of the leakage current on the data stored in the first capacitor, which is beneficial to improving the stability of the driving current in the driving signal generated by the first transistor based on the data stored in the first capacitor.

[0015] In a feasible implementation manner, a display cycle includes a reset phase, a data writing phase and a display phase in sequence;

[0016] The reset phase includes a reset sub-phase;

[0017] In the reset sub-phase, the first scanning signal, the second scanning signal and the second light-emitting control signal are at a first level, and the third scanning signal and the first light-emitting control signal are at a second level;

[0018] The seventh transistor is turned on according to the first light emitting control signal, and the second power supply signal obtained at the first end thereof is transmitted to the first end of the sixth transistor and the first end of the third transistor;

[0019] The sixth transistor is turned on according to the second light emitting control signal, and transmits the second power supply signal obtained at the first end thereof to the first end of the light emitting element;

[0020] The third transistor is turned on according to the second scanning signal, and transmits the second power signal obtained at the first end thereof to the first capacitor;

[0021] The first capacitor resets its first end using the second power signal;

[0022] The light emitting element resets its first end according to the second power signal.

[0023] In the above technical solution, in the reset sub-stage, the loop composed of the seventh transistor and the third transistor between the first end of the first capacitor and the power line is turned on through the first scanning signal and the second scanning signal. The first capacitor does not need to use the fourth transistor in the original pixel driving circuit for providing the second power signal thereto, and can still obtain the second power signal from the power line according to the above loop for a reset operation, so that the first transistor is turned on according to the second power signal after the reset stage, and driving data for threshold voltage compensation is generated using the driving data, and a driving signal is generated according to the driving data. The pixel driving circuit can still realize the driving of the light-emitting element on the basis of reducing the occupied space, which helps to increase the pixel density of the display panel constructed based on the pixel driving circuit and improve the display of the details of the display screen by the display device.

[0024] In addition, since the number of transistors electrically connected to the first end of the first capacitor is reduced, when the first capacitor drives the first transistor to generate a driving signal, the first end of the first capacitor has a reduced leakage path due to the cancellation of the fourth transistor, which helps to improve the stability of the voltage value of the first end of the first capacitor, thereby improving the stability of the current value of the driving signal generated according to the potential value of the first end of the first capacitor, and alleviating the flickering phenomenon of the display panel composed of light-emitting elements.

[0025] In a second aspect, the present application provides a method for controlling a display device, which is used for the display device involved in the first aspect, and the method includes:

[0026] Controlling the seventh transistor and the third transistor to be turned on in the same period, so that the seventh transistor and the third transistor transmit the second power signal to the first capacitor, and reset the first end of the first capacitor;

[0027] The seventh transistor and the sixth transistor are controlled to be turned on in the same period, so that the seventh transistor and the sixth transistor transmit the second power supply signal to the light emitting element, and reset the first end of the light emitting element.

[0028] In the above technical solution, the seventh transistor and the third transistor are controlled to be turned on at the same time, so that the second power supply signal is used as a reset signal to reset the first capacitor, which replaces the process of controlling the conduction of the fourth transistor electrically connected to the power line and the first capacitor to reset the first capacitor. The fourth transistor can be simplified in the original pixel driving circuit, reducing the leakage path of the first capacitor, reducing the influence of the leakage current on the data stored in the first capacitor, and is beneficial to improving the stability of the driving current in the driving signal generated by the first transistor based on the data stored in the first capacitor.

[0029] The embodiment of the present application provides a display device and a control method. The display device includes a display panel. The display panel is provided with a power line, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits. Each sub-pixel circuit includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes: a seventh transistor, a sixth transistor, a third transistor and a first capacitor. The first end of the seventh transistor is electrically connected to the power line, the second end is electrically connected to the first end of the third transistor, the second end of the third transistor is electrically connected to the first end of the first capacitor, the first end of the seventh transistor obtains a second power signal from the power line, and when the seventh transistor and the third transistor are both turned on, the second power signal is transmitted to the first capacitor to reset the first end of the first capacitor. There is no need to set a single transistor connected between the power line and the first capacitor in the pixel driving circuit for resetting. When the first capacitor provides the driving data after threshold voltage compensation to the first transistor, only the leakage current of the third transistor affects the data stored in the first capacitor, thereby reducing the leakage path and reducing the influence of the leakage current on the data stored in the first capacitor, which is beneficial to improving the stability of the driving current in the driving signal generated by the first transistor based on the data stored in the first capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0031] Figure 1 This is a schematic diagram of the structure of a display device provided according to an exemplary embodiment of the present application;

[0032] Figure 2 A schematic structural diagram of a display device provided according to another exemplary embodiment of the present application;

[0033] Figure 3 A schematic structural diagram of a conventional pixel driving circuit is provided for the present application according to an exemplary embodiment;

[0034] Figure 4 A schematic diagram of a P-type pixel driving circuit is provided according to an exemplary embodiment of the present application;

[0035] Figure 5 A driving signal timing diagram of a P-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0036] Figure 6 A driving signal timing diagram of a P-type pixel driving circuit provided by the present application according to another exemplary embodiment;

[0037] Figure 7 A driving signal timing diagram of a P-type pixel driving circuit provided by the present application according to another exemplary embodiment;

[0038] Figure 8 A driving signal timing diagram of a P-type pixel driving circuit provided by the present application according to another exemplary embodiment;

[0039] Fig. 9 A schematic diagram of the structure of a scanning signal generating circuit provided by the present application according to an exemplary embodiment;

[0040] Fig.10 This is a timing diagram of input and output signals of a scanning signal generating circuit provided by the present application according to an exemplary embodiment;

[0041] Fig.11 A timing diagram of input and output signals of a scan signal generating circuit provided by the present application according to another exemplary embodiment;

[0042] Fig.12 This is a structural schematic diagram of a light emitting control signal generating circuit provided by the present application according to an exemplary embodiment;

[0043] Fig.13 This is a timing diagram of input and output signals of a light emitting control signal generating circuit provided in the present application according to an exemplary embodiment.

[0044] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] It should be noted that, in this article, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, the parts, features, and elements with the same names in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment. It should be further understood that the terms "include", "comprise" indicate the existence of features, steps, operations, elements, components, projects, types, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, types, and / or groups.

[0047] In the description of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0048] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] In recent years, display panels built based on organic light-emitting diodes or microdiodes have the characteristics of being light, power-saving, and self-luminous, becoming a hot topic in the display field.

[0050] like Figure 1 As shown, the display device includes a control circuit 10, a data driving circuit 20, a gate driving circuit 30, a display panel 40 and a power supply circuit 70. The control circuit 10 and the data driving circuit 20 are electrically connected, and the control circuit 10 and the gate driving circuit 30 are electrically connected. The display panel 40 and the data driving circuit 20, the gate driving circuit 30 and the power supply circuit 70 are electrically connected.

[0051] The display panel 40 includes a display area AA where a plurality of pixel units 80 are arranged and a non-display area NA outside the display area. In the display area AA, a power line 90, a plurality of gate lines 60 and a plurality of data lines 50 are arranged. The plurality of pixel units 80 are arranged in an array in the display area AA, and each pixel unit 80 is located in an area where the gate line 60 and the data line 50 intersect.

[0052] The gate drive circuit 30 is electrically connected to the gate line 60. The gate drive circuit 30 is configured to obtain a clock signal and a trigger signal from the control circuit 10, and generate a gate drive signal based on the clock signal and the trigger signal, and transmit the gate drive signal to the corresponding pixel unit 80 through the gate line 60 to control the transistor in the pixel unit 80 to be turned on or off.

[0053] More specifically, the gate driver circuit 30 can be made into a separate gate driver integrated circuit (GDIC), and the gate driver circuit 30 can also be integrated into the display panel. The way of integrating the gate driver circuit 30 into the display panel is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the display panel 40 through the COG process (Chip on Glass), and the GDIC can be electrically connected to the display panel 40 through the COF process (Chipon Film). In the COF process, the component is electrically connected to the display panel 40 through a flexible printed circuit (FPC).

[0054] The data driving circuit 20 is a circuit for driving the data line 50, and is configured to obtain display data from the control circuit 10, convert it into an analog data voltage (Vdata), and transmit the data analog voltage to the corresponding pixel unit 80 through the data line 50, so that the light-emitting element 813 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the light-emitting brightness of the light-emitting element 813.

[0055] The data driving circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

[0056] The power circuit 70 is a circuit for providing stable electrical signals, and is configured to provide corresponding required power signals to the display panel 40 , the control circuit 10 , the data driving circuit 20 , and the gate driving circuit 30 .

[0057] In one case, each pixel unit 80 includes three pixel circuits 810, which are respectively used to display red light, blue light, and green light. In another case, each pixel unit 80 includes four pixel circuits 810, which are respectively used to display red light, blue light, green light, and white light. This is not specifically limited here.

[0058] The luminous color of each pixel unit 80 is determined by the properties of the luminous element 813. The luminous element 813 can be any luminous device, including but not limited to OLED and micro LED.

[0059] Micro LED refers to a micro light emitting body made of inorganic semiconductor layers. Micro LEDs can generally include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, such as vertical, horizontal, flip-chip, etc., and is not particularly limited to a specific structure.

[0060] More specifically, if Figure 2 As shown, a pixel circuit 810 includes a pixel driving circuit 814 and a light emitting element 813. The pixel driving circuit 814 is electrically connected to the light emitting element 813, and the pixel driving circuit 814 is configured to drive the light emitting element 813 to emit light. The signals required by the pixel driving circuit 814 include a driving signal, a scanning signal (Scan), and an emission control signal (Emission, referred to as: EM control signal).

[0061] The drive signal may be generated by the control circuit 10 or obtained from the outside. It includes but is not limited to a start pulse signal, a clock signal, and an enable signal. The light-emitting control signal may be a global signal provided by the control circuit 10 or a signal generated by the gate drive circuit 30, which is not specifically limited here. The scanning signal is a successive displacement signal generated by the gate drive circuit 30.

[0062] If the EM control signal is a global signal generated by the control circuit 10 , the gate driving circuit 30 obtains the EM control signal from the control circuit 10 , and transmits the EM control signal to the corresponding pixel driving circuit 814 through the gate line 60 .

[0063] If both the EM control signal and the scan signal are generated by the gate driving circuit 30, the gate driving circuit 30 includes a scan signal generating circuit 301 and an EM control signal generating circuit 302. The scan signal generating circuit 301 outputs the scan signal, and the EM control signal generating circuit 302 outputs the EM control signal.

[0064] Figure 3 FIG. 1 is a schematic diagram of a conventional pixel driving circuit according to an exemplary embodiment of the present application. Figure 3As shown, the conventional pixel driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a first capacitor C1.

[0065] The first end of the fourth transistor M4 is electrically connected to the power line 90, and the control end is electrically connected to the gate line 60. The fourth transistor M4 is configured such that its control end obtains the first scan signal S1 from the gate line 60, and its first end obtains the second power signal Vref from the power line 90. The fourth transistor M4 is turned on when the first scan signal S1 is at a low level, and outputs the second power signal Vref from its second end.

[0066] The first end of the first capacitor C1 is electrically connected to the second end of the fourth transistor M4 , and is configured to obtain the second power signal Vref from the fourth transistor M4 , and reset the first end thereof using the second power signal Vref.

[0067] The first end of the second transistor M2 is electrically connected to the data line 50, and the control end thereof is electrically connected to the gate line 60. The second transistor M2 is configured such that its control end obtains the second scanning signal S2 from the gate line 60, and its first end obtains the driving data Vdata from the data line 50. The second transistor M2 is turned on when the second scanning signal S2 is at a low level, and outputs the driving data Vdata from its second end.

[0068] The first end of the third transistor M3 is electrically connected to the second end of the first transistor M1, the second end thereof is electrically connected to the control end of the first transistor M1, the control end thereof is electrically connected to the gate line 60, and is configured such that its control end obtains the second scanning signal S2 from the gate line 60, is turned on when the second scanning signal S2 is at a low level, and short-circuits the second end and the control end of the first transistor M1.

[0069] The first end of the first transistor M1 is electrically connected to the second end of the second transistor M2, the second end thereof is electrically connected to the first end of the third transistor M3, the control end thereof is electrically connected to the first end of the first capacitor C1, and is configured such that the control end thereof obtains the second power signal Vref from the first capacitor C1. In the present embodiment, the first transistor M1 is a p-type transistor, and the second power signal Vref is at a low level.

[0070] The first transistor M1 is turned on according to the second power signal Vref, and when it is turned on and the second terminal and the control terminal are short-circuited, it obtains driving data compensated for the threshold voltage from its control terminal according to the driving data Vdata and the threshold voltage obtained at its first terminal.

[0071] The first capacitor C1 is further configured to obtain and store the driving data after threshold voltage compensation from the control terminal of the first transistor M1.

[0072] The first end of the fifth transistor M5 is electrically connected to the power line 90, the second end thereof is electrically connected to the first end of the first transistor M1, and the control end thereof is electrically connected to the gate line 60. The fifth transistor M5 is configured such that its control end obtains the light emitting control signal EM from the gate line 60, and its first end obtains the first power supply signal VDD from the power line 90. The fifth transistor M5 is turned on when the light emitting control signal EM is at a low level, and outputs the first power supply signal VDD from its second end.

[0073] The first transistor M1 is also configured to disconnect its second end and control end when the third transistor M3 is turned off, and its control end obtains driving data after threshold voltage compensation from the first capacitor C1, and its first end obtains the first power signal VDD, and generates a driving signal according to the driving data after threshold voltage compensation and the first power signal VDD, wherein the driving current value in the driving signal is determined by the first transistor M1 according to the threshold voltage, the first power signal VDD and the driving data after threshold voltage compensation.

[0074] In the process of the first transistor M1 generating a driving signal, the fourth transistor M4 and the third transistor M3 are turned off, generating a leakage current, which may affect the charge stored in the first capacitor C1, thereby affecting the stability of the driving data after threshold voltage compensation stored at the first end of the first capacitor C1, thereby affecting the stability of the driving current in the driving signal generated according to the driving data after threshold voltage compensation.

[0075] In order to solve the above problems, the present application provides a display device and a control method. The technical concept of the present application is: in the display device, the fourth transistor in the pixel driving circuit is removed, and its ability to provide the second power supply signal to the first capacitor is replaced by a conduction loop composed of a seventh transistor and a third transistor, so that the second power supply signal can still be used to reset the first capacitor in the pixel driving circuit. When the first capacitor provides the driving data after threshold voltage compensation to the first transistor, only the leakage current of the third transistor affects the data stored in the first capacitor, which reduces the leakage path and reduces the influence of the leakage current on the data stored in the first capacitor, which is conducive to improving the stability of the driving current in the driving signal generated by the first transistor based on the data stored in the first capacitor. At the same time, the reduction in the number of devices in the pixel driving circuit reduces the space for the layout of each pixel driving circuit, which helps to increase the pixel density of the display panel constructed based on the pixel driving circuit and improve the display of the display details of the display device.

[0076] The specific circuit structure of the pixel driving circuit provided in this application is explained below.

[0077] Figure 4 FIG. 1 is a circuit structure diagram of a pixel driving circuit provided in accordance with an exemplary embodiment of the present application, as shown in FIG. Figure 4As shown, the transistor includes a first transistor M1, a second transistor M2, a third transistor M3, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a first capacitor C1. Figure 4 The transistors involved are all P-type transistors.

[0078] The first end of the second transistor M2 is electrically connected to the data line 50, and the control end thereof is electrically connected to the gate line 60. The second transistor M2 is configured such that its first end obtains the driving data Vdata from the data line 50, and its control end obtains the third scanning signal S3 from the gate line 60, and controls its conduction state according to the third scanning signal S3.

[0079] The second transistor M2 is configured to be turned on when the third scan signal S3 is at a low level, and transmit the driving data Vdata obtained at its first end to the second end so that the point S obtains the driving data Vdata; and to be turned off when the third scan signal S3 is at a high level, and stop transmitting the electrical signal.

[0080] The first end of the third transistor M3 and the second end of the first transistor M1 are electrically connected at point D, the second end thereof is electrically connected to the control end of the first transistor M1, and the control end thereof is electrically connected to the gate line 60. The third transistor M3 is configured such that its control end obtains the second scanning signal S2 from the gate line 60 and controls its conduction state according to the second scanning signal S2.

[0081] The third transistor M3 is configured to be turned on when the second scan signal S2 is at a low level, short-circuit the second end and the control end of the first transistor M1, and transmit the electrical signal obtained at its first end to its second end; and to be turned off when the second scan signal S2 is at a high level, disconnect the second end and the control end of the first transistor M1, and stop the transmission of the electrical signal between its first end and the second end.

[0082] The first end of the fifth transistor M5 is electrically connected to the power line 90, and the control end is electrically connected to the gate line 50. The fifth transistor M5 is configured such that the first end thereof obtains the first power signal VDD from the power line 90, and the control end thereof obtains the first light emission control signal EM1 from the gate line 50, and controls its conduction state according to the first light emission control signal EM1. In the present embodiment, the first power signal VDD is at a high level.

[0083] The fifth transistor M5 is configured to be turned on when the first light-emitting control signal EM1 is at a low level, and transmit the first power signal VDD obtained at its first end to the second end so that point S obtains the first power signal VDD; and to be turned off when the first light-emitting control signal EM1 is at a high level, and stop transmitting the electrical signal.

[0084] The second end of the first capacitor C1 is electrically connected to the power line 90, and the first end thereof is electrically connected to the control end of the first transistor M1 via point G, and is configured to store an electrical signal obtained from the first end thereof and maintain the potential value of the first end until the first end thereof obtains a new electrical signal.

[0085] The first end of the first transistor M1 is electrically connected to the S point, and is configured to determine the driving data Vdata compensated by the threshold voltage of the first transistor M1 from its control end when it is turned on, the control end and the second end are short-circuited, and the first end thereof obtains the driving data Vdata from the S point, and store the driving data Vdata compensated by the threshold voltage at the first end of the first capacitor C1; when it is turned on, the control end and the second end are disconnected, and the first end thereof obtains the first power supply signal VDD from the S point, the control end thereof obtains the driving data Vdata compensated by the threshold voltage from the second end of the first capacitor C1 through the G point, generates a driving signal according to the electrical signal obtained from the control end and the first end thereof, and outputs the driving signal from the second end thereof.

[0086] The first end of the seventh transistor M7 is electrically connected to the power line 90, the control end is electrically connected to the gate line 60, and the second end is electrically connected to point D. It is configured such that its first end obtains the second power signal Vref from the power line 90 and the first scan signal S1 from the gate line 60, and controls its conduction state according to the first scan signal S1.

[0087] The seventh transistor M7 is configured to be turned on when the first scan signal S1 is at a low level, and output the second power signal Vref obtained at its first end from its second end to point D; and to be turned off when the first scan signal S1 is at a high level, and stop transmitting the electrical signal.

[0088] The first end of the sixth transistor M6 is electrically connected to the second end of the first transistor M1 and the second end of the seventh transistor M7 through point D, the second end thereof is electrically connected to the first end of the light-emitting element LED, and the control end thereof is electrically connected to the gate line 60. The sixth transistor M6 is configured such that its control end obtains the second light-emitting control signal EM2 from the gate line 60, and controls its conduction state according to the second light-emitting control signal EM2.

[0089] The sixth transistor M6 is configured to be turned on when the second light emitting control signal EM2 is at a low level, and transmit the second power signal Vref obtained from the second end of the seventh transistor M7 to its second end, or transmit the driving signal obtained from the second end of the first transistor M1 to its second end.

[0090] The light emitting element LED is configured to obtain a driving signal from a first end thereof and emit light according to the driving signal, or to obtain a second power signal Vref from a first end thereof and reset according to the second power signal Vref.

[0091] When the pixel driving circuit is controlled by a control system consisting of a controller, a gate driving circuit, a data driving circuit and a power supply circuit, it is necessary to control the seventh transistor M7 and the third transistor M3 to be turned on in the same period of time, so that the seventh transistor M7 and the third transistor M3 transmit the second power supply signal Vref to the first capacitor C1, and reset the first end of the first capacitor C1.

[0092] The seventh transistor M7 and the sixth transistor M6 are controlled to be turned on in the same period, so that the seventh transistor M7 and the sixth transistor M6 transmit the second power signal Vref to the light emitting element LED to reset the first end of the light emitting element LED.

[0093] After resetting the first capacitor C1, the third transistor M3 and the second transistor M2 are controlled to be turned on in the same period and the second transistor M2 transmits driving data, so that the first capacitor C1 stores the driving data Vdata after the threshold voltage of the first transistor M1 is compensated determined by the control terminal of the first transistor M1.

[0094] After the first capacitor C1 stores the driving data Vdata after the threshold voltage compensation of the first transistor M1, the fifth transistor M5 and the sixth transistor M6 are controlled to be turned on in the same period and the fifth transistor M5 transmits the first power signal VDD, so that the first transistor M1 generates a driving signal using the driving data Vdata after the threshold voltage compensation of the first transistor M1 stored in the first capacitor C1 and the first power signal VDD to drive the light-emitting element LED to emit light.

[0095] The various driving signal timing diagrams of the above-mentioned pixel driving circuit and the circuit structure for generating each scanning signal and light-emitting control signal are explained below.

[0096] Figure 5 This is a driving signal timing diagram provided by the present application according to an exemplary embodiment, and the driving signal timing diagram is used to drive Figure 4 The pixel driving circuit shown.

[0097] The operation process of the pixel driving circuit is explained below.

[0098] A display cycle T includes a reset phase t1, a data writing phase t2 and a display phase t3.

[0099] The reset phase t1 is divided into four periods: a t11 period, a t12 period, a t13 period, and a t14 period.

[0100] In the driving signal timing diagram, during the periods t11 and t12, the first scanning signal S1, the second scanning signal S2, the third scanning signal S3 and the first light emitting control signal EM1 are at a high level, and the second light emitting control signal EM2 is at a low level.

[0101] Since the second light emitting control signal EM2 is at a low level, the sixth transistor M6 is turned on. However, since the first end of the sixth transistor M6 does not obtain an electrical signal, the sixth transistor M6 does not transmit an electrical signal, and the light emitting element LED does not receive an electrical signal.

[0102] In the driving signal timing diagram, during the period t13, the first scanning signal S1, the second scanning signal S2, and the second light emitting control signal EM2 are at a low level, and the third scanning signal S3 and the first light emitting control signal EM1 are at a high level.

[0103] Since the first scan signal S1 is at a low level, the seventh transistor M7 is turned on, and the second power signal Vref obtained by the first terminal thereof is transmitted to the point D.

[0104] Since the second light emitting control signal EM2 is at a low level, the sixth transistor M6 is turned on and transmits the second power signal Vref obtained by its first end from point D to the first end of the light emitting element LED. In this embodiment, the first end of the light emitting element LED is an input end.

[0105] The first end of the light emitting element LED is reset according to the second power signal Vref.

[0106] Since the second scan signal S2 is at a low level, the third transistor M3 is turned on, and the second power signal Vref obtained at the first end thereof is transmitted to the first end of the first capacitor C1.

[0107] The first terminal of the first capacitor C1 stores the second power signal Vref.

[0108] The data writing phase t2 is divided into three periods: period t21, period t22, and period t23.

[0109] In the driving signal timing diagram, during the period t21, the first scanning signal S1, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at a high level, and the second scanning signal S2 and the third scanning signal S3 are at a low level.

[0110] Since the first scan signal S1 is at a high level, the seventh transistor M7 is turned off and stops transmitting the second power signal Vref.

[0111] Since the second light emitting control signal EM2 is at a high level, the sixth transistor M6 is turned off and stops transmitting the electrical signal.

[0112] Since the first light emitting control signal EM1 is at a high level, the fifth transistor M5 is turned off and cannot transmit the first power signal VDD to the first end of the first transistor M1 .

[0113] Since the second scan signal S2 is at a low level, the third transistor M3 is turned on, and the second end and the control end of the first transistor M1 are short-circuited.

[0114] Since the third scan signal S3 is at a low level, the second transistor M2 is turned on, and the driving data Vdata acquired at the first end thereof is transmitted to the first end of the first transistor M1 .

[0115] Since the first end of the first capacitor C1 stores the second power signal Vref, and the second power signal Vref is at a low level, the control end of the first transistor M1 obtains the second power signal Vref from the first end of the first capacitor C1, and is turned on according to the second power signal Vref, and obtains the driving data Vdata compensated by the threshold voltage Vth1 from the control end according to the driving data Vdata obtained from the first end thereof, and the compensated data is Vdata+Vth1.

[0116] The first end of the first capacitor C1 obtains the compensated driving data Vdata+Vth1 from the control end of the first transistor M1 and stores the data.

[0117] In the time periods t22 and t23 in the driving signal timing diagram, the first scanning signal S1, the second scanning signal S2, the third scanning signal S3, the first light emitting control signal EM1, and the second light emitting control signal EM2 are all at high levels.

[0118] Since each signal is at a high level, each transistor is turned off and no electrical signal is transmitted.

[0119] The light-emitting element LED will not receive a driving signal during this period and will not emit light.

[0120] The display phase t3 is divided into eight time periods: time period t31 to time period t38.

[0121] In the driving signal timing diagram, during the period t31 to t33, the first scanning signal S1, the second scanning signal S2, the third scanning signal S3, and the second light emitting control signal EM2 are at a high level, and the first light emitting control signal EM1 is at a low level.

[0122] Since the first light emitting control signal EM1 is at a low level, the fifth transistor M5 is turned on, and the first power signal VDD obtained by the first end thereof is transmitted to the first end of the first transistor M1.

[0123] Since the third scan signal S3 is at a high level, the second transistor M2 is turned off and does not transmit the driving data Vdata, and the potential value of the first end of the first transistor M1 is not affected by the driving data Vdata.

[0124] Since the second scan signal S2 is at a high level, the third transistor M3 is turned off, and the control terminal and the second terminal of the first transistor M1 are disconnected.

[0125] The control end of the first transistor M1 obtains the compensated data Vdata+Vth1 from the first end of the first capacitor C1 and is turned on according to the data.

[0126] The first transistor M1 outputs a driving signal from its second end according to the electrical signal obtained at its control end and the electrical signal obtained at its first end. The current value of the driving signal is k|Vdata+Vth1-VDD-Vth1|=k|Vdata-VDD|, and the current value of the driving signal is independent of the threshold voltage.

[0127] Since the first scan signal S1 is at a high level, the seventh transistor M7 is turned off and does not transmit the second power signal Vref. The electrical signal generated at the point D is not affected by the second power signal Vref.

[0128] Since the second light emitting control signal EM2 is at a high level, the sixth transistor M6 is turned off, and cannot transmit the driving signal obtained by the first end thereof to the first end of the light emitting element LED.

[0129] Since the light emitting element LED does not obtain the driving signal, the light emitting element LED does not emit light.

[0130] In the driving signal timing diagram, during the period t34 to t38, the first scanning signal S1, the second scanning signal S2, and the third scanning signal S3 are at a high level, and the first light emitting control signal EM1 and the second light emitting control signal EM2 are at a low level.

[0131] Since the level states of the first scan signal S1, the second scan signal S2, the third scan signal S3, and the first light-emitting control signal EM1 remain unchanged from the level states in the period from t31 to T33, the states of the seventh transistor M7, the third transistor M3, the fifth transistor M5, the second transistor M2, and the first transistor M1 remain unchanged.

[0132] Since the second light emitting control signal EM2 is at a low level, the sixth transistor M6 is turned on, and transmits the driving signal obtained by the first end thereof to the first end of the light emitting element LED.

[0133] The light emitting element LED emits light according to the driving signal obtained by the first end thereof.

[0134] In the above technical solution, in the reset stage, the loop composed of the seventh transistor and the sixth transistor between the light-emitting element and the power line is turned on by the first scanning signal and the second light-emitting control signal EM2, so as to ensure that the light-emitting element can be reset. At the same time, the loop composed of the seventh transistor and the third transistor between the first end of the first capacitor and the power line is turned on by the first scanning signal and the second scanning signal. The first capacitor does not need to use the fourth transistor in the original pixel driving circuit for providing the second power signal thereto, but can still obtain the second power signal from the power line according to the above loop for a reset operation, so that the first transistor is turned on according to the second power signal after the reset stage, generates driving data for threshold voltage compensation using driving data, and generates a driving signal according to the driving data. The pixel driving circuit can still realize the driving of the light-emitting element on the basis of reducing the occupied space, which helps to increase the pixel density of the display panel constructed based on the pixel driving circuit and improve the display of the details of the display screen by the display device.

[0135] In addition, since the number of transistors electrically connected to the first end of the first capacitor is reduced, when the first capacitor drives the first transistor to generate a driving signal, the first end of the first capacitor has a reduced leakage path due to the cancellation of the fourth transistor, which helps to improve the stability of the voltage value of the first end of the first capacitor, thereby improving the stability of the current value of the driving signal generated according to the potential value of the first end of the first capacitor, and alleviating the flickering phenomenon of the display panel composed of light-emitting elements.

[0136] Figure 6 is a driving signal timing diagram provided according to another exemplary embodiment of the present application. Figure 5 , only the signal status in the t11 period is different, and the signal status in other periods remains unchanged.

[0137] The signal status and the operation of the pixel driving circuit during the t11 period are explained below.

[0138] In the driving signal timing diagram, during the period t11, the first scanning signal S1 and the second light emitting control signal EM2 are at a low level, and the second scanning signal S2, the third scanning signal S3 and the first light emitting control signal EM1 are at a high level.

[0139] Since the first scan signal S1 is at a low level, the seventh transistor M7 is turned on, and the second power signal Vref obtained by the first terminal thereof is transmitted to the point D.

[0140] Since the second light emitting control signal EM2 is at a low level, the sixth transistor M6 is turned on, and transmits the second power signal Vref obtained by the first end thereof from the point D to the first end of the light emitting element LED.

[0141] The first end of the light emitting element LED is reset according to the second power signal Vref.

[0142] Since the second scan signal S2 is at a high level, the third transistor M3 is turned off, and the second power signal Vref is not transmitted to the first capacitor C1 in this period to reset the first end of the first capacitor C1.

[0143] Since the signal status in other periods is Figure 5 The signal states shown are the same, and the operation process of the pixel driving circuit is the same, which will not be repeated here.

[0144] Figure 7 is a driving signal timing diagram provided according to another exemplary embodiment of the present application. Figure 5 , only the signal status during the t23 period is different, and the signal status during other periods remains unchanged.

[0145] The signal status and the operation of the pixel driving circuit during the t23 period are explained below.

[0146] In the driving signal timing diagram, during the period t23, the first scanning signal S1, the second scanning signal S2, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at a high level, and the third scanning signal S3 is at a low level.

[0147] Since the third scan signal S3 is at a low level, the second transistor M2 is turned on, and the driving data Vdata transmitted from the first end thereof is transmitted to the first end of the first transistor M1 .

[0148] Since the second scan signal S2 is at a high level, the third transistor M3 is turned off, and the second terminal and the control terminal of the first transistor M1 are disconnected.

[0149] The control end of the first transistor M1 obtains the compensated data Vdata+Vth1 from the first end of the first capacitor C1 and is turned on according to the compensated data.

[0150] Since the first end of the first transistor M1 obtains the driving data Vdata from the second transistor M2, when the current value of the driving signal is determined according to the data obtained from its first end and the control end, the current value is k(Vdata+Vth1-Vdata-Vth1)=0, and therefore, the second end of the first transistor M1 does not output the driving signal.

[0151] At the same time, since the second light emitting control signal EM2 is at a high level, the sixth transistor M6 is turned off and no electrical signal is transmitted.

[0152] The light-emitting element LED will not receive a driving signal during this period and will not emit light.

[0153] Since the signal status in other periods is Figure 5 The signal states shown are the same, and the operation process of the pixel driving circuit is the same, which will not be repeated here.

[0154] Figure 8 is a driving signal timing diagram provided according to another exemplary embodiment of the present application. Figure 7 , only the signal status in the t11 period is different, and the signal status in other periods remains unchanged.

[0155] because Figure 8 The waveform of the t11 period is Figure 6 The waveform of the t11 period is the same as that of the pixel driving circuit during the t11 period. Figure 6 The corresponding embodiments are explained in detail and will not be repeated here.

[0156] The scanning signal in the above driving process is provided by a scanning signal generating circuit, and the circuit structure of the scanning signal generating circuit is as follows: Fig. 9 As shown, the circuit structure of the scanning signal generating circuit is explained below.

[0157] The scanning signal generating circuit includes a plurality of driving signal generating units: a first driving signal generating unit D1, a second driving signal generating unit D2, ..., and an Nth driving signal generating unit DN.

[0158] The input end of the first drive signal generating unit D1, the first clock signal input end CLK1, and the second clock signal input end CLK2 are electrically connected to the control circuit 10, and are configured to obtain the first trigger signal STV1 or the second trigger signal STV2 from the input end, obtain the first clock signal CK from the first clock signal input end CLK1, and obtain the second clock signal CB from the second clock signal input end CLK2, and output the first signal s1 according to the two clock signals and the first trigger signal STV1 or the second trigger signal STV2.

[0159] More specifically, the first drive signal generating unit D1 is configured to output a signal consistent with the waveform of the second clock signal CB as the first signal s1 in a second time period when the signal obtained at its input terminal is consistent with the waveform of the first clock signal CK in a first time period. The second time period is the next time period adjacent to the first time period.

[0160] An input terminal of the second driving signal generating unit D2 is electrically connected to an output terminal of the first driving signal generating unit D1 , and a first clock signal input terminal CLK1 and a second clock signal input terminal CLK2 are electrically connected to the control circuit 10 .

[0161] The second driving signal generating unit D2 is configured to obtain the first signal s1 from its input terminal, obtain the second clock signal CB from the first clock signal input terminal CLK1, obtain the second clock signal CK from the first clock signal input terminal CLK2, and output the second signal s2 according to the two clock signals and the first signal s1.

[0162] More specifically, the second drive signal generating unit D2 is configured to output a signal consistent with the waveform of the first clock signal CK as the second signal s2 in a third time period when the signal obtained at its input terminal is consistent with the waveform of the second clock signal CB in the second time period. The third time period is the next time period adjacent to the second time period.

[0163] By analogy, the output terminal of the N-1th driving signal generating unit DN-1 is electrically connected to the input terminal of the Nth driving signal generating unit DN.

[0164] In the drive signal generating units arranged in an odd order, the first clock signal input terminal CLK1 is configured to obtain the first clock signal CK, and the second clock signal input terminal CLK2 is configured to obtain the second clock signal CB. The input terminal of each drive signal generating unit obtains the scan signal generated by the previous drive signal generating unit or the first trigger signal STV1 / second trigger signal STV2 output by the control circuit 10, and generates the corresponding scan signal according to the operating principle of the first drive signal generating unit D1.

[0165] In the drive signal generating units arranged in an even order, the first clock signal input terminal CLK1 is configured to obtain the second clock signal CB, and the second clock signal input terminal CLK2 is configured to obtain the first clock signal CK. The input terminal of each drive signal generating unit obtains the scanning signal generated by the previous drive signal generating unit, and generates the corresponding scanning signal according to the operating principle of the second drive signal generating unit D2.

[0166] Based on the above circuit structure, the scanning signal generating circuit 301 generates a plurality of signals s1 to sN.

[0167] Fig.10 for Fig. 9 The scan signal generating circuit shown in the figure obtains the input and output signal timing diagram of the first trigger signal STV1. Fig.11 for Fig. 9 The scan signal generating circuit shown in the figure obtains the input and output signal timing diagram of the second trigger signal STV2. The operation process of the scan signal generating circuit is explained below based on the input and output signal timing diagram. Among them, a display cycle T includes multiple display time periods, and the time length of each display time period is the same. Fig.10 and Fig.11In the signal timing diagram shown, a display cycle T includes N display time periods: time period t0 to time period tN.

[0168] When the trigger signal obtained by the first driving signal generating unit D1 is the first trigger signal STV1, the input and output signal states of the scanning signal generating circuit change as follows:

[0169] During the period t0, the first trigger signal STV1 is at a low level, the first clock signal CK is at a low level, and the second clock signal CB is at a high level. During the period t1, the second clock signal CB is at a low level.

[0170] Since the waveform of the first trigger signal STV1 and the first clock signal CK are both low level, the first drive signal generating unit D1 outputs the same waveform as the second clock signal CB in the period corresponding to t1, that is, outputs a low level, and the first signal s1 is a low level.

[0171] In the period corresponding to t1, the first trigger signal STV1 is at a low level, the first clock signal CK is at a high level, and the second clock signal CB is at a low level. In the period corresponding to t2, the first clock signal CK is at a low level.

[0172] Since the first trigger signal STV1 is at a low level and the second clock signal CK is at a high level during the period t1, the signal output by the first drive signal generating unit D1 during the period t2 is a default signal at a high level, and the first signal s1 is at a high level.

[0173] Since the first signal s1 is at a low level and the second clock signal CB is at a low level during the period t1, the second drive signal generating unit D2 outputs the same waveform as the first clock signal CK during the period t2, that is, outputs a low level, and the second signal s2 is at a low level.

[0174] During the period t2, the first trigger signal STV1 is at a low level, the first clock signal CK is at a low level, and the second clock signal CB is at a high level. During the period t3, the second clock signal CB is at a low level.

[0175] During the period t2, since the first trigger signal STV1 is at a low level and the first clock signal CK is at a low level, the first drive signal generating unit D1 outputs the same waveform as the second clock signal CB during the period corresponding to t3, that is, outputs a low level, and the first signal s1 is at a low level.

[0176] In the period t2, since the first signal s1 is at a high level and the second clock signal CB is at a low level, the signal output by the second driving signal generating unit D2 in the period t3 is a default signal at a high level, and the second signal s2 is at a high level.

[0177] During the period t2, since the second signal s2 is at a low level and the first clock signal CK is at a low level, the third driving signal generating unit D3 outputs the same waveform as the second clock signal CB during the period t3, that is, outputs a low level, and the third signal s3 is at a low level.

[0178] During the period t3, the first trigger signal STV1 is at a high level, the first clock signal CK is at a high level, and the second clock signal CB is at a low level. During the period t4, the second clock signal CB is at a high level.

[0179] During the period t3, since the first trigger signal STV1 and the first clock signal CK are both high level, during the period t4, the first drive signal generating unit D1 outputs the same waveform as the second clock signal CB, which is high level, that is, the first signal s1 is high level.

[0180] During the period t3, since the first signal s1 is at a low level and the second clock signal CB is at a low level, the second driving signal generating unit D2 outputs the same waveform as the first clock signal CK at a low level during the period t4, that is, the second signal s2 is at a low level.

[0181] In period t3, since the second signal s2 is high and the first clock signal CK is high, the third drive signal generating unit D3 outputs the same waveform as the second clock signal CB in period t4, which is high, that is, the third signal s3 is high.

[0182] During the period t3, since the third signal s3 is at a low level and the second clock signal CB is at a low level, the fourth driving signal generating unit D4 outputs the same waveform as the first clock signal CK at a low level during the period t4, that is, the fourth signal s4 is at a low level.

[0183] By analogy, it can be known that in the period from t0 to tN, according to the first trigger signal STV1 which is low level from t0 to t2 and high level from t3 to tN, each driving signal generating unit generates two low level square wave pulse signals separated by one period in a display cycle T. And the period in which each driving signal generating unit generates the first square wave pulse signal is later than the period in which the driving signal generating unit connected to its input terminal generates the first square wave pulse signal.

[0184] When the trigger signal obtained by the first driving signal generating unit D1 is the second trigger signal STV2, the input and output signal states of the scanning signal generating circuit change as follows:

[0185] During the period t0, the second trigger signal STV2 is at a low level, the first clock signal CK is at a low level, and the second clock signal CB is at a high level. During the period t1, the second clock signal CB is at a low level.

[0186] Since the waveform of the second trigger signal STV2 and the first clock signal CK are both low level, the first drive signal generating unit D1 outputs the same waveform as the second clock signal CB in the period corresponding to t1, that is, outputs a low level, and the first signal s1 is a low level.

[0187] In the period corresponding to t1, the second trigger signal STV2 is high, the first clock signal CK is high, and the second clock signal CB is low. In the period corresponding to t2, the second clock signal CB is high, and the first clock signal CK is low.

[0188] Since the second trigger signal STV2 is high level and the second clock signal CK is high level during the period t1, the first drive signal generating unit D1 outputs the same waveform as the second clock signal CB during the period t2, which is high level, and the first signal s1 is high level.

[0189] Since the first signal s1 is at a low level and the second clock signal CB is at a low level during the period t1, the second drive signal generating unit D2 outputs the same waveform as the first clock signal CK during the period t2, that is, outputs a low level, and the second signal s2 is at a low level.

[0190] In the period t2, the second trigger signal STV1 is at a high level, the first clock signal CK is at a low level, and the second clock signal CB is at a high level.

[0191] During the period t2, since the second trigger signal STV2 is at a high level and the first clock signal CK is at a low level, the first drive signal generating unit D1 outputs a default electrical signal, ie, a high level, during the period corresponding to t3, and the first signal s1 is at a high level.

[0192] Since the second trigger signal STV2 is at a high level from the time period t3 to the time period tN, the generation process of the first signal s1 in the time period t2k+1 from the time period t3 to the time period tN is the same as that in the time period t1, and the first signal s1 is at a high level. In the time period t2k, the generation process of the first signal s1 is the same as that in the time period t2, and the first signal s1 is at a high level. Wherein k is a positive integer.

[0193] During the period t2, since the first signal s1 is high and the second clock signal CB is high, the second drive signal generating unit D2 outputs the same waveform as the first clock signal CK during the period t3, which is high, and the second signal s2 is high.

[0194] During the period t2, since the second signal s2 is at a low level and the first clock signal CK is at a low level, the third driving signal generating unit D3 outputs the same waveform as the second clock signal CB during the period t3, that is, outputs a low level, and the third signal s3 is at a low level.

[0195] By analogy, it can be known that in the period from t0 to tN, according to the second trigger signal STV2 which is low level in the period from t0 and high level in the period from t1 to tN, each driving signal generating unit generates a low level square wave pulse with a time length of one display period in a display cycle T. And the period in which each driving signal generating unit generates a square wave pulse signal is later than the period in which the driving signal generating unit connected to its input terminal generates a square wave pulse signal.

[0196] The circuit structure of the light emitting control signal generating circuit is as follows: Fig.12 As shown, the circuit structure of the light emission control signal generating circuit is explained below.

[0197] The light emission control signal generating circuit includes a plurality of em signal generating units: a first em signal generating unit d1, a second em signal generating unit d2, ..., and a Nem signal generating unit dN.

[0198] The connection relationship between each EM signal generating unit is the same as the connection relationship between each trigger signal generating unit in the scanning signal generating circuit, and will not be repeated here.

[0199] The process of the light emitting control signal generating circuit generating d1 to dN signals is the same as the process of the scanning signal generating circuit generating s1 to sN signals, which will not be described again here.

[0200] Fig.13 This is the input and output signal timing diagram of the light emitting control signal generating circuit, such as Fig.12 and Fig.13 As shown, in a display cycle T, the third trigger signal STV3 is at a high level from time period t0 to time period t7, and is at a low level from time period t8 to time period tN.

[0201] The first signal em1 generated by the first em signal generating unit d1 is at a high level during a period t1 to a period t8 in a display cycle T, and is at a low level during the remaining periods.

[0202] The second signal em2 generated by the second em signal generating unit d2 is at a high level from a period t2 to a period t9 in a display cycle T, and is at a low level in the remaining periods.

[0203] By analogy, the EM signal generated by each EM signal generating unit is at a high level in seven adjacent time periods in a display cycle and at a low level in the remaining time periods, and the time when the EM signal jumps from a low level to a high level is later than the time when the signal acquired at its input end jumps from a low level to a high level.

[0204] The trigger signal obtained at the input end of the first scanning signal generating circuit is the first trigger signal STV1, the trigger signal obtained at the input end of the second scanning signal generating circuit is the second trigger signal STV2, and when the clock signals of each scanning signal generating circuit and the light emitting signal generating circuit are synchronized, for the pixel driving circuit of the first row in the display panel 40, the third signal s3 generated by the second scanning signal generating circuit is used as the first scanning signal S1, the fifth signal s5 is used as the third scanning signal S3, the third signal s3 generated by the first scanning signal generating circuit is used as the second scanning signal S2, the first signal em1 generated by the light emitting control signal generating circuit is used as the first light emitting control signal EM1, and the fourth signal em4 is used as the second light emitting control signal EM2, forming Figure 5 The waveform shown.

[0205] According to the logic of row-by-row driving, for the pixel driving circuit of the second row in the display panel 40, the fourth signal s4 generated by the second scan signal generating circuit is used as the first scan signal S1, the sixth signal s6 is used as the third scan signal S3, the fourth signal s4 generated by the first scan signal generating circuit is used as the second scan signal S2, the second signal em2 generated by the light-emitting control signal generating circuit is used as the first light-emitting control signal EM1, and the fifth signal em5 is used as the second light-emitting control signal EM2.

[0206] The same process is repeated until the corresponding first scanning signal S1, second scanning signal S2, third scanning signal S3, first light emitting control signal EM1 and second light emitting control signal EM2 are provided to the pixel driving circuits of all rows of the display panel 40, so as to achieve the following Figure 5 The driving process shown.

[0207] The trigger signal obtained at the input end of the first scanning signal generating circuit is the first trigger signal STV1, the trigger signal obtained at the input end of the second scanning signal generating circuit is the second trigger signal STV2, and when the clock signals of each scanning signal generating circuit and the light emitting signal generating circuit are synchronized, for the pixel driving circuit of the first row in the display panel 40, the first signal s1 generated by the first scanning signal generating circuit is used as the first scanning signal S1, the third signal s3 is used as the second scanning signal S2, the fifth signal s5 generated by the second scanning signal generating circuit is used as the third scanning signal S3, the first signal em1 generated by the light emitting control signal generating circuit is used as the first light emitting control signal EM1, and the fourth signal em4 is used as the second light emitting control signal EM2, forming Figure 6 The waveform shown.

[0208] According to the logic of row-by-row driving, for the pixel driving circuit of the second row in the display panel 40, the second signal s2 generated by the first scan signal generating circuit is used as the first scan signal S1, the fourth signal s4 is used as the second scan signal S2, the sixth signal s6 generated by the second scan signal generating circuit is used as the third scan signal S3, the second signal em2 generated by the light-emitting control signal generating circuit is used as the first light-emitting control signal EM1, and the fifth signal em5 is used as the second light-emitting control signal EM2.

[0209] The same process is repeated until the corresponding first scanning signal S1, second scanning signal S2, third scanning signal S3, first light emitting control signal EM1 and second light emitting control signal EM2 are provided to the pixel driving circuits of all rows of the display panel 40, so as to achieve the following Figure 6 The driving process shown.

[0210] The trigger signal obtained at the input end of the first scanning signal generating circuit is the first trigger signal STV1, the trigger signal obtained at the input end of the second scanning signal generating circuit is the second trigger signal STV2, and when the clock signals of each scanning signal generating circuit and the light emitting signal generating circuit are synchronized, for the pixel driving circuit of the first row in the display panel 40, the third signal s3 generated by the second scanning signal generating circuit is used as the first scanning signal S1, the third signal s3 generated by the first scanning signal generating circuit is used as the second scanning signal S2, the fifth signal s5 is used as the third scanning signal S3, the first signal em1 generated by the light emitting control signal generating circuit is used as the first light emitting control signal EM1, and the fourth signal em4 is used as the second light emitting control signal EM2, forming Figure 7 The waveform shown.

[0211] According to the logic of row-by-row driving, for the pixel driving circuit of the second row in the display panel 40, the fourth signal s4 generated by the second scan signal generating circuit is used as the first scan signal S1, the fourth signal s4 generated by the first scan signal generating circuit is used as the second scan signal S2, the sixth signal s6 is used as the third scan signal S3, the second signal em2 generated by the light-emitting control signal generating circuit is used as the first light-emitting control signal EM1, and the fifth signal em5 is used as the second light-emitting control signal EM2.

[0212] The same process is repeated until the corresponding first scanning signal S1, second scanning signal S2, third scanning signal S3, first light emitting control signal EM1 and second light emitting control signal EM2 are provided to the pixel driving circuits of all rows of the display panel 40, so as to achieve the following Figure 7 The driving process shown.

[0213] When the trigger signal obtained at the input end of the first scanning signal generating circuit is the first trigger signal STV1 and the clock signals of each scanning signal generating circuit and the light emitting signal generating circuit are synchronized, for the pixel driving circuit of the first row in the display panel 40, the first signal s1 generated by the first scanning signal generating circuit is used as the first scanning signal S1, the third signal s3 is used as the second scanning signal S2, the fifth signal s5 is used as the third scanning signal S3, the first signal em1 generated by the light emitting control signal generating circuit is used as the first light emitting control signal EM1, and the fourth signal em4 is used as the second light emitting control signal EM2, forming Figure 7 The waveform shown.

[0214] According to the logic of row-by-row driving, for the pixel driving circuit of the second row in the display panel 40, the second signal s2 generated by the first scanning signal generating circuit is used as the first scanning signal S1, the fourth signal s4 is used as the second scanning signal S2, and the sixth signal s6 is used as the third scanning signal S3; the second signal em2 generated by the light-emitting control signal generating circuit is used as the first light-emitting control signal EM1, and the fifth signal em5 is used as the second light-emitting control signal EM2.

[0215] Until the corresponding first scanning signal S1, second scanning signal S2, third scanning signal S3, first light emitting control signal EM1 and second light emitting control signal EM2 are provided to the pixel driving circuits of all rows in the display panel 40, so as to achieve the following Figure 8 The driving process shown.

[0216] Due to the reuse of the scanning signal generating circuit and the light emitting control signal generating circuit, the space of the gate driving circuit is reduced, which is beneficial to ensuring the narrow frame characteristic of the display device.

[0217] The above circuits are all based on P-type transistors to describe the circuit connection relationship and driving process of the pixel driving circuit. When the transistors in the pixel driving circuit are all N-type transistors, the electrical signal obtained by the first end of the fifth transistor M5 from the power line 90 is the first power signal VSS, and the first power signal VSS is at a low level. The second power signal Vref obtained by the first end of the seventh transistor M7 from the power line 90 is at a high level.

[0218] Due to the characteristics of N-type transistors, each transistor in the pixel driving circuit is turned on when a high level is obtained and turned off when a low level is obtained. Therefore, the driving signal timing diagram obtained by the pixel driving circuit based on N-type transistors is similar to Figures 5 to 8 The driving signal timing diagram shown has opposite levels in each time period.

[0219] Therefore, the trigger signals obtained by the scanning signal generating circuit and the light emission control signal generating circuit have opposite levels in each period.

[0220] Based on the above scanning signal and light emitting control signal, the driving process of the pixel driving circuit is the same as Figures 5 to 8 The driving process shown is similar and will not be repeated here.

[0221] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0222] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display device, comprising: A display panel, wherein a power line, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits are arranged on the display panel; Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element; Characterized in that the pixel driving circuit comprises: a seventh transistor, a first end of which is electrically connected to the power line, a control end of which is electrically connected to the gate line, and configured to obtain a first scan signal and a second power signal, to control its conduction state by the first scan signal, and to output the second power signal from its second end when it is turned on; a sixth transistor, a first end of which is electrically connected to the second end of the seventh transistor, a control end of which is electrically connected to the gate line, a second end of which is electrically connected to the first end of the light-emitting element, and configured to obtain a second light-emitting control signal and the second power supply signal, and to control its conduction state by the second light-emitting control signal, and to output the second power supply signal from its second end when it is turned on, so as to reset the first end of the light-emitting element; a third transistor, a first end of which is electrically connected to the second end of the seventh transistor, a control end of which is electrically connected to the gate line, and configured to obtain a second scanning signal and the second power supply signal, to control its conduction state by the second scanning signal, and to output the second power supply signal from its second end when it is turned on; The first capacitor has a first terminal electrically connected to the second terminal of the third transistor and is configured to reset the first terminal thereof using the second power signal.

2. The display device according to claim 1, characterized in that The display panel further includes: a second transistor and a first transistor; The first end of the second transistor is electrically connected to the data line, and the control end thereof is electrically connected to the gate line, and is configured to obtain a third scanning signal and driving data, and its conduction state is controlled by the third scanning signal, and the driving data is output from the second end thereof when it is turned on; The first end of the first transistor is electrically connected to the second end of the second transistor, the control end is electrically connected to the first end of the first capacitor, and the second end is electrically connected to the first end of the third transistor, and is configured to obtain the driving data and the second power supply signal, control its conduction state by the second power supply signal, and determine the driving data after threshold voltage compensation from its control end when it is turned on and its second end and the control end are short-circuited; The third transistor is further configured to short-circuit the second terminal and the control terminal of the first transistor when the third transistor is turned on; The first capacitor is further configured to store the threshold voltage compensated driving data.

3. The display device according to claim 2, characterized in that The display panel further includes a fifth transistor; The first terminal of the fifth transistor is electrically connected to the power line, and the control terminal thereof is electrically connected to the gate line, and is configured to obtain a first light-emitting control signal and a first power signal, and control its conduction state by the first light-emitting control signal, and output the first power signal from its second terminal when it is turned on; The first end of the first transistor is electrically connected to the second end of the fifth transistor, and is further configured to obtain the first power signal and the driving data after the threshold voltage is compensated, and output a driving signal from its second end according to the first power signal and the driving data after the threshold voltage is compensated; The sixth transistor is further configured to obtain the driving signal from its first terminal when it is turned on, and transmit the driving signal to the first terminal of the light emitting element; The light emitting element is configured to emit light according to the driving signal.

4. The display device according to claim 3, characterized in that The display device further includes a gate driving circuit, and the gate driving circuit includes a scanning signal generating circuit; The scanning signal generating circuit is electrically connected to the gate line and configured to generate a plurality of scanning sub-signals, wherein three adjacent scanning sub-signals with an interval of a first preset number are transmitted to a row of pixel driving circuits through the gate line; Wherein, within a display period, the phase of each scanning sub-signal is shifted backward successively, and the three adjacent scanning sub-signals with a first preset number of intervals are respectively used as the first scanning signal, the second scanning signal and the third scanning signal of the pixel driving circuit; Wherein, a display cycle includes a plurality of display time periods. In a display cycle, each scanning sub-signal is at a first level in two display time periods whose interval number is a first preset number, and is at a second level in the remaining display time periods.

5. The display device according to claim 3, characterized in that: The display device further includes a gate driving circuit, wherein the gate driving circuit includes a first scanning signal generating circuit and a second scanning signal generating circuit; The first scanning signal generating circuit is electrically connected to the gate line and configured to generate a plurality of first scanning sub-signals, wherein two adjacent first scanning sub-signals with an interval of a third preset number are transmitted to a row of pixel driving circuits through the gate line; The second scanning signal generating circuit is electrically connected to the gate line and is configured to generate a plurality of second scanning sub-signals, each of which is transmitted one by one to the pixel driving circuit of the corresponding row through the gate line; In one display period, the phase of each first scanning sub-signal is shifted backward successively.

6. The display device according to claim 5, characterized in that: A display cycle includes a plurality of display time periods; In a display cycle, the two adjacent first scanning sub-signals whose interval is a third preset number are respectively used as the first scanning signal and the third scanning signal of the pixel driving circuit, and the second scanning sub-signal is used as the second scanning signal of the pixel driving circuit; wherein each first scanning sub-signal is at the first level in one display period, and at the second level in the remaining display period of the display cycle, and each second scanning sub-signal is at the first level in two display periods whose interval is a third preset number, and at the second level in the remaining display period of the display cycle; or In a display cycle, the two adjacent first scanning sub-signals whose interval is a third preset number are respectively used as the first scanning signal and the second scanning signal of the pixel driving circuit, and the second scanning sub-signal is used as the third scanning signal of the pixel driving circuit; wherein each first scanning sub-signal is at the first level in two display time periods whose interval is the third preset number, and is at the second level in the remaining display time periods of the display cycle, and each second scanning sub-signal is at the first level in one display time period; or In a display cycle, the two adjacent first scanning sub-signals whose interval is a third preset number are respectively used as the second scanning signal and the third scanning signal of the pixel driving circuit, and the second scanning sub-signal is used as the first scanning signal of the pixel driving circuit; wherein, each first scanning sub-signal is at the first level in two display time periods whose interval is the third preset number, and is at the second level in the remaining display time periods of the display cycle, and each second scanning sub-signal is at the first level in one display time period.

7. The display device according to claim 4 or 6, characterized in that: The gate driving circuit also includes a light emitting control signal generating circuit; The light emitting control signal generating circuit is electrically connected to the gate line and configured to generate a plurality of light emitting control signals, wherein two adjacent light emitting control signals with an interval of a second preset number are transmitted to a row of pixel driving circuits through the gate line; Wherein, within a display cycle, the phases of the light-emitting control signals are shifted backward successively, and the two adjacent light-emitting control signals with an interval of a second preset number serve as the first light-emitting control signal and the second light-emitting control signal of the pixel driving circuit.

8. The display device according to claim 7, characterized in that: A display cycle includes a reset phase, a data writing phase and a display phase in sequence; The reset phase includes a reset sub-phase; In the reset sub-phase, the first scanning signal, the second scanning signal and the second light-emitting control signal are at a first level, and the third scanning signal and the first light-emitting control signal are at a second level; The seventh transistor is turned on according to the first light emitting control signal, and the second power supply signal obtained at the first end thereof is transmitted to the first end of the sixth transistor and the first end of the third transistor; The sixth transistor is turned on according to the second light emitting control signal, and transmits the second power supply signal obtained at the first end thereof to the first end of the light emitting element; The third transistor is turned on according to the second scanning signal, and transmits the second power signal obtained at the first end thereof to the first capacitor; The first capacitor resets its first end using the second power signal; The light emitting element resets its first end according to the second power signal.

9. The display device according to claim 8, characterized in that: The data writing phase includes a data writing sub-phase; In the data writing sub-phase, the first scanning signal, the first light emitting control signal and the second light emitting control signal are at the second level, and the second scanning signal and the third scanning signal are at the first level; The second transistor is turned on according to the third scanning signal, and transmits the driving data obtained at the first end thereof to the first end of the first transistor; The third transistor is turned on according to the second scanning signal to short-circuit the second end and the control end of the first transistor; The first transistor obtains a second power supply signal from the first capacitor, is turned on according to the second power supply signal, and obtains driving data after threshold voltage compensation from its control terminal according to the driving data; The first capacitor stores the driving data after the threshold voltage is compensated.

10. The display device according to claim 9, characterized in that: The display stage includes a non-luminous stage and a luminous stage; In the display stage, the first scanning signal, the second scanning signal, and the third scanning signal are at the second level, and the first light emitting control signal is at the first level; In the non-light-emitting stage, the second light-emitting control signal is at a second level; The fifth transistor is turned on according to the first light emitting control signal, and transmits the first power signal obtained at the first end thereof to the first end of the first transistor; The control terminal of the first transistor obtains the driving data after the threshold voltage compensation from the first capacitor, and transmits a driving signal to the sixth transistor according to the first power signal, the driving data after the threshold voltage compensation and its threshold voltage; The sixth transistor is turned off according to the second light emitting control signal and does not transmit the driving signal; The light emitting element does not emit light.

11. The display device according to claim 10, characterized in that: In the light emitting stage, the second light emitting control signal is at a first level; The sixth transistor is turned on according to the second light emitting control signal, and transmits the driving signal obtained at the first end thereof to the light emitting element; The light emitting element emits light according to the driving signal.

12. A method for controlling a display device, used for the display device according to any one of claims 1 to 11, characterized in that: The method comprises: Controlling the seventh transistor and the third transistor to be turned on in the same period, so that the seventh transistor and the third transistor transmit the second power supply signal to the first capacitor, and reset the first end of the first capacitor; The seventh transistor and the sixth transistor are controlled to be turned on in the same period, so that the seventh transistor and the sixth transistor transmit the second power supply signal to the light emitting element, and reset the first end of the light emitting element.

13. The method according to claim 12, characterized in that The method further comprises: After resetting the first capacitor, the third transistor and the second transistor are controlled to be turned on in the same period and the second transistor transmits driving data, so that the first capacitor stores driving data after the threshold voltage of the first transistor is compensated determined by the control terminal of the first transistor.

14. The method according to claim 13, characterized in that The method further comprises: After the first capacitor stores the driving data after the threshold voltage of the first transistor is compensated, the fifth transistor and the sixth transistor are controlled to be turned on in the same period and the fifth transistor transmits a first power signal, so that the first transistor generates a driving signal using the driving data after the threshold voltage of the first transistor stored in the first capacitor and the first power signal to drive the light-emitting element to emit light.

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