Memory programming circuit and device

Abstract

The embodiment of the invention discloses a memory programming circuit and memory programming equipment. The memory programming circuit comprises a to-be-programmed memory comprising at least one memory cell; the input and output controller is used for receiving the programming request information sent by the off-chip interface controller and generating a programming instruction aiming at the at least one storage unit based on the programming request information; and the programming control state machine is used for receiving the programming instruction sent by the input and output controller and programming the at least one storage unit based on the programming instruction. Through the circuit, the reliability and the flexibility of memory programming can be improved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a memory programming circuit and device. Background Art

[0002] An electronic fuse (efuse) is a one-time programmable, non-volatile memory device that is usually integrated into a system on chip (SOC) to store chip information, circuit calibration and repair, and safety-related functions. Its programming usually requires high voltage, and the high current brought by the high voltage burns the wire to form a permanent open circuit, which is irreversible to achieve efuse programming. Due to the need for high voltage, efuse programming requires a special control circuit.

[0003] In the related art, efuse programming can be controlled by combining software and hardware. This solution is more complicated and depends on other circuit functions inside the chip. When problems occur in other circuit functions, programming may not be possible, resulting in reduced reliability of memory programming.

[0004] Therefore, how to improve the reliability of memory programming is an urgent problem to be solved. Summary of the invention

[0005] To solve the above technical problems, an embodiment of the present application provides a memory programming circuit and device.

[0006] Among them, the memory programming circuit adopted in the present application is: a memory programming circuit, comprising: a memory to be programmed, including at least one storage unit; an input-output controller, used to receive programming request information sent by an off-chip interface controller, and generate programming instructions for the at least one storage unit based on the programming request information; a programming control state machine, used to receive the programming instructions sent by the input-output controller, and program the at least one storage unit based on the programming instructions.

[0007] In one embodiment of the present application, based on the aforementioned scheme, the input-output controller is also used to decode the programming request information, obtain address information corresponding to at least one storage cell to be programmed and programming mode information corresponding to each storage cell to be programmed, and determine the at least one storage cell to be programmed from the at least one storage cell based on the address information, and generate the programming instruction based on the address information of the at least one storage cell to be programmed and the programming mode information corresponding to each storage cell to be programmed.

[0008] In one embodiment of the present application, based on the aforementioned scheme, the input-output controller is also used to obtain the state configuration signal corresponding to each storage cell to be programmed based on the programming mode information corresponding to each storage cell to be programmed, and generate the programming instruction based on the state configuration signal corresponding to each storage cell to be programmed and the address information.

[0009] In one embodiment of the present application, based on the above-mentioned solution, the programming control state machine is also used to detect the programming state corresponding to the at least one storage unit.

[0010] In one embodiment of the present application, based on the aforementioned solution, the programming control state machine is further used to generate a programming feedback signal based on the programming state corresponding to the at least one storage unit, and send the programming feedback signal to the input-output controller.

[0011] In one embodiment of the present application, based on the above-mentioned solution, the input-output controller is also used to encode the programming feedback signal to obtain the encoded programming feedback signal, and send the encoded programming feedback signal to the off-chip interface controller.

[0012] In one embodiment of the present application, based on the aforementioned scheme, the input-output controller is also used to receive a programming repair request for the storage unit to be repaired sent by the off-chip interface controller, and decode the programming repair request to obtain a programming repair instruction for the storage unit to be repaired; wherein the programming repair request is generated by the off-chip interface controller based on the encoded programming feedback signal.

[0013] In one embodiment of the present application, based on the aforementioned solution, the programming control state machine is further used to receive the programming repair instruction sent by the input-output controller, and program the storage unit to be repaired based on the programming repair instruction.

[0014] In one embodiment of the present application, based on the above solution, if the number of the at least one storage unit is plural, the at least one storage unit is complementary.

[0015] The present application also provides a memory programming device, comprising the memory programming circuit described above.

[0016] A memory programming device comprises the memory programming circuit described above.

[0017] In the above memory programming circuit, on the one hand, through the cooperation of the input-output controller and the programming control state machine, independent programming control of at least one storage unit in the memory to be programmed can be realized without relying on other circuit functions in the off-chip interface controller. The input-output controller is responsible for interacting with the off-chip interface controller, converting programming request information into independent programming instructions, and cooperating with the programming control state machine to complete the programming operation of the memory to be programmed, thereby significantly improving the reliability of memory programming.

[0018] On the other hand, the off-chip interface controller can send various programming requests to the input-output controller according to different requirements. The input-output controller generates corresponding programming instructions based on these requests for execution by the programming control state machine, so that the memory to be programmed can be programmed in a more flexible way, thereby effectively improving the flexibility of memory programming.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings.

[0021] Figure 1 It is a schematic diagram of an implementation environment involved in this application.

[0022] Figure 2 It is a schematic diagram of the internal structure of a storage unit involved in the present application.

[0023] Figure 3 This is a schematic diagram of combining at least two storage units involved in the present application.

[0024] Figure 4 It is a schematic diagram of a memory programming device involved in the present application. DETAILED DESCRIPTION

[0025] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that are the same as the present application. Instead, they are only examples of devices and methods that are the same as some aspects of the present application as detailed in the attached claims.

[0026] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0027] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, while some operations / steps can be integrated or partially integrated, so the actual execution order may change according to actual conditions.

[0028] It should be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0029] It should be noted that in the specific implementation of the present application, when the user-related data is involved, when the embodiment of the present application is applied to a specific product or technology, the user's permission or consent is required, and the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. At the same time, the formulas involved in the embodiments of the present application can be flexibly adjusted, such as increasing or decreasing the corresponding parameters.

[0030] See also Figure 1 , Figure 1 It is a schematic diagram of an implementation environment involved in this application.

[0031] Figure 1 The implementation environment shown includes an input-output controller 110 , a program control state machine 120 , a memory to be programmed 130 , and an off-chip interface controller 140 .

[0032] The input / output controller 110, the programming control state machine 120 and the memory to be programmed 130 are all included in the SOC chip, and Figure 1 The SOC chip has a clear chip boundary and is independent of the off-chip interface controller 140. The off-chip interface controller 140 is relative to the SOC chip, and is located outside the SOC chip, and can communicate and interact with the SOC chip.

[0033] The input-output (IO) controller 110 may be a controller operating at a certain operating frequency. For example, it may be a high-speed IO controller or a low-speed IO controller. In the present application, the programming operation has a low frequency requirement, so a low-speed IO controller may be preferably used. While meeting the programming requirements, the low-speed IO controller has lower power consumption and a simpler design, which can effectively reduce the occupation of hardware resources and the complexity of the overall system. At the same time, since the programming operation is usually a one-time or less frequent operation, the low-speed IO controller is already competent for these tasks. Although the high-speed IO controller can also be used to implement the programming control in the present application, due to its higher operating frequency and more complex architectural design, it may cause resource waste, such as increased chip area, increased power consumption, etc., so it is not the best choice when the programming does not require high performance. In summary, when implementing the technical solution of the present application, the input-output controller 110 may preferably use a low-speed IO controller to optimize resource utilization and reduce power consumption costs while meeting functional requirements.

[0034] The input-output controller 110 has encoding and decoding functions, and can interact with the off-chip interface controller 140 through the input-output interface. The off-chip interface controller 140 can send programming request information for the memory 130 to be programmed to the input-output controller 110, and the input-output controller 110 can decode the programming request information to generate a programming instruction. The input-output controller 110 can also receive a programming feedback signal sent by the programming control state machine 120, encode it, and send the encoded programming feedback signal to the off-chip interface controller 140.

[0035] The programming control state machine 120 can receive the programming instruction sent by the input-output controller 110, and perform programming control on the memory to be programmed 130 based on the programming instruction and through the memory interface. The programming control state machine 120 can parse the programming instruction, and the parsing result is used to control the generation and application of high voltage, the adjustment of current size, and the determination of the programming mode for the target storage unit in the memory to be programmed 130, wherein the programming mode can at least include a manual single programming mode, an automatic multiple programming mode, a single storage unit programming mode, and a multiple storage unit programming mode. Those skilled in the art can flexibly set different programming modes according to different needs, and the embodiments of the present application are not limited thereto.

[0036] The programming control state machine 120 can strictly program the storage cells of the programming memory 130 one by one according to the preset timing control logic, ensuring that the application time, holding time and switching time of the programming signal are accurate and correct, thereby preventing programming failure or hardware damage caused by timing problems.

[0037] The memory to be programmed 130 may include at least one memory cell. Each memory cell may be a non-volatile memory cell based on electronic fuse (efuse) technology. The structure of the memory cell allows a permanent fuse (open circuit) or other permanent state to be formed by high voltage programming to record storage information.

[0038] The memory to be programmed (efuse_inst module) 130 can receive signals from the programming control state machine 120, and permanently change the physical state of the target storage unit to achieve information storage. Different storage units can support multiple programming modes, such as single fuse mode, hierarchical fuse mode or other special programming modes to meet different storage requirements.

[0039] If there are multiple storage units, the multiple storage units can complement each other through a specific circuit structure, such as series connection, parallel connection or matrix connection, etc. This can improve the capacity utilization of the memory and reduce the resource occupation of the independent control circuit.

[0040] The off-chip interface controller 140, also called an off-chip interface host, may be located in a terminal device, which may run specific programming control software. By performing specific operations in the software, the communication interaction between the off-chip interface controller and the input / output controller may be triggered, thereby triggering the programming process of the memory. The terminal device may be a laptop computer, a desktop computer, etc.

[0041] Optionally, the terminal device in the embodiment of the present application can also be a mobile phone, a tablet computer, a PDA, a mobile Internet device (mobile internet device, MID), a vehicle-mounted device, an aircraft, a wearable device (smart devices such as smart watches, smart bracelets, pedometers, etc.), a virtual reality device (for example, a virtual reality (VR) device, an augmented reality (AR) device), and the like.

[0042] Each part is described in detail one by one through the following embodiments.

[0043] The input-output controller may be configured to receive programming request information sent by the off-chip interface controller, and generate a programming instruction for at least one storage unit based on the programming request information.

[0044] The off-chip interface controller may be located in a terminal device, and the terminal device may run specific programming control software. A user may perform specific operations in the software, thereby triggering the off-chip interface controller to generate corresponding programming request information and send it to the input / output controller. The programming request information may include a storage unit that needs to be programmed. Among them, the storage unit in the embodiment of the present application may refer to an efuse macro. Each storage unit may contain multiple unit addresses.

[0045] An eFuse Macro is a basic storage unit. An eFuse Macro can include multiple programmable storage locations, each of which corresponds to a set of physical fuse grids. The Macro can have a matrix storage structure, for example, Figure 2 Shown is a schematic diagram of the internal structure of a storage unit involved in the present application. Figure 2 The figure shows a 8×16 matrix storage unit, which means that there are 8 rows in the storage unit, and each row can select 1 programming storage location; there are 16 columns, and each column can select 1 programming storage location. The total number of programming storage locations is 8×16=128, so the storage unit can store 1 bit of data.

[0046] Furthermore, each programming storage location corresponds to a storage unit programming address (efuse programming address), for example, Figure 2 In the embodiment, the storage unit has a total of 128 programmed storage locations, and the addresses of the programmed storage locations can be 0, 1, 2, ..., 126 and 127 in sequence.

[0047] The memory to be programmed may include at least one storage unit. If the number of the at least one storage unit is multiple (i.e., two or more), the multiple storage units are complementary. Complementary means that different storage units can be combined with each other to form a larger storage unit, or one storage unit can be used as a backup storage unit of another storage unit, etc.

[0048] The programming request information sent by the off-chip interface controller may include address information, which may indicate the address corresponding to the programming storage location, and the address information may indicate which storage unit these programming storage locations belong to. In other words, the address information is used to indicate which programming storage locations in which storage units need to be programmed.

[0049] The programming request information may indicate how to program each programming storage location. For example, if a programming storage location needs to be set to 1, a fuse operation may be performed on it. If a programming storage location needs to be set to 0, a fuse operation may not be performed on it. Therefore, in order to facilitate programming, the programming request information may only indicate that a fuse operation is performed on the programming location information that needs to be programmed to 1, and the remaining programming location information that has not been subjected to a fuse operation is defaulted to 0.

[0050] In addition, the programming request information also includes programming mode information. The programming mode information may include at least a manual single programming mode, an automatic multiple programming mode, a single storage unit programming mode, and a multiple storage unit programming mode. Those skilled in the art may flexibly set different programming modes according to different requirements, and the embodiments of the present application are not limited thereto.

[0051] The manual single-time programming mode refers to programming only one programming storage location of a storage unit at a time. For example, only the programming storage location with address 25 in storage unit 1 is programmed.

[0052] The automatic multiple programming mode refers to programming at least two programming storage locations at a time. The at least two programming storage locations can be located in the same storage unit or in different storage units. For example, programming storage locations with addresses 0 to 63 in storage unit 1 is programmed; for another example, programming storage location with address 1 in storage unit 1 is programmed, and programming storage location with address 129 in storage unit 2 is programmed.

[0053] The single memory cell programming mode refers to programming only one memory cell at a time, for example, programming only memory cell 1 or programming only memory cell 2.

[0054] The multiple memory cell programming mode refers to programming at least two memory cells at a time, for example, programming memory cell 1 and memory cell 2 at the same time.

[0055] After the input-output controller receives the programming request sent by the off-chip interface controller, it needs to decode the programming request information. Thus, the address information corresponding to at least one storage unit to be programmed and the programming mode information corresponding to each storage unit to be programmed are obtained. Next, the input-output controller will determine at least one storage unit to be programmed from at least one storage unit of the memory to be programmed based on the address information. That is, only a part of the at least one storage unit may need to be programmed, so it is possible to determine which storage units need to be programmed and determine them as storage units to be programmed.

[0056] Next, the input-output controller generates a programming instruction based on the address information of at least one storage cell to be programmed and the programming mode information corresponding to each storage cell to be programmed.

[0057] It should be noted that the address information and programming mode information in the programming request information cannot be directly recognized by the programming control state machine and the memory to be programmed, and therefore, need to be decoded and converted by the input / output controller.

[0058] Specifically, in the process of generating programming instructions, the input-output controller converts the address information to obtain the storage unit programming address. Next, the input-output controller is also used to obtain the state configuration signal corresponding to each storage unit to be programmed based on the programming mode information corresponding to each storage unit to be programmed, and generate programming instructions based on the state configuration signal corresponding to each storage unit to be programmed and the storage unit programming address corresponding to the address information.

[0059] The input / output controller also needs to convert the programming mode information to obtain the state machine configuration signal. Thus, a programming instruction can be generated based on the storage unit programming address and the state machine configuration signal. Therefore, the programming instruction includes the storage unit programming address and the state machine configuration signal.

[0060] The programming control state machine can receive programming instructions sent by the input-output controller. The programming control state machine can support multiple programming modes in the programming instructions, that is, the multiple programming mode information mentioned above. The programming control state machine can directly drive the memory to be programmed through the interface of the memory to be programmed through a signal, and perform programming control on at least one storage unit in the memory to be programmed according to the programming instruction.

[0061] Since the programming request information may contain multiple programming mode information, the programming control state machine will control the programming process of the memory to be programmed accordingly under different programming modes.

[0062] When the programming mode information indicates that one of the storage cells in the memory to be programmed is to be programmed, the programming control state machine only needs to perform programming control on the storage cell.

[0063] When the programming mode information indicates that programming storage locations greater than the total number of programming storage locations in a storage unit need to be programmed, the programming control state machine can call at least two storage units for programming. Exemplarily, after receiving the programming instruction, the programming control state machine finds that the programming instruction needs to program 256 programming storage locations, while there are only 128 programming storage locations in a storage unit. Then the programming control state machine will calculate that 2 storage units are needed to obtain 256 programming storage locations. Next, the two storage units will be combined to obtain a combined storage unit, and the combined storage unit will be programmed.

[0064] like Figure 3 The figure shows a schematic diagram of combining at least two storage units involved in the present application. Figure 3 In the example, both storage unit 1 and storage unit 2 have 128 programming storage locations. If the programming control state machine receives a programming instruction and finds that the programming instruction needs to program 256 programming storage locations, it is necessary to combine storage unit 1 and storage unit 2 together to form programming storage locations from 0 to 255. In addition, since the addresses of the 128 programming storage locations in storage unit 1 and storage unit 2 are arranged from 0 to 127 before the combination, after combining the two, it is necessary to arrange the address of the 128 programming storage locations of one of the storage units, such as storage unit 2, from 128 to 255.

[0065] When the programming mode information indicates that at least two storage cells need to be programmed identically, the number of programming storage locations corresponding to the at least two storage cells may be the same, and the addresses may also be the same. For example, the addresses may be 0 to 127. In this way, at least two storage cells may be programmed to the same state, and repeated programming is a redundant design, so that in special circumstances, identically programmed storage cells may be used as spare storage cells.

[0066] In one embodiment of the present application, the programming control state machine can also detect the programming state corresponding to at least one storage unit. In this way, the current programming progress of each storage unit, whether a programming error occurs, and other programming states can be detected. Among them, programming errors may include programming suspension, programming storage location error, programming not started, etc. The specific programming error situation can be set by those skilled in the art and is not limited here.

[0067] Next, the programming state machine may generate a programming feedback signal based on the detected programming state of the at least one storage unit, and the programming feedback signal may be sent to the input-output controller.

[0068] After receiving the programming feedback signal, the input / output controller needs to encode the programming feedback signal to obtain an encoded programming feedback signal, and then send the encoded programming feedback signal to the off-chip interface controller so that the off-chip interface controller can read the encoded programming feedback signal.

[0069] The input / output controller may also receive a programming repair request for the storage unit to be repaired sent by the off-chip interface controller, and decode the programming repair request to obtain a programming repair instruction for the storage unit to be repaired, wherein the programming repair request is generated by the off-chip interface controller based on the encoded programming feedback signal.

[0070] Specifically, the input-output controller has the ability to receive a programming repair request for a storage unit to be repaired sent by an off-chip interface controller. When an error occurs in the storage unit during the programming process or the expected state is not reached, the programming control state machine detects this abnormal state through the interface of the memory to be programmed and generates a corresponding programming feedback signal. After the feedback signal is transmitted to the input-output controller, the input-output controller encodes it into an encoded programming feedback signal and sends this signal to the off-chip interface controller. The off-chip interface controller determines the specific programming state abnormality based on the encoded feedback signal and generates a targeted programming repair request. Those skilled in the art can generate different programming repair requests based on different programming state abnormalities, which are not limited here.

[0071] When the input / output controller receives the programming repair request sent by the off-chip interface controller, it will decode it, parse out the specific address information and repair method of the storage unit to be repaired, and convert it into an executable programming repair instruction. The programming repair instruction will be passed to the programming control state machine, which can program the abnormal storage unit (i.e., the storage unit to be repaired) according to the programming repair instruction to implement the repair operation.

[0072] Through the memory programming circuit described in the present application, on the one hand, through the coordinated work of the input-output controller and the programming control state machine, independent programming control of at least one storage unit in the memory to be programmed can be achieved without relying on other circuit functions in the off-chip interface controller. The input-output controller is responsible for interacting with the off-chip interface controller, converting programming request information into independent programming instructions, and cooperating with the programming control state machine to complete the programming operation of the memory to be programmed, thereby significantly improving the reliability of memory programming.

[0073] On the other hand, the off-chip interface controller can send various programming requests to the input-output controller according to different requirements. The input-output controller generates corresponding programming instructions based on these requests for execution by the programming control state machine, so that the memory to be programmed can be programmed in a more flexible way, thereby effectively improving the flexibility of memory programming.

[0074] In some embodiments of this application, see Figure 4 , Figure 4 This is a schematic diagram of a memory programming device involved in this application. Figure 4 In the invention, the data processing circuit includes the memory programming circuit and the off-chip interface controller as described above.

[0075] Among them, a memory programming circuit includes: a memory to be programmed, including at least one storage unit; an input-output controller, used to receive programming request information sent by an off-chip interface controller, and generate programming instructions for at least one storage unit based on the programming request information; a programming control state machine, used to receive programming instructions sent by the input-output controller, and program at least one storage unit based on the programming instructions.

[0076] In one embodiment of the present application, based on the aforementioned scheme, the input-output controller is also used to decode the programming request information, obtain the address information corresponding to at least one storage cell to be programmed and the programming mode information corresponding to each storage cell to be programmed, and determine at least one storage cell to be programmed from at least one storage cell based on the address information, and generate a programming instruction based on the address information of at least one storage cell to be programmed and the programming mode information corresponding to each storage cell to be programmed.

[0077] In one embodiment of the present application, based on the aforementioned scheme, the input-output controller is also used to obtain a state configuration signal corresponding to each storage cell to be programmed based on the programming mode information corresponding to each storage cell to be programmed, and generate a programming instruction based on the state configuration signal and address information corresponding to each storage cell to be programmed.

[0078] In one embodiment of the present application, based on the above solution, the program control state machine is further used to detect the programming state corresponding to at least one storage unit.

[0079] In one embodiment of the present application, based on the above scheme, the programming control state machine is further used to generate a programming feedback signal based on the programming state corresponding to at least one storage unit, and send the programming feedback signal to the input-output controller.

[0080] In one embodiment of the present application, based on the above-mentioned solution, the input-output controller is further used to encode the programming feedback signal to obtain the encoded programming feedback signal, and send the encoded programming feedback signal to the off-chip interface controller.

[0081] In one embodiment of the present application, based on the aforementioned scheme, the input-output controller is also used to receive a programming repair request for the storage unit to be repaired sent by the off-chip interface controller, and decode the programming repair request to obtain a programming repair instruction for the storage unit to be repaired; wherein the programming repair request is generated by the off-chip interface controller based on the encoded programming feedback signal.

[0082] In one embodiment of the present application, based on the above-mentioned solution, the programming control state machine is further used to receive a programming repair instruction sent by the input-output controller, and program the storage unit to be repaired based on the programming repair instruction.

[0083] In one embodiment of the present application, based on the above solution, if the number of at least one storage unit is plural, at least one storage unit is complementary.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0085] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A memory programming circuit, characterized in that: include: A memory to be programmed comprises at least one storage unit; An input-output controller, configured to receive programming request information sent by the off-chip interface controller, and generate a programming instruction for the at least one storage unit based on the programming request information; The programming control state machine is used to receive the programming instruction sent by the input-output controller and program the at least one storage unit based on the programming instruction.

2. The circuit according to claim 1, characterized in that The input-output controller is also used to decode the programming request information, obtain address information corresponding to at least one storage unit to be programmed and programming mode information corresponding to each storage unit to be programmed, and determine the at least one storage unit to be programmed from the at least one storage unit based on the address information, and generate the programming instruction based on the address information of the at least one storage unit to be programmed and the programming mode information corresponding to each storage unit to be programmed.

3. The circuit according to claim 2, characterized in that The input-output controller is further used to obtain a state configuration signal corresponding to each storage cell to be programmed based on the programming mode information corresponding to each storage cell to be programmed, and to generate the programming instruction based on the state configuration signal corresponding to each storage cell to be programmed and the address information.

4. The circuit according to claim 1, characterized in that The program control state machine is also used to detect the programming state corresponding to the at least one storage unit.

5. The circuit according to claim 4, characterized in that The programming control state machine is further configured to generate a programming feedback signal based on the programming states respectively corresponding to the at least one storage unit, and send the programming feedback signal to the input-output controller.

6. The circuit according to claim 5, characterized in that The input-output controller is further used to encode the programming feedback signal to obtain an encoded programming feedback signal, and send the encoded programming feedback signal to the off-chip interface controller.

7. The circuit according to claim 6, characterized in that The input-output controller is also used to receive a programming repair request for the storage unit to be repaired sent by the off-chip interface controller, and decode the programming repair request to obtain a programming repair instruction for the storage unit to be repaired; wherein the programming repair request is generated by the off-chip interface controller based on the encoded programming feedback signal.

8. The circuit according to claim 7, characterized in that The program control state machine is further used to receive the program repair instruction sent by the input-output controller, and program the storage unit to be repaired based on the program repair instruction.

9. The circuit according to any one of claims 1 to 8, characterized in that: If the number of the at least one storage unit is plural, the at least one storage unit is complementary.

10. A memory programming device, characterized in that: Comprising the memory programming circuit as claimed in claims 1 to 8.

Images